From 77391df361fc44b3d0f975c7cf471209cf1b0159 Mon Sep 17 00:00:00 2001 From: Angele OLLIVIER <a22olliv@fl-tp-br-635.imta.fr> Date: Wed, 19 Mar 2025 12:15:13 +0100 Subject: [PATCH] fin seance --- .../ecg-POIRIER-OLLIVIER.cache/wt/project.wpc | 3 + .../ecg-POIRIER-OLLIVIER.lpr | 7 + .../sources_1/new/OperativeUnit.vhd | 249 ++++++++++++++++++ .../sources_1/new/ecgUnit.vhd | 154 +++++++++++ .../sources_1/new/fsm.vhd | 201 ++++++++++++++ ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr | 228 ++++++++++++++++ 6 files changed, 842 insertions(+) create mode 100644 ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc create mode 100644 ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.hw/ecg-POIRIER-OLLIVIER.lpr create mode 100644 ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd create mode 100644 ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd create mode 100644 ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd create mode 100644 ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc new file mode 100644 index 0000000..9b34209 --- /dev/null +++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.hw/ecg-POIRIER-OLLIVIER.lpr b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.hw/ecg-POIRIER-OLLIVIER.lpr new file mode 100644 index 0000000..afc0a86 --- /dev/null +++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.hw/ecg-POIRIER-OLLIVIER.lpr @@ -0,0 +1,7 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<labtools version="1" minor="0"/> diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd new file mode 100644 index 0000000..379a3e1 --- /dev/null +++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd @@ -0,0 +1,249 @@ +-------------------------------------------------------------------------------- +-- Title : operativeUnit +-- Project : +------------------------------------------------------------------------------- +-- File : operativeUnit.vhd +-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> +-- Company : +-- Created : 2018-04-11 +-- Last update: 2019-02-13 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: Operative unit of a sequential FIR filter. Including shift +-- register for samples, registers for coefficients, a MAC and a register to +-- store the result +------------------------------------------------------------------------------- +-- Copyright (c) 2018 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve +-- the user experience ;) +-- 2018-04-11 1.0 jnbazin Created +-- 2018-04-18 1.0 marzel Modification of SR_Y assignment to a round +-- instead of a trunc +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity OperativeUnit is + + port ( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSample : in std_logic_vector(9 downto 0); -- 8 bit input sample + I_loadShift1 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_loadShift2 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_loadShift3 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_initAddress : in std_logic; -- Control signal to initialize register read address + I_incrAddress : in std_logic; -- Control signal to increment register read address + I_initSum : in std_logic; -- Control signal to initialize the MAC register + I_loadSum : in std_logic; -- Control signal to load the MAC register; + I_loadY : in std_logic; -- Control signal to load Y register + I_Filter : in std_logic_vector(1 downto 0); + I_FilteredSampleDone : in std_logic; + O_processingDone1 : out std_logic; -- Indicate that processing is done + O_processingDone2 : out std_logic; -- Indicate that processing is done + O_processingDone2b : out std_logic; -- Indicate that processing is done + O_processingDone3 : out std_logic; -- Indicate that processing is done + O_Y : out std_logic_vector(9 downto 0) -- filtered sample + ); + +end entity OperativeUnit; + +architecture arch_OperativeUnit of OperativeUnit is + type registerFile95 is array(0 to 94) of signed(10 downto 0); + signal SR_coefRegister1 : registerFile95; + type registerFile3 is array(0 to 2) of signed(10 downto 0); + signal SR_coefRegister2 : registerFile3; + type registerFile2 is array(0 to 1) of signed(10 downto 0); + signal SR_coefRegister2b : registerFile2; + type registerFile11 is array(0 to 10) of signed(10 downto 0); + signal SR_coefRegister3 : registerFile11; + + + signal SR_shiftRegister1 : registerFile95; -- shift register file used to store and shift input samples + signal SR_shiftRegister2 : registerFile3; -- shift register file used to store and shift input samples + signal SR_shiftRegister3 : registerFile11; -- shift register file used to store and shift input samples + signal SC_multOperand1 : signed(9 downto 0); + signal SC_multOperand2 : signed(10 downto 0); + signal SC_MultResult : signed(20 downto 0); -- Result of the multiplication Xi*Hi + signal SC_addResult : signed(27 downto 0); -- result of the accumulation addition + signal SR_sum : signed(27 downto 0); -- Accumulation register + signal SR_Y : signed(9 downto 0); -- filtered sample storage register + signal SR_readAddress : integer range 0 to 94; -- register files read address + +-- DIMENSIONNEMENT !!! + +begin + +-- Low-pass filter provided with octave (or Matlab ;)) command +--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6 + SR_coefRegister1 <= (to_signed(-1, 11), -- ROM register used file to store FIR coefficients + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-2, 11), + to_signed(-2, 11), + to_signed(-2, 11), + to_signed(-3, 11), + to_signed(-3, 11), + to_signed(-3, 11), + to_signed(-4, 11), + to_signed(-4, 11), + to_signed(-5, 11), + to_signed(-5, 11), + to_signed(-6, 11), + to_signed(-6, 11), + to_signed(-7, 11), + to_signed(-7, 11), + to_signed(-8, 11), + to_signed(-8, 11), + to_signed(-9, 11), + to_signed(-10, 11), + to_signed(-10, 11), + to_signed(-11, 11), + to_signed(-11, 11), + to_signed(-12, 11), + to_signed(-13, 11), + to_signed(-13, 11), + to_signed(-14, 11), + to_signed(-14, 11), + to_signed(-15, 11), + to_signed(-15, 11), + to_signed(-16, 11), + to_signed(-16, 11), + to_signed(-17, 11), + to_signed(-17, 11), + to_signed(-18, 11), + to_signed(-18, 11), + to_signed(-18, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(1004, 11) + ); + + SR_coefRegister2 <= (to_signed(961, 11), -- ROM register used file to store FIR coefficients + to_signed(-1554, 11), + to_signed(961, 11) + ); + + SR_coefRegister2b <= (to_signed(-1554, 11), -- ROM register used file to store FIR coefficients + to_signed(897, 11) + ); + + SR_coefRegister3 <= (to_signed(-119, 11), -- ROM register used file to store FIR coefficients + to_signed(122, 11), + to_signed(149, 11), + to_signed(191, 11), + to_signed(226, 11), + to_signed(239, 11) + ); + + + shift : process (I_clock, I_reset) is + begin -- process shift + if I_reset = '1' then -- asynchronous reset (active high) + SR_shiftRegister1 <= (others => (others => '0')); + SR_shiftRegister2 <= (others => (others => '0')); + SR_shiftRegister3 <= (others => (others => '0')); + elsif (rising_edge(I_clock)) then + if (I_loadShift1 = '1') then + SR_shiftRegister1(1 to 94) <= SR_shiftRegister1(0 to 93); + SR_shiftRegister1(0) <= signed(I_inputSample); + elsif (I_loadShift2 = '1') then + SR_shiftRegister2(1 to 2) <= SR_shiftRegister2(0 to 1); + SR_shiftRegister2(0) <= signed(SR_Y); + elsif (I_loadShift3 = '1') then + SR_shiftRegister3(1 to 10) <= SR_shiftRegister3(0 to 9); + SR_shiftRegister3(0) <= signed(SR_Y); + end if; + end if; + end process shift; + + incr_address : process (I_reset, I_clock) is + begin + if I_reset = '1' then -- asynchronous reset (active high) + SR_readAddress <= 0; + elsif (rising_edge(I_clock)) then + if(I_initAddress = '1') then + SR_readAddress <= 0; + end if; + + if (I_incrAddress = '1') then + if (I_Filter = "00") then + if (SR_readAddress < 94) then + SR_readAddress <= SR_readAddress + 1; + end if; + elsif (I_Filter = "01") then + if (SR_readAddress < 2) then + SR_readAddress <= SR_readAddress + 1; + end if; + elsif (I_Filter = "10") then + if (SR_readAddress < 1) then + SR_readAddress <= SR_readAddress + 1; + end if; + else + if (SR_readAddress < 10) then + SR_readAddress <= SR_readAddress + 1; + end if; + end if; + + end if; + end if; + end process incr_address; + + O_processingDone1 <= '1' when (SR_readAddress >=94 and I_Filter="00") else '0' ; + O_processingDone2 <= '1' when (SR_readAddress >=2 and I_Filter="01") else '0' ; + O_processingDone2b <= '1' when (SR_readAddress >=1 and I_Filter="10") else '0' ; + O_processingDone3 <= '1' when (SR_readAddress >=10 and I_Filter="11") else '0' ; + + SC_multOperand1 <= SR_shiftRegister1(SR_readAddress) when I_Filter="00" else SR_shiftRegister2(SR_readAddress) when I_Filter="01" else SR_shiftRegister3(SR_readAddress); + SC_multOperand2 <= SR_coefRegister1(SR_readAddress) when I_Filter="00" else SR_coefRegister2(SR_readAddress) when I_Filter="01" else SR_coefRegister2b(SR_readAddress) when I_Filter="10" else SR_coefRegister3(SR_readAddress) ; -- 8 bits + SC_MultResult <= SC_multOperand1 * SC_multOperand2 ; + SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum; + + sum_acc : process (I_reset, I_clock) is + begin + if I_reset = '1' then -- asynchronous reset (active high) + SR_sum <= (others => '0'); + elsif rising_edge(I_clock) then + if (I_initSum='1') then + SR_sum <= (others => '0'); + elsif (I_loadSum='1') then + SR_sum <= SC_addResult; + end if; + end if; + end process sum_acc; + + store_result : process (I_clock) is + begin + if (rising_edge(I_clock)) then + if (I_loadY='1') then +-- if(SR_sum(6)='1') then +-- SR_Y <= SR_sum(14 downto 7) + 1; +-- else +-- SR_Y <= SR_sum(14 downto 7); +-- end if; + SR_Y <= SR_sum; + end if; + + if (I_FilteredSampleDone = '1') then + O_Y <= std_logic_vector(SR_Y); + end if; + end if; + + end process store_result; + + + +end architecture arch_OperativeUnit; \ No newline at end of file diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd new file mode 100644 index 0000000..9a5c9a5 --- /dev/null +++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd @@ -0,0 +1,154 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03/19/2025 11:55:14 AM +-- Design Name: +-- Module Name: ecgUnit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ecgUnit is +port( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSample : in std_logic_vector(9 downto 0); -- 8 bit input sample + I_inputSampleValid : in std_logic; + O_filteredSample : out std_logic_vector(9 downto 0); -- filtered sample + O_filteredSampleValid : out std_logic + ); +end ecgUnit; + +architecture Behavioral of ecgUnit is + +component fsm is + port ( + I_Clock : in std_logic; + I_reset : in std_logic; + I_inputSampleValid : in std_logic; + I_processing1Done : in std_logic; + I_processing2Done : in std_logic; + I_processing2PrimeDone : in std_logic; + I_processing3Done : in std_logic; + O_loadShift1 : out std_logic; + O_loadShift2 : out std_logic; + O_loadShift3 : out std_logic; + O_initAddress : out std_logic; + O_incrAddress : out std_logic; + O_initSum : out std_logic; + O_loadSum : out std_logic; + O_loadOutput : out std_logic; + O_filter : out std_logic_vector(1 downto 0); + O_FilteredSampleDone : in std_logic); + end component fsm; + + component OperativeUnit is + port ( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSample : in std_logic_vector(9 downto 0); -- 8 bit input sample + I_loadShift1 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_loadShift2 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_loadShift3 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_initAddress : in std_logic; -- Control signal to initialize register read address + I_incrAddress : in std_logic; -- Control signal to increment register read address + I_initSum : in std_logic; -- Control signal to initialize the MAC register + I_loadSum : in std_logic; -- Control signal to load the MAC register; + I_loadY : in std_logic; -- Control signal to load Y register + I_Filter : in std_logic_vector(1 downto 0); + I_FilteredSampleDone : in std_logic; + O_processingDone1 : out std_logic; -- Indicate that processing is done + O_processingDone2 : out std_logic; -- Indicate that processing is done + O_processingDone2b : out std_logic; -- Indicate that processing is done + O_processingDone3 : out std_logic; -- Indicate that processing is done + O_Y : out std_logic_vector(9 downto 0) -- filtered sample + ); + end component OperativeUnit; + + + signal SC_processingDone1 : std_logic; + signal SC_processingDone2 : std_logic; + signal SC_processingDone2b : std_logic; + signal SC_processingDone3 : std_logic; + signal SC_loadShift1 : std_logic; + signal SC_loadShift2 : std_logic; + signal SC_loadShift3 : std_logic; + signal SC_initAddress : std_logic; + signal SC_incrAddress : std_logic; + signal SC_initSum : std_logic; + signal SC_loadSum : std_logic; + signal SC_loadY : std_logic; + signal SC_Filter : std_logic_vector(1 downto 0); + signal SC_FilteredSampleDone : std_logic; + +begin + +controlUnit_1 : entity work.fsm + port map ( + I_Clock => I_clock, + I_reset => I_reset, + I_inputSampleValid => I_inputSampleValid, + I_processing1Done => SC_processingDone1, + I_processing2Done => SC_processingDone2, + I_processing2PrimeDone => SC_processingDone2b, + I_processing3Done => SC_processingDone3, + O_loadShift1 => SC_loadShift1, + O_loadShift2 => SC_loadShift2, + O_loadShift3 => SC_loadShift3, + O_initAddress => SC_initAddress, + O_incrAddress => SC_incrAddress, + O_initSum => SC_initSum, + O_loadSum => SC_loadSum, + O_loadOutput => SC_loadY, + O_filter => SC_Filter, + O_FilteredSampleDone => SC_FilteredSampleDone + ); + +OpUnit : entity work.OperativeUnit + port map ( + I_clock => I_clock, + I_reset => I_reset, + I_inputSample => I_inputSample, + I_loadShift1 => SC_loadShift1, + I_loadShift2 => SC_loadShift2, + I_loadShift3 => SC_loadShift3, + I_initAddress => SC_initAddress, + I_incrAddress => SC_incrAddress, + I_initSum => SC_initSum, + I_loadSum => SC_loadSum, + I_loadY => SC_loadY, + I_Filter => SC_Filter, + I_FilteredSampleDone + O_processingDone1 + O_processingDone2 + O_processingDone2b + O_processingDone3 + O_Y + ); + + + +end Behavioral; diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd new file mode 100644 index 0000000..5d7212a --- /dev/null +++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd @@ -0,0 +1,201 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03/19/2025 09:52:24 AM +-- Design Name: +-- Module Name: fsm - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +entity fsm is + port ( + I_Clock : in std_logic; + I_reset : in std_logic; + I_inputSampleValid : in std_logic; + I_processing1Done : in std_logic; + I_processing2Done : in std_logic; + I_processing2PrimeDone : in std_logic; + I_processing3Done : in std_logic; + O_loadShift1 : out std_logic; + O_loadShift2 : out std_logic; + O_loadShift3 : out std_logic; + O_initAddress : out std_logic; + O_incrAddress : out std_logic; + O_initSum : out std_logic; + O_loadSum : out std_logic; + O_loadOutput : out std_logic; + O_filter : out std_logic_vector(1 downto 0); + O_FilteredSampleDone : in std_logic + ); +end entity fsm; + +architecture a_fsm of fsm is + + type T_State is (WAIT_SAMPLE, STORE, PROCESSING_LOOP_1, OUTPUT_1, PROCESSING_LOOP_2, OUTPUT_2, PROCESSING_LOOP_2b, OUTPUT_2b, PROCESSING_LOOP_3, OUTPUT, WAIT_END_SAMPLE); + signal SR_present : T_State; + signal SC_futur : T_State; + +begin + + process(I_Clock, I_reset) is + begin + if I_reset = '1' then + SR_present <= WAIT_SAMPLE; + elsif(rising_edge(I_Clock)) then + SR_present <= SC_futur; + end if; + end process; + + + process(SR_present, I_reset, I_inputSampleValid, I_processing1Done, I_processing2Done, I_processing2PrimeDone, I_processing3Done) + begin + case SR_present is + + when WAIT_SAMPLE => + if(I_inputSampleValid = '1') then + SC_futur <= STORE; + else + SC_futur <= WAIT_SAMPLE; + end if; + + when STORE => + SC_futur <= PROCESSING_LOOP_1; + + when PROCESSING_LOOP_1 => + if(I_processing1Done = '1') then + SC_futur <= OUTPUT_1; + else + SC_futur <= PROCESSING_LOOP_1; + end if; + + when OUTPUT_1 => + SC_futur <= PROCESSING_LOOP_2; + + when PROCESSING_LOOP_2 => + if(I_processing2Done = '1') then + SC_futur <= OUTPUT_2; + else + SC_futur <= PROCESSING_LOOP_2; + end if; + + when OUTPUT_2 => + SC_futur <= PROCESSING_LOOP_2b; + + when PROCESSING_LOOP_2b => + if(I_processing2PrimeDone = '1') then + SC_futur <= OUTPUT_2b; + else + SC_futur <= PROCESSING_LOOP_2b; + end if; + + when OUTPUT_2b => + SC_futur <= PROCESSING_LOOP_3; + + when PROCESSING_LOOP_3 => + if(I_processing3Done = '1') then + SC_futur <= OUTPUT; + else + SC_futur <= PROCESSING_LOOP_3; + end if; + + when OUTPUT => + SC_futur <= WAIT_END_SAMPLE; + + when WAIT_END_SAMPLE => + if(I_inputSampleValid = '0') then + SC_futur <= WAIT_SAMPLE; + else + SC_futur <= WAIT_END_SAMPLE; + end if; + + end case; + end process; + + + process(SR_present, I_reset, I_inputSampleValid, I_processing1Done, I_processing2Done, I_processing2PrimeDone, I_processing3Done) + begin + + -- default output values + + O_loadShift1 <= '0'; + O_loadShift2 <= '0'; + O_loadShift3 <= '0'; + O_initAddress <= '0'; + O_incrAddress <= '0'; + O_initSum <= '0'; + O_loadSum <= '0'; + O_loadOutput <= '0'; + O_filter <= "00"; + O_FilteredSampleDone <= '0'; + + case SR_present is + + when STORE => + O_loadShift1 <= '1'; + O_initAddress <= '1'; + O_initSum <= '1'; + O_filter <= "00"; + + when PROCESSING_LOOP_1 => + O_incrAddress <= '1'; + O_loadSum <= '1'; + O_filter <= "00"; + + when OUTPUT_1 => + O_loadShift2 <= '1'; + O_initAddress <= '1'; + O_initSum <= '1'; + O_loadOutput <= '1'; + O_filter <= "01"; + + when PROCESSING_LOOP_2 => + O_incrAddress <= '1'; + O_loadSum <= '1'; + O_filter <= "01"; + + when OUTPUT_2 => + O_loadShift3 <= '1'; + O_initAddress <= '1'; + O_loadOutput <= '1'; + O_filter <= "10"; + + when PROCESSING_LOOP_2b => + O_incrAddress <= '1'; + O_loadSum <= '1'; + O_filter <= "10"; + + when OUTPUT_2b => + O_loadShift3 <= '1'; + O_initAddress <= '1'; + O_initSum <= '1'; + O_loadOutput <= '1'; + O_filter <= "11"; + + when PROCESSING_LOOP_3 => + O_incrAddress <= '1'; + O_loadSum <= '1'; + O_filter <= "11"; + + when OUTPUT => + O_FilteredSampleDone <= '1'; + O_filter <= "11"; + + end case; + end process; +end a_fsm; \ No newline at end of file diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr new file mode 100644 index 0000000..d50b962 --- /dev/null +++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr @@ -0,0 +1,228 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<Project Product="Vivado" Version="7" Minor="67" Path="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="97cf4459d323475fb6b3317ae78d27f5"/> + <Option Name="Part" Val="xc7a12ticsg325-1L"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2024.1"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2023.04"/> + <Option Name="SimulatorVersionActiveHdl" Val="14.1"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="BoardPart" Val=""/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="ClassicSocBoot" Val="FALSE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="32"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/OperativeUnit.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/fsm.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/ecgUnit.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="ecgUnit"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="ecgUnit"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="22"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board/> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> -- GitLab