diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 30ffa402b4a5440dfd639740383f7229b380b3c1..0176eae2c4050cd732b46c8cb3a6a519281744ec 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -1,6 +1,6 @@
---
title: "Compte rendu Filtrage ECG"
-author: John Doe
+author: OLLIVIER Angèle et POIRIER Lucas
geometry: margin=1cm
output: pdf_document
mainfont: sans-serif
@@ -18,4 +18,19 @@ mainfont: sans-serif
## Remarques
-(Notez toute information qui vous semble pertinente)
+Nous avons une machine d'état de Moore.
+Nous pourions faire un seul état OUTPUT + STORE en utilisant la valeur de addResult comme valeur d'entrée des registres d'échantillon 2 et 3.
+Pour l'instant nous utilisons SR_Y avec un signal pour indiquer de garder cette valeur pour l'utiliser comme échantillon d'entrée.
+Nous utilisons un autre signal pour indiquer que SR-Y est prêt à être utilisé comme valeur de sortie finale des trois filtres.
+
+Nous avons copié et modifié le testbench du filtre audio pour l'adapter à notre ecg.
+Avec nous avons vérifié le bon enchaînement des états.
+
+A la fin de la dernière séance nous avons utilisé dans le testbench les valeurs de ADCSampleOctave.csv
+Dans ce document il y a aussi les résultats attendus en sortie de l'ecg.
+Ainsi on peut vérifier le fonctionnement de notre ecg.
+Nous n'obtenons pas les résultats attendus.
+
+Pistes :
+- Nos valeurs ne sont pas appelées à la bonne fréquence?
+- Problème dans l'unité de calcul?
\ No newline at end of file
diff --git a/docs/img/FSM.png b/docs/img/FSM.png
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..d02a3a4f53d72d843ef1158ba2724504bac76c02 100644
Binary files a/docs/img/FSM.png and b/docs/img/FSM.png differ
diff --git a/docs/img/OperativeUnit.png b/docs/img/OperativeUnit.png
index 64a947ab89b5c179f8cda30834baa893918774d1..d368c4a78e8caf82c4811e7453ebe0a3f1509074 100644
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/sim/ssm.db b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/sim/ssm.db
new file mode 100644
index 0000000000000000000000000000000000000000..6a4a8ab76871b2c60901b082c17b88f19b046070
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 26 10:00:21 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc
index 9b342093142bd1b298b4af63bdebdead3a3ef56e..6888edec1ac73923cacb7d6dea38f6663dae769b 100644
--- a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:1
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eof:
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/synthesis.wdf b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/synthesis.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..c79836cf99861346bd64582ae89d1b14de6d8fca
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/synthesis.wdf
@@ -0,0 +1,49 @@
+version:1
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/synthesis_details.wdf b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/xsim.wdf b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/xsim.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..51d5206f7011f2f0764fb661278617e58456141a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.ip_user_files/README.txt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_1.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_2.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_3.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_4.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_4.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_5.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_5.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_5.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_6.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_6.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_6.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_7.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_7.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_7.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_8.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_8.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_8.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_9.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_9.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ab2d54f53d91bca6795ec9fa9aaefb41142a333a
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/.jobs/vrs_config_9.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.Vivado_Synthesis.queue.rst b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.vivado.begin.rst b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..2754520ee78580dcc02c5818b05ec2c04599f2dd
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="a22olliv" Host="fl-tp-br-635" Pid="57846" HostCore="4" HostMemory="16257696">
+ </Process>
+</ProcessHandle>
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.vivado.end.rst b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ISEWrap.js b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ISEWrap.sh b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/__synthesis_is_complete__ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.dcp b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..977048343956b3ca3ffe1d03c56c61a199da36fc
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.dcp differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.tcl b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b33ead24174b5e40151d98fc899f18f8a5e56dca
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.tcl
@@ -0,0 +1,110 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a12ticsg325-1L
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/wt [current_project]
+set_property parent.project_path /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property ip_output_repo /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib {
+ /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd
+ /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd
+ /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd
+}
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top ecgUnit -part xc7a12ticsg325-1L
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef ecgUnit.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.vds b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.vds
new file mode 100644
index 0000000000000000000000000000000000000000..f40943f4a35b4dbe0bea6bd8b9708cc04ecc33b3
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.vds
@@ -0,0 +1,281 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Mar 26 10:39:18 2025
+# Process ID: 57918
+# Current directory: /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1
+# Command line: vivado -log ecgUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
+# Log file: /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.vds
+# Journal file: /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-635
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3200.085 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :16873 MB
+#-----------------------------------------------------------
+source ecgUnit.tcl -notrace
+create_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 1573.871 ; gain = 145.809 ; free physical = 6575 ; free virtual = 15594
+Command: read_checkpoint -auto_incremental -incremental /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top ecgUnit -part xc7a12ticsg325-1L
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a12ti'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a12ti'
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 58119
+---------------------------------------------------------------------------------
+Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2006.461 ; gain = 419.684 ; free physical = 5784 ; free virtual = 14790
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'ecgUnit' [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd:44]
+INFO: [Synth 8-638] synthesizing module 'fsm' [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd:48]
+INFO: [Synth 8-256] done synthesizing module 'fsm' (0#1) [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd:48]
+INFO: [Synth 8-638] synthesizing module 'OperativeUnit' [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd:57]
+INFO: [Synth 8-256] done synthesizing module 'OperativeUnit' (0#1) [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd:57]
+INFO: [Synth 8-256] done synthesizing module 'ecgUnit' (0#1) [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd:44]
+---------------------------------------------------------------------------------
+Finished Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2085.430 ; gain = 498.652 ; free physical = 5690 ; free virtual = 14703
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2100.273 ; gain = 513.496 ; free physical = 5682 ; free virtual = 14800
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a12ticsg325-1L
+INFO: [Device 21-403] Loading part xc7a12ticsg325-1L
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2108.277 ; gain = 521.500 ; free physical = 5678 ; free virtual = 14796
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_present_reg' in module 'fsm'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00000000001 | 0000
+ store | 00000000010 | 0001
+ processing_loop_1 | 00000000100 | 0010
+ output_1 | 00000001000 | 0011
+ processing_loop_2 | 00000010000 | 0100
+ output_2 | 00000100000 | 0101
+ processing_loop_2b | 00001000000 | 0110
+ output_2b | 00010000000 | 0111
+ processing_loop_3 | 00100000000 | 1000
+ output | 01000000000 | 1001
+ wait_end_sample | 10000000000 | 1010
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_present_reg' using encoding 'one-hot' in module 'fsm'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2133.199 ; gain = 546.422 ; free physical = 5456 ; free virtual = 14942
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 11 Bit Adders := 1
+ 2 Input 7 Bit Adders := 1
++---Registers :
+ 29 Bit Registers := 1
+ 11 Bit Registers := 111
+ 7 Bit Registers := 1
++---Muxes :
+ 2 Input 29 Bit Muxes := 1
+ 11 Input 11 Bit Muxes := 1
+ 2 Input 11 Bit Muxes := 8
+ 3 Input 11 Bit Muxes := 1
+ 3 Input 10 Bit Muxes := 1
+ 2 Input 10 Bit Muxes := 1
+ 2 Input 7 Bit Muxes := 5
+ 4 Input 7 Bit Muxes := 1
+ 10 Input 2 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 5
+ 2 Input 1 Bit Muxes := 5
+ 4 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+INFO: [Device 21-9227] Part: xc7a12ticsg325-1L does not have CEAM library.
+Part Resources:
+DSPs: 40 (col length:40)
+BRAMs: 40 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+DSP Report: Generating DSP OpUnit/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator OpUnit/SC_addResult is absorbed into DSP OpUnit/SC_addResult.
+DSP Report: operator OpUnit/SC_MultResult is absorbed into DSP OpUnit/SC_addResult.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5010 ; free virtual = 14754
+---------------------------------------------------------------------------------
+ Sort Area is OpUnit/SC_addResult_0 : 0 0 : 1007 1007 : Used 1 time 0
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|OperativeUnit | C+A*B | 11 | 11 | 29 | - | 29 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5002 ; free virtual = 14753
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5002 ; free virtual = 14753
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5691 ; free virtual = 14730
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5683 ; free virtual = 14729
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5672 ; free virtual = 14747
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5670 ; free virtual = 14748
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+DSP Final Report (the ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|OperativeUnit | C+A*B | 30 | 18 | 48 | - | 29 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |BUFG | 1|
+|2 |CARRY4 | 3|
+|3 |DSP48E1 | 1|
+|4 |LUT2 | 12|
+|5 |LUT3 | 18|
+|6 |LUT4 | 75|
+|7 |LUT5 | 45|
+|8 |LUT6 | 390|
+|9 |MUXF7 | 88|
+|10 |MUXF8 | 33|
+|11 |FDCE | 1248|
+|12 |FDPE | 1|
+|13 |FDRE | 22|
+|14 |IBUF | 14|
+|15 |OBUF | 11|
++------+--------+------+
+
+Report Instance Areas:
++------+----------------+--------------+------+
+| |Instance |Module |Cells |
++------+----------------+--------------+------+
+|1 |top | | 1962|
+|2 | OpUnit |OperativeUnit | 1862|
+|3 | controlUnit_1 |fsm | 74|
++------+----------------+--------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.770 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2263.977 ; gain = 0.000 ; free physical = 5705 ; free virtual = 15014
+INFO: [Netlist 29-17] Analyzing 125 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-101] Netlist 'ecgUnit' is not ideal for floorplanning, since the cellview 'OperativeUnit' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.609 ; gain = 0.000 ; free physical = 4897 ; free virtual = 15017
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: eb2b3431
+INFO: [Common 17-83] Releasing license: Synthesis
+25 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:26 . Memory (MB): peak = 2351.609 ; gain = 772.770 ; free physical = 4814 ; free virtual = 15018
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1899.163; main = 1595.578; forked = 399.589
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3323.309; main = 2351.613; forked = 1059.543
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2375.621 ; gain = 0.000 ; free physical = 5110 ; free virtual = 14773
+INFO: [Common 17-1381] The checkpoint '/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 26 10:40:10 2025...
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit_utilization_synth.pb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a4857d630d8a80ba9b918f654f4ac92396068b28
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit_utilization_synth.pb differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit_utilization_synth.rpt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..04298b353c14bd8b8ba34b49d851f529222d6d3f
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit_utilization_synth.rpt
@@ -0,0 +1,189 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 26 10:40:10 2025
+| Host : fl-tp-br-635 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb
+| Design : ecgUnit
+| Device : xc7a12ticsg325-1L
+| Speed File : -1L
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 495 | 0 | 0 | 8000 | 6.19 |
+| LUT as Logic | 495 | 0 | 0 | 8000 | 6.19 |
+| LUT as Memory | 0 | 0 | 0 | 5000 | 0.00 |
+| Slice Registers | 1271 | 0 | 0 | 16000 | 7.94 |
+| Register as Flip Flop | 1271 | 0 | 0 | 16000 | 7.94 |
+| Register as Latch | 0 | 0 | 0 | 16000 | 0.00 |
+| F7 Muxes | 88 | 0 | 0 | 7300 | 1.21 |
+| F8 Muxes | 33 | 0 | 0 | 3650 | 0.90 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 1 | Yes | - | Set |
+| 1248 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 22 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 20 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 20 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 40 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| DSPs | 1 | 0 | 0 | 40 | 2.50 |
+| DSP48E1 only | 1 | | | | |
++----------------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 25 | 0 | 0 | 150 | 16.67 |
+| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 3 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 3 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 12 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 12 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 3 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 144 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 12 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 12 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 150 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 150 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
+| BUFIO | 0 | 0 | 0 | 12 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 3 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 3 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 6 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
+| BUFR | 0 | 0 | 0 | 12 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 1248 | Flop & Latch |
+| LUT6 | 390 | LUT |
+| MUXF7 | 88 | MuxFx |
+| LUT4 | 75 | LUT |
+| LUT5 | 45 | LUT |
+| MUXF8 | 33 | MuxFx |
+| FDRE | 22 | Flop & Latch |
+| LUT3 | 18 | LUT |
+| IBUF | 14 | IO |
+| LUT2 | 12 | LUT |
+| OBUF | 11 | IO |
+| CARRY4 | 3 | CarryLogic |
+| FDPE | 1 | Flop & Latch |
+| DSP48E1 | 1 | Block Arithmetic |
+| BUFG | 1 | Clock |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/gen_run.xml b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..027388ce371ce9a3153610378a295bce721661c9
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/gen_run.xml
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a12ticsg325-1L" LaunchTime="1742981954" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ecgUnit.dcp">
+ <File Type="VDS-TIMINGSUMMARY" Name="ecgUnit_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="ecgUnit.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="ecgUnit_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="ecgUnit_utilization_synth.rpt"/>
+ <File Type="RDS-PROPCONSTRS" Name="ecgUnit_drc_synth.rpt"/>
+ <File Type="RDS-RDS" Name="ecgUnit.vds"/>
+ <File Type="REPORTS-TCL" Name="ecgUnit_reports.tcl"/>
+ <File Type="VDS-TIMING-PB" Name="ecgUnit_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="ecgUnit.tcl"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/new/OperativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/fsm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/ecgUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="ecgUnit"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/ecgUnit.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+</GenRun>
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/htr.txt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..3899de31fa9294996d374c7468b51202b1f7ad77
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/incr_synth_reason.pb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/incr_synth_reason.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4cb4ed43e865edf4e8dcb3c9857bfe8acfc68b23
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/incr_synth_reason.pb
@@ -0,0 +1 @@
+� 6No compile time benefit to using incremental synthesis
\ No newline at end of file
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/project.wdf b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..ef5d0fd5eb41a9b3ec167017dfc78434b739990d
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3937636634343539643332333437356662366233333137616537386432376635:506172656e742050412070726f6a656374204944:00
+eof:3609315318
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/rundef.js b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..4f52e5b9b035779e7cf230326068452323bb6e82
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.bat b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..fe19f5681d4f69e483028a7c77eeccfce057c00d
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.log
@@ -0,0 +1,271 @@
+
+*** Running vivado
+ with args -log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Mar 26 10:39:18 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source ecgUnit.tcl -notrace
+create_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 1573.871 ; gain = 145.809 ; free physical = 6575 ; free virtual = 15594
+Command: read_checkpoint -auto_incremental -incremental /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top ecgUnit -part xc7a12ticsg325-1L
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a12ti'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a12ti'
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 58119
+---------------------------------------------------------------------------------
+Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2006.461 ; gain = 419.684 ; free physical = 5784 ; free virtual = 14790
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'ecgUnit' [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd:44]
+INFO: [Synth 8-638] synthesizing module 'fsm' [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd:48]
+INFO: [Synth 8-256] done synthesizing module 'fsm' (0#1) [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd:48]
+INFO: [Synth 8-638] synthesizing module 'OperativeUnit' [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd:57]
+INFO: [Synth 8-256] done synthesizing module 'OperativeUnit' (0#1) [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd:57]
+INFO: [Synth 8-256] done synthesizing module 'ecgUnit' (0#1) [/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd:44]
+---------------------------------------------------------------------------------
+Finished Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2085.430 ; gain = 498.652 ; free physical = 5690 ; free virtual = 14703
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2100.273 ; gain = 513.496 ; free physical = 5682 ; free virtual = 14800
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a12ticsg325-1L
+INFO: [Device 21-403] Loading part xc7a12ticsg325-1L
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2108.277 ; gain = 521.500 ; free physical = 5678 ; free virtual = 14796
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_present_reg' in module 'fsm'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00000000001 | 0000
+ store | 00000000010 | 0001
+ processing_loop_1 | 00000000100 | 0010
+ output_1 | 00000001000 | 0011
+ processing_loop_2 | 00000010000 | 0100
+ output_2 | 00000100000 | 0101
+ processing_loop_2b | 00001000000 | 0110
+ output_2b | 00010000000 | 0111
+ processing_loop_3 | 00100000000 | 1000
+ output | 01000000000 | 1001
+ wait_end_sample | 10000000000 | 1010
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_present_reg' using encoding 'one-hot' in module 'fsm'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2133.199 ; gain = 546.422 ; free physical = 5456 ; free virtual = 14942
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 11 Bit Adders := 1
+ 2 Input 7 Bit Adders := 1
++---Registers :
+ 29 Bit Registers := 1
+ 11 Bit Registers := 111
+ 7 Bit Registers := 1
++---Muxes :
+ 2 Input 29 Bit Muxes := 1
+ 11 Input 11 Bit Muxes := 1
+ 2 Input 11 Bit Muxes := 8
+ 3 Input 11 Bit Muxes := 1
+ 3 Input 10 Bit Muxes := 1
+ 2 Input 10 Bit Muxes := 1
+ 2 Input 7 Bit Muxes := 5
+ 4 Input 7 Bit Muxes := 1
+ 10 Input 2 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 5
+ 2 Input 1 Bit Muxes := 5
+ 4 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+INFO: [Device 21-9227] Part: xc7a12ticsg325-1L does not have CEAM library.
+Part Resources:
+DSPs: 40 (col length:40)
+BRAMs: 40 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+DSP Report: Generating DSP OpUnit/SC_addResult, operation Mode is: C+A*B.
+DSP Report: operator OpUnit/SC_addResult is absorbed into DSP OpUnit/SC_addResult.
+DSP Report: operator OpUnit/SC_MultResult is absorbed into DSP OpUnit/SC_addResult.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5010 ; free virtual = 14754
+---------------------------------------------------------------------------------
+ Sort Area is OpUnit/SC_addResult_0 : 0 0 : 1007 1007 : Used 1 time 0
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|OperativeUnit | C+A*B | 11 | 11 | 29 | - | 29 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5002 ; free virtual = 14753
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5002 ; free virtual = 14753
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5691 ; free virtual = 14730
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5683 ; free virtual = 14729
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5672 ; free virtual = 14747
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5670 ; free virtual = 14748
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+DSP Final Report (the ' indicates corresponding REG is set)
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+|OperativeUnit | C+A*B | 30 | 18 | 48 | - | 29 | 0 | 0 | 0 | - | - | 0 | 0 |
++--------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
+
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |BUFG | 1|
+|2 |CARRY4 | 3|
+|3 |DSP48E1 | 1|
+|4 |LUT2 | 12|
+|5 |LUT3 | 18|
+|6 |LUT4 | 75|
+|7 |LUT5 | 45|
+|8 |LUT6 | 390|
+|9 |MUXF7 | 88|
+|10 |MUXF8 | 33|
+|11 |FDCE | 1248|
+|12 |FDPE | 1|
+|13 |FDRE | 22|
+|14 |IBUF | 14|
+|15 |OBUF | 11|
++------+--------+------+
+
+Report Instance Areas:
++------+----------------+--------------+------+
+| |Instance |Module |Cells |
++------+----------------+--------------+------+
+|1 |top | | 1962|
+|2 | OpUnit |OperativeUnit | 1862|
+|3 | controlUnit_1 |fsm | 74|
++------+----------------+--------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.762 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2263.770 ; gain = 676.984 ; free physical = 5664 ; free virtual = 14746
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2263.977 ; gain = 0.000 ; free physical = 5705 ; free virtual = 15014
+INFO: [Netlist 29-17] Analyzing 125 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-101] Netlist 'ecgUnit' is not ideal for floorplanning, since the cellview 'OperativeUnit' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.609 ; gain = 0.000 ; free physical = 4897 ; free virtual = 15017
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: eb2b3431
+INFO: [Common 17-83] Releasing license: Synthesis
+25 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:26 . Memory (MB): peak = 2351.609 ; gain = 772.770 ; free physical = 4814 ; free virtual = 15018
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1899.163; main = 1595.578; forked = 399.589
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3323.309; main = 2351.613; forked = 1059.543
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2375.621 ; gain = 0.000 ; free physical = 5110 ; free virtual = 14773
+INFO: [Common 17-1381] The checkpoint '/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 26 10:40:10 2025...
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.sh b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..6f21c2dda8a57251d8a4b3633d99adc64e97f388
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.jou b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..fa7094d074dfedb5f4027e9f15bda3b7807f1ca8
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Mar 26 10:39:18 2025
+# Process ID: 57918
+# Current directory: /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1
+# Command line: vivado -log ecgUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
+# Log file: /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/ecgUnit.vds
+# Journal file: /homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-635
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3200.085 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :16873 MB
+#-----------------------------------------------------------
+source ecgUnit.tcl -notrace
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.pb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..83657dc0ae08c8b822d9ab6318c38ca621679de3
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.runs/synth_1/vivado.pb differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/compile.sh b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f83f51f3f56b67acbd6ae611420ae52fdbb9c3c2
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Mar 26 12:01:10 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_ecgUnit_vhdl.prj"
+xvhdl --incr --relax -prj tb_ecgUnit_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/ecgUnit.tcl b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/ecgUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/ecgUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/ecgUnit_behav.wdb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/ecgUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..4528724ed974bf487eb96ab0e31dd1ba63e2d964
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/ecgUnit_behav.wdb differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/elaborate.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000000000000000000000000000000000000..949ad3eaa5a66ecf5d31eb88ec77cdfd2e9dfc58
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,8 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/elaborate.sh b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b49c091427b88f5cad82bc9c4d2392cca81d16d3
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Mar 26 12:01:14 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit -log elaborate.log
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/simulate.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000000000000000000000000000000000000..3a14ee624a9f4bdaa2d11739bbf5670fa4d48b6c
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/simulate.sh b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e4d9d5b1001b26ec532b057b3588f7b54ee9d312
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Mar 26 11:59:33 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_ecgUnit_behav -key {Behavioral:sim_1:Functional:tb_ecgUnit} -tclbatch tb_ecgUnit.tcl -log simulate.log"
+xsim tb_ecgUnit_behav -key {Behavioral:sim_1:Functional:tb_ecgUnit} -tclbatch tb_ecgUnit.tcl -log simulate.log
+
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit.tcl b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit_behav.wdb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..5d74d2efe9160a948cdb8bef0592b33d61a69b6d
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit_behav.wdb differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit_vhdl.prj b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit_vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..02a4b77c686ad90effc7d37818bfb0e580e31082
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/tb_ecgUnit_vhdl.prj
@@ -0,0 +1,9 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd" \
+"../../../../ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd" \
+"../../../../ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd" \
+"../../../../ecg-POIRIER-OLLIVIER.srcs/sim_1/new/tb_ecgUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xelab.pb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..f69ce9b22f2398d00c579c1790c97f66ae5631ac
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/Compile_Options.txt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..170a0b6eafb6190ab84dffdd19f4fc2f5a4725d3
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "ecgUnit_behav" "xil_defaultlib.ecgUnit" -log "elaborate.log"
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/TempBreakPointFile.txt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_0.lnx64.o b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..7f0ba0fe4a592d2f563ec5aa077be6b612c8bbcb
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_1.c b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..ce5caa5d3a3f08f09ef68a3c939676b22a66af43
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_1.c
@@ -0,0 +1,127 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_31(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_35(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[21] = {(funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 21;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/ecgUnit_behav/xsim.reloc", (void **)funcTab, 21);
+ iki_vhdl_file_variable_register(dp + 13456);
+ iki_vhdl_file_variable_register(dp + 13512);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/ecgUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/ecgUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/ecgUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/ecgUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/ecgUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_1.lnx64.o b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..c8f78529e2164a6232c22a14900416b99935c5e9
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/obj/xsim_1.lnx64.o differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.dbg b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..75ac4a00c95afedaff7686ec2ea87130935d243a
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.mem b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..ea4f227506adab230a069c76e1a68b40815a9b83
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.mem differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.reloc b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..b424483ca01741e8d6e02cb2227618e4f1c9b447
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.reloc differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.rlx b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..b8ebaf57e85f9eb657201d07cd8a9b3119ff2645
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 17174070369012999326 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot ecgUnit_behav xil_defaultlib.ecgUnit" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/ecgUnit_behav/xsimk\" \"xsim.dir/ecgUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/ecgUnit_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.rtti b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..1d94fa60f99ebdd96f3cde46e12a7c39bfeec44f
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.rtti differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.svtype b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..6dc1deb65a85fafe2dcea36f677983510a180e28
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.svtype differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.type b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..302071773db918003980e34d46a20308147d3cd1
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.xdbg b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..55e9f0b421389f11e3bab199ba19457aef5bbef6
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsim.xdbg differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimSettings.ini b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..73d11a6942a6e5ebaba0150ef71424c4156ffeaa
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=144
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=213
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
+OBJECT_NAME_COLUMN_WIDTH=188
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimcrash.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimk b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..5aa815d6733be7e3f43414fa479f36535050a52c
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimk differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimkernel.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..2b0aa14933309d34a9c5bbcd9ad99ed886faec75
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/ecgUnit_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/ecgUnit_behav/xsimk -simmode gui -wdb ecgUnit_behav.wdb -simrunnum 0 -socket 58731
+Design successfully loaded
+Design Loading Memory Usage: 20184 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 40 ms
+Simulation completed
+Simulation Memory Usage: 110120 KB (Peak: 159452 KB)
+Simulation CPU Usage: 50 ms
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/Compile_Options.txt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2b3d98baafcec006e01c101eee1236b4c600847b
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ecgUnit_behav" "xil_defaultlib.tb_ecgUnit" -log "elaborate.log"
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/TempBreakPointFile.txt b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..d2c3ff19c23ba62b578ac71471c62b8c19a0d5c2
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.c b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..51c6329ad8a28a92a2f9c954a570042ca4fefb9c
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.c
@@ -0,0 +1,131 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[25] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 25;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_ecgUnit_behav/xsim.reloc", (void **)funcTab, 25);
+ iki_vhdl_file_variable_register(dp + 13960);
+ iki_vhdl_file_variable_register(dp + 14016);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_ecgUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ecgUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_ecgUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_ecgUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_ecgUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.lnx64.o b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..e95fa7bde05fbc7cb5fbb82dfae3abbce0c9df8b
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.dbg b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.dbg
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index 0000000000000000000000000000000000000000..c1387abd439c5abdfa89732548381648ae777429
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.mem b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.mem
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index 0000000000000000000000000000000000000000..5e05121adaca2631b363daab99306556f46c26a6
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.reloc b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..0c70e59578396b768dfeed54e4d2dc7b65e64db0
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.reloc differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rlx b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..2e64de85aa22d8b0a3aa0b34085041212a2da3f8
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 5992506463090196062 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_ecgUnit_behav/xsimk\" \"xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_ecgUnit_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rtti b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rtti
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.svtype b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.svtype
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index 0000000000000000000000000000000000000000..6dc1deb65a85fafe2dcea36f677983510a180e28
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.type b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.type
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.xdbg b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.xdbg
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index 0000000000000000000000000000000000000000..7eb1c62dca139ba337bacb8516bac7ee2c3c5e5d
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimSettings.ini b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..15c5331be420060504f3add716f20a66b92a7fb1
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=125
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=178
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
+OBJECT_NAME_COLUMN_WIDTH=188
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimcrash.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimk b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimk
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index 0000000000000000000000000000000000000000..018f4d301864f73f83eadd3e1fb34d66b1add0b4
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimkernel.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..7f8e2e822e1ad2d739c1cef33abce7277bfceb4d
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/tb_ecgUnit_behav/xsimk -simmode gui -wdb tb_ecgUnit_behav.wdb -simrunnum 0 -socket 36491
+Design successfully loaded
+Design Loading Memory Usage: 20188 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 40 ms
+Simulation completed
+Simulation Memory Usage: 110124 KB (Peak: 159456 KB)
+Simulation CPU Usage: 50 ms
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ecgunit.vdb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ecgunit.vdb
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index 0000000000000000000000000000000000000000..a430d3d54b69c9cd9585cd5c8da41ffe0ef4b4bb
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diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..e014d76d353f0aab7190fb8cc05a252c79afac12
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,8 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sim_1/new/tb_ecgUnit.vhd,1742986758,vhdl,,,,tb_ecgunit,,,,,,,,
+/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd,1742983392,vhdl,/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd,,,operativeunit,,,,,,,,
+/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd,1742979155,vhdl,/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sim_1/new/tb_ecgUnit.vhd,,,ecgunit,,,,,,,,
+/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd,1742984917,vhdl,/homes/a22olliv/Documents/MEDCON/tp-ecg-etudiant-a22olliv/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd,,,fsm,,,,,,,,
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.ini b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..e8199b2597fb201d9f6673368b7b003f11b596e4
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xvhdl.log b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xvhdl.pb b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b155e40f06a230303a04d2a77f07560e35c5dc93
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.sim/sim_1/behav/xsim/xvhdl.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sim_1/new/tb_ecgUnit.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sim_1/new/tb_ecgUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c5ee6d3ffcd42ed8d56f4da4ff78ed9072720fc8
--- /dev/null
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sim_1/new/tb_ecgUnit.vhd
@@ -0,0 +1,115 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03/26/2025 09:54:33 AM
+-- Design Name:
+-- Module Name: tb_ecgUnit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity tb_ecgUnit is
+-- Port ( );
+end tb_ecgUnit;
+
+architecture Behavioral of tb_ecgUnit is
+
+begin
+
+
+end Behavioral;
+
+
+-------------------------------------------------------------------------------
+-- Title : FirUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-26
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-- 2018-04-18 1.1 marzel Modified to add more test inputs
+-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_ecgUnit is
+end entity tb_ecgUnit;
+
+architecture archi_tb_ecgUnit of tb_ecgUnit is
+ component ecgUnit is
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(10 downto 0) -- filtered sample
+ );
+ end component ecgUnit;
+
+ signal SC_clock : std_logic := '0';
+ signal SC_reset : std_logic;
+ signal SC_inputSample : std_logic_vector(10 downto 0);
+ signal SC_inputSampleValid : std_logic:='0';
+ signal SC_filteredSample : std_logic_vector(10 downto 0);
+ signal SC_filteredSampleValid : std_logic;
+
+begin
+
+ SC_clock <= not SC_clock after 5 ns;
+ SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
+
+ -- Sample period = 20 clk period
+ SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
+
+ -- Null signal followed by a Dirac and then an arbitrary sequence
+SC_inputSample <= std_logic_vector(to_signed(-17,11)), -- -17
+ std_logic_vector(to_signed(-16,11)) after 1295 ns, -- -16
+ std_logic_vector(to_signed(-14,11)) after 2695 ns; -- -14
+
+
+
+
+ ecgUnit_1 : entity work.ecgUnit
+ port map (
+ I_clock => SC_clock,
+ I_reset => SC_reset,
+ I_inputSample => SC_inputSample,
+ I_inputSampleValid => SC_inputSampleValid,
+ O_filteredSample => SC_filteredSample
+ );
+end architecture archi_tb_ecgUnit;
\ No newline at end of file
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd
index 379a3e15d24ff7430ae42894027aa2c1ec789a0e..e53f5944c35858bddd9365297198b79181b81d9b 100644
--- a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/OperativeUnit.vhd
@@ -34,7 +34,7 @@ entity OperativeUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(9 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(10 downto 0); --
I_loadShift1 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_loadShift2 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_loadShift3 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
@@ -49,7 +49,7 @@ entity OperativeUnit is
O_processingDone2 : out std_logic; -- Indicate that processing is done
O_processingDone2b : out std_logic; -- Indicate that processing is done
O_processingDone3 : out std_logic; -- Indicate that processing is done
- O_Y : out std_logic_vector(9 downto 0) -- filtered sample
+ O_Y : out std_logic_vector(10 downto 0) -- filtered sample
);
end entity OperativeUnit;
@@ -68,12 +68,12 @@ architecture arch_OperativeUnit of OperativeUnit is
signal SR_shiftRegister1 : registerFile95; -- shift register file used to store and shift input samples
signal SR_shiftRegister2 : registerFile3; -- shift register file used to store and shift input samples
signal SR_shiftRegister3 : registerFile11; -- shift register file used to store and shift input samples
- signal SC_multOperand1 : signed(9 downto 0);
+ signal SC_multOperand1 : signed(10 downto 0);
signal SC_multOperand2 : signed(10 downto 0);
- signal SC_MultResult : signed(20 downto 0); -- Result of the multiplication Xi*Hi
- signal SC_addResult : signed(27 downto 0); -- result of the accumulation addition
- signal SR_sum : signed(27 downto 0); -- Accumulation register
- signal SR_Y : signed(9 downto 0); -- filtered sample storage register
+ signal SC_MultResult : signed(21 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(28 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(28 downto 0); -- Accumulation register
+ signal SR_Y : signed(10 downto 0); -- filtered sample storage register
signal SR_readAddress : integer range 0 to 94; -- register files read address
-- DIMENSIONNEMENT !!!
@@ -82,54 +82,101 @@ begin
-- Low-pass filter provided with octave (or Matlab ;)) command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
- SR_coefRegister1 <= (to_signed(-1, 11), -- ROM register used file to store FIR coefficients
- to_signed(-1, 11),
- to_signed(-1, 11),
- to_signed(-1, 11),
- to_signed(-1, 11),
- to_signed(-1, 11),
- to_signed(-2, 11),
- to_signed(-2, 11),
- to_signed(-2, 11),
- to_signed(-3, 11),
- to_signed(-3, 11),
- to_signed(-3, 11),
- to_signed(-4, 11),
- to_signed(-4, 11),
- to_signed(-5, 11),
- to_signed(-5, 11),
- to_signed(-6, 11),
- to_signed(-6, 11),
- to_signed(-7, 11),
- to_signed(-7, 11),
- to_signed(-8, 11),
- to_signed(-8, 11),
- to_signed(-9, 11),
- to_signed(-10, 11),
- to_signed(-10, 11),
- to_signed(-11, 11),
- to_signed(-11, 11),
- to_signed(-12, 11),
- to_signed(-13, 11),
- to_signed(-13, 11),
- to_signed(-14, 11),
- to_signed(-14, 11),
- to_signed(-15, 11),
- to_signed(-15, 11),
- to_signed(-16, 11),
- to_signed(-16, 11),
- to_signed(-17, 11),
- to_signed(-17, 11),
- to_signed(-18, 11),
- to_signed(-18, 11),
- to_signed(-18, 11),
- to_signed(-19, 11),
- to_signed(-19, 11),
- to_signed(-19, 11),
- to_signed(-19, 11),
- to_signed(-19, 11),
- to_signed(-19, 11),
- to_signed(1004, 11)
+ SR_coefRegister1 <= (to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-4, 11),
+ to_signed(-4, 11),
+ to_signed(-5, 11),
+ to_signed(-5, 11),
+ to_signed(-6, 11),
+ to_signed(-6, 11),
+ to_signed(-7, 11),
+ to_signed(-7, 11),
+ to_signed(-8, 11),
+ to_signed(-8, 11),
+ to_signed(-9, 11),
+ to_signed(-10, 11),
+ to_signed(-10, 11),
+ to_signed(-11, 11),
+ to_signed(-11, 11),
+ to_signed(-12, 11),
+ to_signed(-13, 11),
+ to_signed(-13, 11),
+ to_signed(-14, 11),
+ to_signed(-14, 11),
+ to_signed(-15, 11),
+ to_signed(-15, 11),
+ to_signed(-16, 11),
+ to_signed(-16, 11),
+ to_signed(-17, 11),
+ to_signed(-17, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(1004, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-17, 11),
+ to_signed(-17, 11),
+ to_signed(-16, 11),
+ to_signed(-16, 11),
+ to_signed(-15, 11),
+ to_signed(-15, 11),
+ to_signed(-14, 11),
+ to_signed(-14, 11),
+ to_signed(-13, 11),
+ to_signed(-13, 11),
+ to_signed(-12, 11),
+ to_signed(-11, 11),
+ to_signed(-11, 11),
+ to_signed(-10, 11),
+ to_signed(-10, 11),
+ to_signed(-9, 11),
+ to_signed(-8, 11),
+ to_signed(-8, 11),
+ to_signed(-7, 11),
+ to_signed(-7, 11),
+ to_signed(-6, 11),
+ to_signed(-6, 11),
+ to_signed(-5, 11),
+ to_signed(-5, 11),
+ to_signed(-4, 11),
+ to_signed(-4, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11)
);
SR_coefRegister2 <= (to_signed(961, 11), -- ROM register used file to store FIR coefficients
@@ -146,7 +193,12 @@ begin
to_signed(149, 11),
to_signed(191, 11),
to_signed(226, 11),
- to_signed(239, 11)
+ to_signed(239, 11),
+ to_signed(226,11),
+ to_signed(191, 11),
+ to_signed(149,11),
+ to_signed(122,11),
+ to_signed(-119,11)
);
@@ -183,18 +235,26 @@ begin
if (I_Filter = "00") then
if (SR_readAddress < 94) then
SR_readAddress <= SR_readAddress + 1;
+ else
+ SR_readAddress <= 0;
end if;
elsif (I_Filter = "01") then
if (SR_readAddress < 2) then
SR_readAddress <= SR_readAddress + 1;
+ else
+ SR_readAddress <= 0;
end if;
elsif (I_Filter = "10") then
if (SR_readAddress < 1) then
SR_readAddress <= SR_readAddress + 1;
+ else
+ SR_readAddress <= 0;
end if;
else
if (SR_readAddress < 10) then
SR_readAddress <= SR_readAddress + 1;
+ else
+ SR_readAddress <= 0;
end if;
end if;
@@ -229,12 +289,11 @@ begin
begin
if (rising_edge(I_clock)) then
if (I_loadY='1') then
--- if(SR_sum(6)='1') then
--- SR_Y <= SR_sum(14 downto 7) + 1;
--- else
--- SR_Y <= SR_sum(14 downto 7);
--- end if;
- SR_Y <= SR_sum;
+ if(SR_sum(10)='1') then
+ SR_Y <= SR_sum(21 downto 11) + 1;
+ else
+ SR_Y <= SR_sum(21 downto 11);
+ end if;
end if;
if (I_FilteredSampleDone = '1') then
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd
index 9a5c9a581dcebc2080c21791b92cf12f26fd97ca..31a70644bcde9a0a00f6f226ac488e69cb34a0e7 100644
--- a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/ecgUnit.vhd
@@ -35,10 +35,9 @@ entity ecgUnit is
port(
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(9 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(9 downto 0); -- filtered sample
- O_filteredSampleValid : out std_logic
+ O_filteredSample : out std_logic_vector(10 downto 0) -- filtered sample
);
end ecgUnit;
@@ -141,12 +140,12 @@ OpUnit : entity work.OperativeUnit
I_loadSum => SC_loadSum,
I_loadY => SC_loadY,
I_Filter => SC_Filter,
- I_FilteredSampleDone
- O_processingDone1
- O_processingDone2
- O_processingDone2b
- O_processingDone3
- O_Y
+ I_FilteredSampleDone => SC_FilteredSampleDone,
+ O_processingDone1 => SC_ProcessingDone1,
+ O_processingDone2 => SC_ProcessingDone2,
+ O_processingDone2b => SC_ProcessingDone2b,
+ O_processingDone3 => SC_ProcessingDone3,
+ O_Y => O_filteredSample
);
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd
index 5d7212aebea7880388547a49722cd6f0e7de54da..375f47df15fd5478fb1ac9f2db58b07f2419661b 100644
--- a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/sources_1/new/fsm.vhd
@@ -41,13 +41,14 @@ entity fsm is
O_loadSum : out std_logic;
O_loadOutput : out std_logic;
O_filter : out std_logic_vector(1 downto 0);
- O_FilteredSampleDone : in std_logic
+ O_FilteredSampleDone : out std_logic
);
end entity fsm;
architecture a_fsm of fsm is
- type T_State is (WAIT_SAMPLE, STORE, PROCESSING_LOOP_1, OUTPUT_1, PROCESSING_LOOP_2, OUTPUT_2, PROCESSING_LOOP_2b, OUTPUT_2b, PROCESSING_LOOP_3, OUTPUT, WAIT_END_SAMPLE);
+ type T_State is (WAIT_SAMPLE, STORE, PROCESSING_LOOP_1, OUTPUT_1, STORE1, PROCESSING_LOOP_2, OUTPUT_2, STORE2, PROCESSING_LOOP_2b, OUTPUT_2b, STORE2b,PROCESSING_LOOP_3, OUTPUT, WAIT_END_SAMPLE);
+
signal SR_present : T_State;
signal SC_futur : T_State;
@@ -85,6 +86,9 @@ begin
end if;
when OUTPUT_1 =>
+ SC_futur <= STORE1;
+
+ when STORE1 =>
SC_futur <= PROCESSING_LOOP_2;
when PROCESSING_LOOP_2 =>
@@ -95,6 +99,9 @@ begin
end if;
when OUTPUT_2 =>
+ SC_futur <= STORE2;
+
+ when STORE2 =>
SC_futur <= PROCESSING_LOOP_2b;
when PROCESSING_LOOP_2b =>
@@ -105,6 +112,9 @@ begin
end if;
when OUTPUT_2b =>
+ SC_futur <= STORE2b;
+
+ when STORE2b =>
SC_futur <= PROCESSING_LOOP_3;
when PROCESSING_LOOP_3 =>
@@ -158,10 +168,12 @@ begin
O_filter <= "00";
when OUTPUT_1 =>
+ O_loadOutput <= '1';
+
+ when STORE1 =>
O_loadShift2 <= '1';
- O_initAddress <= '1';
+ O_initAddress <= '1';
O_initSum <= '1';
- O_loadOutput <= '1';
O_filter <= "01";
when PROCESSING_LOOP_2 =>
@@ -170,9 +182,12 @@ begin
O_filter <= "01";
when OUTPUT_2 =>
+ O_loadOutput <= '1';
+
+ when STORE2 =>
O_loadShift3 <= '1';
- O_initAddress <= '1';
- O_loadOutput <= '1';
+ O_initAddress <= '1';
+ O_initSum <= '1';
O_filter <= "10";
when PROCESSING_LOOP_2b =>
@@ -181,10 +196,11 @@ begin
O_filter <= "10";
when OUTPUT_2b =>
- O_loadShift3 <= '1';
+ O_loadOutput <= '1';
+
+ when STORE2b =>
O_initAddress <= '1';
O_initSum <= '1';
- O_loadOutput <= '1';
O_filter <= "11";
when PROCESSING_LOOP_3 =>
@@ -194,7 +210,19 @@ begin
when OUTPUT =>
O_FilteredSampleDone <= '1';
- O_filter <= "11";
+ O_filter <= "11";
+
+ when others =>
+ O_loadShift1 <= '0';
+ O_loadShift2 <= '0';
+ O_loadShift3 <= '0';
+ O_initAddress <= '0';
+ O_incrAddress <= '0';
+ O_initSum <= '0';
+ O_loadSum <= '0';
+ O_loadOutput <= '0';
+ O_filter <= "00";
+ O_FilteredSampleDone <= '0';
end case;
end process;
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp
new file mode 100755
index 0000000000000000000000000000000000000000..3860a8a97002bf7cca63fc42f38f1d504500dfb0
Binary files /dev/null and b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.srcs/utils_1/imports/synth_1/ecgUnit.dcp differ
diff --git a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr
index d50b96287441e120976c606803ac19222bea6aa5..fd0550756cc8c36f3964c3c812f2f06f6a8498a5 100644
--- a/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr
+++ b/ecg-POIRIER-OLLIVIER/ecg-POIRIER-OLLIVIER.xpr
@@ -58,7 +58,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTXSimLaunchSim" Val="46"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -120,10 +120,18 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sim_1/new/tb_ecgUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="ecgUnit"/>
+ <Option Name="TopModule" Val="tb_ecgUnit"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopArchitecture" Val="archi_tb_ecgUnit"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@@ -137,6 +145,14 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/ecgUnit.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@@ -164,22 +180,19 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ecgUnit.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
- <Desc>Default settings for Implementation.</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>