diff --git a/proj/proj.cache/wt/project.wpc b/proj/proj.cache/wt/project.wpc
index de67d9ce23793f8584f54b90c2cdeadf8114ad0a..2599f423253c09ec78d9135689798dbecf72df68 100644
--- a/proj/proj.cache/wt/project.wpc
+++ b/proj/proj.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:3
+6d6f64655f636f756e7465727c4755494d6f6465:7
 eof:
diff --git a/proj/proj.cache/wt/synthesis.wdf b/proj/proj.cache/wt/synthesis.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..050133441fcbaaab0041ccb08d90261add1cae0b
--- /dev/null
+++ b/proj/proj.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303230636c673438342d31:00:00
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+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323430302e3133334d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3731352e3537384d42:00:00
+eof:2126513422
diff --git a/proj/proj.cache/wt/synthesis_details.wdf b/proj/proj.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/proj/proj.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/proj/proj.runs/.jobs/vrs_config_1.xml b/proj/proj.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0621275c2f89ff8c8fa6e739c6b18fb66a7bac9c
--- /dev/null
+++ b/proj/proj.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/proj.runs/synth_1/.Vivado_Synthesis.queue.rst b/proj/proj.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/proj.runs/synth_1/.vivado.begin.rst b/proj/proj.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..a423b8991930e3f9758c144bd4da30283a84d276
--- /dev/null
+++ b/proj/proj.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado" Owner="a23aboul" Host="fl-tp-br-104" Pid="74769" HostCore="12" HostMemory="16040124">
+    </Process>
+</ProcessHandle>
diff --git a/proj/proj.runs/synth_1/.vivado.end.rst b/proj/proj.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/proj.runs/synth_1/ISEWrap.js b/proj/proj.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/proj.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
+//  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/proj/proj.runs/synth_1/ISEWrap.sh b/proj/proj.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/proj.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
+#  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/proj.runs/synth_1/__synthesis_is_complete__ b/proj/proj.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/proj.runs/synth_1/ecgUnit.dcp b/proj/proj.runs/synth_1/ecgUnit.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..36b2cbf1281d1ca2c3ce7c7bb98f337a38eb8e1c
Binary files /dev/null and b/proj/proj.runs/synth_1/ecgUnit.dcp differ
diff --git a/proj/proj.runs/synth_1/ecgUnit.tcl b/proj/proj.runs/synth_1/ecgUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6ca0b713d13cec628e06266fce2840b4c7aaeebc
--- /dev/null
+++ b/proj/proj.runs/synth_1/ecgUnit.tcl
@@ -0,0 +1,109 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+namespace eval ::optrace {
+  variable script "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/ecgUnit.tcl"
+  variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7z020clg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.cache/wt [current_project]
+set_property parent.project_path /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property board_part avnet.com:zedboard:part0:1.4 [current_project]
+set_property ip_output_repo /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib {
+  /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd
+  /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd
+  /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl
+}
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top ecgUnit -part xc7z020clg484-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef ecgUnit.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb"  } 
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/proj/proj.runs/synth_1/ecgUnit.vds b/proj/proj.runs/synth_1/ecgUnit.vds
new file mode 100644
index 0000000000000000000000000000000000000000..7741495002f58c5caf1b570e76c6ac7aa220e9bf
--- /dev/null
+++ b/proj/proj.runs/synth_1/ecgUnit.vds
@@ -0,0 +1,260 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar 25 17:37:19 2025
+# Process ID: 74841
+# Current directory: /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1
+# Command line: vivado -log ecgUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
+# Log file: /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/ecgUnit.vds
+# Journal file: /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/vivado.jou
+# Running On        :fl-tp-br-104
+# Platform          :Ubuntu
+# Operating System  :Ubuntu 24.04.2 LTS
+# Processor Detail  :12th Gen Intel(R) Core(TM) i5-12500
+# CPU Frequency     :1511.163 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory       :16425 MB
+# Swap memory       :4294 MB
+# Total Virtual     :20720 MB
+# Available Virtual :15733 MB
+#-----------------------------------------------------------
+source ecgUnit.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 4328 ; free virtual = 14423
+Command: synth_design -top ecgUnit -part xc7z020clg484-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 75043
+---------------------------------------------------------------------------------
+Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2112.207 ; gain = 427.652 ; free physical = 3579 ; free virtual = 13672
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'ecgUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl:23]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:31]
+WARNING: [Synth 8-614] signal 'SR_presentState' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:49]
+WARNING: [Synth 8-614] signal 'I_inputSampleValid' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:49]
+WARNING: [Synth 8-614] signal 'I_processingDone' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:49]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:31]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:31]
+WARNING: [Synth 8-614] signal 'SR_shiftRegister1' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister1' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_shiftRegister2' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister2' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_shiftRegister3' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister3' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister4' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:31]
+INFO: [Synth 8-256] done synthesizing module 'ecgUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl:23]
+---------------------------------------------------------------------------------
+Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2192.176 ; gain = 507.621 ; free physical = 3482 ; free virtual = 13577
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2207.020 ; gain = 522.465 ; free physical = 3479 ; free virtual = 13575
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z020clg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2215.023 ; gain = 530.469 ; free physical = 3479 ; free virtual = 13575
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:45]
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:45]
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+             wait_sample |                      00001000000 |                             0000
+                  store1 |                      00010000000 |                             0001
+        processing_loop1 |                      00000000001 |                             0100
+                  store2 |                      00000000010 |                             0010
+        processing_loop2 |                      00000010000 |                             0101
+               inter_iir |                      01000000000 |                             1000
+        processing_loop3 |                      10000000000 |                             0110
+                  store3 |                      00000000100 |                             0011
+        processing_loop4 |                      00000001000 |                             0111
+                  output |                      00100000000 |                             1001
+         wait_end_sample |                      00000100000 |                             1010
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:45]
+WARNING: [Synth 8-327] inferring latch for variable 'O_cntrMux_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:54]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2232.836 ; gain = 548.281 ; free physical = 3445 ; free virtual = 13542
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input    8 Bit       Adders := 1     
+	   2 Input    4 Bit       Adders := 1     
++---Registers : 
+	               20 Bit    Registers := 1     
+	                8 Bit    Registers := 49    
+	                4 Bit    Registers := 1     
++---Muxes : 
+	   2 Input   20 Bit        Muxes := 1     
+	  11 Input   11 Bit        Muxes := 1     
+	   2 Input   11 Bit        Muxes := 6     
+	   4 Input    8 Bit        Muxes := 1     
+	  16 Input    5 Bit        Muxes := 1     
+	  11 Input    4 Bit        Muxes := 1     
+	   2 Input    4 Bit        Muxes := 2     
+	  11 Input    2 Bit        Muxes := 1     
+	  11 Input    1 Bit        Muxes := 3     
+	   2 Input    1 Bit        Muxes := 3     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+INFO: [Device 21-9227] Part: xc7z020clg484-1 does not have CEAM library.
+Part Resources:
+DSPs: 220 (col length:60)
+BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2394.188 ; gain = 709.633 ; free physical = 3273 ; free virtual = 13379
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3275 ; free virtual = 13382
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3275 ; free virtual = 13382
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     1|
+|2     |CARRY4 |    13|
+|3     |LUT2   |    10|
+|4     |LUT3   |     8|
+|5     |LUT4   |    28|
+|6     |LUT5   |    44|
+|7     |LUT6   |   143|
+|8     |MUXF7  |    48|
+|9     |MUXF8  |    24|
+|10    |FDCE   |   421|
+|11    |FDPE   |     1|
+|12    |LD     |    13|
+|13    |IBUF   |    11|
+|14    |OBUF   |     9|
++------+-------+------+
+
+Report Instance Areas: 
++------+------------------+--------------+------+
+|      |Instance          |Module        |Cells |
++------+------------------+--------------+------+
+|1     |top               |              |   774|
+|2     |  controlUnit_1   |controlUnit   |    69|
+|3     |  operativeUnit_1 |operativeUnit |   684|
++------+------------------+--------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 15 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.133 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2411.055 ; gain = 0.000 ; free physical = 3576 ; free virtual = 13673
+INFO: [Netlist 29-17] Analyzing 98 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.832 ; gain = 0.000 ; free physical = 3446 ; free virtual = 13632
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 13 instances were transformed.
+  LD => LDCE: 13 instances
+
+Synth Design complete | Checksum: 180e514
+INFO: [Common 17-83] Releasing license: Synthesis
+21 Infos, 15 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:23 . Memory (MB): peak = 2530.832 ; gain = 850.246 ; free physical = 3446 ; free virtual = 13632
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2027.500; main = 1749.055; forked = 398.951
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3460.230; main = 2530.836; forked = 1060.102
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2554.844 ; gain = 0.000 ; free physical = 3446 ; free virtual = 13632
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/ecgUnit.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 25 17:38:28 2025...
diff --git a/proj/proj.runs/synth_1/ecgUnit_utilization_synth.pb b/proj/proj.runs/synth_1/ecgUnit_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..09a1d260e6ef4e8be935fbd04cbedd735c4760f6
Binary files /dev/null and b/proj/proj.runs/synth_1/ecgUnit_utilization_synth.pb differ
diff --git a/proj/proj.runs/synth_1/ecgUnit_utilization_synth.rpt b/proj/proj.runs/synth_1/ecgUnit_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..70e5ecf3e9788f1712a4557e8b143bcbfc358e11
--- /dev/null
+++ b/proj/proj.runs/synth_1/ecgUnit_utilization_synth.rpt
@@ -0,0 +1,184 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date         : Tue Mar 25 17:38:28 2025
+| Host         : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command      : report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb
+| Design       : ecgUnit
+| Device       : xc7z020clg484-1
+| Speed File   : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs*             |  204 |     0 |          0 |     53200 |  0.38 |
+|   LUT as Logic          |  204 |     0 |          0 |     53200 |  0.38 |
+|   LUT as Memory         |    0 |     0 |          0 |     17400 |  0.00 |
+| Slice Registers         |  435 |     0 |          0 |    106400 |  0.41 |
+|   Register as Flip Flop |  422 |     0 |          0 |    106400 |  0.40 |
+|   Register as Latch     |   13 |     0 |          0 |    106400 |  0.01 |
+| F7 Muxes                |   48 |     0 |          0 |     26600 |  0.18 |
+| F8 Muxes                |   24 |     0 |          0 |     13300 |  0.18 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 1     |          Yes |           - |          Set |
+| 434   |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 0     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |       140 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |       140 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       280 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |       220 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   20 |     0 |          0 |       200 | 10.00 |
+| Bonded IPADs                |    0 |     0 |          0 |         2 |  0.00 |
+| Bonded IOPADs               |    0 |     0 |          0 |       130 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         4 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         4 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        16 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        16 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         4 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |       192 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        16 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        16 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       200 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       200 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       200 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
+| BUFIO      |    0 |     0 |          0 |        16 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         4 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         4 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |         8 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        72 |  0.00 |
+| BUFR       |    0 |     0 |          0 |        16 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE     |  421 |        Flop & Latch |
+| LUT6     |  143 |                 LUT |
+| MUXF7    |   48 |               MuxFx |
+| LUT5     |   44 |                 LUT |
+| LUT4     |   28 |                 LUT |
+| MUXF8    |   24 |               MuxFx |
+| LDCE     |   13 |        Flop & Latch |
+| CARRY4   |   13 |          CarryLogic |
+| IBUF     |   11 |                  IO |
+| LUT2     |   10 |                 LUT |
+| OBUF     |    9 |                  IO |
+| LUT3     |    8 |                 LUT |
+| FDPE     |    1 |        Flop & Latch |
+| BUFG     |    1 |               Clock |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/proj.runs/synth_1/gen_run.xml b/proj/proj.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a30f4c560a969a3d62cca956d2c192f483916ad7
--- /dev/null
+++ b/proj/proj.runs/synth_1/gen_run.xml
@@ -0,0 +1,56 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7z020clg484-1" LaunchTime="1742920636">
+  <File Type="VDS-TIMINGSUMMARY" Name="ecgUnit_timing_summary_synth.rpt"/>
+  <File Type="RDS-DCP" Name="ecgUnit.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="ecgUnit_utilization_synth.pb"/>
+  <File Type="RDS-UTIL" Name="ecgUnit_utilization_synth.rpt"/>
+  <File Type="RDS-PROPCONSTRS" Name="ecgUnit_drc_synth.rpt"/>
+  <File Type="RDS-RDS" Name="ecgUnit.vds"/>
+  <File Type="REPORTS-TCL" Name="ecgUnit_reports.tcl"/>
+  <File Type="VDS-TIMING-PB" Name="ecgUnit_timing_summary_synth.pb"/>
+  <File Type="PA-TCL" Name="ecgUnit.tcl"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/hdl/ecgUnit.vhdl">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../src/hdl/ecgUnit.vhdl"/>
+        <Attr Name="ImportTime" Val="1742920067"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="ecgUnit"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
diff --git a/proj/proj.runs/synth_1/htr.txt b/proj/proj.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..3899de31fa9294996d374c7468b51202b1f7ad77
--- /dev/null
+++ b/proj/proj.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+#          the basic steps of a run.  Note that runme.bat/sh needs
+#          to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
diff --git a/proj/proj.runs/synth_1/project.wdf b/proj/proj.runs/synth_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..a3e3ef4d4512e57c1fd25e8d09a2df341daf2f07
--- /dev/null
+++ b/proj/proj.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00
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+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6638333533666134313436623437323661333866313835343032393465663463:506172656e742050412070726f6a656374204944:00
+eof:3533762494
diff --git a/proj/proj.runs/synth_1/rundef.js b/proj/proj.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..7d2be323b5ac44046374105757468be8eb61097b
--- /dev/null
+++ b/proj/proj.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;";
+} else {
+  PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/proj/proj.runs/synth_1/runme.bat b/proj/proj.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/proj.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem  Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/proj.runs/synth_1/runme.log b/proj/proj.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..bcf04697658589e81b395edfd34d67d871aec390
--- /dev/null
+++ b/proj/proj.runs/synth_1/runme.log
@@ -0,0 +1,250 @@
+
+*** Running vivado
+    with args -log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+  **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+  **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+  **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+  **** Start of session at: Tue Mar 25 17:37:19 2025
+    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source ecgUnit.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 4328 ; free virtual = 14423
+Command: synth_design -top ecgUnit -part xc7z020clg484-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 75043
+---------------------------------------------------------------------------------
+Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2112.207 ; gain = 427.652 ; free physical = 3579 ; free virtual = 13672
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'ecgUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl:23]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:31]
+WARNING: [Synth 8-614] signal 'SR_presentState' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:49]
+WARNING: [Synth 8-614] signal 'I_inputSampleValid' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:49]
+WARNING: [Synth 8-614] signal 'I_processingDone' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:49]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:31]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:31]
+WARNING: [Synth 8-614] signal 'SR_shiftRegister1' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister1' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_shiftRegister2' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister2' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_shiftRegister3' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister3' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+WARNING: [Synth 8-614] signal 'SR_coefRegister4' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:200]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd:31]
+INFO: [Synth 8-256] done synthesizing module 'ecgUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl:23]
+---------------------------------------------------------------------------------
+Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2192.176 ; gain = 507.621 ; free physical = 3482 ; free virtual = 13577
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2207.020 ; gain = 522.465 ; free physical = 3479 ; free virtual = 13575
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z020clg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2215.023 ; gain = 530.469 ; free physical = 3479 ; free virtual = 13575
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:45]
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:45]
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+             wait_sample |                      00001000000 |                             0000
+                  store1 |                      00010000000 |                             0001
+        processing_loop1 |                      00000000001 |                             0100
+                  store2 |                      00000000010 |                             0010
+        processing_loop2 |                      00000010000 |                             0101
+               inter_iir |                      01000000000 |                             1000
+        processing_loop3 |                      10000000000 |                             0110
+                  store3 |                      00000000100 |                             0011
+        processing_loop4 |                      00000001000 |                             0111
+                  output |                      00100000000 |                             1001
+         wait_end_sample |                      00000100000 |                             1010
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:45]
+WARNING: [Synth 8-327] inferring latch for variable 'O_cntrMux_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd:54]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2232.836 ; gain = 548.281 ; free physical = 3445 ; free virtual = 13542
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input    8 Bit       Adders := 1     
+	   2 Input    4 Bit       Adders := 1     
++---Registers : 
+	               20 Bit    Registers := 1     
+	                8 Bit    Registers := 49    
+	                4 Bit    Registers := 1     
++---Muxes : 
+	   2 Input   20 Bit        Muxes := 1     
+	  11 Input   11 Bit        Muxes := 1     
+	   2 Input   11 Bit        Muxes := 6     
+	   4 Input    8 Bit        Muxes := 1     
+	  16 Input    5 Bit        Muxes := 1     
+	  11 Input    4 Bit        Muxes := 1     
+	   2 Input    4 Bit        Muxes := 2     
+	  11 Input    2 Bit        Muxes := 1     
+	  11 Input    1 Bit        Muxes := 3     
+	   2 Input    1 Bit        Muxes := 3     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+INFO: [Device 21-9227] Part: xc7z020clg484-1 does not have CEAM library.
+Part Resources:
+DSPs: 220 (col length:60)
+BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2394.188 ; gain = 709.633 ; free physical = 3273 ; free virtual = 13379
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3275 ; free virtual = 13382
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3275 ; free virtual = 13382
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     1|
+|2     |CARRY4 |    13|
+|3     |LUT2   |    10|
+|4     |LUT3   |     8|
+|5     |LUT4   |    28|
+|6     |LUT5   |    44|
+|7     |LUT6   |   143|
+|8     |MUXF7  |    48|
+|9     |MUXF8  |    24|
+|10    |FDCE   |   421|
+|11    |FDPE   |     1|
+|12    |LD     |    13|
+|13    |IBUF   |    11|
+|14    |OBUF   |     9|
++------+-------+------+
+
+Report Instance Areas: 
++------+------------------+--------------+------+
+|      |Instance          |Module        |Cells |
++------+------------------+--------------+------+
+|1     |top               |              |   774|
+|2     |  controlUnit_1   |controlUnit   |    69|
+|3     |  operativeUnit_1 |operativeUnit |   684|
++------+------------------+--------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 15 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.125 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 2400.133 ; gain = 715.570 ; free physical = 3293 ; free virtual = 13391
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2411.055 ; gain = 0.000 ; free physical = 3576 ; free virtual = 13673
+INFO: [Netlist 29-17] Analyzing 98 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2530.832 ; gain = 0.000 ; free physical = 3446 ; free virtual = 13632
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 13 instances were transformed.
+  LD => LDCE: 13 instances
+
+Synth Design complete | Checksum: 180e514
+INFO: [Common 17-83] Releasing license: Synthesis
+21 Infos, 15 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:23 . Memory (MB): peak = 2530.832 ; gain = 850.246 ; free physical = 3446 ; free virtual = 13632
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2027.500; main = 1749.055; forked = 398.951
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3460.230; main = 2530.836; forked = 1060.102
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2554.844 ; gain = 0.000 ; free physical = 3446 ; free virtual = 13632
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/ecgUnit.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file ecgUnit_utilization_synth.rpt -pb ecgUnit_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 25 17:38:28 2025...
diff --git a/proj/proj.runs/synth_1/runme.sh b/proj/proj.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3098a02d2611a7a80c200b46bf4598a36260163c
--- /dev/null
+++ b/proj/proj.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+# 
+
+if [ -z "$PATH" ]; then
+  PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin
+else
+  PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log ecgUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
diff --git a/proj/proj.runs/synth_1/vivado.jou b/proj/proj.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..e16ec7632496ac59b9face642902eac74f93ce53
--- /dev/null
+++ b/proj/proj.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar 25 17:37:19 2025
+# Process ID: 74841
+# Current directory: /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1
+# Command line: vivado -log ecgUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ecgUnit.tcl
+# Log file: /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/ecgUnit.vds
+# Journal file: /homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/proj/proj.runs/synth_1/vivado.jou
+# Running On        :fl-tp-br-104
+# Platform          :Ubuntu
+# Operating System  :Ubuntu 24.04.2 LTS
+# Processor Detail  :12th Gen Intel(R) Core(TM) i5-12500
+# CPU Frequency     :1511.163 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory       :16425 MB
+# Swap memory       :4294 MB
+# Total Virtual     :20720 MB
+# Available Virtual :15733 MB
+#-----------------------------------------------------------
+source ecgUnit.tcl -notrace
diff --git a/proj/proj.runs/synth_1/vivado.pb b/proj/proj.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ed2e4190f2cf119ee332ab8735928eaacd5c15d1
Binary files /dev/null and b/proj/proj.runs/synth_1/vivado.pb differ
diff --git a/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl b/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..c6f723c0a98174d48c19c6c44ce8e6a10190050c
--- /dev/null
+++ b/proj/proj.srcs/sources_1/imports/hdl/ecgUnit.vhdl
@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------------
+-- Title      : ecgUnit
+-- Project    : 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ecgUnit is
+
+  port (
+    I_clock               : in  std_logic;  -- global clock
+    I_reset               : in  std_logic;  -- asynchronous global reset
+    I_inputSample         : in  std_logic_vector(7 downto 0);  -- 8 bit input sample
+    I_inputSampleValid    : in  std_logic;
+    O_filteredSample      : out std_logic_vector(7 downto 0);  -- filtered sample
+    O_filteredSampleValid : out std_logic
+    );
+
+end entity ecgUnit;
+
+architecture archi_ecgUnit of ecgUnit is
+
+  component controlUnit is
+      port (
+        I_clock               : in  std_logic;  -- global clock
+        I_reset               : in  std_logic;  -- asynchronous global reset
+        I_inputSampleValid    : in  std_logic;  -- Control signal to load the input sample in the sample shift register and shift the register
+        I_processingDone      : in  std_logic;
+        O_loadShift1          : out std_logic;  -- filtered sample
+        O_loadShift2          : out std_logic;  -- filtered sample
+        O_loadShift3          : out std_logic;  -- filtered sample
+        O_initAddress         : out std_logic;  -- Control signal to initialize register read address
+        O_incrAddress         : out std_logic;  -- Control signal to increment register read address
+        O_initSum             : out std_logic;  -- Control signal to initialize the MAC register
+        O_cntrMux             : out std_logic_vector(1 downto 0);
+        O_loadSum             : out std_logic;  -- Control signal to load the MAC register;
+        O_loadY               : out std_logic;  -- Control signal to load Y register
+        O_FilteredSampleValid : out std_logic  -- Data valid signal for filtered sample
+        );
+    end component controlUnit;
+
+  component operativeUnit is
+      port (
+        I_clock          : in  std_logic;   -- global clock
+        I_reset          : in  std_logic;   -- asynchronous global reset
+        I_inputSample    : in  std_logic_vector(7 downto 0);  -- 8 bit input sample
+        I_loadShift1     : in  std_logic;  -- Control signal to load the input sample in the sample shift register and shift the register
+        I_loadShift2     : in  std_logic;  
+        I_loadShift3     : in  std_logic;
+        I_initAddress    : in  std_logic;  -- Control signal to initialize register read address
+        I_incrAddress    : in  std_logic;  -- Control signal to increment register read address
+        I_initSum        : in  std_logic;  -- Control signal to initialize the MAC register
+        I_loadSum        : in  std_logic;  -- Control signal to load the MAC register;
+        I_cntrMux        : in  std_logic_vector(1 downto 0);
+        I_loadY          : in  std_logic;   -- Control signal to load Y register
+        O_processingDone : out std_logic;   -- Indicate that processing is done
+        O_Y              : out std_logic_vector(7 downto 0)   -- filtered sample
+        );
+    end component operativeUnit;
+
+  signal SC_processingDone : std_logic;
+  signal SC_loadShift1     : std_logic;
+  signal SC_loadShift2     : std_logic;
+  signal SC_loadShift3     : std_logic;
+  signal SC_initAddress    : std_logic;
+  signal SC_incrAddress    : std_logic;
+  signal SC_initSum        : std_logic;
+  signal SC_cntrMux        : std_logic_vector(1 downto 0);
+  signal SC_loadSum        : std_logic;
+  signal SC_loadY          : std_logic;
+
+begin
+
+  controlUnit_1 : entity work.controlUnit
+    port map (
+      I_clock               => I_clock,
+      I_reset               => I_reset,
+      I_inputSampleValid    => I_inputSampleValid,
+      I_processingDone      => SC_processingDone,
+      O_loadShift1          => SC_loadShift1,
+      O_loadShift2          => SC_loadShift2,
+      O_loadShift3          => SC_loadShift3,
+      O_initAddress         => SC_initAddress,
+      O_incrAddress         => SC_incrAddress,
+      O_initSum             => SC_initSum,
+      O_cntrMux             => SC_cntrMux,
+      O_loadSum             => SC_loadSum,
+      O_loadY               => SC_loadY,
+      O_FilteredSampleValid => O_FilteredSampleValid);
+      
+  operativeUnit_1 : entity work.operativeUnit
+    port map (
+      I_clock          => I_clock,
+      I_reset          => I_reset,
+      I_inputSample    => I_inputSample,
+      I_loadShift1     => SC_loadShift1,
+      I_loadShift2     => SC_loadShift2,
+      I_loadShift3     => SC_loadShift3,
+      I_initAddress    => SC_initAddress,
+      I_incrAddress    => SC_incrAddress,
+      I_initSum        => SC_initSum,
+      I_cntrMux        => SC_cntrMux,
+      I_loadSum        => SC_loadSum,
+      I_loadY          => SC_loadY,
+      O_processingDone => SC_processingDone,
+      O_Y              => O_filteredSample);
+
+
+end architecture archi_ecgUnit;
diff --git a/proj/proj.xpr b/proj/proj.xpr
index a783aa4d16914a3207ffbab545470fdf346470fb..57a5670639bdd44a0b465580ea86724b823481de 100644
--- a/proj/proj.xpr
+++ b/proj/proj.xpr
@@ -99,14 +99,21 @@
       </File>
       <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/imports/hdl/ecgUnit.vhdl">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../src/hdl/ecgUnit.vhdl"/>
+          <Attr Name="ImportTime" Val="1742920067"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="controlUnit"/>
+        <Option Name="TopModule" Val="ecgUnit"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
@@ -120,7 +127,7 @@
       <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="controlUnit"/>
+        <Option Name="TopModule" Val="ecgUnit"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -162,11 +169,12 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="22">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
         <Step Id="synth_design"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
diff --git a/src/hdl/ecgUnit.vhdl b/src/hdl/ecgUnit.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391