diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index 4143964a1b451d8e2b22c755b217e7238d41b1f8..62ce02fc7a9ef7ded5b09b5332a4125df3704ad1 100644
--- a/docs/img/FSM.drawio
+++ b/docs/img/FSM.drawio
@@ -1,6 +1,6 @@
-<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (X11; Linux x86_64; rv:133.0) Gecko/20100101 Firefox/133.0" version="26.1.1">
+<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (X11; Linux x86_64; rv:135.0) Gecko/20100101 Firefox/135.0" version="26.1.2">
<diagram name="Page-1" id="lufUWjv2mjaYaQ6cVEt1">
- <mxGraphModel dx="1535" dy="2341" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
+ <mxGraphModel dx="2248" dy="2804" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
<root>
<mxCell id="0" />
<mxCell id="1" parent="0" />
@@ -235,7 +235,7 @@
<mxCell id="FC-L6MPvyguzHvPPfmFm-76" value="Store2" style="ellipse;whiteSpace=wrap;html=1;fontSize=21;fontFamily=Ubuntu Mono;fillColor=#dae8fc;strokeColor=#6c8ebf;" parent="1" vertex="1">
<mxGeometry x="255" y="-315" width="160" height="80" as="geometry" />
</mxCell>
- <mxCell id="q2NBXy2qhxmf1ht5OkMo-2" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=1;exitDx=0;exitDy=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" edge="1" parent="1" source="FC-L6MPvyguzHvPPfmFm-77" target="bw7OO0sNot4gaAuLXok9-3">
+ <mxCell id="q2NBXy2qhxmf1ht5OkMo-2" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=1;exitDx=0;exitDy=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;" parent="1" source="FC-L6MPvyguzHvPPfmFm-77" target="bw7OO0sNot4gaAuLXok9-3" edge="1">
<mxGeometry relative="1" as="geometry" />
</mxCell>
<mxCell id="FC-L6MPvyguzHvPPfmFm-77" value="Processing<br>Loop2" style="ellipse;whiteSpace=wrap;html=1;fontSize=21;fontFamily=Ubuntu Mono;fillColor=#dae8fc;strokeColor=#6c8ebf;" parent="1" vertex="1">
@@ -274,7 +274,7 @@
<mxCell id="FC-L6MPvyguzHvPPfmFm-84" value="<span style="font-family: &quot;Ubuntu Mono&quot;; font-size: 15px;">processingDone = '1'</span>" style="text;whiteSpace=wrap;html=1;" parent="1" vertex="1">
<mxGeometry x="358" y="-20" width="182" height="40" as="geometry" />
</mxCell>
- <mxCell id="q2NBXy2qhxmf1ht5OkMo-3" value="<font style="font-size: 14px;">processingDone = '1'</font>" style="text;html=1;align=center;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" vertex="1" parent="1">
+ <mxCell id="q2NBXy2qhxmf1ht5OkMo-3" value="<font style="font-size: 14px;">processingDone = '1'</font>" style="text;html=1;align=center;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
<mxGeometry x="337.5" y="343" width="148" height="29" as="geometry" />
</mxCell>
</root>
diff --git a/docs/img/FSM.png b/docs/img/FSM.png
new file mode 100644
index 0000000000000000000000000000000000000000..0d6c7f0fde1e5d71837ad69a8597f271c2bd36c4
Binary files /dev/null and b/docs/img/FSM.png differ
diff --git a/docs/img/OperativeUnit.drawio b/docs/img/OperativeUnit.drawio
index d839989621a3c537588ecf151980d95a43958319..dac8b8175be487f50dcec005489063b2550a01da 100644
--- a/docs/img/OperativeUnit.drawio
+++ b/docs/img/OperativeUnit.drawio
@@ -1,6 +1,6 @@
-<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (X11; Linux x86_64; rv:133.0) Gecko/20100101 Firefox/133.0" version="26.1.1">
+<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (X11; Linux x86_64; rv:135.0) Gecko/20100101 Firefox/135.0" version="26.1.3">
<diagram name="Page-1" id="HnFJvu7xD7cCTyxCgidn">
- <mxGraphModel dx="2680" dy="2064" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
+ <mxGraphModel dx="3211" dy="2470" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
<root>
<mxCell id="0" />
<mxCell id="1" parent="0" />
@@ -109,14 +109,14 @@
<mxGeometry relative="1" as="geometry">
<Array as="points">
<mxPoint x="440" y="340" />
- <mxPoint x="440" y="530" />
- <mxPoint x="1120" y="530" />
+ <mxPoint x="440" y="540" />
+ <mxPoint x="1120" y="540" />
</Array>
</mxGeometry>
</mxCell>
- <mxCell id="dccOzbdqGY2gTYpR8YRW-1" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=1;entryY=0.5;entryDx=0;entryDy=0;" parent="1" target="7X3AgIlieK-k1dyfllYh-177" edge="1">
+ <mxCell id="dccOzbdqGY2gTYpR8YRW-1" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=1;entryY=0.5;entryDx=0;entryDy=0;" parent="1" target="7X3AgIlieK-k1dyfllYh-177" edge="1">
<mxGeometry relative="1" as="geometry">
- <mxPoint x="400" as="sourcePoint" />
+ <mxPoint x="600" y="-40" as="sourcePoint" />
</mxGeometry>
</mxCell>
<mxCell id="7X3AgIlieK-k1dyfllYh-177" value="" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;rotation=-90;strokeWidth=2;" parent="1" vertex="1">
@@ -216,7 +216,13 @@
</mxGeometry>
</mxCell>
<mxCell id="7X3AgIlieK-k1dyfllYh-193" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=0;exitDx=0;exitDy=0;entryX=0.5;entryY=1;entryDx=0;entryDy=0;" parent="1" source="7X3AgIlieK-k1dyfllYh-194" target="7X3AgIlieK-k1dyfllYh-264" edge="1">
- <mxGeometry relative="1" as="geometry" />
+ <mxGeometry relative="1" as="geometry">
+ <Array as="points">
+ <mxPoint x="920" y="350" />
+ <mxPoint x="920" y="620" />
+ <mxPoint x="750" y="620" />
+ </Array>
+ </mxGeometry>
</mxCell>
<mxCell id="7X3AgIlieK-k1dyfllYh-194" value="" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;rotation=90;strokeWidth=2;" parent="1" vertex="1">
<mxGeometry x="750" y="340" width="280" height="20" as="geometry" />
@@ -378,7 +384,13 @@
</mxGeometry>
</mxCell>
<mxCell id="7X3AgIlieK-k1dyfllYh-219" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=0;exitDx=0;exitDy=0;entryX=0.25;entryY=1;entryDx=0;entryDy=0;" parent="1" source="7X3AgIlieK-k1dyfllYh-220" target="7X3AgIlieK-k1dyfllYh-264" edge="1">
- <mxGeometry relative="1" as="geometry" />
+ <mxGeometry relative="1" as="geometry">
+ <Array as="points">
+ <mxPoint x="1840" y="330" />
+ <mxPoint x="1840" y="630" />
+ <mxPoint x="820" y="630" />
+ </Array>
+ </mxGeometry>
</mxCell>
<mxCell id="7X3AgIlieK-k1dyfllYh-220" value="" style="shape=trapezoid;perimeter=trapezoidPerimeter;whiteSpace=wrap;html=1;fixedSize=1;rotation=90;strokeWidth=2;" parent="1" vertex="1">
<mxGeometry x="1670" y="320" width="280" height="20" as="geometry" />
@@ -568,8 +580,7 @@
<mxCell id="7X3AgIlieK-k1dyfllYh-257" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" target="7X3AgIlieK-k1dyfllYh-164" edge="1">
<mxGeometry relative="1" as="geometry">
<Array as="points">
- <mxPoint x="830" />
- <mxPoint x="330" />
+ <mxPoint x="330" y="-41" />
</Array>
<mxPoint x="880" y="-41" as="sourcePoint" />
</mxGeometry>
@@ -587,9 +598,7 @@
<mxCell id="7X3AgIlieK-k1dyfllYh-259" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.75;exitY=1;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" target="7X3AgIlieK-k1dyfllYh-220" edge="1">
<mxGeometry relative="1" as="geometry">
<Array as="points">
- <mxPoint x="880" y="-41" />
- <mxPoint x="880" />
- <mxPoint x="1810" />
+ <mxPoint x="1810" y="-41" />
</Array>
<mxPoint x="910" y="-40.700000000000045" as="sourcePoint" />
</mxGeometry>
@@ -700,7 +709,7 @@
<mxCell id="7X3AgIlieK-k1dyfllYh-281" value="" style="shape=waypoint;sketch=0;size=6;pointerEvents=1;points=[];fillColor=default;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;strokeWidth=2;" parent="1" vertex="1">
<mxGeometry x="970" y="840" width="20" height="20" as="geometry" />
</mxCell>
- <mxCell id="slADeYBO6sJwLNavmEFx-1" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=0;exitDx=0;exitDy=0;" edge="1" parent="1" source="7X3AgIlieK-k1dyfllYh-282">
+ <mxCell id="slADeYBO6sJwLNavmEFx-1" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.5;exitY=0;exitDx=0;exitDy=0;" parent="1" source="7X3AgIlieK-k1dyfllYh-282" edge="1">
<mxGeometry relative="1" as="geometry">
<mxPoint x="1020" y="1400.0000000000005" as="targetPoint" />
</mxGeometry>
diff --git a/docs/img/OperativeUnit.png b/docs/img/OperativeUnit.png
new file mode 100644
index 0000000000000000000000000000000000000000..17e2f00dbce84000bf4c1fa00b9f77c01d986538
Binary files /dev/null and b/docs/img/OperativeUnit.png differ
diff --git a/proj/proj.cache/sim/ssm.db b/proj/proj.cache/sim/ssm.db
new file mode 100644
index 0000000000000000000000000000000000000000..5472ff778f8dd79ba9359c71fe9f8ad3ed82fdcd
--- /dev/null
+++ b/proj/proj.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 26 09:52:40 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
diff --git a/proj/proj.cache/wt/project.wpc b/proj/proj.cache/wt/project.wpc
index 2599f423253c09ec78d9135689798dbecf72df68..ccef59f4e980f6836ccd89b1b0fae72dd48bd715 100644
--- a/proj/proj.cache/wt/project.wpc
+++ b/proj/proj.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:7
+6d6f64655f636f756e7465727c4755494d6f6465:9
eof:
diff --git a/proj/proj.cache/wt/xsim.wdf b/proj/proj.cache/wt/xsim.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af
--- /dev/null
+++ b/proj/proj.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:241934075
diff --git a/proj/proj.ip_user_files/README.txt b/proj/proj.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/proj/proj.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/proj/proj.runs/synth_1/gen_run.xml b/proj/proj.runs/synth_1/gen_run.xml
index a30f4c560a969a3d62cca956d2c192f483916ad7..958cd9793f51240205cf68571caec94dfb432911 100644
--- a/proj/proj.runs/synth_1/gen_run.xml
+++ b/proj/proj.runs/synth_1/gen_run.xml
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7z020clg484-1" LaunchTime="1742920636">
- <File Type="VDS-TIMINGSUMMARY" Name="ecgUnit_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="ecgUnit.dcp"/>
<File Type="RDS-UTIL-PB" Name="ecgUnit_utilization_synth.pb"/>
+ <File Type="PA-TCL" Name="ecgUnit.tcl"/>
<File Type="RDS-UTIL" Name="ecgUnit_utilization_synth.rpt"/>
- <File Type="RDS-PROPCONSTRS" Name="ecgUnit_drc_synth.rpt"/>
- <File Type="RDS-RDS" Name="ecgUnit.vds"/>
<File Type="REPORTS-TCL" Name="ecgUnit_reports.tcl"/>
- <File Type="VDS-TIMING-PB" Name="ecgUnit_timing_summary_synth.pb"/>
- <File Type="PA-TCL" Name="ecgUnit.tcl"/>
+ <File Type="RDS-RDS" Name="ecgUnit.vds"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
diff --git a/proj/proj.sim/sim_1/behav/xsim/compile.log b/proj/proj.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000000000000000000000000000000000000..99185ab0035125988369ea04abc3d4a0979226a5
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/ecgUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'ecgUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/tb_ecgUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_ecgUnit'
diff --git a/proj/proj.sim/sim_1/behav/xsim/compile.sh b/proj/proj.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..556d14a0936ec1f0fc29f4b701485f6768c4b438
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Mar 26 12:16:55 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_ecgUnit_vhdl.prj"
+xvhdl --incr --relax -prj tb_ecgUnit_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/proj/proj.sim/sim_1/behav/xsim/elaborate.log b/proj/proj.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000000000000000000000000000000000000..6463ed7c7cbbe0a5338561b16c1ba3a2f36cb411
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,19 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_ecgunit of entity xil_defaultlib.ecgUnit [ecgunit_default]
+Compiling architecture archi_tb_ecgunit of entity xil_defaultlib.tb_ecgunit
+Built simulation snapshot tb_ecgUnit_behav
diff --git a/proj/proj.sim/sim_1/behav/xsim/elaborate.sh b/proj/proj.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..abeedf59e6779ffeeeb8669cc864699cfe8b16ed
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Mar 26 12:16:57 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit -log elaborate.log
+
diff --git a/proj/proj.sim/sim_1/behav/xsim/simulate.log b/proj/proj.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/proj.sim/sim_1/behav/xsim/simulate.sh b/proj/proj.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b706ecf478b160f0d0d2a66786caadd721ddb0b5
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Mar 26 12:16:59 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_ecgUnit_behav -key {Behavioral:sim_1:Functional:tb_ecgUnit} -tclbatch tb_ecgUnit.tcl -log simulate.log"
+xsim tb_ecgUnit_behav -key {Behavioral:sim_1:Functional:tb_ecgUnit} -tclbatch tb_ecgUnit.tcl -log simulate.log
+
diff --git a/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit.tcl b/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit_behav.wdb b/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..50d690e28db45070860c46ba7fd89b7c1919f3b6
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit_behav.wdb differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit_vhdl.prj b/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit_vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..ff09f013b26897a27f64bea2cb35772720b813f4
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/tb_ecgUnit_vhdl.prj
@@ -0,0 +1,9 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../src/hdl/ecgUnit.vhd" \
+"../../../../../src/hdl/tb_ecgUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/proj/proj.sim/sim_1/behav/xsim/xelab.pb b/proj/proj.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..447b4c6ba2ff649440a26263089c43217cc703aa
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/Compile_Options.txt b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2b3d98baafcec006e01c101eee1236b4c600847b
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "tb_ecgUnit_behav" "xil_defaultlib.tb_ecgUnit" -log "elaborate.log"
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/TempBreakPointFile.txt b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..a3a7c954e8263016cab9e19528913427802245c1
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.c b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..3a43f8cc40d17928473b16476819bf8c4b5e161e
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.c
@@ -0,0 +1,139 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_31(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_56(char*, char *);
+IKI_DLLESPEC extern void execute_57(char*, char *);
+IKI_DLLESPEC extern void execute_58(char*, char *);
+IKI_DLLESPEC extern void execute_59(char*, char *);
+IKI_DLLESPEC extern void execute_60(char*, char *);
+IKI_DLLESPEC extern void execute_61(char*, char *);
+IKI_DLLESPEC extern void execute_62(char*, char *);
+IKI_DLLESPEC extern void execute_63(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[33] = {(funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 33;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_ecgUnit_behav/xsim.reloc", (void **)funcTab, 33);
+ iki_vhdl_file_variable_register(dp + 10824);
+ iki_vhdl_file_variable_register(dp + 10880);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_ecgUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_ecgUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_ecgUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_ecgUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_ecgUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.lnx64.o b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..26ef4888394ea3a5d640da14f5b5ab8b491c3de1
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diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.dbg b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..257859cf84ded5d25fe24a5f21a55fcb672888ee
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.dbg differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.mem b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..b26d6414ae11a0b5e63fd489d4619cbef2f3af84
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.mem differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.reloc b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..7b572362d8463683a3bcfdff8b022496ea469934
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.reloc differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rlx b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..744b9d2175949d47b3a0e9545b30c4036883a974
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 3078891113684295243 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot tb_ecgUnit_behav xil_defaultlib.tb_ecgUnit" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_ecgUnit_behav/xsimk\" \"xsim.dir/tb_ecgUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_ecgUnit_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rtti b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..86bdbb4a13e331e26347368763599d007b7dfe10
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.rtti differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.svtype b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..6dc1deb65a85fafe2dcea36f677983510a180e28
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.svtype differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.type b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..ff90d39d13bdecb3b508c0857f0ba892000abe36
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.type differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.xdbg b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..8fd10c36af4053f157449f38cf43de0b425fd58e
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsim.xdbg differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimSettings.ini b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..26b8c8443d63973247db26eb419548dc41c590e1
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=174
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=84
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=209
+OBJECT_NAME_COLUMN_WIDTH=183
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimcrash.log b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimk b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..01988ce4a9997967155a423e8bea513c96f29238
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimk differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimkernel.log b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..e2cc3ca77222dff3226b319996c8f2c0068e1918
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/tb_ecgUnit_behav/xsimkernel.log
@@ -0,0 +1,4 @@
+Running: xsim.dir/tb_ecgUnit_behav/xsimk -simmode gui -wdb tb_ecgUnit_behav.wdb -simrunnum 0 -socket 45159
+Design successfully loaded
+Design Loading Memory Usage: 20180 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 30 ms
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..7bcb1141070623d105fd1cb0b0f214b16a82874b
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ecgunit.vdb b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ecgunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..0b6457272763b838ea1d76de64943a72903a6abc
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ecgunit.vdb differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..c11670d1d534a82c1733918f4b5dd91b13c33ea3
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_ecgunit.vdb b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_ecgunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..2a3cf79407a1315e72df5748ee8f3c6f2b8eb12e
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_ecgunit.vdb differ
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..9dd952024e38d3b3fb0e6f0480b9c1b540c42320
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,8 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/controlUnit.vhd,1742601775,vhdl,/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/ecgUnit.vhd,,,controlunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/ecgUnit.vhd,1742921658,vhdl,/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/tb_ecgUnit.vhd,,,ecgunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd,1742987796,vhdl,/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/ecgUnit.vhd,,,operativeunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/tb_ecgUnit.vhd,1742984785,vhdl,,,,tb_ecgunit,,,,,,,,
diff --git a/proj/proj.sim/sim_1/behav/xsim/xsim.ini b/proj/proj.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..e8199b2597fb201d9f6673368b7b003f11b596e4
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/proj/proj.sim/sim_1/behav/xsim/xvhdl.log b/proj/proj.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000000000000000000000000000000000000..99185ab0035125988369ea04abc3d4a0979226a5
--- /dev/null
+++ b/proj/proj.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/ecgUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'ecgUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-ecg-etudiant-a23aboul/src/hdl/tb_ecgUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_ecgUnit'
diff --git a/proj/proj.sim/sim_1/behav/xsim/xvhdl.pb b/proj/proj.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..0e789ec02b9b32d91b199aa9ebeea7b58a8f8064
Binary files /dev/null and b/proj/proj.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/proj/proj.xpr b/proj/proj.xpr
index d4b890f8f6b174827f5b3f838b6558c4568e5f7a..836c76da0ae1cb2f0dc281a88b873c0bce10d67d 100644
--- a/proj/proj.xpr
+++ b/proj/proj.xpr
@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zedboard"/>
- <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTXSimLaunchSim" Val="30"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -123,9 +123,15 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/hdl/tb_ecgUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="ecgUnit"/>
+ <Option Name="TopModule" Val="tb_ecgUnit"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index f1e19abbf8d63333cd0c582a68dee3c62b4be187..afc87cb3a1be9d6624784f095a8adefe4891c008 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -39,7 +39,7 @@ architecture arch_operativeUnit of operativeUnit is
signal SR_shiftRegister1 : registerFile; -- shift register file used to store and shift input samples
signal SR_shiftRegister2 : registerFile;
signal SR_shiftRegister3 : registerFile;
- signal SC_multOperand1 : signed(7 downto 0);
+ signal SC_multOperand1 : signed(7 downto 0):=(others => '0');
signal SC_multOperand2 : signed(7 downto 0);
signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi
signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition
@@ -197,7 +197,7 @@ begin
O_processingDone <= '1' when SR_readAddress=15 else '0' ;
- Mux : process (SR_readAddress, I_cntrMux) is
+ Mux : process (I_clock,SR_readAddress, I_cntrMux) is
begin
case I_cntrMux is
@@ -214,15 +214,20 @@ begin
SC_multOperand1 <= SR_shiftRegister3(SR_readAddress);
SC_multOperand2 <= SR_coefRegister4(SR_readAddress);
end case;
+-- if(I_incrAddress = '0' and I_initAddress = '0') then
+-- SC_multOperand1 <= (others => '0');
+-- SC_multOperand2 <= (others => '0');
+-- end if;
end process;
- SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 16 bits
- SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2 ; -- 16 bits
+ SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum ;
sum_acc : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_sum <= (others => '0');
+ -- SC_addResult <= (others => '0');
elsif rising_edge(I_clock) then
if I_initSum = '1' then
SR_sum <= (others => '0');
diff --git a/src/hdl/tb_ecgUnit.vhd b/src/hdl/tb_ecgUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0d5a6384f224b918e9b6edd850dfa90958e9f7f7
--- /dev/null
+++ b/src/hdl/tb_ecgUnit.vhd
@@ -0,0 +1,87 @@
+-------------------------------------------------------------------------------
+-- Title : EcgUnit
+-- Project :
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_ecgUnit is
+end entity tb_ecgUnit;
+
+architecture archi_tb_ecgUnit of tb_ecgUnit is
+ component ecgUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
+ O_filteredSampleValid : out std_logic
+ );
+
+end component ecgUnit;
+
+ signal SC_clock : std_logic := '0';
+ signal SC_reset : std_logic;
+ signal SC_inputSample : std_logic_vector(7 downto 0);
+ signal SC_inputSampleValid : std_logic:='0';
+ signal SC_filteredSample : std_logic_vector(7 downto 0);
+ signal SC_filteredSampleValid : std_logic;
+ signal SC_counter : integer range 0 to 99 := 0;
+
+begin
+
+ SC_clock <= not SC_clock after 5 ns;
+ SC_reset <= '1' , '0' after 76 ns;
+
+ -- Processus pour gérer le compteur
+ process(SC_clock, SC_reset)
+ begin
+ if SC_reset = '1' then
+ SC_counter <= 0; -- Réinitialisation du compteur lors du reset
+ elsif rising_edge(SC_clock) then
+ if SC_counter = 99 then
+ SC_counter <= 0; -- Réinitialiser le compteur lorsqu'il atteint 3
+ else
+ SC_counter <= SC_counter + 1; -- Incrémenter le compteur
+ end if;
+ end if;
+ end process;
+
+ -- Définition de SC_inputSampleValid en fonction de SC_counter
+ SC_inputSampleValid <= '1' when SC_counter < 10 and SC_reset='0' else '0';
+
+ -- Null signal followed by a Dirac and then an arbitrary sequence
+ SC_inputSample <= "00000000",
+ "01111111" after 1076 ns,
+ "00000000" after 2076 ns,
+ "00100100" after 3076 ns,
+ "01100100" after 4076 ns,
+ "10100010" after 5076 ns,
+ "11011011" after 6076 ns,
+ "00001011" after 7076 ns,
+ "10000000" after 8076 ns,
+ "01111111" after 9076 ns,
+ "10111010" after 10076 ns;
+
+
+-- the filter output on 8 bits is a sequence of signed numbers (with the assumption
+-- of rounding the output, so the accuracy can be slightly different depending
+-- on your final stage):
+ -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
+ -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
+
+
+ ecgUnit_1 : entity work.ecgUnit
+ port map (
+ I_clock => SC_clock,
+ I_reset => SC_reset,
+ I_inputSample => SC_inputSample,
+ I_inputSampleValid => SC_inputSampleValid,
+ O_filteredSample => SC_filteredSample,
+ O_filteredSampleValid => SC_filteredSampleValid);
+
+end architecture archi_tb_ecgUnit;