diff --git a/proj/proj.xpr b/proj/proj.xpr
index 57a5670639bdd44a0b465580ea86724b823481de..d4b890f8f6b174827f5b3f838b6558c4568e5f7a 100644
--- a/proj/proj.xpr
+++ b/proj/proj.xpr
@@ -103,10 +103,8 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/sources_1/imports/hdl/ecgUnit.vhdl">
+ <File Path="$PPRDIR/../src/hdl/ecgUnit.vhd">
<FileInfo>
- <Attr Name="ImportPath" Val="$PPRDIR/../src/hdl/ecgUnit.vhdl"/>
- <Attr Name="ImportTime" Val="1742920067"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
diff --git a/src/hdl/ecgUnit.vhd b/src/hdl/ecgUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c6f723c0a98174d48c19c6c44ce8e6a10190050c
--- /dev/null
+++ b/src/hdl/ecgUnit.vhd
@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------------
+-- Title : ecgUnit
+-- Project :
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ecgUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
+ O_filteredSampleValid : out std_logic
+ );
+
+end entity ecgUnit;
+
+architecture archi_ecgUnit of ecgUnit is
+
+ component controlUnit is
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_processingDone : in std_logic;
+ O_loadShift1 : out std_logic; -- filtered sample
+ O_loadShift2 : out std_logic; -- filtered sample
+ O_loadShift3 : out std_logic; -- filtered sample
+ O_initAddress : out std_logic; -- Control signal to initialize register read address
+ O_incrAddress : out std_logic; -- Control signal to increment register read address
+ O_initSum : out std_logic; -- Control signal to initialize the MAC register
+ O_cntrMux : out std_logic_vector(1 downto 0);
+ O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadY : out std_logic; -- Control signal to load Y register
+ O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
+ );
+ end component controlUnit;
+
+ component operativeUnit is
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_loadShift1 : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShift2 : in std_logic;
+ I_loadShift3 : in std_logic;
+ I_initAddress : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress : in std_logic; -- Control signal to increment register read address
+ I_initSum : in std_logic; -- Control signal to initialize the MAC register
+ I_loadSum : in std_logic; -- Control signal to load the MAC register;
+ I_cntrMux : in std_logic_vector(1 downto 0);
+ I_loadY : in std_logic; -- Control signal to load Y register
+ O_processingDone : out std_logic; -- Indicate that processing is done
+ O_Y : out std_logic_vector(7 downto 0) -- filtered sample
+ );
+ end component operativeUnit;
+
+ signal SC_processingDone : std_logic;
+ signal SC_loadShift1 : std_logic;
+ signal SC_loadShift2 : std_logic;
+ signal SC_loadShift3 : std_logic;
+ signal SC_initAddress : std_logic;
+ signal SC_incrAddress : std_logic;
+ signal SC_initSum : std_logic;
+ signal SC_cntrMux : std_logic_vector(1 downto 0);
+ signal SC_loadSum : std_logic;
+ signal SC_loadY : std_logic;
+
+begin
+
+ controlUnit_1 : entity work.controlUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSampleValid => I_inputSampleValid,
+ I_processingDone => SC_processingDone,
+ O_loadShift1 => SC_loadShift1,
+ O_loadShift2 => SC_loadShift2,
+ O_loadShift3 => SC_loadShift3,
+ O_initAddress => SC_initAddress,
+ O_incrAddress => SC_incrAddress,
+ O_initSum => SC_initSum,
+ O_cntrMux => SC_cntrMux,
+ O_loadSum => SC_loadSum,
+ O_loadY => SC_loadY,
+ O_FilteredSampleValid => O_FilteredSampleValid);
+
+ operativeUnit_1 : entity work.operativeUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSample => I_inputSample,
+ I_loadShift1 => SC_loadShift1,
+ I_loadShift2 => SC_loadShift2,
+ I_loadShift3 => SC_loadShift3,
+ I_initAddress => SC_initAddress,
+ I_incrAddress => SC_incrAddress,
+ I_initSum => SC_initSum,
+ I_cntrMux => SC_cntrMux,
+ I_loadSum => SC_loadSum,
+ I_loadY => SC_loadY,
+ O_processingDone => SC_processingDone,
+ O_Y => O_filteredSample);
+
+
+end architecture archi_ecgUnit;
diff --git a/src/hdl/ecgUnit.vhdl b/src/hdl/ecgUnit.vhdl
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000