diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index cd056f619d4a6c4caddd9df5b41f43ed435892f3..8c2031ccbe0d9a013046fce5eba38e89d91e9be6 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -9,17 +9,24 @@
### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
-
+Le design comporte deux processus: un séquentiel avec reset asynchrone pour l'état et un combinatoire pour la logique de transition.
### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
-
+La simulation vous permet-elle de valider votre description VHDL. les outputs sont corrects
+
### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
-
+La conception de l’unité de contrôle est Validé.
### Question filtre 4 : Combien de processus sont utilisés et de quelles natures sont-ils ?
-
+quatre processus sont définis :
+1 shift (Processus séquentiel)
+2 incr_address (Processus séquentiel)
+3 sum_acc (Processus séquentiel)
+4 store_result (Processus séquentiel)
### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
-
+La simulation vous permet-elle de valider votre description VHDL. les outputs sont corrects
+
### Question filtre 6 : Validez-vous la conception de l’unité opérative ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ?
+La conception de l’unité de contrôle est Validé.
diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index bd839a9b01be6c20eb7b6840fcbab9fd73e2336d..008be45fe172af5ab6abaef9b45b1bfd05f5ea0e 100644
--- a/docs/img/FSM.drawio
+++ b/docs/img/FSM.drawio
@@ -1,52 +1,52 @@
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diff --git a/docs/img/FSM.png b/docs/img/FSM.png
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..0ac156b1c1a9e11587dd9de4a2bfbc8975af8ecd 100644
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diff --git a/docs/img/Q2.png b/docs/img/Q2.png
new file mode 100644
index 0000000000000000000000000000000000000000..7b5a313c004bd37c74dc441f312097ca1dd51f39
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diff --git a/docs/img/Q5.png b/docs/img/Q5.png
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diff --git a/proj/AudioProc.cache/sim/ssm.db b/proj/AudioProc.cache/sim/ssm.db
new file mode 100644
index 0000000000000000000000000000000000000000..15ddb6901fb5ba0a2d057e9acf25ba54bfa4f578
--- /dev/null
+++ b/proj/AudioProc.cache/sim/ssm.db
@@ -0,0 +1,11 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Tue Mar 18 16:52:12 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,
diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
new file mode 100644
index 0000000000000000000000000000000000000000..c7c2fb6900fc092f4c13bd3f83a7b96eb456e558
--- /dev/null
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:5
+eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..0632972bcea2c978eada2572bb97eae3107cdb8c
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diff --git a/proj/AudioProc.cache/wt/synthesis_details.wdf b/proj/AudioProc.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/proj/AudioProc.cache/wt/webtalk_pa.xml b/proj/AudioProc.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..21991dfd5751bf4d98f3e1b408674a80a41e545a
--- /dev/null
+++ b/proj/AudioProc.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Mar 18 16:52:54 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="bf8a24dcdbf84b51a0b6a21a3bdfb156" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Flow_PerfOptimized_High" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af
--- /dev/null
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
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diff --git a/proj/AudioProc.hw/AudioProc.lpr b/proj/AudioProc.hw/AudioProc.lpr
new file mode 100644
index 0000000000000000000000000000000000000000..afc0a86cf8f820e635f040c3869b4b647d11ec04
--- /dev/null
+++ b/proj/AudioProc.hw/AudioProc.lpr
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0"/>
diff --git a/proj/AudioProc.ip_user_files/README.txt b/proj/AudioProc.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100755
index 0000000000000000000000000000000000000000..c6b126bb4b8be62560df51240c9200f63d5efb97
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,103 @@
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+
+ -- Clock in ports
+ clk_in1 => clk_in1,
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_1.xml b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..16be6d2f3e206798826cd66ee56974f8b4fa198f
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/impl_1/.Vivado_Implementation.queue.rst b/proj/AudioProc.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.init_design.begin.rst b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..28391ea2f57be0dc019d59691076406033e5c7a5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23aboul" Host="" Pid="35875">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.init_design.end.rst b/proj/AudioProc.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..28391ea2f57be0dc019d59691076406033e5c7a5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23aboul" Host="" Pid="35875">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.end.rst b/proj/AudioProc.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.place_design.begin.rst b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..28391ea2f57be0dc019d59691076406033e5c7a5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23aboul" Host="" Pid="35875">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.place_design.end.rst b/proj/AudioProc.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.route_design.begin.rst b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..28391ea2f57be0dc019d59691076406033e5c7a5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23aboul" Host="" Pid="35875">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.route_design.end.rst b/proj/AudioProc.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.vivado.begin.rst b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..4232726d85eaa59ed4d69ac55ab95a7374df7fde
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="a23aboul" Host="fl-tp-br-104" Pid="35804" HostCore="12" HostMemory="16040140">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.vivado.end.rst b/proj/AudioProc.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..28391ea2f57be0dc019d59691076406033e5c7a5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23aboul" Host="" Pid="35875">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.end.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/ISEWrap.js b/proj/AudioProc.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/impl_1/ISEWrap.sh b/proj/AudioProc.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bin b/proj/AudioProc.runs/impl_1/audioProc.bin
new file mode 100644
index 0000000000000000000000000000000000000000..e3c4fc3fb83705466df557ec52b52e1bde60d4f3
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc.bin differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bit b/proj/AudioProc.runs/impl_1/audioProc.bit
new file mode 100644
index 0000000000000000000000000000000000000000..6a492b2e16758de1de836c3c317ec7737680bc5e
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc.bit differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.tcl b/proj/AudioProc.runs/impl_1/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..29bc097dde2762e3b78c82f8bb97cbcb6a88dffe
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc.tcl
@@ -0,0 +1,284 @@
+namespace eval ::optrace {
+ variable script "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param chipscope.maxJobs 1
+ set_param runs.launchOptions { -jobs 2 }
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7a200tsbg484-1
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.cache/wt [current_project]
+ set_property parent.project_path /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.xpr [current_project]
+ set_property ip_repo_paths /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/repo [current_project]
+ update_ip_catalog
+ set_property ip_output_repo /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/audioProc.dcp
+ read_ip -quiet /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+OPTRACE "read constraints: implementation" START { }
+ read_xdc /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ link_design -top audioProc -part xc7a200tsbg484-1
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx" }
+ set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_io -file audioProc_io_placed.rpt" "report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb" "report_control_sets -verbose -file audioProc_control_sets_placed.rpt" }
+ set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx" "report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx" "report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx" "report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb" "report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt" "report_clock_utilization -file audioProc_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx" }
+ set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+ write_checkpoint -force audioProc_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ catch { write_mem_info -force -no_partial_mmi audioProc.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force audioProc.bit -bin_file
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force audioProc}
+ catch {file copy -force audioProc.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/proj/AudioProc.runs/impl_1/audioProc.vdi b/proj/AudioProc.runs/impl_1/audioProc.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..65076075d9ad6b1ec84aea86e79a84410edecc19
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -0,0 +1,769 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar 18 16:54:31 2025
+# Process ID: 35875
+# Current directory: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-104
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :12th Gen Intel(R) Core(TM) i5-12500
+# CPU Frequency :1916.620 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16425 MB
+# Swap memory :4294 MB
+# Total Virtual :20720 MB
+# Available Virtual :15343 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.551 ; gain = 325.840 ; free physical = 3205 ; free virtual = 14018
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2098.832 ; gain = 0.000 ; free physical = 2832 ; free virtual = 13628
+INFO: [Netlist 29-17] Analyzing 90 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+get_clocks: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2815.324 ; gain = 624.898 ; free physical = 2199 ; free virtual = 13036
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2815.324 ; gain = 0.000 ; free physical = 2188 ; free virtual = 13036
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2815.324 ; gain = 1120.898 ; free physical = 2188 ; free virtual = 13036
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.83 . Memory (MB): peak = 2879.355 ; gain = 64.031 ; free physical = 2205 ; free virtual = 13039
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2879.355 ; gain = 0.000 ; free physical = 2204 ; free virtual = 13038
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Phase 1 Initialization | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Phase 2 Timer Update And Timing Data Collection | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 1c4537e51
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Retarget | Checksum: 1c4537e51
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 2092676cd
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Constant propagation | Checksum: 2092676cd
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Sweep | Checksum: 23f78c28e
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+BUFG optimization | Checksum: 23f78c28e
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Shift Register Optimization | Checksum: 23f78c28e
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Post Processing Netlist | Checksum: 23f78c28e
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Phase 9 Finalization | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 2 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Ending Netlist Obfuscation Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+INFO: [Common 17-83] Releasing license: Implementation
+34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12694
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12694
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1866 ; free virtual = 12685
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12889edb3
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1867 ; free virtual = 12686
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1867 ; free virtual = 12686
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 162133ba4
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.49 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1839 ; free virtual = 12662
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1d345fc39
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1844 ; free virtual = 12667
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1d345fc39
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1844 ; free virtual = 12667
+Phase 1 Placer Initialization | Checksum: 1d345fc39
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1844 ; free virtual = 12667
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 259bcf59f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1874 ; free virtual = 12698
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1eb9fea2e
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1903 ; free virtual = 12727
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1eb9fea2e
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1903 ; free virtual = 12727
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 2135c9eff
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1897 ; free virtual = 12722
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 147 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 65 nets or LUTs. Breaked 0 LUT, combined 65 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3275.156 ; gain = 0.000 ; free physical = 1904 ; free virtual = 12713
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 65 | 65 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 65 | 65 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1045e841e
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1904 ; free virtual = 12713
+Phase 2.4 Global Placement Core | Checksum: df357595
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+Phase 2 Global Placement | Checksum: df357595
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 126b0a524
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 260476615
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 235f4885a
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 21dc0f0a9
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.5 Fast Optimization
+Phase 3.5 Fast Optimization | Checksum: 1b18dbe5a
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1913 ; free virtual = 12722
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 14fc209cd
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1905 ; free virtual = 12714
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1755c839f
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1905 ; free virtual = 12714
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: e875e6cf
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1905 ; free virtual = 12714
+
+Phase 3.9 Fast Optimization
+Phase 3.9 Fast Optimization | Checksum: 2289630fa
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1895 ; free virtual = 12704
+Phase 3 Detail Placement | Checksum: 2289630fa
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1895 ; free virtual = 12704
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 20923581e
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.032 |
+Phase 1 Physical Synthesis Initialization | Checksum: fd4c8aa0
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1898 ; free virtual = 12707
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 1bf3592a3
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1898 ; free virtual = 12707
+Phase 4.1.1.1 BUFG Insertion | Checksum: 20923581e
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.512. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Phase 4.1 Post Commit Optimization | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Phase 4.3 Placer Reporting | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1898 ; free virtual = 12707
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: f1510904
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Ending Placer Task | Checksum: ef412fe0
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+69 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1860 ; free virtual = 12669
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1864 ; free virtual = 12673
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12672
+Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12674
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12673
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12673
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12673
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1862 ; free virtual = 12673
+Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1862 ; free virtual = 12673
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 2abcc7f3 ConstDB: 0 ShapeSum: 2c697c89 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: c6e40866 | NumContArr: 8ffb2756 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2dc3124f6
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3498.910 ; gain = 189.945 ; free physical = 1607 ; free virtual = 12420
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2dc3124f6
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3498.910 ; gain = 189.945 ; free physical = 1608 ; free virtual = 12420
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2dc3124f6
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3498.910 ; gain = 189.945 ; free physical = 1608 ; free virtual = 12420
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 29b99456b
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 3567.668 ; gain = 258.703 ; free physical = 1529 ; free virtual = 12343
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.533 | TNS=0.000 | WHS=-0.147 | THS=-17.211|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.000344164 %
+ Global Horizontal Routing Utilization = 0.000132188 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 1011
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 1001
+ Number of Partially Routed Nets = 10
+ Number of Node Overlaps = 5
+
+Phase 2 Router Initialization | Checksum: 275108769
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12335
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 275108769
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12335
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 25ae08356
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12336
+Phase 4 Initial Routing | Checksum: 25ae08356
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12336
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 241
+ Number of Nodes with overlaps = 113
+ Number of Nodes with overlaps = 64
+ Number of Nodes with overlaps = 48
+ Number of Nodes with overlaps = 29
+ Number of Nodes with overlaps = 21
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.059 | TNS=-0.059 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 28b704ddd
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 5.2 Global Iteration 1
+ Number of Nodes with overlaps = 31
+ Number of Nodes with overlaps = 30
+ Number of Nodes with overlaps = 18
+ Number of Nodes with overlaps = 10
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.247 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.2 Global Iteration 1 | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+Phase 5 Rip-up And Reroute | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+Phase 6 Delay and Skew Optimization | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.340 | TNS=0.000 | WHS=0.142 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+Phase 7 Post Hold Fix | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0778621 %
+ Global Horizontal Routing Utilization = 0.099967 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 202c526cf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 202c526cf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.340 | TNS=0.000 | WHS=0.142 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 202c526cf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+Total Elapsed time in route_design: 26.43 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: f4216adf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: f4216adf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+88 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:27 . Memory (MB): peak = 3575.059 ; gain = 274.098 ; free physical = 1524 ; free virtual = 12338
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+108 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1501 ; free virtual = 12316
+Wrote PlaceDB: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1499 ; free virtual = 12316
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1508 ; free virtual = 12325
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1508 ; free virtual = 12325
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1508 ; free virtual = 12325
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1507 ; free virtual = 12325
+Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1507 ; free virtual = 12325
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+Command: write_bitstream -force audioProc.bit -bin_file
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./audioProc.bit...
+Writing bitstream ./audioProc.bin...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+119 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3915.926 ; gain = 252.824 ; free physical = 1128 ; free virtual = 11967
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 18 16:56:35 2025...
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5841840e6f2e76ca2ee66cf39f4b00efa13ae849
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:56:20 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..0e7122da3afd099da521255a2b05fc24a22a4440
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..2d65421eebe93bf0e65be9b6a0a6f5a0652fa9c1
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
@@ -0,0 +1,252 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:56:21 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Device Cell Placement Summary for Global Clock g1
+8. Device Cell Placement Summary for Global Clock g2
+9. Device Cell Placement Summary for Global Clock g3
+10. Clock Region Cell Placement per Global Clock: Region X1Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 120 | 0 | 0 | 0 |
+| BUFIO | 0 | 40 | 0 | 0 | 0 |
+| BUFMR | 0 | 20 | 0 | 0 | 0 |
+| BUFR | 0 | 40 | 0 | 0 | 0 |
+| MMCM | 1 | 10 | 0 | 0 | 0 |
+| PLL | 0 | 10 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 459 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1 |
+| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 1 | 120 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/clkout4_buf/O | clk_1/inst/clk_out4 |
+| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/clkf_buf/O | clk_1/inst/clkfbout_buf_clk_wiz_0 |
+| g3 | src3 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 0 | 1 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/clkout3_buf/O | clk_1/inst/clk_out3 |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT0 | clk_1/inst/clk_out1_clk_wiz_0 |
+| src1 | g1 | MMCME2_ADV/CLKOUT3 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT3 | clk_1/inst/clk_out4_clk_wiz_0 |
+| src2 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKFBOUT | clk_1/inst/clkfbout_clk_wiz_0 |
+| src3 | g3 | MMCME2_ADV/CLKOUT2 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT2 | clk_1/inst/clk_out3_clk_wiz_0 |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
+| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y2 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 579 | 4000 | 245 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
+| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y4 | 0 | 0 |
+| Y3 | 0 | 0 |
+| Y2 | 0 | 0 |
+| Y1 | 0 | 0 |
+| Y0 | 0 | 0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+| g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 10.000 | {0.000 5.000} | 459 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 459 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+7. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| g1 | BUFG/O | n/a | clk_out4_clk_wiz_0 | 20.000 | {0.000 10.000} | 120 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 120 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+8. Device Cell Placement Summary for Global Clock g2
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+| g2 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | 0 | 0 | 1 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+9. Device Cell Placement Summary for Global Clock g3
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| g3 | BUFG/O | n/a | clk_out3_clk_wiz_0 | 83.333 | {0.000 41.667} | 0 | 1 | 0 | 0 | clk_1/inst/clk_out3 |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+10. Clock Region Cell Placement per Global Clock: Region X1Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+| g0 | n/a | BUFG/O | None | 459 | 0 | 459 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
+| g1 | n/a | BUFG/O | None | 120 | 0 | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
+| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
+| g3 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out3 |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y3 [get_cells clk_1/inst/clkf_buf]
+set_property LOC BUFGCTRL_X0Y2 [get_cells clk_1/inst/clkout4_buf]
+set_property LOC BUFGCTRL_X0Y0 [get_cells clk_1/inst/clkout3_buf]
+set_property LOC BUFGCTRL_X0Y1 [get_cells clk_1/inst/clkout1_buf]
+
+# Location of IO Primitives which is load of clock spine
+set_property LOC IOB_X1Y118 [get_cells ac_mclk_OBUF_inst]
+
+# Location of clock ports
+set_property LOC IOB_X1Y124 [get_ports CLK100MHZ]
+
+# Clock net "clk_1/inst/clk_out4" driven by instance "clk_1/inst/clkout4_buf" located at site "BUFGCTRL_X0Y2"
+#startgroup
+create_pblock {CLKAG_clk_1/inst/clk_out4}
+add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out4"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
+
+# Clock net "clk_1/inst/clk_out1" driven by instance "clk_1/inst/clkout1_buf" located at site "BUFGCTRL_X0Y1"
+#startgroup
+create_pblock {CLKAG_clk_1/inst/clk_out1}
+add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out1"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
diff --git a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d09d09a9def7cf6b0b6494a008100e77cdeed1a4
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
@@ -0,0 +1,109 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:55:49 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+| Design : audioProc
+| Device : xc7a200t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 31 |
+| Minimum number of control sets | 31 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 83 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 31 |
+| >= 0 to < 4 | 1 |
+| >= 4 to < 6 | 9 |
+| >= 6 to < 8 | 5 |
+| >= 8 to < 10 | 3 |
+| >= 10 to < 12 | 1 |
+| >= 12 to < 14 | 1 |
+| >= 14 to < 16 | 0 |
+| >= 16 | 11 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 34 | 20 |
+| No | No | Yes | 10 | 5 |
+| No | Yes | No | 44 | 14 |
+| Yes | No | No | 63 | 24 |
+| Yes | No | Yes | 310 | 100 |
+| Yes | Yes | No | 128 | 35 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++-------------------------------------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++-------------------------------------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| clk_1/inst/clk_out1 | dbuttons/IV[2]_i_1_n_0 | | 1 | 1 | 1.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[5]_i_1_n_0 | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | initialize_audio/initWord[23]_i_1_n_0 | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out1 | lrclkcnt[3]_i_2_n_0 | lrclkcnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0 | | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out1 | | audio_inout/Cnt_Bclk[4]_i_1_n_0 | 2 | 5 | 2.50 |
+| rightFir/firUnit_1/controlUnit_1/SR_futurState | | | 2 | 5 | 2.50 |
+| leftFir/firUnit_1/controlUnit_1/SR_futurState | | | 3 | 5 | 1.67 |
+| clk_1/inst/clk_out1 | audio_inout/BCLK_Fall_int | rightFir/firUnit_1/operativeUnit_1/AR[0] | 2 | 5 | 2.50 |
+| clk_1/inst/clk_out1 | | | 4 | 6 | 1.50 |
+| clk_1/inst/clk_out4 | rstn_IBUF | | 3 | 6 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0 | initialize_audio/twi_controller/sclCnt0 | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/state_reg[3][0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | | initialize_audio/twi_controller/busFreeCnt0 | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/dataByte[7]_i_1_n_0 | | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[2] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[2] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out1 | | rightFir/firUnit_1/operativeUnit_1/AR[0] | 5 | 10 | 2.00 |
+| clk_1/inst/clk_out1 | dbuttons/cnt2 | dbuttons/cnt2[12]_i_1_n_0 | 4 | 13 | 3.25 |
+| clk_1/inst/clk_out4 | | | 11 | 18 | 1.64 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | | 7 | 19 | 2.71 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 8 | 19 | 2.38 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 6 | 19 | 3.17 |
+| clk_1/inst/clk_out1 | audio_inout/D_L_O_int | rightFir/firUnit_1/operativeUnit_1/AR[0] | 6 | 24 | 4.00 |
+| clk_1/inst/clk_out1 | audio_inout/D_R_O_int[23]_i_1_n_0 | rightFir/firUnit_1/operativeUnit_1/AR[0] | 5 | 24 | 4.80 |
+| clk_1/inst/clk_out1 | audio_inout/Data_Out_int[31]_i_1_n_0 | | 9 | 25 | 2.78 |
+| clk_1/inst/clk_out4 | | initialize_audio/delaycnt0 | 9 | 32 | 3.56 |
+| clk_1/inst/clk_out1 | audio_inout/p_4_in | audio_inout/Data_In_int[31]_i_1_n_0 | 6 | 32 | 5.33 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 39 | 128 | 3.28 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 41 | 128 | 3.12 |
++-------------------------------------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..e5044e7c51a5bdf4b629cc8fbbc22d7e25e18bc5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:55:41 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..f0c1cb2d00d7347420959479be2b38f9c51da16f
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..cb5bb3226dc0fb7cffeddb74a85bce825dc47e0a
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..4bba8878fab3fcb6af2393d0acada77e4136b511
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
@@ -0,0 +1,60 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:56:19 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 3
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+| PDRC-153 | Warning | Gated clock check | 2 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+PDRC-153#1 Warning
+Gated clock check
+Net leftFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Related violations: <none>
+
+PDRC-153#2 Warning
+Gated clock check
+Net rightFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..4bf2dab85431efc2aa1288865f01f9efa0be72a9
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f5f5bc7466dd7e904ae9b4fe8f25bee98b7277ff
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
@@ -0,0 +1,526 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:55:50 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_io -file audioProc_io_placed.rpt
+| Design : audioProc
+| Device : xc7a200t
+| Speed File : -1
+| Package : sbg484
+| Package Version : FINAL 2012-06-12
+| Package Pin Delay Version : VERS. 2.0 2012-06-12
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 25 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA21 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B22 | BTNC | High Range | IO_L20N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| C2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| C22 | BTNL | High Range | IO_L20P_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D14 | BTNR | High Range | IO_L6P_T0_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D22 | BTND | High Range | IO_L22N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E22 | sw | High Range | IO_L22P_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
+| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F15 | BTNU | High Range | IO_0_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | rstn | High Range | IO_L12N_T1_MRCC_35 | INPUT | LVCMOS15 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| G22 | sw3 | High Range | IO_L24N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| H17 | sw4 | High Range | IO_L6P_T0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | sw5 | High Range | IO_0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | sw6 | High Range | IO_L19P_T3_A22_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M17 | sw7 | High Range | IO_25_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| P19 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | CLK100MHZ | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | ac_adc_sdata | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| T5 | ac_bclk | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T20 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U5 | ac_lrclk | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U6 | ac_mclk | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U16 | led3 | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U21 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V5 | sda | High Range | IO_L16N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V15 | led4 | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W5 | scl | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W6 | ac_dac_sdata | High Range | IO_L15P_T2_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W15 | led6 | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W16 | led5 | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y13 | led7 | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..d77b02cd75c030eef1e2a80571c7bffdeeab233c
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..aac88211a9c328f5ca2b5043a2f0dd78c2359938
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
@@ -0,0 +1,147 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:56:19 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 22
++-----------+----------+--------------------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+----------+--------------------------------+------------+
+| TIMING-18 | Warning | Missing input or output delay | 11 |
+| TIMING-20 | Warning | Non-clocked latch | 10 |
+| LATCH-1 | Advisory | Existing latches in the design | 1 |
++-----------+----------+--------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-18#1 Warning
+Missing input or output delay
+An input delay is missing on BTNC relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay
+An input delay is missing on ac_adc_sdata relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay
+An input delay is missing on rstn relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay
+An input delay is missing on sw3 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay
+An input delay is missing on sw4 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay
+An input delay is missing on sw5 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay
+An input delay is missing on sw6 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#8 Warning
+Missing input or output delay
+An input delay is missing on sw7 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#9 Warning
+Missing input or output delay
+An output delay is missing on ac_bclk relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#10 Warning
+Missing input or output delay
+An output delay is missing on ac_dac_sdata relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#11 Warning
+Missing input or output delay
+An output delay is missing on ac_lrclk relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-20#1 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#2 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#3 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#4 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#5 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#6 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#7 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#8 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#9 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#10 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]/G is not reached by a timing clock
+Related violations: <none>
+
+LATCH-1#1 Advisory
+Existing latches in the design
+There are 10 latches found in the design. Inferred latches are often the result of HDL coding mistakes, such as incomplete if or case statements.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..551b780d595cbc16aac465cd000dd0cfc9498e94
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..c0e7a56b198984760682d55f375e0808b067f923
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..d8a34f51f293e6719cbf5dbf814ea1b10009e2e7
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3d0f98be30655f6f5d99daccf88feeba5b287dea
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
@@ -0,0 +1,160 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:56:20 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 0.249 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 0.097 |
+| Device Static (W) | 0.151 |
+| Effective TJA (C/W) | 3.3 |
+| Max Ambient (C) | 84.2 |
+| Junction Temperature (C) | 25.8 |
+| Confidence Level | Low |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks | 0.003 | 7 | --- | --- |
+| Slice Logic | 0.001 | 1354 | --- | --- |
+| LUT as Logic | 0.001 | 582 | 133800 | 0.43 |
+| CARRY4 | <0.001 | 38 | 33450 | 0.11 |
+| Register | <0.001 | 589 | 267600 | 0.22 |
+| F7/F8 Muxes | <0.001 | 49 | 133800 | 0.04 |
+| Others | 0.000 | 23 | --- | --- |
+| Signals | 0.001 | 1013 | --- | --- |
+| MMCM | 0.085 | 1 | 10 | 10.00 |
+| I/O | 0.006 | 20 | 285 | 7.02 |
+| Static Power | 0.151 | | | |
+| Total | 0.249 | | | |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.037 | 0.007 | 0.031 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.078 | 0.047 | 0.031 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | High | User specified more than 95% of clocks | |
+| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Low | | |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 3.3 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++--------------------+-------------------------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++--------------------+-------------------------------+-----------------+
+| CLK100MHZ | CLK100MHZ | 10.0 |
+| clk_out1_clk_wiz_0 | clk_1/inst/clk_out1_clk_wiz_0 | 10.0 |
+| clk_out3_clk_wiz_0 | clk_1/inst/clk_out3_clk_wiz_0 | 83.3 |
+| clk_out4_clk_wiz_0 | clk_1/inst/clk_out4_clk_wiz_0 | 20.0 |
+| clkfbout_clk_wiz_0 | clk_1/inst/clkfbout_clk_wiz_0 | 10.0 |
++--------------------+-------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-----------------------+-----------+
+| Name | Power (W) |
++-----------------------+-----------+
+| audioProc | 0.097 |
+| clk_1 | 0.086 |
+| inst | 0.086 |
+| leftFir | 0.001 |
+| firUnit_1 | 0.001 |
+| operativeUnit_1 | 0.001 |
+| rightFir | 0.001 |
+| firUnit_1 | 0.001 |
+| operativeUnit_1 | 0.001 |
++-----------------------+-----------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..f2154f99fba6c1ae46e55b1b4898e75e75851ace
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..df00f8288dac80ef6f28b3cbb42d633093e1c749
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..0595fb58220ab86edee07852d5e1f5b4a6a9db91
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 1503 :
+ # of nets not needing routing.......... : 479 :
+ # of internally routed nets........ : 479 :
+ # of routable nets..................... : 1024 :
+ # of fully routed nets............. : 1024 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..027cc4df05df8c64b47b8ed7e5dbeb7ddd3b784b
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..da21b74859f6025f93fc5ada237fa4b131a53d16
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a381016fa5df66bd9fb7801e4a24e546f2e8c5b5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
@@ -0,0 +1,3150 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:56:20 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+ Inter-SLR Compensation : Conservative
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule Severity Description Violations
+--------- -------- ------------------------------ ----------
+TIMING-18 Warning Missing input or output delay 11
+TIMING-20 Warning Non-clocked latch 10
+LATCH-1 Advisory Existing latches in the design 1
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (50)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (10)
+5. checking no_input_delay (10)
+6. checking no_output_delay (5)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (50)
+-------------------------
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[1]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[2]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[3]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[1]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[2]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[3]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/Q (HIGH)
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (10)
+-------------------------------------------------
+ There are 10 pins that are not constrained for maximum delay. (HIGH)
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (10)
+-------------------------------
+ There are 10 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (5)
+-------------------------------
+ There are 5 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 0.368 0.000 0 1164 0.147 0.000 0 1164 3.000 0.000 0 589
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+CLK100MHZ {0.000 5.000} 10.000 100.000
+ clk_out1_clk_wiz_0 {0.000 5.000} 10.000 100.000
+ clk_out3_clk_wiz_0 {0.000 41.667} 83.333 12.000
+ clk_out4_clk_wiz_0 {0.000 10.000} 20.000 50.000
+ clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+CLK100MHZ 3.000 0.000 0 1
+ clk_out1_clk_wiz_0 0.368 0.000 0 939 0.153 0.000 0 939 4.500 0.000 0 461
+ clk_out3_clk_wiz_0 81.178 0.000 0 2
+ clk_out4_clk_wiz_0 14.860 0.000 0 225 0.147 0.000 0 225 9.500 0.000 0 122
+ clkfbout_clk_wiz_0 7.845 0.000 0 3
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: CLK100MHZ
+ To Clock: CLK100MHZ
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: CLK100MHZ
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { CLK100MHZ }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0
+ To Clock: clk_out1_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 0.368ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.153ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.368ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.561ns (logic 4.380ns (45.812%) route 5.181ns (54.188%))
+ Logic Levels: 14 (CARRY4=5 LUT2=2 LUT3=1 LUT4=2 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.020ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.596ns = ( 8.404 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y125 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y125 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.224 0.671 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X155Y126 LUT6 (Prop_lut6_I2_O) 0.124 0.795 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_19__0/O
+ net (fo=1, routed) 0.000 0.795 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_19__0_n_0
+ SLICE_X155Y126 MUXF7 (Prop_muxf7_I1_O) 0.217 1.012 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_11__0/O
+ net (fo=1, routed) 0.000 1.012 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_11__0_n_0
+ SLICE_X155Y126 MUXF8 (Prop_muxf8_I1_O) 0.094 1.106 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_6__0/O
+ net (fo=10, routed) 0.946 2.052 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[6]
+ SLICE_X161Y122 LUT5 (Prop_lut5_I0_O) 0.316 2.368 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_11__0/O
+ net (fo=2, routed) 0.446 2.815 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_11__0_n_0
+ SLICE_X158Y122 LUT3 (Prop_lut3_I2_O) 0.124 2.939 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_1__0/O
+ net (fo=2, routed) 0.829 3.767 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_1__0_n_0
+ SLICE_X156Y121 LUT4 (Prop_lut4_I0_O) 0.124 3.891 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_5__0/O
+ net (fo=1, routed) 0.000 3.891 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_5__0_n_0
+ SLICE_X156Y121 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 4.292 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.292 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X156Y122 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.626 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.663 5.289 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X156Y124 LUT4 (Prop_lut4_I0_O) 0.303 5.592 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5__0/O
+ net (fo=1, routed) 0.000 5.592 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5__0_n_0
+ SLICE_X156Y124 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.993 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.009 6.002 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X156Y125 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.336 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.710 7.046 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X157Y126 LUT2 (Prop_lut2_I0_O) 0.303 7.349 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3__0/O
+ net (fo=1, routed) 0.000 7.349 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3__0_n_0
+ SLICE_X157Y126 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 7.896 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[2]
+ net (fo=1, routed) 0.354 8.250 rightFir/firUnit_1/operativeUnit_1/SC_addResult[14]
+ SLICE_X156Y126 LUT2 (Prop_lut2_I0_O) 0.302 8.552 r rightFir/firUnit_1/operativeUnit_1/SR_sum[14]_i_1__0/O
+ net (fo=1, routed) 0.000 8.552 rightFir/firUnit_1/operativeUnit_1/p_1_in[14]
+ SLICE_X156Y126 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.696 8.404 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y126 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/C
+ clock pessimism 0.568 8.971
+ clock uncertainty -0.084 8.888
+ SLICE_X156Y126 FDCE (Setup_fdce_C_D) 0.032 8.920 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]
+ -------------------------------------------------------------------
+ required time 8.920
+ arrival time -8.552
+ -------------------------------------------------------------------
+ slack 0.368
+
+Slack (MET) : 0.427ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.501ns (logic 4.258ns (44.815%) route 5.243ns (55.185%))
+ Logic Levels: 14 (CARRY4=5 LUT2=2 LUT3=1 LUT4=2 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.019ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.595ns = ( 8.405 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y125 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y125 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.224 0.671 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X155Y126 LUT6 (Prop_lut6_I2_O) 0.124 0.795 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_19__0/O
+ net (fo=1, routed) 0.000 0.795 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_19__0_n_0
+ SLICE_X155Y126 MUXF7 (Prop_muxf7_I1_O) 0.217 1.012 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_11__0/O
+ net (fo=1, routed) 0.000 1.012 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_11__0_n_0
+ SLICE_X155Y126 MUXF8 (Prop_muxf8_I1_O) 0.094 1.106 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_6__0/O
+ net (fo=10, routed) 0.946 2.052 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[6]
+ SLICE_X161Y122 LUT5 (Prop_lut5_I0_O) 0.316 2.368 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_11__0/O
+ net (fo=2, routed) 0.446 2.815 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_11__0_n_0
+ SLICE_X158Y122 LUT3 (Prop_lut3_I2_O) 0.124 2.939 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_1__0/O
+ net (fo=2, routed) 0.829 3.767 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_1__0_n_0
+ SLICE_X156Y121 LUT4 (Prop_lut4_I0_O) 0.124 3.891 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_5__0/O
+ net (fo=1, routed) 0.000 3.891 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_5__0_n_0
+ SLICE_X156Y121 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 4.292 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.292 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X156Y122 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.626 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.663 5.289 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X156Y124 LUT4 (Prop_lut4_I0_O) 0.303 5.592 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5__0/O
+ net (fo=1, routed) 0.000 5.592 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5__0_n_0
+ SLICE_X156Y124 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.993 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.009 6.002 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X156Y125 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.336 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.710 7.046 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X157Y126 LUT2 (Prop_lut2_I0_O) 0.303 7.349 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3__0/O
+ net (fo=1, routed) 0.000 7.349 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3__0_n_0
+ SLICE_X157Y126 CARRY4 (Prop_carry4_S[0]_O[1])
+ 0.424 7.773 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[1]
+ net (fo=1, routed) 0.416 8.189 rightFir/firUnit_1/operativeUnit_1/SC_addResult[13]
+ SLICE_X159Y127 LUT2 (Prop_lut2_I0_O) 0.303 8.492 r rightFir/firUnit_1/operativeUnit_1/SR_sum[13]_i_1__0/O
+ net (fo=1, routed) 0.000 8.492 rightFir/firUnit_1/operativeUnit_1/p_1_in[13]
+ SLICE_X159Y127 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.697 8.405 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y127 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/C
+ clock pessimism 0.568 8.972
+ clock uncertainty -0.084 8.889
+ SLICE_X159Y127 FDCE (Setup_fdce_C_D) 0.031 8.920 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]
+ -------------------------------------------------------------------
+ required time 8.920
+ arrival time -8.492
+ -------------------------------------------------------------------
+ slack 0.427
+
+Slack (MET) : 0.562ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.411ns (logic 4.902ns (52.089%) route 4.509ns (47.911%))
+ Logic Levels: 14 (CARRY4=6 LUT2=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.669ns = ( 8.331 - 10.000 )
+ Source Clock Delay (SCD): -1.076ns
+ Clock Pessimism Removal (CPR): 0.569ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.743 -1.076 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y130 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X146Y130 FDCE (Prop_fdce_C_Q) 0.478 -0.598 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/Q
+ net (fo=2, routed) 1.108 0.511 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_6[4]
+ SLICE_X143Y129 LUT6 (Prop_lut6_I1_O) 0.301 0.812 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_25/O
+ net (fo=1, routed) 0.000 0.812 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_25_n_0
+ SLICE_X143Y129 MUXF7 (Prop_muxf7_I1_O) 0.245 1.057 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_16/O
+ net (fo=1, routed) 0.000 1.057 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_16_n_0
+ SLICE_X143Y129 MUXF8 (Prop_muxf8_I0_O) 0.104 1.161 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_10/O
+ net (fo=8, routed) 0.899 2.059 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[4]
+ SLICE_X143Y128 LUT5 (Prop_lut5_I0_O) 0.344 2.403 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_17/O
+ net (fo=3, routed) 0.524 2.927 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_17_n_0
+ SLICE_X142Y126 LUT3 (Prop_lut3_I2_O) 0.326 3.253 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_3/O
+ net (fo=1, routed) 0.379 3.632 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_3_n_0
+ SLICE_X143Y126 CARRY4 (Prop_carry4_DI[1]_CO[3])
+ 0.507 4.139 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.139 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X143Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.473 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.796 5.269 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X145Y127 LUT4 (Prop_lut4_I0_O) 0.303 5.572 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5/O
+ net (fo=1, routed) 0.000 5.572 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5_n_0
+ SLICE_X145Y127 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.973 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.973 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X145Y128 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 6.195 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[0]
+ net (fo=2, routed) 0.448 6.643 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[11]
+ SLICE_X147Y127 LUT2 (Prop_lut2_I0_O) 0.299 6.942 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_1/O
+ net (fo=1, routed) 0.000 6.942 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_1_n_0
+ SLICE_X147Y127 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 7.343 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/CO[3]
+ net (fo=1, routed) 0.000 7.343 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_n_0
+ SLICE_X147Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 7.677 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[1]
+ net (fo=1, routed) 0.355 8.032 leftFir/firUnit_1/operativeUnit_1/SC_addResult[13]
+ SLICE_X146Y128 LUT2 (Prop_lut2_I0_O) 0.303 8.335 r leftFir/firUnit_1/operativeUnit_1/SR_sum[13]_i_1/O
+ net (fo=1, routed) 0.000 8.335 leftFir/firUnit_1/operativeUnit_1/p_1_in[13]
+ SLICE_X146Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.623 8.331 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/C
+ clock pessimism 0.569 8.899
+ clock uncertainty -0.084 8.816
+ SLICE_X146Y128 FDCE (Setup_fdce_C_D) 0.081 8.897 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]
+ -------------------------------------------------------------------
+ required time 8.897
+ arrival time -8.335
+ -------------------------------------------------------------------
+ slack 0.562
+
+Slack (MET) : 0.590ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.338ns (logic 4.077ns (43.662%) route 5.261ns (56.338%))
+ Logic Levels: 14 (CARRY4=5 LUT2=2 LUT3=1 LUT4=2 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.020ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.596ns = ( 8.404 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y125 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y125 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.224 0.671 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X155Y126 LUT6 (Prop_lut6_I2_O) 0.124 0.795 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_19__0/O
+ net (fo=1, routed) 0.000 0.795 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_19__0_n_0
+ SLICE_X155Y126 MUXF7 (Prop_muxf7_I1_O) 0.217 1.012 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_11__0/O
+ net (fo=1, routed) 0.000 1.012 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_11__0_n_0
+ SLICE_X155Y126 MUXF8 (Prop_muxf8_I1_O) 0.094 1.106 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_i_6__0/O
+ net (fo=10, routed) 0.946 2.052 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[6]
+ SLICE_X161Y122 LUT5 (Prop_lut5_I0_O) 0.316 2.368 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_11__0/O
+ net (fo=2, routed) 0.446 2.815 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_11__0_n_0
+ SLICE_X158Y122 LUT3 (Prop_lut3_I2_O) 0.124 2.939 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_1__0/O
+ net (fo=2, routed) 0.829 3.767 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_1__0_n_0
+ SLICE_X156Y121 LUT4 (Prop_lut4_I0_O) 0.124 3.891 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_5__0/O
+ net (fo=1, routed) 0.000 3.891 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_5__0_n_0
+ SLICE_X156Y121 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 4.292 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.292 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X156Y122 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.626 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.663 5.289 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X156Y124 LUT4 (Prop_lut4_I0_O) 0.303 5.592 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5__0/O
+ net (fo=1, routed) 0.000 5.592 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5__0_n_0
+ SLICE_X156Y124 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.993 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.009 6.002 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X156Y125 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.336 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.710 7.046 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X157Y126 LUT2 (Prop_lut2_I0_O) 0.303 7.349 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3__0/O
+ net (fo=1, routed) 0.000 7.349 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3__0_n_0
+ SLICE_X157Y126 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.247 7.596 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[0]
+ net (fo=1, routed) 0.434 8.030 rightFir/firUnit_1/operativeUnit_1/SC_addResult[12]
+ SLICE_X156Y126 LUT2 (Prop_lut2_I0_O) 0.299 8.329 r rightFir/firUnit_1/operativeUnit_1/SR_sum[12]_i_1__0/O
+ net (fo=1, routed) 0.000 8.329 rightFir/firUnit_1/operativeUnit_1/p_1_in[12]
+ SLICE_X156Y126 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.696 8.404 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y126 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/C
+ clock pessimism 0.568 8.971
+ clock uncertainty -0.084 8.888
+ SLICE_X156Y126 FDCE (Setup_fdce_C_D) 0.031 8.919 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]
+ -------------------------------------------------------------------
+ required time 8.919
+ arrival time -8.329
+ -------------------------------------------------------------------
+ slack 0.590
+
+Slack (MET) : 0.657ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.314ns (logic 4.806ns (51.602%) route 4.508ns (48.398%))
+ Logic Levels: 14 (CARRY4=6 LUT2=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.669ns = ( 8.331 - 10.000 )
+ Source Clock Delay (SCD): -1.076ns
+ Clock Pessimism Removal (CPR): 0.569ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.743 -1.076 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y130 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X146Y130 FDCE (Prop_fdce_C_Q) 0.478 -0.598 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/Q
+ net (fo=2, routed) 1.108 0.511 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_6[4]
+ SLICE_X143Y129 LUT6 (Prop_lut6_I1_O) 0.301 0.812 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_25/O
+ net (fo=1, routed) 0.000 0.812 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_25_n_0
+ SLICE_X143Y129 MUXF7 (Prop_muxf7_I1_O) 0.245 1.057 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_16/O
+ net (fo=1, routed) 0.000 1.057 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_16_n_0
+ SLICE_X143Y129 MUXF8 (Prop_muxf8_I0_O) 0.104 1.161 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_10/O
+ net (fo=8, routed) 0.899 2.059 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[4]
+ SLICE_X143Y128 LUT5 (Prop_lut5_I0_O) 0.344 2.403 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_17/O
+ net (fo=3, routed) 0.524 2.927 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_17_n_0
+ SLICE_X142Y126 LUT3 (Prop_lut3_I2_O) 0.326 3.253 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_3/O
+ net (fo=1, routed) 0.379 3.632 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_3_n_0
+ SLICE_X143Y126 CARRY4 (Prop_carry4_DI[1]_CO[3])
+ 0.507 4.139 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.139 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X143Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.473 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.796 5.269 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X145Y127 LUT4 (Prop_lut4_I0_O) 0.303 5.572 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5/O
+ net (fo=1, routed) 0.000 5.572 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5_n_0
+ SLICE_X145Y127 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.973 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.973 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X145Y128 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 6.195 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[0]
+ net (fo=2, routed) 0.448 6.643 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[11]
+ SLICE_X147Y127 LUT2 (Prop_lut2_I0_O) 0.299 6.942 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_1/O
+ net (fo=1, routed) 0.000 6.942 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_1_n_0
+ SLICE_X147Y127 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 7.343 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/CO[3]
+ net (fo=1, routed) 0.000 7.343 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_n_0
+ SLICE_X147Y128 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 7.582 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[2]
+ net (fo=1, routed) 0.353 7.936 leftFir/firUnit_1/operativeUnit_1/SC_addResult[14]
+ SLICE_X146Y128 LUT2 (Prop_lut2_I0_O) 0.302 8.238 r leftFir/firUnit_1/operativeUnit_1/SR_sum[14]_i_1/O
+ net (fo=1, routed) 0.000 8.238 leftFir/firUnit_1/operativeUnit_1/p_1_in[14]
+ SLICE_X146Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.623 8.331 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]/C
+ clock pessimism 0.569 8.899
+ clock uncertainty -0.084 8.816
+ SLICE_X146Y128 FDCE (Setup_fdce_C_D) 0.079 8.895 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[14]
+ -------------------------------------------------------------------
+ required time 8.895
+ arrival time -8.238
+ -------------------------------------------------------------------
+ slack 0.657
+
+Slack (MET) : 0.666ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.244ns (logic 4.786ns (51.775%) route 4.458ns (48.225%))
+ Logic Levels: 14 (CARRY4=6 LUT2=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.668ns = ( 8.332 - 10.000 )
+ Source Clock Delay (SCD): -1.076ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.743 -1.076 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y130 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X146Y130 FDCE (Prop_fdce_C_Q) 0.478 -0.598 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/Q
+ net (fo=2, routed) 1.108 0.511 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_6[4]
+ SLICE_X143Y129 LUT6 (Prop_lut6_I1_O) 0.301 0.812 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_25/O
+ net (fo=1, routed) 0.000 0.812 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_25_n_0
+ SLICE_X143Y129 MUXF7 (Prop_muxf7_I1_O) 0.245 1.057 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_16/O
+ net (fo=1, routed) 0.000 1.057 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_16_n_0
+ SLICE_X143Y129 MUXF8 (Prop_muxf8_I0_O) 0.104 1.161 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__29_carry__0_i_10/O
+ net (fo=8, routed) 0.899 2.059 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[4]
+ SLICE_X143Y128 LUT5 (Prop_lut5_I0_O) 0.344 2.403 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_17/O
+ net (fo=3, routed) 0.524 2.927 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_17_n_0
+ SLICE_X142Y126 LUT3 (Prop_lut3_I2_O) 0.326 3.253 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_3/O
+ net (fo=1, routed) 0.379 3.632 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_3_n_0
+ SLICE_X143Y126 CARRY4 (Prop_carry4_DI[1]_CO[3])
+ 0.507 4.139 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.139 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X143Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.473 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.796 5.269 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X145Y127 LUT4 (Prop_lut4_I0_O) 0.303 5.572 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5/O
+ net (fo=1, routed) 0.000 5.572 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_5_n_0
+ SLICE_X145Y127 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.973 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.973 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X145Y128 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 6.195 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[0]
+ net (fo=2, routed) 0.448 6.643 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[11]
+ SLICE_X147Y127 LUT2 (Prop_lut2_I0_O) 0.299 6.942 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_1/O
+ net (fo=1, routed) 0.000 6.942 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_1_n_0
+ SLICE_X147Y127 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 7.343 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/CO[3]
+ net (fo=1, routed) 0.000 7.343 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_n_0
+ SLICE_X147Y128 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 7.565 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[0]
+ net (fo=1, routed) 0.304 7.869 leftFir/firUnit_1/operativeUnit_1/SC_addResult[12]
+ SLICE_X149Y128 LUT2 (Prop_lut2_I0_O) 0.299 8.168 r leftFir/firUnit_1/operativeUnit_1/SR_sum[12]_i_1/O
+ net (fo=1, routed) 0.000 8.168 leftFir/firUnit_1/operativeUnit_1/p_1_in[12]
+ SLICE_X149Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.624 8.332 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X149Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/C
+ clock pessimism 0.554 8.885
+ clock uncertainty -0.084 8.802
+ SLICE_X149Y128 FDCE (Setup_fdce_C_D) 0.032 8.834 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]
+ -------------------------------------------------------------------
+ required time 8.834
+ arrival time -8.168
+ -------------------------------------------------------------------
+ slack 0.666
+
+Slack (MET) : 0.778ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[10]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.195ns (logic 4.387ns (47.713%) route 4.808ns (52.287%))
+ Logic Levels: 12 (CARRY4=4 LUT2=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.021ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.671ns = ( 8.329 - 10.000 )
+ Source Clock Delay (SCD): -1.082ns
+ Clock Pessimism Removal (CPR): 0.569ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.737 -1.082 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y126 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X146Y126 FDCE (Prop_fdce_C_Q) 0.518 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.149 0.585 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.124 0.709 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25/O
+ net (fo=1, routed) 0.000 0.709 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I1_O) 0.214 0.923 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17/O
+ net (fo=1, routed) 0.000 0.923 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I1_O) 0.088 1.011 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_11/O
+ net (fo=10, routed) 0.704 1.715 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[1]
+ SLICE_X144Y124 LUT5 (Prop_lut5_I0_O) 0.319 2.034 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9/O
+ net (fo=3, routed) 0.801 2.835 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9_n_0
+ SLICE_X143Y124 LUT3 (Prop_lut3_I1_O) 0.153 2.988 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_1/O
+ net (fo=1, routed) 0.365 3.353 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_1_n_0
+ SLICE_X143Y125 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.588 3.941 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry/CO[3]
+ net (fo=1, routed) 0.000 3.941 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_n_0
+ SLICE_X143Y126 CARRY4 (Prop_carry4_CI_O[3])
+ 0.313 4.254 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[3]
+ net (fo=4, routed) 0.812 5.066 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_4
+ SLICE_X145Y127 LUT4 (Prop_lut4_I1_O) 0.306 5.372 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_7/O
+ net (fo=1, routed) 0.000 5.372 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_7_n_0
+ SLICE_X145Y127 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.952 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/O[2]
+ net (fo=2, routed) 0.478 6.430 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X147Y127 LUT2 (Prop_lut2_I0_O) 0.302 6.732 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_3/O
+ net (fo=1, routed) 0.000 6.732 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_3_n_0
+ SLICE_X147Y127 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 7.312 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/O[2]
+ net (fo=1, routed) 0.499 7.811 leftFir/firUnit_1/operativeUnit_1/SC_addResult[10]
+ SLICE_X146Y127 LUT2 (Prop_lut2_I0_O) 0.302 8.113 r leftFir/firUnit_1/operativeUnit_1/SR_sum[10]_i_1/O
+ net (fo=1, routed) 0.000 8.113 leftFir/firUnit_1/operativeUnit_1/p_1_in[10]
+ SLICE_X146Y127 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[10]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.621 8.329 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y127 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[10]/C
+ clock pessimism 0.569 8.897
+ clock uncertainty -0.084 8.814
+ SLICE_X146Y127 FDCE (Setup_fdce_C_D) 0.077 8.891 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[10]
+ -------------------------------------------------------------------
+ required time 8.891
+ arrival time -8.113
+ -------------------------------------------------------------------
+ slack 0.778
+
+Slack (MET) : 0.796ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.130ns (logic 4.453ns (48.775%) route 4.677ns (51.225%))
+ Logic Levels: 11 (CARRY4=4 LUT2=1 LUT3=2 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.020ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.596ns = ( 8.404 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y125 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y125 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.290 0.738 rightFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X160Y121 LUT6 (Prop_lut6_I2_O) 0.124 0.862 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25__0/O
+ net (fo=1, routed) 0.000 0.862 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25__0_n_0
+ SLICE_X160Y121 MUXF7 (Prop_muxf7_I1_O) 0.217 1.079 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17__0/O
+ net (fo=1, routed) 0.000 1.079 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17__0_n_0
+ SLICE_X160Y121 MUXF8 (Prop_muxf8_I1_O) 0.094 1.173 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_11__0/O
+ net (fo=10, routed) 0.758 1.930 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[1]
+ SLICE_X157Y121 LUT5 (Prop_lut5_I0_O) 0.310 2.240 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9__0/O
+ net (fo=3, routed) 0.599 2.839 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9__0_n_0
+ SLICE_X159Y120 LUT3 (Prop_lut3_I0_O) 0.351 3.190 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.347 3.537 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X156Y121 CARRY4 (Prop_carry4_DI[0]_O[2])
+ 0.764 4.301 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[2]
+ net (fo=2, routed) 0.572 4.873 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_5
+ SLICE_X156Y123 LUT3 (Prop_lut3_I2_O) 0.302 5.175 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry_i_1__0/O
+ net (fo=1, routed) 0.000 5.175 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry_i_1__0_n_0
+ SLICE_X156Y123 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.576 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry/CO[3]
+ net (fo=1, routed) 0.000 5.576 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry_n_0
+ SLICE_X156Y124 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 5.910 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/O[1]
+ net (fo=2, routed) 0.692 6.602 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[8]
+ SLICE_X157Y125 CARRY4 (Prop_carry4_DI[0]_O[3])
+ 0.794 7.396 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/O[3]
+ net (fo=1, routed) 0.419 7.815 rightFir/firUnit_1/operativeUnit_1/SC_addResult[11]
+ SLICE_X156Y126 LUT2 (Prop_lut2_I0_O) 0.306 8.121 r rightFir/firUnit_1/operativeUnit_1/SR_sum[11]_i_1__0/O
+ net (fo=1, routed) 0.000 8.121 rightFir/firUnit_1/operativeUnit_1/p_1_in[11]
+ SLICE_X156Y126 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.696 8.404 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y126 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]/C
+ clock pessimism 0.568 8.971
+ clock uncertainty -0.084 8.888
+ SLICE_X156Y126 FDCE (Setup_fdce_C_D) 0.029 8.917 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]
+ -------------------------------------------------------------------
+ required time 8.917
+ arrival time -8.121
+ -------------------------------------------------------------------
+ slack 0.796
+
+Slack (MET) : 0.862ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.114ns (logic 4.451ns (48.836%) route 4.663ns (51.164%))
+ Logic Levels: 12 (CARRY4=4 LUT2=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.021ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.671ns = ( 8.329 - 10.000 )
+ Source Clock Delay (SCD): -1.082ns
+ Clock Pessimism Removal (CPR): 0.569ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.737 -1.082 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y126 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X146Y126 FDCE (Prop_fdce_C_Q) 0.518 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.149 0.585 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.124 0.709 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25/O
+ net (fo=1, routed) 0.000 0.709 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I1_O) 0.214 0.923 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17/O
+ net (fo=1, routed) 0.000 0.923 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I1_O) 0.088 1.011 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_11/O
+ net (fo=10, routed) 0.704 1.715 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[1]
+ SLICE_X144Y124 LUT5 (Prop_lut5_I0_O) 0.319 2.034 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9/O
+ net (fo=3, routed) 0.801 2.835 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9_n_0
+ SLICE_X143Y124 LUT3 (Prop_lut3_I1_O) 0.153 2.988 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_1/O
+ net (fo=1, routed) 0.365 3.353 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_1_n_0
+ SLICE_X143Y125 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.588 3.941 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry/CO[3]
+ net (fo=1, routed) 0.000 3.941 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_n_0
+ SLICE_X143Y126 CARRY4 (Prop_carry4_CI_O[3])
+ 0.313 4.254 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[3]
+ net (fo=4, routed) 0.812 5.066 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_4
+ SLICE_X145Y127 LUT4 (Prop_lut4_I1_O) 0.306 5.372 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_7/O
+ net (fo=1, routed) 0.000 5.372 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_7_n_0
+ SLICE_X145Y127 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.952 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/O[2]
+ net (fo=2, routed) 0.478 6.430 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X147Y127 LUT2 (Prop_lut2_I0_O) 0.302 6.732 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_3/O
+ net (fo=1, routed) 0.000 6.732 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_i_3_n_0
+ SLICE_X147Y127 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 7.372 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/O[3]
+ net (fo=1, routed) 0.354 7.726 leftFir/firUnit_1/operativeUnit_1/SC_addResult[11]
+ SLICE_X146Y127 LUT2 (Prop_lut2_I0_O) 0.306 8.032 r leftFir/firUnit_1/operativeUnit_1/SR_sum[11]_i_1/O
+ net (fo=1, routed) 0.000 8.032 leftFir/firUnit_1/operativeUnit_1/p_1_in[11]
+ SLICE_X146Y127 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.621 8.329 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y127 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]/C
+ clock pessimism 0.569 8.897
+ clock uncertainty -0.084 8.814
+ SLICE_X146Y127 FDCE (Setup_fdce_C_D) 0.081 8.895 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[11]
+ -------------------------------------------------------------------
+ required time 8.895
+ arrival time -8.032
+ -------------------------------------------------------------------
+ slack 0.862
+
+Slack (MET) : 0.890ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.085ns (logic 4.598ns (50.611%) route 4.487ns (49.389%))
+ Logic Levels: 14 (CARRY4=6 LUT2=3 LUT3=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.021ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.671ns = ( 8.329 - 10.000 )
+ Source Clock Delay (SCD): -1.082ns
+ Clock Pessimism Removal (CPR): 0.569ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.737 -1.082 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y126 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X146Y126 FDCE (Prop_fdce_C_Q) 0.518 -0.564 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.149 0.585 leftFir/firUnit_1/operativeUnit_1/SR_readAddress[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.124 0.709 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25/O
+ net (fo=1, routed) 0.000 0.709 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_25_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I1_O) 0.214 0.923 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17/O
+ net (fo=1, routed) 0.000 0.923 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_17_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I1_O) 0.088 1.011 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_11/O
+ net (fo=10, routed) 0.704 1.715 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[1]
+ SLICE_X144Y124 LUT5 (Prop_lut5_I0_O) 0.319 2.034 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9/O
+ net (fo=3, routed) 0.801 2.835 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_9_n_0
+ SLICE_X143Y124 LUT3 (Prop_lut3_I1_O) 0.153 2.988 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_1/O
+ net (fo=1, routed) 0.365 3.353 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_1_n_0
+ SLICE_X143Y125 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.588 3.941 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry/CO[3]
+ net (fo=1, routed) 0.000 3.941 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_n_0
+ SLICE_X143Y126 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.275 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[1]
+ net (fo=2, routed) 0.513 4.788 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_6
+ SLICE_X145Y126 LUT2 (Prop_lut2_I1_O) 0.303 5.091 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry_i_2/O
+ net (fo=1, routed) 0.000 5.091 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry_i_2_n_0
+ SLICE_X145Y126 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 5.489 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry/CO[3]
+ net (fo=1, routed) 0.000 5.489 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry_n_0
+ SLICE_X145Y127 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 5.711 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/O[0]
+ net (fo=2, routed) 0.448 6.160 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[7]
+ SLICE_X147Y126 LUT2 (Prop_lut2_I0_O) 0.299 6.459 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__0_i_1/O
+ net (fo=1, routed) 0.000 6.459 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__0_i_1_n_0
+ SLICE_X147Y126 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 6.860 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.860 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__0_n_0
+ SLICE_X147Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 7.194 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/O[1]
+ net (fo=1, routed) 0.506 7.700 leftFir/firUnit_1/operativeUnit_1/SC_addResult[9]
+ SLICE_X146Y127 LUT2 (Prop_lut2_I0_O) 0.303 8.003 r leftFir/firUnit_1/operativeUnit_1/SR_sum[9]_i_1/O
+ net (fo=1, routed) 0.000 8.003 leftFir/firUnit_1/operativeUnit_1/p_1_in[9]
+ SLICE_X146Y127 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.621 8.329 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X146Y127 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]/C
+ clock pessimism 0.569 8.897
+ clock uncertainty -0.084 8.814
+ SLICE_X146Y127 FDCE (Setup_fdce_C_D) 0.079 8.893 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[9]
+ -------------------------------------------------------------------
+ required time 8.893
+ arrival time -8.003
+ -------------------------------------------------------------------
+ slack 0.890
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.153ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.937ns
+ Source Clock Delay (SCD): -0.692ns
+ Clock Pessimism Removal (CPR): -0.258ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.608 -0.692 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X151Y123 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X151Y123 FDCE (Prop_fdce_C_Q) 0.141 -0.551 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][2]/Q
+ net (fo=2, routed) 0.101 -0.450 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7]_7[2]
+ SLICE_X149Y123 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.877 -0.937 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X149Y123 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]/C
+ clock pessimism 0.258 -0.679
+ SLICE_X149Y123 FDCE (Hold_fdce_C_D) 0.076 -0.603 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]
+ -------------------------------------------------------------------
+ required time 0.603
+ arrival time -0.450
+ -------------------------------------------------------------------
+ slack 0.153
+
+Slack (MET) : 0.154ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[8]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[15]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.259ns (logic 0.209ns (80.663%) route 0.050ns (19.337%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.928ns
+ Source Clock Delay (SCD): -0.684ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.616 -0.684 audio_inout/clk_out1
+ SLICE_X152Y133 FDRE r audio_inout/D_L_O_int_reg[8]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X152Y133 FDRE (Prop_fdre_C_Q) 0.164 -0.520 r audio_inout/D_L_O_int_reg[8]/Q
+ net (fo=1, routed) 0.050 -0.470 audio_inout/in_audioL[8]
+ SLICE_X153Y133 LUT6 (Prop_lut6_I1_O) 0.045 -0.425 r audio_inout/Data_Out_int[15]_i_1/O
+ net (fo=1, routed) 0.000 -0.425 audio_inout/Data_Out_int[15]_i_1_n_0
+ SLICE_X153Y133 FDRE r audio_inout/Data_Out_int_reg[15]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.886 -0.928 audio_inout/clk_out1
+ SLICE_X153Y133 FDRE r audio_inout/Data_Out_int_reg[15]/C
+ clock pessimism 0.257 -0.671
+ SLICE_X153Y133 FDRE (Hold_fdre_C_D) 0.092 -0.579 audio_inout/Data_Out_int_reg[15]
+ -------------------------------------------------------------------
+ required time 0.579
+ arrival time -0.425
+ -------------------------------------------------------------------
+ slack 0.154
+
+Slack (MET) : 0.167ns (arrival time - required time)
+ Source: audio_inout/D_R_O_int_reg[4]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[11]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.294ns (logic 0.186ns (63.237%) route 0.108ns (36.763%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.036ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.930ns
+ Source Clock Delay (SCD): -0.686ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.614 -0.686 audio_inout/clk_out1
+ SLICE_X153Y131 FDRE r audio_inout/D_R_O_int_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y131 FDRE (Prop_fdre_C_Q) 0.141 -0.545 r audio_inout/D_R_O_int_reg[4]/Q
+ net (fo=1, routed) 0.108 -0.437 audio_inout/in_audioR[4]
+ SLICE_X155Y131 LUT6 (Prop_lut6_I2_O) 0.045 -0.392 r audio_inout/Data_Out_int[11]_i_1/O
+ net (fo=1, routed) 0.000 -0.392 audio_inout/Data_Out_int[11]_i_1_n_0
+ SLICE_X155Y131 FDRE r audio_inout/Data_Out_int_reg[11]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.884 -0.930 audio_inout/clk_out1
+ SLICE_X155Y131 FDRE r audio_inout/Data_Out_int_reg[11]/C
+ clock pessimism 0.280 -0.650
+ SLICE_X155Y131 FDRE (Hold_fdre_C_D) 0.091 -0.559 audio_inout/Data_Out_int_reg[11]
+ -------------------------------------------------------------------
+ required time 0.559
+ arrival time -0.392
+ -------------------------------------------------------------------
+ slack 0.167
+
+Slack (MET) : 0.167ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][2]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.252ns (logic 0.141ns (55.855%) route 0.111ns (44.145%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.905ns
+ Source Clock Delay (SCD): -0.663ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.637 -0.663 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X157Y121 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y121 FDCE (Prop_fdce_C_Q) 0.141 -0.522 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][2]/Q
+ net (fo=2, routed) 0.111 -0.410 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10]_10[2]
+ SLICE_X159Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.909 -0.905 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][2]/C
+ clock pessimism 0.257 -0.648
+ SLICE_X159Y120 FDCE (Hold_fdce_C_D) 0.070 -0.578 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][2]
+ -------------------------------------------------------------------
+ required time 0.578
+ arrival time -0.410
+ -------------------------------------------------------------------
+ slack 0.167
+
+Slack (MET) : 0.169ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.252ns (logic 0.141ns (55.928%) route 0.111ns (44.072%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.937ns
+ Source Clock Delay (SCD): -0.692ns
+ Clock Pessimism Removal (CPR): -0.258ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.608 -0.692 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y123 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y123 FDCE (Prop_fdce_C_Q) 0.141 -0.551 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][1]/Q
+ net (fo=2, routed) 0.111 -0.440 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13]_13[1]
+ SLICE_X145Y123 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.877 -0.937 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y123 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]/C
+ clock pessimism 0.258 -0.679
+ SLICE_X145Y123 FDCE (Hold_fdce_C_D) 0.070 -0.609 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]
+ -------------------------------------------------------------------
+ required time 0.609
+ arrival time -0.440
+ -------------------------------------------------------------------
+ slack 0.169
+
+Slack (MET) : 0.172ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.255ns (logic 0.141ns (55.393%) route 0.114ns (44.607%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.938ns
+ Source Clock Delay (SCD): -0.693ns
+ Clock Pessimism Removal (CPR): -0.258ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.607 -0.693 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y125 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y125 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][3]/Q
+ net (fo=2, routed) 0.114 -0.438 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9]_9[3]
+ SLICE_X145Y125 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.876 -0.938 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y125 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/C
+ clock pessimism 0.258 -0.680
+ SLICE_X145Y125 FDCE (Hold_fdce_C_D) 0.070 -0.610 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]
+ -------------------------------------------------------------------
+ required time 0.610
+ arrival time -0.438
+ -------------------------------------------------------------------
+ slack 0.172
+
+Slack (MET) : 0.172ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.263ns (logic 0.141ns (53.584%) route 0.122ns (46.416%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.931ns
+ Source Clock Delay (SCD): -0.688ns
+ Clock Pessimism Removal (CPR): -0.258ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.612 -0.688 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y130 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y130 FDCE (Prop_fdce_C_Q) 0.141 -0.547 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][7]/Q
+ net (fo=2, routed) 0.122 -0.425 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7]_7[7]
+ SLICE_X147Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.883 -0.931 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]/C
+ clock pessimism 0.258 -0.673
+ SLICE_X147Y131 FDCE (Hold_fdce_C_D) 0.076 -0.597 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][7]
+ -------------------------------------------------------------------
+ required time 0.597
+ arrival time -0.425
+ -------------------------------------------------------------------
+ slack 0.172
+
+Slack (MET) : 0.174ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.254ns (logic 0.141ns (55.468%) route 0.113ns (44.532%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.904ns
+ Source Clock Delay (SCD): -0.661ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.639 -0.661 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y120 FDCE (Prop_fdce_C_Q) 0.141 -0.520 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][3]/Q
+ net (fo=2, routed) 0.113 -0.407 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10]_10[3]
+ SLICE_X163Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.910 -0.904 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X163Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]/C
+ clock pessimism 0.257 -0.647
+ SLICE_X163Y120 FDCE (Hold_fdce_C_D) 0.066 -0.581 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[11][3]
+ -------------------------------------------------------------------
+ required time 0.581
+ arrival time -0.407
+ -------------------------------------------------------------------
+ slack 0.174
+
+Slack (MET) : 0.175ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.309ns (logic 0.186ns (60.107%) route 0.123ns (39.893%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.934ns
+ Source Clock Delay (SCD): -0.690ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.610 -0.690 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X149Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X149Y128 FDCE (Prop_fdce_C_Q) 0.141 -0.549 r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[12]/Q
+ net (fo=4, routed) 0.123 -0.425 leftFir/firUnit_1/operativeUnit_1/p_0_in[5]
+ SLICE_X148Y128 LUT4 (Prop_lut4_I0_O) 0.045 -0.380 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_1/O
+ net (fo=1, routed) 0.000 -0.380 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_1_n_0
+ SLICE_X148Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.880 -0.934 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X148Y128 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/C
+ clock pessimism 0.257 -0.677
+ SLICE_X148Y128 FDCE (Hold_fdce_C_D) 0.121 -0.556 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]
+ -------------------------------------------------------------------
+ required time 0.556
+ arrival time -0.380
+ -------------------------------------------------------------------
+ slack 0.175
+
+Slack (MET) : 0.176ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.208ns (logic 0.128ns (61.625%) route 0.080ns (38.375%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.909ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.635 -0.665 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X160Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y124 FDCE (Prop_fdce_C_Q) 0.128 -0.537 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6][4]/Q
+ net (fo=2, routed) 0.080 -0.457 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[6]_6[4]
+ SLICE_X161Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.905 -0.909 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]/C
+ clock pessimism 0.257 -0.652
+ SLICE_X161Y124 FDCE (Hold_fdce_C_D) 0.019 -0.633 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]
+ -------------------------------------------------------------------
+ required time 0.633
+ arrival time -0.457
+ -------------------------------------------------------------------
+ slack 0.176
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out1_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT0 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_1/inst/clkout1_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y132 lrclkD1_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y133 lrclkD2_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X148Y133 lrclkcnt_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X148Y133 lrclkcnt_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y133 lrclkcnt_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y133 lrclkcnt_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y133 pulse48kHz_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X158Y130 audio_inout/BCLK_int_reg/C
+Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y132 lrclkD1_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y132 lrclkD1_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y133 lrclkD2_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y133 lrclkD2_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y133 lrclkcnt_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y133 lrclkcnt_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y132 lrclkD1_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y132 lrclkD1_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y133 lrclkD2_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y133 lrclkD2_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X148Y133 lrclkcnt_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y133 lrclkcnt_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y133 lrclkcnt_reg[2]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out3_clk_wiz_0
+ To Clock: clk_out3_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 81.178ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out3_clk_wiz_0
+Waveform(ns): { 0.000 41.667 }
+Period(ns): 83.333
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT2 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 83.333 81.178 BUFGCTRL_X0Y0 clk_1/inst/clkout3_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT2 n/a 1.249 83.333 82.084 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT2
+Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 83.333 130.027 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT2
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out4_clk_wiz_0
+ To Clock: clk_out4_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 14.860ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.147ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 14.860ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[6]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.805ns (logic 0.952ns (19.811%) route 3.853ns (80.189%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.036ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.581ns = ( 18.419 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.492 3.814 initialize_audio/twi_controller_n_8
+ SLICE_X161Y110 FDRE r initialize_audio/initA_reg[6]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.711 18.419 initialize_audio/clk_out4
+ SLICE_X161Y110 FDRE r initialize_audio/initA_reg[6]/C
+ clock pessimism 0.554 18.972
+ clock uncertainty -0.094 18.878
+ SLICE_X161Y110 FDRE (Setup_fdre_C_CE) -0.205 18.673 initialize_audio/initA_reg[6]
+ -------------------------------------------------------------------
+ required time 18.673
+ arrival time -3.814
+ -------------------------------------------------------------------
+ slack 14.860
+
+Slack (MET) : 14.888ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[0]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.810ns (logic 0.952ns (19.791%) route 3.858ns (80.209%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.497 3.819 initialize_audio/twi_controller_n_8
+ SLICE_X162Y113 FDRE r initialize_audio/initA_reg[0]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/clk_out4
+ SLICE_X162Y113 FDRE r initialize_audio/initA_reg[0]/C
+ clock pessimism 0.554 18.969
+ clock uncertainty -0.094 18.875
+ SLICE_X162Y113 FDRE (Setup_fdre_C_CE) -0.169 18.706 initialize_audio/initA_reg[0]
+ -------------------------------------------------------------------
+ required time 18.706
+ arrival time -3.819
+ -------------------------------------------------------------------
+ slack 14.888
+
+Slack (MET) : 14.888ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[1]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.810ns (logic 0.952ns (19.791%) route 3.858ns (80.209%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.497 3.819 initialize_audio/twi_controller_n_8
+ SLICE_X162Y113 FDRE r initialize_audio/initA_reg[1]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/clk_out4
+ SLICE_X162Y113 FDRE r initialize_audio/initA_reg[1]/C
+ clock pessimism 0.554 18.969
+ clock uncertainty -0.094 18.875
+ SLICE_X162Y113 FDRE (Setup_fdre_C_CE) -0.169 18.706 initialize_audio/initA_reg[1]
+ -------------------------------------------------------------------
+ required time 18.706
+ arrival time -3.819
+ -------------------------------------------------------------------
+ slack 14.888
+
+Slack (MET) : 14.890ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[2]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.810ns (logic 0.952ns (19.791%) route 3.858ns (80.209%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.037ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.497 3.819 initialize_audio/twi_controller_n_8
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[2]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[2]/C
+ clock pessimism 0.554 18.971
+ clock uncertainty -0.094 18.877
+ SLICE_X162Y111 FDRE (Setup_fdre_C_CE) -0.169 18.708 initialize_audio/initA_reg[2]
+ -------------------------------------------------------------------
+ required time 18.708
+ arrival time -3.819
+ -------------------------------------------------------------------
+ slack 14.890
+
+Slack (MET) : 14.890ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[3]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.810ns (logic 0.952ns (19.791%) route 3.858ns (80.209%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.037ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.497 3.819 initialize_audio/twi_controller_n_8
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[3]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[3]/C
+ clock pessimism 0.554 18.971
+ clock uncertainty -0.094 18.877
+ SLICE_X162Y111 FDRE (Setup_fdre_C_CE) -0.169 18.708 initialize_audio/initA_reg[3]
+ -------------------------------------------------------------------
+ required time 18.708
+ arrival time -3.819
+ -------------------------------------------------------------------
+ slack 14.890
+
+Slack (MET) : 14.890ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[4]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.810ns (logic 0.952ns (19.791%) route 3.858ns (80.209%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.037ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.497 3.819 initialize_audio/twi_controller_n_8
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[4]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[4]/C
+ clock pessimism 0.554 18.971
+ clock uncertainty -0.094 18.877
+ SLICE_X162Y111 FDRE (Setup_fdre_C_CE) -0.169 18.708 initialize_audio/initA_reg[4]
+ -------------------------------------------------------------------
+ required time 18.708
+ arrival time -3.819
+ -------------------------------------------------------------------
+ slack 14.890
+
+Slack (MET) : 14.890ns (required time - arrival time)
+ Source: initialize_audio/initWord_reg[17]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[5]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.810ns (logic 0.952ns (19.791%) route 3.858ns (80.209%))
+ Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
+ Clock Path Skew: -0.037ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
+ Source Clock Delay (SCD): -0.992ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.827 -0.992 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[17]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.456 -0.536 r initialize_audio/initWord_reg[17]/Q
+ net (fo=2, routed) 0.954 0.418 initialize_audio/data1[1]
+ SLICE_X160Y111 LUT4 (Prop_lut4_I2_O) 0.124 0.542 f initialize_audio/state[3]_i_4/O
+ net (fo=1, routed) 0.777 1.319 initialize_audio/state[3]_i_4_n_0
+ SLICE_X160Y110 LUT5 (Prop_lut5_I4_O) 0.124 1.443 r initialize_audio/state[3]_i_3/O
+ net (fo=3, routed) 0.975 2.418 initialize_audio/twi_controller/state_reg[3]_0
+ SLICE_X159Y112 LUT6 (Prop_lut6_I5_O) 0.124 2.542 f initialize_audio/twi_controller/initA[6]_i_6/O
+ net (fo=1, routed) 0.655 3.198 initialize_audio/twi_controller/initA[6]_i_6_n_0
+ SLICE_X158Y112 LUT5 (Prop_lut5_I4_O) 0.124 3.322 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.497 3.819 initialize_audio/twi_controller_n_8
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[5]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
+ SLICE_X162Y111 FDRE r initialize_audio/initA_reg[5]/C
+ clock pessimism 0.554 18.971
+ clock uncertainty -0.094 18.877
+ SLICE_X162Y111 FDRE (Setup_fdre_C_CE) -0.169 18.708 initialize_audio/initA_reg[5]
+ -------------------------------------------------------------------
+ required time 18.708
+ arrival time -3.819
+ -------------------------------------------------------------------
+ slack 14.890
+
+Slack (MET) : 15.193ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[1]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.469ns (logic 0.952ns (21.300%) route 3.517ns (78.700%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.994ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.825 -0.994 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y115 FDSE (Prop_fdse_C_Q) 0.456 -0.538 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
+ net (fo=7, routed) 0.870 0.333 initialize_audio/twi_controller/sclCnt[0]
+ SLICE_X158Y115 LUT6 (Prop_lut6_I2_O) 0.124 0.457 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.506 0.963 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X159Y115 LUT2 (Prop_lut2_I0_O) 0.124 1.087 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 0.831 1.917 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X163Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.041 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.458 2.499 initialize_audio/twi_controller/dataByte0
+ SLICE_X163Y114 LUT2 (Prop_lut2_I1_O) 0.124 2.623 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.852 3.476 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/C
+ clock pessimism 0.554 18.967
+ clock uncertainty -0.094 18.873
+ SLICE_X159Y113 FDRE (Setup_fdre_C_CE) -0.205 18.668 initialize_audio/twi_controller/dataByte_reg[1]
+ -------------------------------------------------------------------
+ required time 18.668
+ arrival time -3.476
+ -------------------------------------------------------------------
+ slack 15.193
+
+Slack (MET) : 15.193ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[6]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.469ns (logic 0.952ns (21.300%) route 3.517ns (78.700%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.994ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.825 -0.994 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y115 FDSE (Prop_fdse_C_Q) 0.456 -0.538 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
+ net (fo=7, routed) 0.870 0.333 initialize_audio/twi_controller/sclCnt[0]
+ SLICE_X158Y115 LUT6 (Prop_lut6_I2_O) 0.124 0.457 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.506 0.963 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X159Y115 LUT2 (Prop_lut2_I0_O) 0.124 1.087 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 0.831 1.917 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X163Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.041 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.458 2.499 initialize_audio/twi_controller/dataByte0
+ SLICE_X163Y114 LUT2 (Prop_lut2_I1_O) 0.124 2.623 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.852 3.476 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
+ clock pessimism 0.554 18.967
+ clock uncertainty -0.094 18.873
+ SLICE_X159Y113 FDRE (Setup_fdre_C_CE) -0.205 18.668 initialize_audio/twi_controller/dataByte_reg[6]
+ -------------------------------------------------------------------
+ required time 18.668
+ arrival time -3.476
+ -------------------------------------------------------------------
+ slack 15.193
+
+Slack (MET) : 15.193ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[0]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[7]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.469ns (logic 0.952ns (21.300%) route 3.517ns (78.700%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.994ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.825 -0.994 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y115 FDSE (Prop_fdse_C_Q) 0.456 -0.538 f initialize_audio/twi_controller/sclCnt_reg[0]/Q
+ net (fo=7, routed) 0.870 0.333 initialize_audio/twi_controller/sclCnt[0]
+ SLICE_X158Y115 LUT6 (Prop_lut6_I2_O) 0.124 0.457 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.506 0.963 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X159Y115 LUT2 (Prop_lut2_I0_O) 0.124 1.087 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 0.831 1.917 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X163Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.041 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.458 2.499 initialize_audio/twi_controller/dataByte0
+ SLICE_X163Y114 LUT2 (Prop_lut2_I1_O) 0.124 2.623 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.852 3.476 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/C
+ clock pessimism 0.554 18.967
+ clock uncertainty -0.094 18.873
+ SLICE_X159Y113 FDRE (Setup_fdre_C_CE) -0.205 18.668 initialize_audio/twi_controller/dataByte_reg[7]
+ -------------------------------------------------------------------
+ required time 18.668
+ arrival time -3.476
+ -------------------------------------------------------------------
+ slack 15.193
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.147ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[4]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.251ns (logic 0.186ns (74.147%) route 0.065ns (25.853%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X160Y111 FDRE r initialize_audio/initWord_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y111 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initWord_reg[4]/Q
+ net (fo=2, routed) 0.065 -0.448 initialize_audio/initWord_reg_n_0_[4]
+ SLICE_X161Y111 LUT6 (Prop_lut6_I4_O) 0.045 -0.403 r initialize_audio/data_i[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.403 initialize_audio/data_i[4]_i_1_n_0
+ SLICE_X161Y111 FDRE r initialize_audio/data_i_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X161Y111 FDRE r initialize_audio/data_i_reg[4]/C
+ clock pessimism 0.254 -0.641
+ SLICE_X161Y111 FDRE (Hold_fdre_C_D) 0.091 -0.550 initialize_audio/data_i_reg[4]
+ -------------------------------------------------------------------
+ required time 0.550
+ arrival time -0.403
+ -------------------------------------------------------------------
+ slack 0.147
+
+Slack (MET) : 0.151ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/sclCnt_reg[5]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.285ns (logic 0.186ns (65.373%) route 0.099ns (34.627%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.900ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y115 FDSE (Prop_fdse_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.099 -0.417 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X158Y115 LUT6 (Prop_lut6_I2_O) 0.045 -0.372 r initialize_audio/twi_controller/sclCnt[5]_i_1/O
+ net (fo=1, routed) 0.000 -0.372 initialize_audio/twi_controller/sclCnt01_in[5]
+ SLICE_X158Y115 FDRE r initialize_audio/twi_controller/sclCnt_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.914 -0.900 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y115 FDRE r initialize_audio/twi_controller/sclCnt_reg[5]/C
+ clock pessimism 0.256 -0.644
+ SLICE_X158Y115 FDRE (Hold_fdre_C_D) 0.121 -0.523 initialize_audio/twi_controller/sclCnt_reg[5]
+ -------------------------------------------------------------------
+ required time 0.523
+ arrival time -0.372
+ -------------------------------------------------------------------
+ slack 0.151
+
+Slack (MET) : 0.167ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/dataByte_reg[5]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[6]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.296ns (logic 0.186ns (62.919%) route 0.110ns (37.081%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.037ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y113 FDRE (Prop_fdre_C_Q) 0.141 -0.515 r initialize_audio/twi_controller/dataByte_reg[5]/Q
+ net (fo=1, routed) 0.110 -0.405 initialize_audio/twi_controller/dataByte[5]
+ SLICE_X159Y113 LUT4 (Prop_lut4_I3_O) 0.045 -0.360 r initialize_audio/twi_controller/dataByte[6]_i_1/O
+ net (fo=1, routed) 0.000 -0.360 initialize_audio/twi_controller/p_1_in[6]
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
+ clock pessimism 0.280 -0.619
+ SLICE_X159Y113 FDRE (Hold_fdre_C_D) 0.092 -0.527 initialize_audio/twi_controller/dataByte_reg[6]
+ -------------------------------------------------------------------
+ required time 0.527
+ arrival time -0.360
+ -------------------------------------------------------------------
+ slack 0.167
+
+Slack (MET) : 0.177ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[19]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[3]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.307ns (logic 0.186ns (60.488%) route 0.121ns (39.512%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.038ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.897ns
+ Source Clock Delay (SCD): -0.655ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.645 -0.655 initialize_audio/clk_out4
+ SLICE_X159Y111 FDRE r initialize_audio/initWord_reg[19]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y111 FDRE (Prop_fdre_C_Q) 0.141 -0.514 r initialize_audio/initWord_reg[19]/Q
+ net (fo=2, routed) 0.121 -0.392 initialize_audio/data1[3]
+ SLICE_X161Y112 LUT6 (Prop_lut6_I0_O) 0.045 -0.347 r initialize_audio/data_i[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.347 initialize_audio/data_i[3]_i_1_n_0
+ SLICE_X161Y112 FDRE r initialize_audio/data_i_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.917 -0.897 initialize_audio/clk_out4
+ SLICE_X161Y112 FDRE r initialize_audio/data_i_reg[3]/C
+ clock pessimism 0.280 -0.617
+ SLICE_X161Y112 FDRE (Hold_fdre_C_D) 0.092 -0.525 initialize_audio/data_i_reg[3]
+ -------------------------------------------------------------------
+ required time 0.525
+ arrival time -0.347
+ -------------------------------------------------------------------
+ slack 0.177
+
+Slack (MET) : 0.183ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.288ns (logic 0.186ns (64.606%) route 0.102ns (35.394%))
+ Logic Levels: 1 (LUT5=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.903ns
+ Source Clock Delay (SCD): -0.660ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.640 -0.660 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y119 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y119 FDSE (Prop_fdse_C_Q) 0.141 -0.519 r initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
+ net (fo=5, routed) 0.102 -0.417 initialize_audio/twi_controller/sel0[2]
+ SLICE_X160Y119 LUT5 (Prop_lut5_I4_O) 0.045 -0.372 r initialize_audio/twi_controller/busFreeCnt[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.372 initialize_audio/twi_controller/busFreeCnt00_in[4]
+ SLICE_X160Y119 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.911 -0.903 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y119 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[4]/C
+ clock pessimism 0.256 -0.647
+ SLICE_X160Y119 FDSE (Hold_fdse_C_D) 0.092 -0.555 initialize_audio/twi_controller/busFreeCnt_reg[4]
+ -------------------------------------------------------------------
+ required time 0.555
+ arrival time -0.372
+ -------------------------------------------------------------------
+ slack 0.183
+
+Slack (MET) : 0.185ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/busFreeCnt_reg[3]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.289ns (logic 0.186ns (64.382%) route 0.103ns (35.618%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.903ns
+ Source Clock Delay (SCD): -0.660ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.640 -0.660 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y119 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y119 FDSE (Prop_fdse_C_Q) 0.141 -0.519 r initialize_audio/twi_controller/busFreeCnt_reg[2]/Q
+ net (fo=5, routed) 0.103 -0.416 initialize_audio/twi_controller/sel0[2]
+ SLICE_X160Y119 LUT4 (Prop_lut4_I1_O) 0.045 -0.371 r initialize_audio/twi_controller/busFreeCnt[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.371 initialize_audio/twi_controller/busFreeCnt00_in[3]
+ SLICE_X160Y119 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.911 -0.903 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y119 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[3]/C
+ clock pessimism 0.256 -0.647
+ SLICE_X160Y119 FDSE (Hold_fdse_C_D) 0.091 -0.556 initialize_audio/twi_controller/busFreeCnt_reg[3]
+ -------------------------------------------------------------------
+ required time 0.556
+ arrival time -0.371
+ -------------------------------------------------------------------
+ slack 0.185
+
+Slack (MET) : 0.195ns (arrival time - required time)
+ Source: initialize_audio/state_reg[3]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[1]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.323ns (logic 0.186ns (57.653%) route 0.137ns (42.347%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.037ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.898ns
+ Source Clock Delay (SCD): -0.655ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.645 -0.655 initialize_audio/clk_out4
+ SLICE_X160Y112 FDRE r initialize_audio/state_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.514 f initialize_audio/state_reg[3]/Q
+ net (fo=15, routed) 0.137 -0.377 initialize_audio/state_reg_n_0_[3]
+ SLICE_X159Y112 LUT6 (Prop_lut6_I1_O) 0.045 -0.332 r initialize_audio/data_i[1]_i_1/O
+ net (fo=1, routed) 0.000 -0.332 initialize_audio/data_i[1]_i_1_n_0
+ SLICE_X159Y112 FDRE r initialize_audio/data_i_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.916 -0.898 initialize_audio/clk_out4
+ SLICE_X159Y112 FDRE r initialize_audio/data_i_reg[1]/C
+ clock pessimism 0.280 -0.618
+ SLICE_X159Y112 FDRE (Hold_fdre_C_D) 0.091 -0.527 initialize_audio/data_i_reg[1]
+ -------------------------------------------------------------------
+ required time 0.527
+ arrival time -0.332
+ -------------------------------------------------------------------
+ slack 0.195
+
+Slack (MET) : 0.196ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[1]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/sclCnt_reg[3]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.329ns (logic 0.186ns (56.600%) route 0.143ns (43.400%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.900ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y115 FDSE (Prop_fdse_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/sclCnt_reg[1]/Q
+ net (fo=6, routed) 0.143 -0.373 initialize_audio/twi_controller/sclCnt[1]
+ SLICE_X158Y115 LUT4 (Prop_lut4_I3_O) 0.045 -0.328 r initialize_audio/twi_controller/sclCnt[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.328 initialize_audio/twi_controller/sclCnt01_in[3]
+ SLICE_X158Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.914 -0.900 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[3]/C
+ clock pessimism 0.256 -0.644
+ SLICE_X158Y115 FDSE (Hold_fdse_C_D) 0.120 -0.524 initialize_audio/twi_controller/sclCnt_reg[3]
+ -------------------------------------------------------------------
+ required time 0.524
+ arrival time -0.328
+ -------------------------------------------------------------------
+ slack 0.196
+
+Slack (MET) : 0.199ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[1]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/sclCnt_reg[4]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.333ns (logic 0.186ns (55.919%) route 0.147ns (44.081%))
+ Logic Levels: 1 (LUT5=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.900ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y115 FDSE (Prop_fdse_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/sclCnt_reg[1]/Q
+ net (fo=6, routed) 0.147 -0.369 initialize_audio/twi_controller/sclCnt[1]
+ SLICE_X158Y115 LUT5 (Prop_lut5_I1_O) 0.045 -0.324 r initialize_audio/twi_controller/sclCnt[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.324 initialize_audio/twi_controller/sclCnt[4]_i_1_n_0
+ SLICE_X158Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.914 -0.900 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y115 FDSE r initialize_audio/twi_controller/sclCnt_reg[4]/C
+ clock pessimism 0.256 -0.644
+ SLICE_X158Y115 FDSE (Hold_fdse_C_D) 0.121 -0.523 initialize_audio/twi_controller/sclCnt_reg[4]
+ -------------------------------------------------------------------
+ required time 0.523
+ arrival time -0.324
+ -------------------------------------------------------------------
+ slack 0.199
+
+Slack (MET) : 0.217ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/bitCount_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/bitCount_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.323ns (logic 0.186ns (57.523%) route 0.137ns (42.477%))
+ Logic Levels: 1 (LUT5=1)
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/bitCount_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X163Y116 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/bitCount_reg[1]/Q
+ net (fo=5, routed) 0.137 -0.378 initialize_audio/twi_controller/bitCount[1]
+ SLICE_X163Y115 LUT5 (Prop_lut5_I3_O) 0.045 -0.333 r initialize_audio/twi_controller/bitCount[2]_i_1/O
+ net (fo=1, routed) 0.000 -0.333 initialize_audio/twi_controller/bitCount[2]_i_1_n_0
+ SLICE_X163Y115 FDRE r initialize_audio/twi_controller/bitCount_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y115 FDRE r initialize_audio/twi_controller/bitCount_reg[2]/C
+ clock pessimism 0.257 -0.642
+ SLICE_X163Y115 FDRE (Hold_fdre_C_D) 0.091 -0.551 initialize_audio/twi_controller/bitCount_reg[2]
+ -------------------------------------------------------------------
+ required time 0.551
+ arrival time -0.333
+ -------------------------------------------------------------------
+ slack 0.217
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out4_clk_wiz_0
+Waveform(ns): { 0.000 10.000 }
+Period(ns): 20.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT3 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y2 clk_1/inst/clkout4_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT3 n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y112 initialize_audio/data_i_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y112 initialize_audio/data_i_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y112 initialize_audio/data_i_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y112 initialize_audio/data_i_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y111 initialize_audio/data_i_reg[4]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X161Y112 initialize_audio/data_i_reg[5]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y113 initialize_audio/data_i_reg[6]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y113 initialize_audio/data_i_reg[7]/C
+Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 20.000 193.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y112 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y112 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y111 initialize_audio/data_i_reg[4]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y111 initialize_audio/data_i_reg[4]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y112 initialize_audio/data_i_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y112 initialize_audio/data_i_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[3]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y112 initialize_audio/data_i_reg[3]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y111 initialize_audio/data_i_reg[4]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X161Y111 initialize_audio/data_i_reg[4]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clkfbout_clk_wiz_0
+ To Clock: clkfbout_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clkfbout_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKFBOUT }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y3 clk_1/inst/clkf_buf/I
+Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBOUT
+Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBOUT
+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..248bd8917df8e1a4678a760c240c6fe89ea550c7
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..129d334b3c5ba8a072b0ba1fea6a74fad71f02d4
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..bd6db8e6420bba4cd2121cdf1ce068921f048fdd
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
@@ -0,0 +1,227 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:55:49 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs | 582 | 0 | 800 | 133800 | 0.43 |
+| LUT as Logic | 582 | 0 | 800 | 133800 | 0.43 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register as Flip Flop | 579 | 0 | 1600 | 267600 | 0.22 |
+| Register as Latch | 10 | 0 | 1600 | 267600 | <0.01 |
+| F7 Muxes | 33 | 0 | 400 | 66900 | 0.05 |
+| F8 Muxes | 16 | 0 | 200 | 33450 | 0.05 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 328 | Yes | - | Reset |
+| 20 | Yes | Set | - |
+| 239 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice | 237 | 0 | 200 | 33450 | 0.71 |
+| SLICEL | 148 | 0 | | | |
+| SLICEM | 89 | 0 | | | |
+| LUT as Logic | 582 | 0 | 800 | 133800 | 0.43 |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 509 | | | | |
+| using O5 and O6 | 73 | | | | |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| LUT as Distributed RAM | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| LUT as Shift Register | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| Slice Registers | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register driven from within the Slice | 257 | | | | |
+| Register driven from outside the Slice | 332 | | | | |
+| LUT in front of the register is unused | 258 | | | | |
+| LUT in front of the register is used | 74 | | | | |
+| Unique Control Sets | 31 | | 200 | 33450 | 0.09 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 20 | 20 | 0 | 285 | 7.02 |
+| IOB Master Pads | 8 | | | | |
+| IOB Slave Pads | 10 | | | | |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 0 | 10 | 10.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| FDCE | 318 | Flop & Latch |
+| LUT6 | 252 | LUT |
+| FDRE | 239 | Flop & Latch |
+| LUT2 | 115 | LUT |
+| LUT5 | 107 | LUT |
+| LUT4 | 73 | LUT |
+| LUT3 | 67 | LUT |
+| LUT1 | 41 | LUT |
+| CARRY4 | 38 | CarryLogic |
+| MUXF7 | 33 | MuxFx |
+| FDSE | 20 | Flop & Latch |
+| MUXF8 | 16 | MuxFx |
+| IBUF | 11 | IO |
+| LDCE | 10 | Flop & Latch |
+| OBUF | 9 | IO |
+| BUFG | 4 | Clock |
+| OBUFT | 2 | IO |
+| FDPE | 2 | Flop & Latch |
+| MMCME2_ADV | 1 | Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/clockInfo.txt b/proj/AudioProc.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdd28adce0878088a12e4ab87ccf93657fce6ada
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.1
+| Date : Tue Mar 18 16:55:46 2025
+| Host : fl-tp-br-104
+| Design : design_1
+| Device : xc7a200t-sbg484-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/proj/AudioProc.runs/impl_1/gen_run.xml b/proj/AudioProc.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6f9e597256f090475dfa8075eeea0d04fd8a7ba3
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/gen_run.xml
@@ -0,0 +1,208 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1742313174">
+ <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS" Name="audioProc_postroute_physopted.rqs"/>
+ <File Type="ROUTE-RQS" Name="audioProc_routed.rqs"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BG-BGN" Name="audioProc.bgn"/>
+ <File Type="BITSTR-SYSDEF" Name="audioProc.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="audioProc.ltx"/>
+ <File Type="RBD_FILE" Name="audioProc.rbd"/>
+ <File Type="NPI_FILE" Name="audioProc.npi"/>
+ <File Type="RNPI_FILE" Name="audioProc.rnpi"/>
+ <File Type="CFI_FILE" Name="audioProc.cfi"/>
+ <File Type="RCFI_FILE" Name="audioProc.rcfi"/>
+ <File Type="PL-PDI-FILE" Name="audioProc_pld.pdi"/>
+ <File Type="BOOT-PDI-FILE" Name="audioProc_boot.pdi"/>
+ <File Type="RDI-RDI" Name="audioProc.vdi"/>
+ <File Type="PDI-FILE" Name="audioProc.pdi"/>
+ <File Type="BITSTR-MMI" Name="audioProc.mmi"/>
+ <File Type="BITSTR-BMM" Name="audioProc_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="audioProc.nky"/>
+ <File Type="BITSTR-RBT" Name="audioProc.rbt"/>
+ <File Type="BITSTR-MSK" Name="audioProc.msk"/>
+ <File Type="BG-BIN" Name="audioProc.bin"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+ <File Type="BG-BIT" Name="audioProc.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="audioProc_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="audioProc_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="audioProc_bus_skew_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="audioProc_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="audioProc_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="audioProc_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="audioProc_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="audioProc_postroute_physopt.dcp"/>
+ <File Type="BG-DRC" Name="audioProc.drc"/>
+ <File Type="ROUTE-RQS-PB" Name="audioProc_rqs_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="audioProc_bus_skew_routed.rpx"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="audioProc_bus_skew_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW" Name="audioProc_bus_skew_routed.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="audioProc_utilization_placed.pb"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="audioProc_methodology_drc_opted.rpt"/>
+ <File Type="PLACE-UTIL" Name="audioProc_utilization_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="audioProc_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-IO" Name="audioProc_io_placed.rpt"/>
+ <File Type="PHYSOPT-TIMING" Name="audioProc_timing_summary_physopted.rpt"/>
+ <File Type="PWROPT-DRC" Name="audioProc_drc_pwropted.rpt"/>
+ <File Type="PWROPT-TIMING" Name="audioProc_timing_summary_pwropted.rpt"/>
+ <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
+ <File Type="PLACE-TIMING" Name="audioProc_timing_summary_placed.rpt"/>
+ <File Type="INIT-TIMING" Name="audioProc_timing_summary_init.rpt"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
+ <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
+ <File Type="OPT-DCP" Name="audioProc_opt.dcp"/>
+ <File Type="OPT-RQA-PB" Name="audioProc_rqa_opted.pb"/>
+ <File Type="OPT-HWDEF" Name="audioProc.hwdef"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="audioProc_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="OPT-TIMING" Name="audioProc_timing_summary_opted.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="audioProc_incremental_reuse_placed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
+ <File Type="PLACE-DCP" Name="audioProc_placed.dcp"/>
+ <File Type="PLACE-RQA-PB" Name="audioProc_rqa_placed.pb"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="audioProc_incremental_reuse_pre_placed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="audioProc_drc_routed.rpx"/>
+ <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="audioProc_postplace_pwropt.dcp"/>
+ <File Type="PHYSOPT-DCP" Name="audioProc_physopt.dcp"/>
+ <File Type="PHYSOPT-DRC" Name="audioProc_drc_physopted.rpt"/>
+ <File Type="ROUTE-ERROR-DCP" Name="audioProc_routed_error.dcp"/>
+ <File Type="ROUTE-DCP" Name="audioProc_routed.dcp"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="audioProc_routed_bb.dcp"/>
+ <File Type="ROUTE-DRC" Name="audioProc_drc_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="audioProc_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="audioProc_drc_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="audioProc_power_routed.rpt"/>
+ <File Type="ROUTE-PWR-SUM" Name="audioProc_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR-RPX" Name="audioProc_power_routed.rpx"/>
+ <File Type="ROUTE-STATUS" Name="audioProc_route_status.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="audioProc_route_status.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="audioProc_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-TIMING-PB" Name="audioProc_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMING-RPX" Name="audioProc_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-SIMILARITY" Name="audioProc_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="audioProc_clock_utilization_routed.rpt"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+ <Desc>Vivado Implementation Defaults</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+</GenRun>
diff --git a/proj/AudioProc.runs/impl_1/htr.txt b/proj/AudioProc.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2498e464293307c0340b7226ed1775e71d1403fc
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/init_design.pb b/proj/AudioProc.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..5a1553e4e84aced5f4db12aec59c9e0c550bd643
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/init_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/opt_design.pb b/proj/AudioProc.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..36ed247a61c61f42d3e7b8fe336dd1da65e66f8c
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/opt_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/place_design.pb b/proj/AudioProc.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..888a80aa2a1a9d9efce8f6b0386a35e65aca6aff
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/place_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/project.wdf b/proj/AudioProc.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..fb61d154c839bc8ff8ff046e913d3157ad1a07d7
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
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diff --git a/proj/AudioProc.runs/impl_1/route_design.pb b/proj/AudioProc.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..60087d8db97cb933931817d5d3d92e7784bb6441
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/route_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/rundef.js b/proj/AudioProc.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..52db31ee15cfd6fce55ef683261e82bb3df928c0
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/rundef.js
@@ -0,0 +1,45 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/impl_1/runme.bat b/proj/AudioProc.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/impl_1/runme.log b/proj/AudioProc.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..90047388c7983e133438e62ed514de45c1c085d3
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.log
@@ -0,0 +1,759 @@
+
+*** Running vivado
+ with args -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Tue Mar 18 16:54:31 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.551 ; gain = 325.840 ; free physical = 3205 ; free virtual = 14018
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2098.832 ; gain = 0.000 ; free physical = 2832 ; free virtual = 13628
+INFO: [Netlist 29-17] Analyzing 90 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+get_clocks: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2815.324 ; gain = 624.898 ; free physical = 2199 ; free virtual = 13036
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2815.324 ; gain = 0.000 ; free physical = 2188 ; free virtual = 13036
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2815.324 ; gain = 1120.898 ; free physical = 2188 ; free virtual = 13036
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.83 . Memory (MB): peak = 2879.355 ; gain = 64.031 ; free physical = 2205 ; free virtual = 13039
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2879.355 ; gain = 0.000 ; free physical = 2204 ; free virtual = 13038
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Phase 1 Initialization | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Phase 2 Timer Update And Timing Data Collection | Checksum: 1a5dadbe7
+
+Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 1c4537e51
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Retarget | Checksum: 1c4537e51
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 2092676cd
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Constant propagation | Checksum: 2092676cd
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12692
+Sweep | Checksum: 23f78c28e
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+BUFG optimization | Checksum: 23f78c28e
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Shift Register Optimization | Checksum: 23f78c28e
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 23f78c28e
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Post Processing Netlist | Checksum: 23f78c28e
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Phase 9 Finalization | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 2 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+Ending Netlist Obfuscation Task | Checksum: 1784a9325
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3172.082 ; gain = 0.000 ; free physical = 1849 ; free virtual = 12693
+INFO: [Common 17-83] Releasing license: Implementation
+34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12693
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12694
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1875 ; free virtual = 12694
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1866 ; free virtual = 12685
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12889edb3
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1867 ; free virtual = 12686
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1867 ; free virtual = 12686
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 162133ba4
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.49 . Memory (MB): peak = 3260.125 ; gain = 0.000 ; free physical = 1839 ; free virtual = 12662
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1d345fc39
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1844 ; free virtual = 12667
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1d345fc39
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1844 ; free virtual = 12667
+Phase 1 Placer Initialization | Checksum: 1d345fc39
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1844 ; free virtual = 12667
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 259bcf59f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1874 ; free virtual = 12698
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1eb9fea2e
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1903 ; free virtual = 12727
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1eb9fea2e
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3267.152 ; gain = 7.027 ; free physical = 1903 ; free virtual = 12727
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 2135c9eff
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1897 ; free virtual = 12722
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 147 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 65 nets or LUTs. Breaked 0 LUT, combined 65 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3275.156 ; gain = 0.000 ; free physical = 1904 ; free virtual = 12713
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 65 | 65 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 65 | 65 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1045e841e
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1904 ; free virtual = 12713
+Phase 2.4 Global Placement Core | Checksum: df357595
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+Phase 2 Global Placement | Checksum: df357595
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 126b0a524
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 260476615
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 235f4885a
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 21dc0f0a9
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1911 ; free virtual = 12720
+
+Phase 3.5 Fast Optimization
+Phase 3.5 Fast Optimization | Checksum: 1b18dbe5a
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1913 ; free virtual = 12722
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 14fc209cd
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1905 ; free virtual = 12714
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1755c839f
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1905 ; free virtual = 12714
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: e875e6cf
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1905 ; free virtual = 12714
+
+Phase 3.9 Fast Optimization
+Phase 3.9 Fast Optimization | Checksum: 2289630fa
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1895 ; free virtual = 12704
+Phase 3 Detail Placement | Checksum: 2289630fa
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3275.156 ; gain = 15.031 ; free physical = 1895 ; free virtual = 12704
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 20923581e
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.032 | TNS=-0.032 |
+Phase 1 Physical Synthesis Initialization | Checksum: fd4c8aa0
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1898 ; free virtual = 12707
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 1bf3592a3
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1898 ; free virtual = 12707
+Phase 4.1.1.1 BUFG Insertion | Checksum: 20923581e
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.512. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Phase 4.1 Post Commit Optimization | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Phase 4.3 Placer Reporting | Checksum: d8c506bc
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1898 ; free virtual = 12707
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: f1510904
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+Ending Placer Task | Checksum: ef412fe0
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+69 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 3276.949 ; gain = 16.824 ; free physical = 1898 ; free virtual = 12707
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1860 ; free virtual = 12669
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1864 ; free virtual = 12673
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12672
+Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12674
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12673
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12673
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1863 ; free virtual = 12673
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1862 ; free virtual = 12673
+Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3276.949 ; gain = 0.000 ; free physical = 1862 ; free virtual = 12673
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 2abcc7f3 ConstDB: 0 ShapeSum: 2c697c89 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: c6e40866 | NumContArr: 8ffb2756 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2dc3124f6
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3498.910 ; gain = 189.945 ; free physical = 1607 ; free virtual = 12420
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2dc3124f6
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3498.910 ; gain = 189.945 ; free physical = 1608 ; free virtual = 12420
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2dc3124f6
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3498.910 ; gain = 189.945 ; free physical = 1608 ; free virtual = 12420
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 29b99456b
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 3567.668 ; gain = 258.703 ; free physical = 1529 ; free virtual = 12343
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.533 | TNS=0.000 | WHS=-0.147 | THS=-17.211|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.000344164 %
+ Global Horizontal Routing Utilization = 0.000132188 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 1011
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 1001
+ Number of Partially Routed Nets = 10
+ Number of Node Overlaps = 5
+
+Phase 2 Router Initialization | Checksum: 275108769
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12335
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 275108769
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12335
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 25ae08356
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12336
+Phase 4 Initial Routing | Checksum: 25ae08356
+
+Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1522 ; free virtual = 12336
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 241
+ Number of Nodes with overlaps = 113
+ Number of Nodes with overlaps = 64
+ Number of Nodes with overlaps = 48
+ Number of Nodes with overlaps = 29
+ Number of Nodes with overlaps = 21
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.059 | TNS=-0.059 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 28b704ddd
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 5.2 Global Iteration 1
+ Number of Nodes with overlaps = 31
+ Number of Nodes with overlaps = 30
+ Number of Nodes with overlaps = 18
+ Number of Nodes with overlaps = 10
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.247 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.2 Global Iteration 1 | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+Phase 5 Rip-up And Reroute | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+Phase 6 Delay and Skew Optimization | Checksum: 1fb38632d
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.340 | TNS=0.000 | WHS=0.142 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+Phase 7 Post Hold Fix | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0778621 %
+ Global Horizontal Routing Utilization = 0.099967 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1525 ; free virtual = 12339
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 1ae620df2
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 202c526cf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 202c526cf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.340 | TNS=0.000 | WHS=0.142 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 202c526cf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+Total Elapsed time in route_design: 26.43 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: f4216adf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: f4216adf
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:26 . Memory (MB): peak = 3575.059 ; gain = 266.094 ; free physical = 1524 ; free virtual = 12338
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+88 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:27 . Memory (MB): peak = 3575.059 ; gain = 274.098 ; free physical = 1524 ; free virtual = 12338
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+108 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1501 ; free virtual = 12316
+Wrote PlaceDB: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1499 ; free virtual = 12316
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1508 ; free virtual = 12325
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1508 ; free virtual = 12325
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1508 ; free virtual = 12325
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1507 ; free virtual = 12325
+Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3663.102 ; gain = 0.000 ; free physical = 1507 ; free virtual = 12325
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+Command: write_bitstream -force audioProc.bit -bin_file
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2/O, cell leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2__0/O, cell rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./audioProc.bit...
+Writing bitstream ./audioProc.bin...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+119 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 3915.926 ; gain = 252.824 ; free physical = 1128 ; free virtual = 11967
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 18 16:56:35 2025...
diff --git a/proj/AudioProc.runs/impl_1/runme.sh b/proj/AudioProc.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4cf87fa7e82248ea64c8b18d7ae18b939906b885
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+
+
diff --git a/proj/AudioProc.runs/impl_1/vivado.jou b/proj/AudioProc.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..59712724d345a5021b269b3d8306bb063d8fdd3e
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar 18 16:54:31 2025
+# Process ID: 35875
+# Current directory: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-104
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :12th Gen Intel(R) Core(TM) i5-12500
+# CPU Frequency :1916.620 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16425 MB
+# Swap memory :4294 MB
+# Total Virtual :20720 MB
+# Available Virtual :15343 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado.pb b/proj/AudioProc.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..2c8dc5a4594909929ecff24f71f6894521228ef7
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/vivado.pb differ
diff --git a/proj/AudioProc.runs/impl_1/write_bitstream.pb b/proj/AudioProc.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..73854f42fcd148a6e64a4cdc4d2bde80ce49433b
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/write_bitstream.pb differ
diff --git a/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst b/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc b/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..bc42a567f1eb25b1eb644eb4ae61d31d0f0d15a8
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc
@@ -0,0 +1,51 @@
+set_property SRC_FILE_INFO {cfile:/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc rfile:../../../../src/constraints/NexysVideo_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports { led3 }];#[get_ports {LED[3]}]
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports { led4 }];#[get_ports {LED[4]}]
+set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports { led5 }];#[get_ports {LED[5]}]
+set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports { led6 }];#[get_ports {LED[6]}]
+set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports { led7 }];#[get_ports {LED[7]}]
+set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports BTNC]
+set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports BTND]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports BTNL]
+set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports BTNR]
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports BTNU]
+set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports rstn]
+set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports sw]
+set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports { sw3 }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports { sw4 }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports { sw5 }]; #IO_0_15 Sch=sw[5]
+set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { sw6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { sw7 }]; #IO_25_15 Sch=sw[7]
+set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ac_adc_sdata]
+set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ac_bclk]
+set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ac_dac_sdata]
+set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ac_lrclk]
+set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ac_mclk]
+set_property src_info {type:XDC file:1 line:202 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports scl]
+set_property src_info {type:XDC file:1 line:203 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports sda]
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..c8fc24b13d3716405dd29d2ae10c5b4f522c69b0
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="a23aboul" Host="fl-tp-br-104" Pid="35327" HostCore="12" HostMemory="16040140">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/.vivado.end.rst b/proj/AudioProc.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.js b/proj/AudioProc.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.sh b/proj/AudioProc.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/synth_1/__synthesis_is_complete__ b/proj/AudioProc.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/audioProc.dcp b/proj/AudioProc.runs/synth_1/audioProc.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..81d28e54c38378253645942c6403b97210623bc6
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/audioProc.dcp differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc.tcl b/proj/AudioProc.runs/synth_1/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0c8f20a71033ed3357254b74416a9896b3ae473d
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc.tcl
@@ -0,0 +1,129 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/audioProc.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a200tsbg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.cache/wt [current_project]
+set_property parent.project_path /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_repo_paths /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/repo [current_project]
+update_ip_catalog
+set_property ip_output_repo /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_verilog -library xil_defaultlib {
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v
+}
+read_vhdl -library xil_defaultlib {
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/operativeUnit.vhd
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd
+ /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/i2s_ctl.vhd
+}
+read_ip -quiet /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc
+set_property used_in_implementation false [get_files /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+
+read_xdc dont_touch.xdc
+set_property used_in_implementation false [get_files dont_touch.xdc]
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef audioProc.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/proj/AudioProc.runs/synth_1/audioProc.vds b/proj/AudioProc.runs/synth_1/audioProc.vds
new file mode 100644
index 0000000000000000000000000000000000000000..c4ea35d5b9de76018570764b29043994241a5fd4
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -0,0 +1,461 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar 18 16:52:56 2025
+# Process ID: 35398
+# Current directory: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1
+# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+# Log file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/audioProc.vds
+# Journal file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-104
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :12th Gen Intel(R) Core(TM) i5-12500
+# CPU Frequency :2166.016 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16425 MB
+# Swap memory :4294 MB
+# Total Virtual :20720 MB
+# Available Virtual :15339 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 3322 ; free virtual = 14045
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+WARNING: [Vivado_Tcl 4-393] The 'Implementation' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+INFO: [IP_Flow 19-2162] IP 'clk_wiz_0' is locked:
+* IP definition 'Clocking Wizard (5.2)' for IP 'clk_wiz_0' (customized with software release 2015.3) has a newer major version in the IP Catalog.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 35592
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2500.762 ; gain = 419.496 ; free physical = 2138 ; free virtual = 12890
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:13]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/.Xil/Vivado-35398-fl-tp-br-104/realtime/clk_wiz_0_stub.vhdl:18]
+WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:85]
+WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:85]
+INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:24]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:51]
+INFO: [Synth 8-638] synthesizing module 'TWICtl' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:330]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:363]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:381]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:399]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:417]
+INFO: [Synth 8-256] done synthesizing module 'TWICtl' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:151]
+INFO: [Synth 8-6155] done synthesizing module 'audio_init' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:24]
+INFO: [Synth 8-6157] synthesizing module 'debounce' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'debounce' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v:23]
+INFO: [Synth 8-638] synthesizing module 'i2s_ctl' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-256] done synthesizing module 'i2s_ctl' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'fir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:28]
+ Parameter dwidth bound to: 24 - type: integer
+ Parameter ntaps bound to: 16 - type: integer
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:43]
+WARNING: [Synth 8-614] signal 'SR_presentState' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:61]
+WARNING: [Synth 8-614] signal 'I_inputSampleValid' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:61]
+WARNING: [Synth 8-614] signal 'I_processingDone' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:61]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:28]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7023] instance 'leftFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7023] instance 'rightFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+INFO: [Synth 8-6155] done synthesizing module 'audioProc' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:13]
+WARNING: [Synth 8-6014] Unused sequential element timeOutCnt_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:236]
+WARNING: [Synth 8-6014] Unused sequential element errTypeR_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:313]
+WARNING: [Synth 8-6014] Unused sequential element regData1_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:135]
+WARNING: [Synth 8-6014] Unused sequential element initFbWe_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:150]
+WARNING: [Synth 8-3848] Net dbg_output_0 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:18]
+WARNING: [Synth 8-3848] Net dbg_output_1 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:19]
+WARNING: [Synth 8-3848] Net dbg_output_2 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:20]
+WARNING: [Synth 8-3848] Net dbg_output_3 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:21]
+WARNING: [Synth 8-3848] Net dbg_output_4 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:22]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataL_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:225]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataR_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:226]
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2584.730 ; gain = 503.465 ; free physical = 2035 ; free virtual = 12790
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2602.543 ; gain = 521.277 ; free physical = 2039 ; free virtual = 12794
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2602.543 ; gain = 521.277 ; free physical = 2039 ; free virtual = 12794
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2602.543 ; gain = 0.000 ; free physical = 2039 ; free virtual = 12794
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/audioProc_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/audioProc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2750.324 ; gain = 0.000 ; free physical = 2008 ; free virtual = 12777
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2750.324 ; gain = 0.000 ; free physical = 2008 ; free virtual = 12777
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2750.324 ; gain = 669.059 ; free physical = 2012 ; free virtual = 12782
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 2012 ; free virtual = 12782
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
+Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 2012 ; free virtual = 12782
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ stidle | 0001 | 0000
+ ststart | 0100 | 0001
+ stwrite | 0000 | 0011
+ stsack | 0011 | 0110
+ stread | 0010 | 0010
+ stmnackstart | 0110 | 1001
+ stmack | 0111 | 0111
+ stmnackstop | 0101 | 1000
+ ststop | 1100 | 0101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'gray' in module 'TWICtl'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00001 | 000
+ store | 00010 | 001
+ processing_loop | 00100 | 010
+ output | 01000 | 011
+ wait_end_sample | 10000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:57]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 2007 ; free virtual = 12776
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 32 Bit Adders := 1
+ 2 Input 31 Bit Adders := 1
+ 2 Input 13 Bit Adders := 5
+ 2 Input 8 Bit Adders := 4
+ 2 Input 7 Bit Adders := 5
+ 2 Input 6 Bit Adders := 2
+ 2 Input 5 Bit Adders := 4
+ 2 Input 4 Bit Adders := 5
+ 2 Input 3 Bit Adders := 3
+ 2 Input 2 Bit Adders := 3
++---Registers :
+ 33 Bit Registers := 1
+ 32 Bit Registers := 3
+ 31 Bit Registers := 1
+ 24 Bit Registers := 2
+ 20 Bit Registers := 2
+ 13 Bit Registers := 5
+ 8 Bit Registers := 37
+ 7 Bit Registers := 3
+ 5 Bit Registers := 4
+ 4 Bit Registers := 4
+ 3 Bit Registers := 1
+ 2 Bit Registers := 2
+ 1 Bit Registers := 18
++---Muxes :
+ 2 Input 32 Bit Muxes := 3
+ 2 Input 24 Bit Muxes := 2
+ 2 Input 20 Bit Muxes := 2
+ 2 Input 8 Bit Muxes := 16
+ 2 Input 5 Bit Muxes := 9
+ 8 Input 5 Bit Muxes := 1
+ 5 Input 5 Bit Muxes := 2
+ 16 Input 5 Bit Muxes := 2
+ 9 Input 4 Bit Muxes := 1
+ 21 Input 4 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 11
+ 5 Input 3 Bit Muxes := 2
+ 3 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 45
+ 4 Input 1 Bit Muxes := 21
+ 3 Input 1 Bit Muxes := 5
+ 9 Input 1 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 6
+ 36 Input 1 Bit Muxes := 1
+ 5 Input 1 Bit Muxes := 4
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1982 ; free virtual = 12758
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12765
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12765
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |clk_wiz | 1|
+|2 |CARRY4 | 38|
+|3 |LUT1 | 43|
+|4 |LUT2 | 115|
+|5 |LUT3 | 67|
+|6 |LUT4 | 73|
+|7 |LUT5 | 107|
+|8 |LUT6 | 252|
+|9 |MUXF7 | 33|
+|10 |MUXF8 | 16|
+|11 |FDCE | 318|
+|12 |FDPE | 2|
+|13 |FDRE | 239|
+|14 |FDSE | 20|
+|15 |LD | 10|
+|16 |IBUF | 8|
+|17 |IOBUF | 2|
+|18 |OBUF | 9|
++------+--------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 1 critical warnings and 39 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 2758.328 ; gain = 529.281 ; free physical = 1981 ; free virtual = 12764
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.336 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2758.336 ; gain = 0.000 ; free physical = 2300 ; free virtual = 13083
+INFO: [Netlist 29-17] Analyzing 99 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2758.336 ; gain = 0.000 ; free physical = 2299 ; free virtual = 13083
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 12 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+ LD => LDCE: 10 instances
+
+Synth Design complete | Checksum: 138d1f1b
+INFO: [Common 17-83] Releasing license: Synthesis
+50 Infos, 107 Warnings, 1 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:44 . Memory (MB): peak = 2758.336 ; gain = 1064.875 ; free physical = 2299 ; free virtual = 13083
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2292.884; main = 1927.028; forked = 418.377
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3863.039; main = 2758.332; forked = 1104.707
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2782.340 ; gain = 0.000 ; free physical = 2291 ; free virtual = 13075
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 18 16:54:27 2025...
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e0716309b799442a55decaf4be80dbc67dc6eeb3
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..bdda8901a05bdb6da18dccb0d014632e22f4a1bc
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
@@ -0,0 +1,192 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Tue Mar 18 16:54:27 2025
+| Host : fl-tp-br-104 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 649 | 0 | 0 | 134600 | 0.48 |
+| LUT as Logic | 649 | 0 | 0 | 134600 | 0.48 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 589 | 0 | 0 | 269200 | 0.22 |
+| Register as Flip Flop | 579 | 0 | 0 | 269200 | 0.22 |
+| Register as Latch | 10 | 0 | 0 | 269200 | <0.01 |
+| F7 Muxes | 33 | 0 | 0 | 67300 | 0.05 |
+| F8 Muxes | 16 | 0 | 0 | 33650 | 0.05 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 328 | Yes | - | Reset |
+| 20 | Yes | Set | - |
+| 239 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 19 | 0 | 0 | 285 | 6.67 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 318 | Flop & Latch |
+| LUT6 | 252 | LUT |
+| FDRE | 239 | Flop & Latch |
+| LUT2 | 115 | LUT |
+| LUT5 | 107 | LUT |
+| LUT4 | 73 | LUT |
+| LUT3 | 67 | LUT |
+| LUT1 | 43 | LUT |
+| CARRY4 | 38 | CarryLogic |
+| MUXF7 | 33 | MuxFx |
+| FDSE | 20 | Flop & Latch |
+| MUXF8 | 16 | MuxFx |
+| LDCE | 10 | Flop & Latch |
+| IBUF | 10 | IO |
+| OBUF | 9 | IO |
+| OBUFT | 2 | IO |
+| FDPE | 2 | Flop & Latch |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/AudioProc.runs/synth_1/dont_touch.xdc b/proj/AudioProc.runs/synth_1/dont_touch.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..66c19266d666c8aaf421dd6518561f88157b1f7f
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/dont_touch.xdc
@@ -0,0 +1,7 @@
+# This file is automatically generated.
+# It contains project source information necessary for synthesis and implementation.
+
+# XDC: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc
+
+# IP: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==clk_wiz_0 || ORIG_REF_NAME==clk_wiz_0} -quiet] -quiet
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..860de4316c485711afd2abb5866f808ccbfea3cf
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1742313173">
+ <File Type="VDS-TIMINGSUMMARY" Name="audioProc_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="audioProc.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="audioProc_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="audioProc_utilization_synth.rpt"/>
+ <File Type="VDS-TIMING-PB" Name="audioProc_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="RDS-RDS" Name="audioProc.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="audioProc_drc_synth.rpt"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
+ <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
+ </StratHandle>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+</GenRun>
diff --git a/proj/AudioProc.runs/synth_1/htr.txt b/proj/AudioProc.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6eaa206564a408917c3a3780eaa04c938f0a3fb9
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
diff --git a/proj/AudioProc.runs/synth_1/rundef.js b/proj/AudioProc.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..aff081c0d785dcdfe807351ed4a33a8d2902062e
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/synth_1/runme.bat b/proj/AudioProc.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..afdfed421acc520b49d34425937935aaeff1d85f
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -0,0 +1,451 @@
+
+*** Running vivado
+ with args -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Tue Mar 18 16:52:56 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 3322 ; free virtual = 14045
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+WARNING: [Vivado_Tcl 4-393] The 'Implementation' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+INFO: [IP_Flow 19-2162] IP 'clk_wiz_0' is locked:
+* IP definition 'Clocking Wizard (5.2)' for IP 'clk_wiz_0' (customized with software release 2015.3) has a newer major version in the IP Catalog.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 35592
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2500.762 ; gain = 419.496 ; free physical = 2138 ; free virtual = 12890
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:13]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/.Xil/Vivado-35398-fl-tp-br-104/realtime/clk_wiz_0_stub.vhdl:18]
+WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:85]
+WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:85]
+INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:24]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:51]
+INFO: [Synth 8-638] synthesizing module 'TWICtl' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:330]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:363]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:381]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:399]
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:417]
+INFO: [Synth 8-256] done synthesizing module 'TWICtl' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:151]
+INFO: [Synth 8-6155] done synthesizing module 'audio_init' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:24]
+INFO: [Synth 8-6157] synthesizing module 'debounce' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'debounce' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v:23]
+INFO: [Synth 8-638] synthesizing module 'i2s_ctl' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-256] done synthesizing module 'i2s_ctl' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'fir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:28]
+ Parameter dwidth bound to: 24 - type: integer
+ Parameter ntaps bound to: 16 - type: integer
+INFO: [Synth 8-226] default block is never used [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:43]
+WARNING: [Synth 8-614] signal 'SR_presentState' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:61]
+WARNING: [Synth 8-614] signal 'I_inputSampleValid' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:61]
+WARNING: [Synth 8-614] signal 'I_processingDone' is read in the process but is not in the sensitivity list [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:61]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:28]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'leftFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7023] instance 'leftFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'rightFir' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7023] instance 'rightFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+INFO: [Synth 8-6155] done synthesizing module 'audioProc' (0#1) [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:13]
+WARNING: [Synth 8-6014] Unused sequential element timeOutCnt_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:236]
+WARNING: [Synth 8-6014] Unused sequential element errTypeR_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd:313]
+WARNING: [Synth 8-6014] Unused sequential element regData1_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:135]
+WARNING: [Synth 8-6014] Unused sequential element initFbWe_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v:150]
+WARNING: [Synth 8-3848] Net dbg_output_0 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:18]
+WARNING: [Synth 8-3848] Net dbg_output_1 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:19]
+WARNING: [Synth 8-3848] Net dbg_output_2 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:20]
+WARNING: [Synth 8-3848] Net dbg_output_3 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:21]
+WARNING: [Synth 8-3848] Net dbg_output_4 in module/entity fir does not have driver. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd:22]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataL_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:225]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataR_reg was removed. [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:226]
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2584.730 ; gain = 503.465 ; free physical = 2035 ; free virtual = 12790
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2602.543 ; gain = 521.277 ; free physical = 2039 ; free virtual = 12794
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2602.543 ; gain = 521.277 ; free physical = 2039 ; free virtual = 12794
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2602.543 ; gain = 0.000 ; free physical = 2039 ; free virtual = 12794
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/constraints/NexysVideo_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/audioProc_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/audioProc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2750.324 ; gain = 0.000 ; free physical = 2008 ; free virtual = 12777
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2750.324 ; gain = 0.000 ; free physical = 2008 ; free virtual = 12777
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2750.324 ; gain = 669.059 ; free physical = 2012 ; free virtual = 12782
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 2012 ; free virtual = 12782
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
+Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 2012 ; free virtual = 12782
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ stidle | 0001 | 0000
+ ststart | 0100 | 0001
+ stwrite | 0000 | 0011
+ stsack | 0011 | 0110
+ stread | 0010 | 0010
+ stmnackstart | 0110 | 1001
+ stmack | 0111 | 0111
+ stmnackstop | 0101 | 1000
+ ststop | 1100 | 0101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'gray' in module 'TWICtl'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00001 | 000
+ store | 00010 | 001
+ processing_loop | 00100 | 010
+ output | 01000 | 011
+ wait_end_sample | 10000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd:57]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 2007 ; free virtual = 12776
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 32 Bit Adders := 1
+ 2 Input 31 Bit Adders := 1
+ 2 Input 13 Bit Adders := 5
+ 2 Input 8 Bit Adders := 4
+ 2 Input 7 Bit Adders := 5
+ 2 Input 6 Bit Adders := 2
+ 2 Input 5 Bit Adders := 4
+ 2 Input 4 Bit Adders := 5
+ 2 Input 3 Bit Adders := 3
+ 2 Input 2 Bit Adders := 3
++---Registers :
+ 33 Bit Registers := 1
+ 32 Bit Registers := 3
+ 31 Bit Registers := 1
+ 24 Bit Registers := 2
+ 20 Bit Registers := 2
+ 13 Bit Registers := 5
+ 8 Bit Registers := 37
+ 7 Bit Registers := 3
+ 5 Bit Registers := 4
+ 4 Bit Registers := 4
+ 3 Bit Registers := 1
+ 2 Bit Registers := 2
+ 1 Bit Registers := 18
++---Muxes :
+ 2 Input 32 Bit Muxes := 3
+ 2 Input 24 Bit Muxes := 2
+ 2 Input 20 Bit Muxes := 2
+ 2 Input 8 Bit Muxes := 16
+ 2 Input 5 Bit Muxes := 9
+ 8 Input 5 Bit Muxes := 1
+ 5 Input 5 Bit Muxes := 2
+ 16 Input 5 Bit Muxes := 2
+ 9 Input 4 Bit Muxes := 1
+ 21 Input 4 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 11
+ 5 Input 3 Bit Muxes := 2
+ 3 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 45
+ 4 Input 1 Bit Muxes := 21
+ 3 Input 1 Bit Muxes := 5
+ 9 Input 1 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 6
+ 36 Input 1 Bit Muxes := 1
+ 5 Input 1 Bit Muxes := 4
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1982 ; free virtual = 12758
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12765
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12765
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |clk_wiz | 1|
+|2 |CARRY4 | 38|
+|3 |LUT1 | 43|
+|4 |LUT2 | 115|
+|5 |LUT3 | 67|
+|6 |LUT4 | 73|
+|7 |LUT5 | 107|
+|8 |LUT6 | 252|
+|9 |MUXF7 | 33|
+|10 |MUXF8 | 16|
+|11 |FDCE | 318|
+|12 |FDPE | 2|
+|13 |FDRE | 239|
+|14 |FDSE | 20|
+|15 |LD | 10|
+|16 |IBUF | 8|
+|17 |IOBUF | 2|
+|18 |OBUF | 9|
++------+--------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.328 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 1 critical warnings and 39 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 2758.328 ; gain = 529.281 ; free physical = 1981 ; free virtual = 12764
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2758.336 ; gain = 677.062 ; free physical = 1981 ; free virtual = 12764
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2758.336 ; gain = 0.000 ; free physical = 2300 ; free virtual = 13083
+INFO: [Netlist 29-17] Analyzing 99 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2758.336 ; gain = 0.000 ; free physical = 2299 ; free virtual = 13083
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 12 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+ LD => LDCE: 10 instances
+
+Synth Design complete | Checksum: 138d1f1b
+INFO: [Common 17-83] Releasing license: Synthesis
+50 Infos, 107 Warnings, 1 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:44 . Memory (MB): peak = 2758.336 ; gain = 1064.875 ; free physical = 2299 ; free virtual = 13083
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2292.884; main = 1927.028; forked = 418.377
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3863.039; main = 2758.332; forked = 1104.707
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2782.340 ; gain = 0.000 ; free physical = 2291 ; free virtual = 13075
+INFO: [Common 17-1381] The checkpoint '/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 18 16:54:27 2025...
diff --git a/proj/AudioProc.runs/synth_1/runme.sh b/proj/AudioProc.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b4b4cab7a3c5a753c2e2066bd41f29824f6ab5cd
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..c23c262e76c2321014a31b13dfe2dca67be39beb
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Mar 18 16:52:56 2025
+# Process ID: 35398
+# Current directory: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1
+# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+# Log file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/audioProc.vds
+# Journal file: /homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-104
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :12th Gen Intel(R) Core(TM) i5-12500
+# CPU Frequency :2166.016 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16425 MB
+# Swap memory :4294 MB
+# Total Virtual :20720 MB
+# Available Virtual :15339 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8f400cb24f2f4a80d335faf4585f5ed64d455a74
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/vivado.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/.nfs00000000023af225000000cc b/proj/AudioProc.sim/sim_1/behav/xsim/.nfs00000000023af225000000cc
new file mode 100644
index 0000000000000000000000000000000000000000..3265020ab6a16686ce4636fd49de7b80b5accbf3
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/.nfs00000000023af225000000cc
@@ -0,0 +1,38 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot audioProc_behav xil_defaultlib.audioProc xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+WARNING: [VRFC 10-9380] size mismatch in mixed-language port association of VHDL port 'en_tx_i' [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:136]
+WARNING: [VRFC 10-5021] port 'reset' is not connected on this instance [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:85]
+WARNING: [VRFC 10-5021] port 'dbg_output_0' is not connected on this instance [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:195]
+WARNING: [VRFC 10-5021] port 'dbg_output_0' is not connected on this instance [/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v:204]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.std_logic_arith
+Compiling package ieee.std_logic_unsigned
+Compiling package ieee.math_real
+Compiling package ieee.numeric_std
+Compiling module unisims_ver.IBUF
+Compiling module unisims_ver.MMCME2_ADV(CLKFBOUT_MULT_F=6.0,C...
+Compiling module unisims_ver.BUFG
+Compiling module xil_defaultlib.clk_wiz_0_clk_wiz
+Compiling module xil_defaultlib.clk_wiz_0
+Compiling architecture behavioral of entity xil_defaultlib.TWICtl [twictl_default]
+Compiling module xil_defaultlib.audio_init
+Compiling module xil_defaultlib.debounce
+Compiling architecture behavioral of entity xil_defaultlib.i2s_ctl [i2s_ctl_default]
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture myarch of entity xil_defaultlib.fir [\fir(dwidth=24,ntaps=16)\]
+Compiling module xil_defaultlib.audioProc
+Compiling module xil_defaultlib.glbl
+Built simulation snapshot audioProc_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/.nfs00000000028e57ef000000cd b/proj/AudioProc.sim/sim_1/behav/xsim/.nfs00000000028e57ef000000cd
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/audioProc.tcl b/proj/AudioProc.sim/sim_1/behav/xsim/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/audioProc.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/audioProc_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/audioProc_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..e4a9461ef93560e000683bd3dc1c68117c5fe63e
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/audioProc_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000000000000000000000000000000000000..54abb730f4508fc6e434d127e1c175d82147b12a
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..483fee42b0853457d0ffbdbe30406260ee92417a
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Tue Mar 18 17:33:17 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000000000000000000000000000000000000..ca74b1ceae89ecaafc2730eed71d53d797cf5f35
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,19 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..71d81085af1d450cd31b47a00a2e1bccf437e1c3
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Tue Mar 18 17:33:19 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
new file mode 100755
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..afe3748c0c0e3160f2f6d34c54d8fcefbbb7abda
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Tue Mar 18 17:33:20 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..bd7be2ecc1a19e71becb89aef59b6b6a9b28842d
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..0107b4e0d82614c83b8f672cdff5fbeac1c3cfc2
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -0,0 +1,9 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../src/hdl/firUnit.vhd" \
+"../../../../../src/hdl/tb_firUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..f17fb2dfa33c0317a5b8bf49cd8cf2f51e64bf31
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/Compile_Options.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..f3cebc99ece0e8fe86988ba6ddf5df500f7b77ae
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "audioProc_behav" "xil_defaultlib.audioProc" "xil_defaultlib.glbl" -log "elaborate.log"
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/TempBreakPointFile.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..5ac3a6827d62a4bce096fae5e24ef4b89111d879
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_1.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..b9f78e33b4efd260ae3108b0227ae470c42e0b96
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_1.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_2.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..cde52e6b537010fdbe3277b5fdb5358f5dec98e8
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_2.c
@@ -0,0 +1,479 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_219(char*, char *);
+IKI_DLLESPEC extern void execute_220(char*, char *);
+IKI_DLLESPEC extern void execute_301(char*, char *);
+IKI_DLLESPEC extern void execute_302(char*, char *);
+IKI_DLLESPEC extern void execute_308(char*, char *);
+IKI_DLLESPEC extern void execute_309(char*, char *);
+IKI_DLLESPEC extern void execute_398(char*, char *);
+IKI_DLLESPEC extern void execute_399(char*, char *);
+IKI_DLLESPEC extern void execute_400(char*, char *);
+IKI_DLLESPEC extern void execute_401(char*, char *);
+IKI_DLLESPEC extern void execute_402(char*, char *);
+IKI_DLLESPEC extern void execute_403(char*, char *);
+IKI_DLLESPEC extern void execute_404(char*, char *);
+IKI_DLLESPEC extern void execute_405(char*, char *);
+IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_411(char*, char *);
+IKI_DLLESPEC extern void execute_412(char*, char *);
+IKI_DLLESPEC extern void execute_413(char*, char *);
+IKI_DLLESPEC extern void execute_414(char*, char *);
+IKI_DLLESPEC extern void execute_415(char*, char *);
+IKI_DLLESPEC extern void execute_416(char*, char *);
+IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_394(char*, char *);
+IKI_DLLESPEC extern void execute_395(char*, char *);
+IKI_DLLESPEC extern void execute_310(char*, char *);
+IKI_DLLESPEC extern void execute_6(char*, char *);
+IKI_DLLESPEC extern void execute_7(char*, char *);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_12(char*, char *);
+IKI_DLLESPEC extern void execute_13(char*, char *);
+IKI_DLLESPEC extern void execute_14(char*, char *);
+IKI_DLLESPEC extern void execute_15(char*, char *);
+IKI_DLLESPEC extern void execute_16(char*, char *);
+IKI_DLLESPEC extern void execute_17(char*, char *);
+IKI_DLLESPEC extern void execute_18(char*, char *);
+IKI_DLLESPEC extern void execute_19(char*, char *);
+IKI_DLLESPEC extern void execute_20(char*, char *);
+IKI_DLLESPEC extern void execute_22(char*, char *);
+IKI_DLLESPEC extern void execute_23(char*, char *);
+IKI_DLLESPEC extern void execute_24(char*, char *);
+IKI_DLLESPEC extern void execute_25(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_31(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_35(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_56(char*, char *);
+IKI_DLLESPEC extern void execute_57(char*, char *);
+IKI_DLLESPEC extern void execute_58(char*, char *);
+IKI_DLLESPEC extern void execute_59(char*, char *);
+IKI_DLLESPEC extern void execute_60(char*, char *);
+IKI_DLLESPEC extern void execute_61(char*, char *);
+IKI_DLLESPEC extern void execute_62(char*, char *);
+IKI_DLLESPEC extern void execute_63(char*, char *);
+IKI_DLLESPEC extern void execute_64(char*, char *);
+IKI_DLLESPEC extern void execute_65(char*, char *);
+IKI_DLLESPEC extern void execute_66(char*, char *);
+IKI_DLLESPEC extern void execute_67(char*, char *);
+IKI_DLLESPEC extern void execute_68(char*, char *);
+IKI_DLLESPEC extern void execute_69(char*, char *);
+IKI_DLLESPEC extern void execute_70(char*, char *);
+IKI_DLLESPEC extern void execute_71(char*, char *);
+IKI_DLLESPEC extern void execute_72(char*, char *);
+IKI_DLLESPEC extern void execute_73(char*, char *);
+IKI_DLLESPEC extern void execute_74(char*, char *);
+IKI_DLLESPEC extern void execute_75(char*, char *);
+IKI_DLLESPEC extern void execute_76(char*, char *);
+IKI_DLLESPEC extern void execute_77(char*, char *);
+IKI_DLLESPEC extern void execute_78(char*, char *);
+IKI_DLLESPEC extern void execute_79(char*, char *);
+IKI_DLLESPEC extern void execute_80(char*, char *);
+IKI_DLLESPEC extern void execute_81(char*, char *);
+IKI_DLLESPEC extern void execute_82(char*, char *);
+IKI_DLLESPEC extern void execute_83(char*, char *);
+IKI_DLLESPEC extern void execute_84(char*, char *);
+IKI_DLLESPEC extern void execute_85(char*, char *);
+IKI_DLLESPEC extern void execute_86(char*, char *);
+IKI_DLLESPEC extern void execute_87(char*, char *);
+IKI_DLLESPEC extern void execute_88(char*, char *);
+IKI_DLLESPEC extern void execute_89(char*, char *);
+IKI_DLLESPEC extern void execute_90(char*, char *);
+IKI_DLLESPEC extern void execute_91(char*, char *);
+IKI_DLLESPEC extern void execute_92(char*, char *);
+IKI_DLLESPEC extern void execute_93(char*, char *);
+IKI_DLLESPEC extern void execute_94(char*, char *);
+IKI_DLLESPEC extern void execute_95(char*, char *);
+IKI_DLLESPEC extern void execute_96(char*, char *);
+IKI_DLLESPEC extern void execute_97(char*, char *);
+IKI_DLLESPEC extern void execute_98(char*, char *);
+IKI_DLLESPEC extern void execute_99(char*, char *);
+IKI_DLLESPEC extern void execute_100(char*, char *);
+IKI_DLLESPEC extern void execute_101(char*, char *);
+IKI_DLLESPEC extern void execute_102(char*, char *);
+IKI_DLLESPEC extern void execute_103(char*, char *);
+IKI_DLLESPEC extern void execute_104(char*, char *);
+IKI_DLLESPEC extern void execute_105(char*, char *);
+IKI_DLLESPEC extern void execute_106(char*, char *);
+IKI_DLLESPEC extern void execute_107(char*, char *);
+IKI_DLLESPEC extern void execute_108(char*, char *);
+IKI_DLLESPEC extern void execute_109(char*, char *);
+IKI_DLLESPEC extern void execute_110(char*, char *);
+IKI_DLLESPEC extern void execute_111(char*, char *);
+IKI_DLLESPEC extern void execute_112(char*, char *);
+IKI_DLLESPEC extern void execute_113(char*, char *);
+IKI_DLLESPEC extern void execute_114(char*, char *);
+IKI_DLLESPEC extern void execute_115(char*, char *);
+IKI_DLLESPEC extern void execute_131(char*, char *);
+IKI_DLLESPEC extern void execute_311(char*, char *);
+IKI_DLLESPEC extern void execute_312(char*, char *);
+IKI_DLLESPEC extern void execute_315(char*, char *);
+IKI_DLLESPEC extern void execute_316(char*, char *);
+IKI_DLLESPEC extern void execute_328(char*, char *);
+IKI_DLLESPEC extern void execute_329(char*, char *);
+IKI_DLLESPEC extern void execute_330(char*, char *);
+IKI_DLLESPEC extern void execute_331(char*, char *);
+IKI_DLLESPEC extern void execute_332(char*, char *);
+IKI_DLLESPEC extern void execute_333(char*, char *);
+IKI_DLLESPEC extern void execute_334(char*, char *);
+IKI_DLLESPEC extern void execute_335(char*, char *);
+IKI_DLLESPEC extern void execute_336(char*, char *);
+IKI_DLLESPEC extern void execute_337(char*, char *);
+IKI_DLLESPEC extern void execute_338(char*, char *);
+IKI_DLLESPEC extern void execute_339(char*, char *);
+IKI_DLLESPEC extern void execute_340(char*, char *);
+IKI_DLLESPEC extern void execute_341(char*, char *);
+IKI_DLLESPEC extern void execute_342(char*, char *);
+IKI_DLLESPEC extern void execute_343(char*, char *);
+IKI_DLLESPEC extern void execute_344(char*, char *);
+IKI_DLLESPEC extern void execute_345(char*, char *);
+IKI_DLLESPEC extern void execute_346(char*, char *);
+IKI_DLLESPEC extern void execute_347(char*, char *);
+IKI_DLLESPEC extern void execute_348(char*, char *);
+IKI_DLLESPEC extern void execute_349(char*, char *);
+IKI_DLLESPEC extern void execute_350(char*, char *);
+IKI_DLLESPEC extern void execute_351(char*, char *);
+IKI_DLLESPEC extern void execute_352(char*, char *);
+IKI_DLLESPEC extern void execute_353(char*, char *);
+IKI_DLLESPEC extern void execute_354(char*, char *);
+IKI_DLLESPEC extern void execute_355(char*, char *);
+IKI_DLLESPEC extern void execute_356(char*, char *);
+IKI_DLLESPEC extern void execute_357(char*, char *);
+IKI_DLLESPEC extern void execute_358(char*, char *);
+IKI_DLLESPEC extern void execute_359(char*, char *);
+IKI_DLLESPEC extern void execute_360(char*, char *);
+IKI_DLLESPEC extern void execute_361(char*, char *);
+IKI_DLLESPEC extern void execute_362(char*, char *);
+IKI_DLLESPEC extern void execute_363(char*, char *);
+IKI_DLLESPEC extern void execute_364(char*, char *);
+IKI_DLLESPEC extern void execute_365(char*, char *);
+IKI_DLLESPEC extern void execute_366(char*, char *);
+IKI_DLLESPEC extern void execute_367(char*, char *);
+IKI_DLLESPEC extern void execute_368(char*, char *);
+IKI_DLLESPEC extern void execute_369(char*, char *);
+IKI_DLLESPEC extern void execute_370(char*, char *);
+IKI_DLLESPEC extern void execute_371(char*, char *);
+IKI_DLLESPEC extern void execute_372(char*, char *);
+IKI_DLLESPEC extern void execute_373(char*, char *);
+IKI_DLLESPEC extern void execute_374(char*, char *);
+IKI_DLLESPEC extern void execute_375(char*, char *);
+IKI_DLLESPEC extern void execute_376(char*, char *);
+IKI_DLLESPEC extern void execute_377(char*, char *);
+IKI_DLLESPEC extern void execute_378(char*, char *);
+IKI_DLLESPEC extern void execute_379(char*, char *);
+IKI_DLLESPEC extern void execute_380(char*, char *);
+IKI_DLLESPEC extern void execute_381(char*, char *);
+IKI_DLLESPEC extern void execute_382(char*, char *);
+IKI_DLLESPEC extern void execute_383(char*, char *);
+IKI_DLLESPEC extern void execute_384(char*, char *);
+IKI_DLLESPEC extern void execute_387(char*, char *);
+IKI_DLLESPEC extern void execute_138(char*, char *);
+IKI_DLLESPEC extern void execute_196(char*, char *);
+IKI_DLLESPEC extern void execute_197(char*, char *);
+IKI_DLLESPEC extern void execute_198(char*, char *);
+IKI_DLLESPEC extern void execute_199(char*, char *);
+IKI_DLLESPEC extern void execute_396(char*, char *);
+IKI_DLLESPEC extern void execute_397(char*, char *);
+IKI_DLLESPEC extern void execute_174(char*, char *);
+IKI_DLLESPEC extern void execute_175(char*, char *);
+IKI_DLLESPEC extern void execute_176(char*, char *);
+IKI_DLLESPEC extern void execute_177(char*, char *);
+IKI_DLLESPEC extern void execute_178(char*, char *);
+IKI_DLLESPEC extern void execute_179(char*, char *);
+IKI_DLLESPEC extern void execute_180(char*, char *);
+IKI_DLLESPEC extern void execute_181(char*, char *);
+IKI_DLLESPEC extern void execute_182(char*, char *);
+IKI_DLLESPEC extern void execute_183(char*, char *);
+IKI_DLLESPEC extern void execute_184(char*, char *);
+IKI_DLLESPEC extern void execute_185(char*, char *);
+IKI_DLLESPEC extern void execute_186(char*, char *);
+IKI_DLLESPEC extern void execute_187(char*, char *);
+IKI_DLLESPEC extern void execute_188(char*, char *);
+IKI_DLLESPEC extern void execute_189(char*, char *);
+IKI_DLLESPEC extern void execute_190(char*, char *);
+IKI_DLLESPEC extern void execute_191(char*, char *);
+IKI_DLLESPEC extern void execute_192(char*, char *);
+IKI_DLLESPEC extern void execute_193(char*, char *);
+IKI_DLLESPEC extern void execute_194(char*, char *);
+IKI_DLLESPEC extern void execute_195(char*, char *);
+IKI_DLLESPEC extern void execute_201(char*, char *);
+IKI_DLLESPEC extern void execute_202(char*, char *);
+IKI_DLLESPEC extern void execute_204(char*, char *);
+IKI_DLLESPEC extern void execute_205(char*, char *);
+IKI_DLLESPEC extern void execute_206(char*, char *);
+IKI_DLLESPEC extern void execute_207(char*, char *);
+IKI_DLLESPEC extern void execute_208(char*, char *);
+IKI_DLLESPEC extern void execute_209(char*, char *);
+IKI_DLLESPEC extern void execute_210(char*, char *);
+IKI_DLLESPEC extern void execute_211(char*, char *);
+IKI_DLLESPEC extern void execute_212(char*, char *);
+IKI_DLLESPEC extern void execute_213(char*, char *);
+IKI_DLLESPEC extern void execute_214(char*, char *);
+IKI_DLLESPEC extern void execute_215(char*, char *);
+IKI_DLLESPEC extern void execute_216(char*, char *);
+IKI_DLLESPEC extern void execute_217(char*, char *);
+IKI_DLLESPEC extern void execute_218(char*, char *);
+IKI_DLLESPEC extern void execute_238(char*, char *);
+IKI_DLLESPEC extern void execute_262(char*, char *);
+IKI_DLLESPEC extern void execute_263(char*, char *);
+IKI_DLLESPEC extern void execute_241(char*, char *);
+IKI_DLLESPEC extern void execute_242(char*, char *);
+IKI_DLLESPEC extern void execute_243(char*, char *);
+IKI_DLLESPEC extern void execute_244(char*, char *);
+IKI_DLLESPEC extern void execute_245(char*, char *);
+IKI_DLLESPEC extern void execute_246(char*, char *);
+IKI_DLLESPEC extern void execute_247(char*, char *);
+IKI_DLLESPEC extern void execute_248(char*, char *);
+IKI_DLLESPEC extern void execute_249(char*, char *);
+IKI_DLLESPEC extern void execute_251(char*, char *);
+IKI_DLLESPEC extern void execute_252(char*, char *);
+IKI_DLLESPEC extern void execute_253(char*, char *);
+IKI_DLLESPEC extern void execute_254(char*, char *);
+IKI_DLLESPEC extern void execute_255(char*, char *);
+IKI_DLLESPEC extern void execute_256(char*, char *);
+IKI_DLLESPEC extern void execute_257(char*, char *);
+IKI_DLLESPEC extern void execute_258(char*, char *);
+IKI_DLLESPEC extern void execute_259(char*, char *);
+IKI_DLLESPEC extern void execute_260(char*, char *);
+IKI_DLLESPEC extern void execute_261(char*, char *);
+IKI_DLLESPEC extern void execute_304(char*, char *);
+IKI_DLLESPEC extern void execute_305(char*, char *);
+IKI_DLLESPEC extern void execute_306(char*, char *);
+IKI_DLLESPEC extern void execute_307(char*, char *);
+IKI_DLLESPEC extern void execute_417(char*, char *);
+IKI_DLLESPEC extern void execute_418(char*, char *);
+IKI_DLLESPEC extern void execute_419(char*, char *);
+IKI_DLLESPEC extern void execute_420(char*, char *);
+IKI_DLLESPEC extern void execute_421(char*, char *);
+IKI_DLLESPEC extern void execute_422(char*, char *);
+IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_18(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_19(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_21(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_22(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_23(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_24(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_25(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_26(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_74(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_76(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_708(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_709(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_710(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_712(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_723(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_768(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_809(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_841(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_261(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_262(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_263(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_705(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_706(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_707(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[340] = {(funcp)execute_219, (funcp)execute_220, (funcp)execute_301, (funcp)execute_302, (funcp)execute_308, (funcp)execute_309, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_411, (funcp)execute_412, (funcp)execute_413, (funcp)execute_414, (funcp)execute_415, (funcp)execute_416, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_394, (funcp)execute_395, (funcp)execute_310, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_88, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_96, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_103, (funcp)execute_104, (funcp)execute_105, (funcp)execute_106, (funcp)execute_107, (funcp)execute_108, (funcp)execute_109, (funcp)execute_110, (funcp)execute_111, (funcp)execute_112, (funcp)execute_113, (funcp)execute_114, (funcp)execute_115, (funcp)execute_131, (funcp)execute_311, (funcp)execute_312, (funcp)execute_315, (funcp)execute_316, (funcp)execute_328, (funcp)execute_329, (funcp)execute_330, (funcp)execute_331, (funcp)execute_332, (funcp)execute_333, (funcp)execute_334, (funcp)execute_335, (funcp)execute_336, (funcp)execute_337, (funcp)execute_338, (funcp)execute_339, (funcp)execute_340, (funcp)execute_341, (funcp)execute_342, (funcp)execute_343, (funcp)execute_344, (funcp)execute_345, (funcp)execute_346, (funcp)execute_347, (funcp)execute_348, (funcp)execute_349, (funcp)execute_350, (funcp)execute_351, (funcp)execute_352, (funcp)execute_353, (funcp)execute_354, (funcp)execute_355, (funcp)execute_356, (funcp)execute_357, (funcp)execute_358, (funcp)execute_359, (funcp)execute_360, (funcp)execute_361, (funcp)execute_362, (funcp)execute_363, (funcp)execute_364, (funcp)execute_365, (funcp)execute_366, (funcp)execute_367, (funcp)execute_368, (funcp)execute_369, (funcp)execute_370, (funcp)execute_371, (funcp)execute_372, (funcp)execute_373, (funcp)execute_374, (funcp)execute_375, (funcp)execute_376, (funcp)execute_377, (funcp)execute_378, (funcp)execute_379, (funcp)execute_380, (funcp)execute_381, (funcp)execute_382, (funcp)execute_383, (funcp)execute_384, (funcp)execute_387, (funcp)execute_138, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_199, (funcp)execute_396, (funcp)execute_397, (funcp)execute_174, (funcp)execute_175, (funcp)execute_176, (funcp)execute_177, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)execute_189, (funcp)execute_190, (funcp)execute_191, (funcp)execute_192, (funcp)execute_193, (funcp)execute_194, (funcp)execute_195, (funcp)execute_201, (funcp)execute_202, (funcp)execute_204, (funcp)execute_205, (funcp)execute_206, (funcp)execute_207, (funcp)execute_208, (funcp)execute_209, (funcp)execute_210, (funcp)execute_211, (funcp)execute_212, (funcp)execute_213, (funcp)execute_214, (funcp)execute_215, (funcp)execute_216, (funcp)execute_217, (funcp)execute_218, (funcp)execute_238, (funcp)execute_262, (funcp)execute_263, (funcp)execute_241, (funcp)execute_242, (funcp)execute_243, (funcp)execute_244, (funcp)execute_245, (funcp)execute_246, (funcp)execute_247, (funcp)execute_248, (funcp)execute_249, (funcp)execute_251, (funcp)execute_252, (funcp)execute_253, (funcp)execute_254, (funcp)execute_255, (funcp)execute_256, (funcp)execute_257, (funcp)execute_258, (funcp)execute_259, (funcp)execute_260, (funcp)execute_261, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_307, (funcp)execute_417, (funcp)execute_418, (funcp)execute_419, (funcp)execute_420, (funcp)execute_421, (funcp)execute_422, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_18, (funcp)transaction_19, (funcp)transaction_21, (funcp)transaction_22, (funcp)transaction_23, (funcp)transaction_24, (funcp)transaction_25, (funcp)transaction_26, (funcp)transaction_38, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_73, (funcp)transaction_74, (funcp)transaction_75, (funcp)transaction_76, (funcp)transaction_77, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_708, (funcp)transaction_709, (funcp)transaction_710, (funcp)transaction_712, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_723, (funcp)transaction_768, (funcp)transaction_809, (funcp)transaction_841, (funcp)transaction_48, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_261, (funcp)transaction_262, (funcp)transaction_263, (funcp)transaction_264, (funcp)transaction_294, (funcp)transaction_705, (funcp)transaction_706, (funcp)transaction_707};
+const int NumRelocateId= 340;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/audioProc_behav/xsim.reloc", (void **)funcTab, 340);
+ iki_vhdl_file_variable_register(dp + 184064);
+ iki_vhdl_file_variable_register(dp + 184120);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/audioProc_behav/xsim.reloc");
+}
+
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+
+void wrapper_func_0(char *dp)
+
+{
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 269296, dp + 187616, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 269240, dp + 187672, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 276936, dp + 187840, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 276824, dp + 187896, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 276880, dp + 187952, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 276744, dp + 188960, 0, 23, 0, 23, 24, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 276784, dp + 189016, 0, 23, 0, 23, 24, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 281176, dp + 189576, 0, 23, 0, 23, 24, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 289352, dp + 189632, 0, 23, 0, 23, 24, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 268976, dp + 267168, 0, 7, 0, 7, 8, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 269016, dp + 267224, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 269072, dp + 267280, 0, 0, 0, 0, 1, 1);
+
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/audioProc_behav/xsim.reloc");
+ wrapper_func_0(dp);
+
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/audioProc_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/audioProc_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/audioProc_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_2.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_2.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..84478b326a5a665fa0bb581a4138fab661c81146
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/obj/xsim_2.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..717a7d40892b1ce2108e8804b07cb531316c50f0
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..bac607a08665544142ad3437e3d7829c6d084996
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.reloc b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..aead9776010ae5723a0ba4a67c3e8aa2ad8c9df5
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.reloc differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..290033811d9a4d96017d4de7639f31f2bd3aded6
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 8728133783113533148 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot audioProc_behav xil_defaultlib.audioProc xil_defaultlib.glbl" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/audioProc_behav/xsimk\" \"xsim.dir/audioProc_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/audioProc_behav/obj/xsim_1.lnx64.o\" \"xsim.dir/audioProc_behav/obj/xsim_2.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..dc4e9c22f305c50be90efad4d8f2737de24d0b3c
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.rtti differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.svtype b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..8240d0639442c8d02b45edeef15a77a5e7555de0
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.svtype differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..343518172d40aec56cbdb4bf9764f8844d2eeaea
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.type differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..da452a77372054d1690b4ab2b4aab39ed6ae6455
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsim.xdbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimcrash.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..17ff6321fb3e03839ccf2b7d13083caf8baa9e6f
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimk differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..3941a0c525149a1b146410be85f472e580aaf59e
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/audioProc_behav/xsimkernel.log
@@ -0,0 +1,4 @@
+Running: xsim.dir/audioProc_behav/xsimk -simmode gui -wdb audioProc_behav.wdb -simrunnum 0 -socket 45063
+Design successfully loaded
+Design Loading Memory Usage: 21324 KB (Peak: 21544 KB)
+Design Loading CPU Usage: 30 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..8a25a911b8deeb63be565a8d140a089d2d79bd2f
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log"
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..a765d9d11cc2a79b1ae73cc6bb7599b63bd54b64
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7ab0c10e23b830327d22ea4376c550b7ddc16698
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -0,0 +1,132 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_31(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_56(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[26] = {(funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 26;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 26);
+ iki_vhdl_file_variable_register(dp + 7880);
+ iki_vhdl_file_variable_register(dp + 7936);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_firUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_firUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_firUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..78ffee9ce8aeac033747ccb6b9e6b700e626c76a
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..6bafc2e54858b84881f8117b4ad981947e65a0e7
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..76aa07d52f576f907fcf28171da941e529935c80
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..be4062d2641c1989a01d09cf57f1eb682854173b
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..737c5fcbfedc8b46f60747151cfe99e2a6b825d2
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 7405425269517266624 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_firUnit_behav/xsimk\" \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..b361afaee11bceb9d57edd9d5b234e6d910463f7
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
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index 0000000000000000000000000000000000000000..6dc1deb65a85fafe2dcea36f677983510a180e28
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
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index 0000000000000000000000000000000000000000..db7420d28ff2db72d51d1e280609f1c719280b04
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..66c1fed697468ab7d29fb0134778046b79cfde30
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..565e42fd1150853bcabfd6a6072dc9e3d69f2d93
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..cc2bf96d8e006d5e7936b3fd331ace4e658954cb
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -0,0 +1,4 @@
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 46489
+Design successfully loaded
+Design Loading Memory Usage: 20176 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 10 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/audio@proc.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/audio@proc.sdb
new file mode 100644
index 0000000000000000000000000000000000000000..1862590b8b7b0e82768af2ff3c7b67e92411dae8
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/audio_init.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/audio_init.sdb
new file mode 100644
index 0000000000000000000000000000000000000000..95d3ced5b2d4c9a5b64b3d7ebc6595ae98ca02f6
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0.sdb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0_clk_wiz.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0_clk_wiz.sdb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/debounce.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/debounce.sdb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fir.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fir.vdb
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Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/fir.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..52579d96902ba625e8a45cc11702fb0748feec3e
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/i2s_ctl.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/i2s_ctl.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..1f03e846af515e600e55878c4908d5039da001c5
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..c4c60f3448371cf4337da6b5ffe034335d09cd9a
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..026e3613b25b2817c37a26e04c59049bc49e7a88
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/twictl.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/twictl.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..cdfd0b87d48a5b97d8d5e23cac12074729d15d41
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/twictl.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/twiutils.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/twiutils.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..6f91d13b0a281aef6109e451352d340d6ad7a3a5
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/twiutils.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..fa7ed06fe672a535027513de227d7c0502290489
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,17 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v,1708598507,verilog,,,,glbl,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/TWICtl.vhd,1742312270,vhdl,,,,twictl;twiutils,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v,1742312270,verilog,,,,audioProc,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v,1742312270,verilog,,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v,,audio_init,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/controlUnit.vhd,1742313082,vhdl,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v,1742312270,verilog,,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v,,debounce,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/fir.vhd,1742312270,vhdl,,,,fir,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd,1742312270,vhdl,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/i2s_ctl.vhd,1742312270,vhdl,,,,i2s_ctl,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/operativeUnit.vhd,1742313058,vhdl,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/tb_firUnit.vhd,1742312270,vhdl,,,,tb_firunit,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.v,1742312270,verilog,,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v,,clk_wiz_0,,,,,,,,
+/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,1742312270,verilog,,/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.v,,clk_wiz_0_clk_wiz,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..65c1bae3d8499ab13e863c8b22ed50ca77e3133e
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,490 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak
new file mode 100644
index 0000000000000000000000000000000000000000..65c1bae3d8499ab13e863c8b22ed50ca77e3133e
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -0,0 +1,490 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000000000000000000000000000000000000..54abb730f4508fc6e434d127e1c175d82147b12a
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ace38d25684630601f104b5f5e7f8b6756477681
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log
new file mode 100644
index 0000000000000000000000000000000000000000..9e961f1e047fd40157758d9effc5fa2f38c9b51b
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log
@@ -0,0 +1,12 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module clk_wiz_0_clk_wiz
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/ip/clk_wiz_0/clk_wiz_0.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module clk_wiz_0
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audio_init.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module audio_init
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/debounce.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module debounce
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/src/hdl/audioProc.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module audioProc
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module glbl
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e228b262321d29da4ca0edc45b8bf44866811a24
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb differ
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..71b54c570c80b3d9ba2dd565b5d5bfd1529b783c
--- /dev/null
+++ b/proj/AudioProc.xpr
@@ -0,0 +1,304 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/a23aboul/Bureau/MEDCOM/tp-filtre-etudiant-a23aboul/proj/AudioProc.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="6e78d971ee90445ab6fdf606480cb396"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="2"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_firUnit"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_firUnit"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
+ <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
+ </StratHandle>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+ <Desc>Vivado Implementation Defaults</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 705905d8efbad8482d22e650f8cce92ef78290f4..fbc7911f3293a0e2a686950ae3c1a66cd0e79961 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -49,34 +49,62 @@ architecture archi_operativeUnit of controlUnit is
begin
- process (_BLANK_) is
+ process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
- SR_presentState <= _BLANK_
+ SR_presentState <= WAIT_SAMPLE;
elsif rising_edge(I_clock) then -- rising clock edge
- _BLANK_
+ SR_presentState <= SR_futurState;
end if;
end process;
- process (_BLANK_) is
+ process (I_clock) is
begin
case SR_presentState is
when WAIT_SAMPLE =>
- _BLANK_
+ if ( I_inputSampleValid ='1') then
+ SR_futurState <= STORE;
+ else
+ SR_futurState <= WAIT_SAMPLE;
+ end if;
+
+
+ when STORE =>
+ SR_futurState <= PROCESSING_LOOP;
+
+
+ when PROCESSING_LOOP=>
+ if ( I_processingDone ='1') then
+ SR_futurState <= OUTPUT;
+ else
+ SR_futurState <= PROCESSING_LOOP;
+ end if;
+
+
+ when OUTPUT=>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+
+ when WAIT_END_SAMPLE=>
+ if (I_inputSampleValid ='0') then
+ SR_futurState <= WAIT_SAMPLE;
+ else
+ SR_futurState <= WAIT_END_SAMPLE;
+ end if;
+
when others => null;
end case;
end process;
- O_loadShift <= '1' when _BLANK_ ;
- O_initAddress <= '1' when _BLANK_ ;
- O_incrAddress <= '1' when _BLANK_ ;
- O_initSum <= '1' when _BLANK_ ;
- O_loadSum <= '1' when _BLANK_ ;
- O_loadY <= '1' when _BLANK_ ;
- O_FilteredSampleValid <= '1' when _BLANK_ ;
-
+ O_loadShift <= '1' when SR_presentState = STORE else '0';
+ O_initAddress <= '1' when SR_presentState = STORE else '0' ;
+ O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP else '0' ;
+ O_initSum <= '1' when SR_presentState = STORE else '0';
+ O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP else '0' ;
+ O_loadY <= '1' when SR_presentState = OUTPUT else '0' ;
+ O_FilteredSampleValid <= '1' when SR_presentState = OUTPUT else '0';
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 1286aff5a65b975b333b4136df7781bb98c0742e..25bdc852d1cd534a86730165447e7ad8c4d7dd52 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -62,7 +62,6 @@ architecture arch_operativeUnit of operativeUnit is
signal SR_readAddress : integer range 0 to 15; -- register files read address
-
begin
-- Low-pass filter provided with octave (or Matlab ;)) command
@@ -85,42 +84,74 @@ begin
to_signed(2, 8)
);
- shift : process (_BLANK_) is
+ shift : process (I_reset, I_clock) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));
- elsif _BLANK_
-
+ elsif rising_edge(I_clock) then
+ if I_loadShift = '1' then
+ for i in 15 downto 1 loop
+ SR_shiftRegister(i) <= SR_shiftRegister(i-1);
+ end loop;
+ SR_shiftRegister(0) <= signed(I_inputSample);
+ end if;
end if;
end process shift;
- incr_address : process (_BLANK_) is
+
+ incr_address : process (I_reset, I_clock) is
begin
+
+
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0;
- elsif _BLANK_
-
+ elsif rising_edge(I_clock) then
+ if I_initAddress = '1' then
+ SR_readAddress <= 0;
+ elsif I_incrAddress = '1' then
+ if SR_readAddress = 15 then
+ SR_readAddress <= 0;
+ else
+ SR_readAddress <= SR_readAddress + 1;
+ end if;
+ end if;
end if;
end process incr_address;
- O_processingDone <= '1' when _BLANK_ ;
+ O_processingDone <= '1' when SR_readAddress=15 else '0' ;
- SC_multOperand1 <= _BLANK_ ; -- 8 bits
- SC_multOperand2 <= _BLANK_ ; -- 8 bits
- SC_MultResult <= _BLANK_ ; -- 16 bits
+ SC_multOperand1 <= SR_shiftRegister(SR_readAddress) ; -- 8 bits
+ SC_multOperand2 <= SR_coefRegister(SR_readAddress) ; -- 8 bits
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 16 bits
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
- sum_acc : process (_BLANK_) is
+ sum_acc : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_sum <= (others => '0');
- elsif _BLANK_
+ elsif rising_edge(I_clock) then
+ if I_initSum = '1' then
+ SR_sum <= (others => '0');
+ elsif I_loadSum = '1' then
+ SR_sum <= SC_addResult;
+ end if;
end if;
end process sum_acc;
-
- store_result : process (_BLANK_) is
+
+ store_result : process (I_reset, I_clock) is
begin
- _BLANK_
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_Y <= (others => '0');
+ elsif rising_edge(I_clock) then
+ if I_loadY = '1' then
+ -- Rounding: add 1 if bit 11 is '1'
+ if SR_sum(6) = '1' then
+ SR_Y <= to_signed( to_integer(SR_sum(14 downto 7)) + 1, 8) ;
+ else
+ SR_Y <= SR_sum(14 downto 7);
+ end if;
+ end if;
+ end if;
end process store_result;