diff --git a/docs/img/OperativeUnit.drawio b/docs/img/OperativeUnit.drawio
index 8b5275deca9629c3cb4b177e2fc7af94d0467e76..a710859803a05ee06291a9547ec84d3923e3d96f 100644
--- a/docs/img/OperativeUnit.drawio
+++ b/docs/img/OperativeUnit.drawio
@@ -1,6 +1,6 @@
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+<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:136.0) Gecko/20100101 Firefox/136.0" version="26.1.1">
<diagram name="Page-1" id="HnFJvu7xD7cCTyxCgidn">
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+ <mxGraphModel dx="2761" dy="1646" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
<root>
<mxCell id="0" />
<mxCell id="1" parent="0" />
@@ -810,7 +810,7 @@
<mxCell id="o0McHQSmAaqEuiDyRwqv-361" value="I_process" style="edgeLabel;html=1;align=right;verticalAlign=middle;resizable=0;points=[];fontFamily=Ubuntu Mono;fontSize=14;" parent="1" vertex="1" connectable="0">
<mxGeometry x="496" y="590" as="geometry" />
</mxCell>
- <mxCell id="dNHIPUE1VRKQBVQlvAgs-3" value="" style="endArrow=classic;html=1;rounded=0;entryX=0.184;entryY=1.1;entryDx=0;entryDy=0;entryPerimeter=0;strokeWidth=2;" edge="1" parent="1">
+ <mxCell id="dNHIPUE1VRKQBVQlvAgs-3" value="" style="endArrow=classic;html=1;rounded=0;entryX=0.184;entryY=1.1;entryDx=0;entryDy=0;entryPerimeter=0;strokeWidth=2;" parent="1" edge="1">
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@@ -821,15 +821,24 @@
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</mxGeometry>
</mxCell>
- <mxCell id="dNHIPUE1VRKQBVQlvAgs-4" value="I_process" style="edgeLabel;html=1;align=right;verticalAlign=middle;resizable=0;points=[];fontFamily=Ubuntu Mono;fontSize=14;" vertex="1" connectable="0" parent="1">
+ <mxCell id="dNHIPUE1VRKQBVQlvAgs-4" value="I_process" style="edgeLabel;html=1;align=right;verticalAlign=middle;resizable=0;points=[];fontFamily=Ubuntu Mono;fontSize=14;" parent="1" vertex="1" connectable="0">
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+ </mxCell>
+ <mxCell id="8PHknglAfl4I-ohuEPsr-2" value="<div>I_InputSample</div>" style="text;html=1;align=center;verticalAlign=middle;whiteSpace=wrap;rounded=0;" vertex="1" parent="1">
+ <mxGeometry x="240" y="110" width="60" height="30" as="geometry" />
+ </mxCell>
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diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 68cb949054d6f1d00fe352baeb8864af9bb79d98..4e9efb5e0ec151bc48c93bca6dfe8a3485d53c16 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -4,7 +4,7 @@
-------------------------------------------------------------------------------
-- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr
->
+
-- Company :
-- Created : 2018-04-11
-- Last update: 2019-02-13
@@ -28,7 +28,10 @@ entity controlUnit is
I_reset : in std_logic; -- asynchronous global reset
I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_processingDone : in std_logic;
+ O_Process : out std_logic_vector(1 downto 0);
O_loadShift : out std_logic; -- filtered sample
+ O_loadShiftHighPass : out std_logic;
+ O_loadShiftDerivative : out std_logic;
O_initAddress : out std_logic; -- Control signal to initialize register read address
O_incrAddress : out std_logic; -- Control signal to increment register read address
O_initSum : out std_logic; -- Control signal to initialize the MAC register
@@ -39,7 +42,7 @@ entity controlUnit is
end entity controlUnit;
architecture archi_operativeUnit of controlUnit is
- type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE); -- state list
+ type T_state is (WAIT_SAMPLE, STORE1,STORE2,STORE3, PROCESSING_LOOP1, PROCESSING_LOOP2, PROCESSING_LOOP3, OUTPUT, WAIT_END_SAMPLE); -- state list
signal SR_presentState : T_state;
signal SR_futurState : T_state;
begin
@@ -56,21 +59,41 @@ begin
case SR_presentState is
when WAIT_SAMPLE =>
if (I_inputSampleValid ='1') then
- SR_futurState <= STORE;
+ SR_futurState <= STORE1;
else
SR_futurState <= WAIT_SAMPLE;
end if;
- when STORE =>
- SR_futurState <= PROCESSING_LOOP;
+ when STORE1 =>
+ SR_futurState <= PROCESSING_LOOP1;
- when PROCESSING_LOOP =>
+ when PROCESSING_LOOP1 =>
if (I_processingDone ='1') then
- SR_futurState <= OUTPUT;
+ SR_futurState <= STORE2;
+ else
+ SR_futurState <= PROCESSING_LOOP1;
+ end if;
+
+ when STORE2 =>
+ SR_futurState <= PROCESSING_LOOP2;
+
+ when PROCESSING_LOOP2 =>
+ if (I_processingDone ='1') then
+ SR_futurState <= STORE3;
else
- SR_futurState <= PROCESSING_LOOP;
+ SR_futurState <= PROCESSING_LOOP2;
end if;
+ when STORE3 =>
+ SR_futurState <= PROCESSING_LOOP3;
+
+ when PROCESSING_LOOP3 =>
+ if (I_processingDone ='1') then
+ SR_futurState <= OUTPUT;
+ else
+ SR_futurState <= PROCESSING_LOOP3;
+ end if;
+
when OUTPUT =>
SR_futurState <= WAIT_END_SAMPLE;
@@ -87,11 +110,87 @@ begin
when others => null;
end case;
end process;
- O_loadShift <= '1' when SR_presentState=STORE else '0';
- O_initAddress <= '1' when SR_presentState=STORE else '0';
- O_incrAddress <= '1' when SR_presentState=PROCESSING_LOOP else '0';
- O_initSum <= '1' when SR_presentState=STORE else '0';
- O_loadSum <= '1' when SR_presentState=PROCESSING_LOOP else '0' ;
- O_loadY <= '1' when SR_presentState=OUTPUT else '0';
+
+
+ process(SR_presentState, I_reset, I_inputSampleValid, I_processingDone)
+ begin
+
+ -- default output values
+
+ O_loadShift <= '0';
+ O_loadShiftHighPass <= '0';
+ O_loadShiftDerivative <= '0';
+ O_initAddress <= '0';
+ O_Process <= "00";
+ O_incrAddress <= '0';
+ O_initSum <= '0';
+ O_loadSum <= '0';
+ O_loadY <= '0';
+
+ case SR_presentState is
+-- OUTPUT, GLOBAL_OUTPUT, WAIT_END_SAMPLE
+
+ when STORE1 =>
+ O_loadShift <= '1';
+ O_initAddress <= '1';
+ O_initSum <= '1';
+ O_initSum <='0';
+
+ when PROCESSING_LOOP1 =>
+ O_incrAddress <= '1';
+ O_loadSum <= '1';
+
+
+ when STORE2 =>
+ O_loadShiftHighPass <= '1';
+ O_initAddress <= '1';
+ O_initSum <= '1';
+ O_loadSum <= '0';
+ O_incrAddress <= '0';
+ O_Process <= "01";
+
+ when PROCESSING_LOOP2 =>
+ O_loadShiftHighPass <='0';
+ O_initAddress <='0';
+ O_incrAddress <= '1';
+ O_initSum <='0';
+ O_loadSum <= '1';
+
+
+ when STORE3 =>
+ O_loadShiftDerivative <= '1';
+ O_initAddress <= '1';
+ O_initSum <= '1';
+ O_loadSum <= '0';
+ O_incrAddress <= '0';
+ O_Process <= "10";
+
+
+ when PROCESSING_LOOP3 =>
+ O_loadShiftDerivative <='0';
+ O_initAddress <='0';
+ O_incrAddress <= '1';
+ O_initSum <='0';
+ O_loadSum <= '1';
+
+
+ when OUTPUT =>
+ O_loadSum <= '0';
+ O_incrAddress <= '0';
+ O_loadY <='1';
+
+ when WAIT_END_SAMPLE =>
+ O_loadShift <= '0';
+ O_loadShiftHighPass <= '0';
+ O_loadShiftDerivative <= '0';
+ O_initAddress <= '0';
+ O_Process <= "00";
+ O_incrAddress <= '0';
+ O_initSum <= '0';
+ O_loadSum <= '0';
+ O_loadY <= '0';
+
+ end case;
+ end process;
end architecture archi_operativeUnit;
\ No newline at end of file
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 7bca8fc46b5822cb6f1b63435b2d5d0cd5aaf004..a607130baccc9272bba7fbfb8c454f3f6f8ac9a4 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -4,7 +4,6 @@
-------------------------------------------------------------------------------
-- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr
->
-- Company :
-- Created : 2018-04-11
-- Last update: 2019-02-13
@@ -34,6 +33,9 @@ entity operativeUnit is
I_reset : in std_logic; -- asynchronous global reset
I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShiftHighPass : in std_logic;
+ I_loadShiftDerivative : in std_logic;
+ I_Process : in std_logic_vector(1 downto 0);
I_initAddress : in std_logic; -- Control signal to initialize register read address
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
@@ -44,22 +46,30 @@ entity operativeUnit is
);
end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
- type registerFile is array(0 to 15) of signed(7 downto 0);
- signal SR_coefRegister : registerFile;
+ type registerFile1 is array(0 to 15) of signed(10 downto 0);
+ type registerFile2 is array(0 to 4) of signed(10 downto 0);
+ type registerFile3 is array(0 to 29) of signed(10 downto 0);
+
+ signal SR_coefRegisterHighPass: registerFile1;
+ signal SR_coefRegisterDerivative: registerFile2;
- signal SR_shiftRegister : registerFile; -- shift register file used to store and shift input samples
- signal SC_multOperand1 : signed(7 downto 0);
- signal SC_multOperand2 : signed(7 downto 0);
- signal SC_MultResult : signed(15 downto 0); -- Result of the multiplication Xi*Hi
- signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition
- signal SR_sum : signed(19 downto 0); -- Accumulation register
- signal SR_Y : signed(7 downto 0); -- filtered sample storage register
- signal SR_readAddress : integer range 0 to 15; -- register files read address
+ signal SR_shiftRegisterInitial : registerFile1; -- shift register file used to store and shift input samples
+ signal SR_shiftRegisterFiltered : registerFile2;
+ signal SR_shiftRegisterDerivated : registerFile3;
+ signal SC_multOperand1 : signed(10 downto 0);
+ signal SC_multOperand2 : signed(10 downto 0);
+ signal SC_MultResult : signed(21 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(26 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(26 downto 0); -- Accumulation register
+ signal SR_Y : signed(10 downto 0); -- filtered sample storage register
+ signal SR_sample : signed(26 downto 0); -- sample filtered
+ signal SR_readAddress : integer range 0 to 29; -- register files read address
begin
-- Low-pass filter provided with octave (or Matlab ;)) command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
- SR_coefRegister <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
+
+ SR_coefRegisterHighPass <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
to_signed(3, 8),
to_signed(6, 8),
to_signed(10, 8),
@@ -76,14 +86,34 @@ begin
to_signed(3, 8),
to_signed(2, 8)
);
+
+ SR_coefRegisterDerivative <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
+ to_signed(3, 8),
+ to_signed(6, 8),
+ to_signed(10, 8),
+ to_signed(15, 8),
+ to_signed(20, 8)
+ );
+
shift : process (I_reset, I_clock) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
- SR_shiftRegister <= (others => (others => '0'));
+ SR_shiftRegisterInitial <= (others => (others => '0'));
+ SR_shiftRegisterFiltered <= (others => (others => '0'));
+ SR_shiftRegisterDerivated <= (others => (others => '0'));
elsif (rising_edge(I_clock)) then
if (I_loadShift = '1') then
- SR_shiftRegister(1 to 15) <= SR_shiftRegister(0 to 14);
- SR_shiftRegister(0) <= signed(I_inputSample);
+ SR_shiftRegisterInitial(1 to 15) <= SR_shiftRegisterInitial(0 to 14);
+ SR_shiftRegisterInitial(0) <= signed(I_inputSample);
+ end if;
+ if (I_loadShiftHighPass = '1') then
+ SR_shiftRegisterFiltered(1 to 4) <= SR_shiftRegisterFiltered(0 to 3);
+ SR_shiftRegisterFiltered(0) <= signed(SR_sample);
+ end if;
+
+ if (I_loadShiftDerivative = '1') then
+ SR_shiftRegisterDerivated(1 to 29) <= SR_shiftRegisterDerivated(0 to 28);
+ SR_shiftRegisterDerivated(0) <= signed(SR_sample);
end if;
end if;
end process shift;
@@ -98,19 +128,51 @@ begin
end if;
if (I_incrAddress = '1') then
- if (SR_readAddress < 15) then
- -- SR_readAddress <= SR_readAddress;
- -- else
- SR_readAddress <= SR_readAddress + 1;
+ if (I_process="00") then
+ if (SR_readAddress < 15) then
+ -- SR_readAddress <= SR_readAddress;
+ -- else
+ SR_readAddress <= SR_readAddress + 1;
+ end if;
+ end if;
+
+ if (I_process="01") then
+ if (SR_readAddress < 4) then
+ -- SR_readAddress <= SR_readAddress;
+ -- else
+ SR_readAddress <= SR_readAddress + 1;
+ end if;
+ end if;
+
+ if (I_process="10") then
+ if (SR_readAddress < 29) then
+ -- SR_readAddress <= SR_readAddress;
+ -- else
+ SR_readAddress <= SR_readAddress + 1;
+ end if;
end if;
+
end if;
end if;
end process incr_address;
- O_processingDone <= '1' when SR_readAddress >= 15 else '0';
- SC_multOperand1 <= SR_shiftRegister(SR_readAddress) ; -- 8 bits
- SC_multOperand2 <= SR_coefRegister(SR_readAddress) ; -- 8 bits
- SC_MultResult <= SC_multOperand1*SC_multOperand2; -- 16 bits
+
+
+ O_processingDone <= '1' when(SR_readAddress >= 15 and (I_process="00")) or(SR_readAddress >= 4 and (I_process="01")) or(SR_readAddress >= 29 and (I_process="10")) else '0';
+
+
+ SC_multOperand1 <= SR_shiftRegisterInitial(SR_readAddress) when (I_process="00") else
+ SR_shiftRegisterFiltered(SR_readAddress) when (I_process="01") else
+ SR_shiftRegisterDerivated(SR_readAddress);
+ -- 11 bits
+ SC_multOperand2 <= SR_coefRegisterHighPass(SR_readAddress) when (I_process="00") else -- 11 bits
+ SR_coefRegisterDerivative(SR_readAddress) when (I_process="01") else
+ SR_shiftRegisterDerivated(SR_readAddress);
+
+ SC_MultResult <= SC_multOperand1*SC_multOperand2; -- 22 bits
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+
+
+
sum_acc : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
@@ -123,9 +185,13 @@ begin
end if;
end if;
end process sum_acc;
+
store_result : process (I_clock) is
begin
if (rising_edge(I_clock)) then
+ -- utiliser addresult et reisze au moment du shift, partie fractionnaire à prendre en compte aevc les coefficietns, utiliser add_result et non sr_sum
+
+ end if;
if (I_loadY='1') then
if(SR_sum(6)='1') then
SR_Y <= SR_sum(14 downto 7) + 1;