diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 30ffa402b4a5440dfd639740383f7229b380b3c1..80bd4759a30be9fb12e53cc0d22153f396dc74a0 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -6,7 +6,7 @@ output: pdf_document
mainfont: sans-serif
---
-# Compte rendu du TP Carrefour
+# Compte rendu du tp ecg
## Diagramme de la FSM
@@ -18,4 +18,10 @@ mainfont: sans-serif
## Remarques
-(Notez toute information qui vous semble pertinente)
+Les coefficientgs des filtres ont été calculé avec Matlab, ils ont été codés en 11 bits signés avec 2 bits de partie fractionnaires.
+
+Pour économiser un registre, le coefficient 1/30 du moyennage a été introduit dans les coefficients du filtre dérivitatif.
+
+Nous avons simulé notre filtre. Le compteur d'adresse a été débugé rt les états se déroulent comme souhaité. Nous n'avons pas eu le temps de comparer avec le code de référence.
+Nous ne sommes pas certains que les coefficients des filtres entre VHDL et octave soient identiques, cela aurait rendu difficile cette comparaison.
+
diff --git a/docs/img/FSM.png b/docs/img/FSM.png
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..ae867a8911c697cb692d217b2f2a1a2c474cee79 100644
Binary files a/docs/img/FSM.png and b/docs/img/FSM.png differ
diff --git a/docs/img/OperativeUnit.png b/docs/img/OperativeUnit.png
index 64a947ab89b5c179f8cda30834baa893918774d1..16e9ad468450619ef659046ad4a93b95c0220c6e 100644
Binary files a/docs/img/OperativeUnit.png and b/docs/img/OperativeUnit.png differ
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 4e9efb5e0ec151bc48c93bca6dfe8a3485d53c16..2b896c5ea17edf8180dce58c90d0542e368b5552 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -105,9 +105,8 @@ begin
SR_futurState <= WAIT_END_SAMPLE;
end if;
-
-
- when others => null;
+ when others =>
+ SR_futurState <= WAIT_SAMPLE ;
end case;
end process;
@@ -117,15 +116,15 @@ begin
-- default output values
- O_loadShift <= '0';
- O_loadShiftHighPass <= '0';
- O_loadShiftDerivative <= '0';
- O_initAddress <= '0';
- O_Process <= "00";
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '0';
+-- O_loadShift <= '0';
+-- O_loadShiftHighPass <= '0';
+-- O_loadShiftDerivative <= '0';
+-- O_initAddress <= '0';
+-- O_Process <= "00";
+-- O_incrAddress <= '0';
+-- O_initSum <= '0';
+-- O_loadSum <= '0';
+-- O_loadY <= '0';
case SR_presentState is
-- OUTPUT, GLOBAL_OUTPUT, WAIT_END_SAMPLE
@@ -156,6 +155,7 @@ begin
O_incrAddress <= '1';
O_initSum <='0';
O_loadSum <= '1';
+--
when STORE3 =>
@@ -174,6 +174,7 @@ begin
O_initSum <='0';
O_loadSum <= '1';
+
when OUTPUT =>
O_loadSum <= '0';
@@ -191,6 +192,16 @@ begin
O_loadSum <= '0';
O_loadY <= '0';
+ when others =>
+ O_loadShift <= '0';
+ O_loadShiftHighPass <= '0';
+ O_loadShiftDerivative <= '0';
+ O_initAddress <= '0';
+ O_Process <= "00";
+ O_incrAddress <= '0';
+ O_initSum <= '0';
+ O_loadSum <= '0';
+ O_loadY <= '0';
end case;
end process;
end architecture archi_operativeUnit;
\ No newline at end of file
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 2c317f0ec840bcf248f38de4cb7f766b7afb95df..9ab9405b72a199fd65ed7ae0807cff4a25c8fc51 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -28,9 +28,9 @@ entity firUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
+ O_filteredSample : out std_logic_vector(10 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic
);
@@ -40,36 +40,47 @@ architecture archi_firUnit of firUnit is
component controlUnit is
port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSampleValid : in std_logic;
- I_processingDone : in std_logic;
- O_loadShift : out std_logic;
- O_initAddress : out std_logic;
- O_incrAddress : out std_logic;
- O_initSum : out std_logic;
- O_loadSum : out std_logic;
- O_loadY : out std_logic;
- O_FilteredSampleValid : out std_logic);
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_processingDone : in std_logic;
+ O_Process : out std_logic_vector(1 downto 0);
+ O_loadShift : out std_logic; -- filtered sample
+ O_loadShiftHighPass : out std_logic;
+ O_loadShiftDerivative : out std_logic;
+ O_initAddress : out std_logic; -- Control signal to initialize register read address
+ O_incrAddress : out std_logic; -- Control signal to increment register read address
+ O_initSum : out std_logic; -- Control signal to initialize the MAC register
+ O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadY : out std_logic; -- Control signal to load Y register
+ O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
+ );
end component controlUnit;
component operativeUnit is
port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
- I_loadShift : in std_logic;
- I_initAddress : in std_logic;
- I_incrAddress : in std_logic;
- I_initSum : in std_logic;
- I_loadSum : in std_logic;
- I_loadY : in std_logic;
- O_processingDone : out std_logic;
- O_Y : out std_logic_vector(7 downto 0));
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShiftHighPass : in std_logic;
+ I_loadShiftDerivative : in std_logic;
+ I_Process : in std_logic_vector(1 downto 0);
+ I_initAddress : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress : in std_logic; -- Control signal to increment register read address
+ I_initSum : in std_logic; -- Control signal to initialize the MAC register
+ I_loadSum : in std_logic; -- Control signal to load the MAC register;
+ I_loadY : in std_logic; -- Control signal to load Y register
+ O_processingDone : out std_logic; -- Indicate that processing is done
+ O_Y : out std_logic_vector(7 downto 0) -- filtered sample
+ );
end component operativeUnit;
signal SC_processingDone : std_logic;
signal SC_loadShift : std_logic;
+ signal SC_loadShiftHighPass :std_logic;
+ signal SC_loadShiftDerivative : std_logic;
+ signal SC_Process : std_logic_vector(1 downto 0);
signal SC_initAddress : std_logic;
signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic;
@@ -85,6 +96,9 @@ begin
I_inputSampleValid => I_inputSampleValid,
I_processingDone => SC_processingDone,
O_loadShift => SC_loadShift,
+ O_Process => SC_Process,
+ O_loadShiftHighPass => SC_loadShiftHighPass,
+ O_loadShiftDerivative => SC_loadShiftDerivative,
O_initAddress => SC_initAddress,
O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum,
@@ -98,6 +112,9 @@ begin
I_reset => I_reset,
I_inputSample => I_inputSample,
I_loadShift => SC_loadShift,
+ I_loadShiftHighPass => SC_loadShiftHighPass,
+ I_loadShiftDerivative => SC_loadShiftDerivative,
+ I_Process => SC_Process,
I_initAddress => SC_initAddress,
I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum,
@@ -105,5 +122,8 @@ begin
I_loadY => SC_loadY,
O_processingDone => SC_processingDone,
O_Y => O_filteredSample);
+
+
+
end architecture archi_firUnit;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index a607130baccc9272bba7fbfb8c454f3f6f8ac9a4..bbe2321894bace4d5e09030d26536320a9a27dba 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -31,7 +31,7 @@ entity operativeUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_loadShiftHighPass : in std_logic;
I_loadShiftDerivative : in std_logic;
@@ -42,7 +42,7 @@ entity operativeUnit is
I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadY : in std_logic; -- Control signal to load Y register
O_processingDone : out std_logic; -- Indicate that processing is done
- O_Y : out std_logic_vector(7 downto 0) -- filtered sample
+ O_Y : out std_logic_vector(10 downto 0) -- filtered sample
);
end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
@@ -62,37 +62,36 @@ architecture arch_operativeUnit of operativeUnit is
signal SC_addResult : signed(26 downto 0); -- result of the accumulation addition
signal SR_sum : signed(26 downto 0); -- Accumulation register
signal SR_Y : signed(10 downto 0); -- filtered sample storage register
- signal SR_sample : signed(26 downto 0); -- sample filtered
signal SR_readAddress : integer range 0 to 29; -- register files read address
-
+ signal SR_readAddress_1 : integer range 0 to 15;
+ signal SR_readAddress_2 : integer range 0 to 4;
begin
-- Low-pass filter provided with octave (or Matlab ;)) command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
- SR_coefRegisterHighPass <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
- to_signed(3, 8),
- to_signed(6, 8),
- to_signed(10, 8),
- to_signed(15, 8),
- to_signed(20, 8),
- to_signed(24, 8),
- to_signed(26, 8),
- to_signed(26, 8),
- to_signed(24, 8),
- to_signed(20, 8),
- to_signed(15, 8),
- to_signed(10, 8),
- to_signed(6, 8),
- to_signed(3, 8),
- to_signed(2, 8)
+ SR_coefRegisterHighPass <= (to_signed(12, 11), -- ROM register used file to store FIR coefficients
+ to_signed(20, 11),
+ to_signed(42,11),
+ to_signed(76,11),
+ to_signed(118, 11),
+ to_signed(160, 11),
+ to_signed(194, 11),
+ to_signed(214, 11),
+ to_signed(214, 11),
+ to_signed(194, 11),
+ to_signed(160, 11),
+ to_signed(118, 11),
+ to_signed(76, 11),
+ to_signed(42, 11),
+ to_signed(20, 11),
+ to_signed(12, 11)
);
- SR_coefRegisterDerivative <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients
- to_signed(3, 8),
- to_signed(6, 8),
- to_signed(10, 8),
- to_signed(15, 8),
- to_signed(20, 8)
+ SR_coefRegisterDerivative <= (to_signed(256, 11), -- ROM register used file to store FIR coefficients
+ to_signed(511, 11),
+ to_signed(0, 11),
+ to_signed(-512, 11),
+ to_signed(-256, 11)
);
shift : process (I_reset, I_clock) is
@@ -108,12 +107,20 @@ begin
end if;
if (I_loadShiftHighPass = '1') then
SR_shiftRegisterFiltered(1 to 4) <= SR_shiftRegisterFiltered(0 to 3);
- SR_shiftRegisterFiltered(0) <= signed(SR_sample);
+ if(SC_addResult(1)='1') then
+ SR_shiftRegisterFiltered(0) <= signed(SC_addResult(12 downto 2)) + 1;
+ else
+ SR_shiftRegisterFiltered(0) <= signed(SC_addResult(12 downto 2));
+ end if;
end if;
if (I_loadShiftDerivative = '1') then
SR_shiftRegisterDerivated(1 to 29) <= SR_shiftRegisterDerivated(0 to 28);
- SR_shiftRegisterDerivated(0) <= signed(SR_sample);
+ if(SC_addResult(1)='1') then
+ SR_shiftRegisterFiltered(0) <= signed(SC_addResult(12 downto 2)) + 1;
+ else
+ SR_shiftRegisterFiltered(0) <= signed(SC_addResult(12 downto 2));
+ end if;
end if;
end if;
end process shift;
@@ -130,25 +137,25 @@ begin
if (I_incrAddress = '1') then
if (I_process="00") then
if (SR_readAddress < 15) then
- -- SR_readAddress <= SR_readAddress;
- -- else
- SR_readAddress <= SR_readAddress + 1;
+ SR_readAddress <= SR_readAddress +1;
+ else
+ SR_readAddress <= 0;
end if;
end if;
if (I_process="01") then
if (SR_readAddress < 4) then
- -- SR_readAddress <= SR_readAddress;
- -- else
- SR_readAddress <= SR_readAddress + 1;
+ SR_readAddress <= SR_readAddress +1;
+ else
+ SR_readAddress <= 0;
end if;
end if;
if (I_process="10") then
if (SR_readAddress < 29) then
- -- SR_readAddress <= SR_readAddress;
- -- else
- SR_readAddress <= SR_readAddress + 1;
+ SR_readAddress <= SR_readAddress +1;
+ else
+ SR_readAddress <= 0;
end if;
end if;
@@ -159,13 +166,15 @@ begin
O_processingDone <= '1' when(SR_readAddress >= 15 and (I_process="00")) or(SR_readAddress >= 4 and (I_process="01")) or(SR_readAddress >= 29 and (I_process="10")) else '0';
+ SR_readAddress_1 <= SR_readAddress when (I_process = "00") else 0;
+ SR_readAddress_2 <= SR_readAddress when (I_process = "01") else 0;
- SC_multOperand1 <= SR_shiftRegisterInitial(SR_readAddress) when (I_process="00") else
- SR_shiftRegisterFiltered(SR_readAddress) when (I_process="01") else
+ SC_multOperand1 <= SR_shiftRegisterInitial(SR_readAddress_1) when (I_process="00") else
+ SR_shiftRegisterFiltered(SR_readAddress_2) when (I_process="01") else
SR_shiftRegisterDerivated(SR_readAddress);
-- 11 bits
- SC_multOperand2 <= SR_coefRegisterHighPass(SR_readAddress) when (I_process="00") else -- 11 bits
- SR_coefRegisterDerivative(SR_readAddress) when (I_process="01") else
+ SC_multOperand2 <= SR_coefRegisterHighPass(SR_readAddress_1) when (I_process="00") else -- 11 bits
+ SR_coefRegisterDerivative(SR_readAddress_2) when (I_process="01") else
SR_shiftRegisterDerivated(SR_readAddress);
SC_MultResult <= SC_multOperand1*SC_multOperand2; -- 22 bits
@@ -189,14 +198,11 @@ begin
store_result : process (I_clock) is
begin
if (rising_edge(I_clock)) then
- -- utiliser addresult et reisze au moment du shift, partie fractionnaire à prendre en compte aevc les coefficietns, utiliser add_result et non sr_sum
-
- end if;
if (I_loadY='1') then
- if(SR_sum(6)='1') then
- SR_Y <= SR_sum(14 downto 7) + 1;
+ if(SR_sum(1)='1') then
+ SR_Y <= SR_sum(12 downto 2) + 1;
else
- SR_Y <= SR_sum(14 downto 7);
+ SR_Y <= SR_sum(12 downto 2);
end if;
end if;
end if;
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index e19d713585d5121f39e78cd67ed5edb8a48f4ed0..879ea70b1f0f81f4fd808ae6a0b8ecdabdef02a7 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -33,17 +33,17 @@ architecture archi_tb_firUnit of tb_firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSample : in std_logic_vector(10 downto 0);
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0);
+ O_filteredSample : out std_logic_vector(10 downto 0);
O_filteredSampleValid : out std_logic);
end component firUnit;
signal SC_clock : std_logic := '0';
signal SC_reset : std_logic;
- signal SC_inputSample : std_logic_vector(7 downto 0);
+ signal SC_inputSample : std_logic_vector(10 downto 0);
signal SC_inputSampleValid : std_logic:='0';
- signal SC_filteredSample : std_logic_vector(7 downto 0);
+ signal SC_filteredSample : std_logic_vector(10 downto 0);
signal SC_filteredSampleValid : std_logic;
begin
@@ -55,17 +55,17 @@ begin
SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
-- Null signal followed by a Dirac and then an arbitrary sequence
- SC_inputSample <= "00000000",
- "01111111" after 401 ns,
- "00000000" after 601 ns,
- "00100100" after 4201 ns,
- "01100100" after 4401 ns,
- "10100010" after 4601 ns,
- "11011011" after 4801 ns,
- "00001011" after 5001 ns,
- "10000000" after 5201 ns,
- "01111111" after 5401 ns,
- "10111010" after 5601 ns;
+ SC_inputSample <= "11111111010",
+ "11111111000" after 401 ns,
+ "11111110100" after 601 ns;
+ "11111110100" after 4201 ns,
+ "11111110010" after 4401 ns,
+ "11111110110" after 4601 ns,
+-- "11011011" after 4801 ns,
+-- "00001011" after 5001 ns,
+-- "10000000" after 5201 ns,
+-- "01111111" after 5401 ns,
+-- "10111010" after 5601 ns;
-- the filter output on 8 bits is a sequence of signed numbers (with the assumption