diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
index 4e6ebcf8c6fc253a5b143e7519395aa5fae879b0..24316b6b8b0a68181175a75771cf5d65e230ea28 100644
--- a/proj/AudioProc.cache/wt/project.wpc
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:10
+6d6f64655f636f756e7465727c4755494d6f6465:11
eof:
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
index 50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af..51d5206f7011f2f0764fb661278617e58456141a 100644
--- a/proj/AudioProc.cache/wt/xsim.wdf
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -1,4 +1,4 @@
version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:241934075
+eof:2427094519
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat b/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat
index 882944f8a84e3797afeecc4f0a7e65ed42eafd3c..ec142925812a60743d3c1fe759a1d70b968dfd56 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat
@@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : AMD Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
-REM Generated by Vivado on Tue Mar 18 22:56:13 +0100 2025
+REM Generated by Vivado on Wed Mar 26 08:48:39 +0100 2025
REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
deleted file mode 100644
index e9b0a658a9ad9ffd7ded52bc3bfb9964f8ee4ebd..0000000000000000000000000000000000000000
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
+++ /dev/null
@@ -1,8 +0,0 @@
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'firUnit'
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat
index 6a296dfee0f4e29aa2a589520c56c3d67cbe1e32..e4cd71b96051448b88df1e607146baf44a8425cf 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat
@@ -6,7 +6,7 @@ REM Filename : elaborate.bat
REM Simulator : AMD Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
-REM Generated by Vivado on Tue Mar 18 22:56:15 +0100 2025
+REM Generated by Vivado on Wed Mar 26 08:48:40 +0100 2025
REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat
index 75921806cf5780698cb4b6c5acee956140ceded9..d26deb800b2a45e92bcc22f3a3426e88283a75cc 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat
@@ -6,7 +6,7 @@ REM Filename : simulate.bat
REM Simulator : AMD Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
-REM Generated by Vivado on Tue Mar 18 22:56:16 +0100 2025
+REM Generated by Vivado on Wed Mar 26 08:21:34 +0100 2025
REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index 17915c2f009563f3866d10cae821faa97bc4fc3f..1af9289b9f243781fe34d4c65a2e4e7d2bdda81a 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb and b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj
index 51cfd6dc986e82e69f3c0153fd167cb9cad472b3..723662f25d2ccb74f010e09a6721e3bde3683993 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
index 977edfdc3b090cc560d422298ee6523588da95bd..ca75b06cc02438e064f6e57ab34d52a6743447ab 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
index aadc0cde6f6320e416ef4b953df9c100fb9701e2..d1c96de42f037a927078846ba02a36939e409847 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
index baf8869697e8ab2616e6693dc647e35b3a0a8127..8d6de19b68c2c74bd91917b8e5f4f65af21c45e5 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -1,6 +1,6 @@
{
- crc : 7733031991265798486 ,
+ crc : 724585655620237082 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
buildDate : "Nov 8 2024" ,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
index b2ea0ee92f5a93add8fa8cf58e9ae5e1604e3b25..e6e54e6a68ad4f3efba350184f75b7dc9dc80ea8 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
index 0ce4533366d0e0810008bee6c7e196ee59f94239..2ce28257e993e6666405e451e5f8da6a497cef36 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
index 3393fc6ade93cd18ce6121bd5570d773a856e47a..35cd212f2eb2f79b2263cf84795b4bef167c4bc9 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
index 686fcde19130535a2bc8b8a559404927b1f505b0..cf9dd51f8f35851ffc876f135b3cc7c04e2de0aa 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -26,8 +26,8 @@ INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=220
-SCOPE_DESIGN_UNIT_COLUMN_WIDTH=160
-SCOPE_BLOCK_TYPE_COLUMN_WIDTH=304
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=304
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=160
OBJECT_NAME_COLUMN_WIDTH=350
OBJECT_VALUE_COLUMN_WIDTH=92
OBJECT_DATA_TYPE_COLUMN_WIDTH=140
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe
index 2320308396f9a5dc2e0354164bd94a40633a5047..17d97b96c983ca633fdb8eb1f3260a6d151edb34 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
index 2c09a02ac940f2c76e5918005c786890a5dc43ce..0039134e19a840e7ef3071608b369203f09aceb2 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -1,4 +1,4 @@
-Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51894
+Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 58402
Design successfully loaded
-Design Loading Memory Usage: 28580 KB (Peak: 28580 KB)
-Design Loading CPU Usage: 468 ms
+Design Loading Memory Usage: 28572 KB (Peak: 28572 KB)
+Design Loading CPU Usage: 452 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
index 138ffec8953ffa512b6bced01e5bcf795a5ca2b2..23c23a0c4a6f5e63b0cafebf56f8f1c864527649 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
index 8a2a74eb0d641f71e7ce3f4bc3cf98d2fa275027..4400b165f35fec02650d84b80cfa6ef6d3349dfc 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
index 09dd06999bcae67a80939e5fa5b29f99e837e20a..50b0b2b266e1adf34072198e8cab971f32306af8 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
index d622895935dd9c9719a4168f07ef8608bf438897..0637dd20e63ccad1b19942d223c95b5caec16c53 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index f84a889ce805062041da17655c6e447ba443d7ae..a254e12ddf4bb6757d286bcfaac3d3ab42ea2024 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -2,7 +2,7 @@
2020.2
Nov 8 2024
22:36:57
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742333722,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1741454254,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742334967,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1741730766,vhdl,,,,tb_firunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742555269,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1742333380,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742975282,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1742233686,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
index e9b0a658a9ad9ffd7ded52bc3bfb9964f8ee4ebd..99a934f04b95990a677be7928ba4fde42f5969d9 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -1,5 +1,3 @@
-INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib
-INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
index 6da5d2db73ad6dd87651bc3b4576dfb18c38f281..a1c21cd58a8c1cae026ca4df26d884d49de51759 100644
Binary files a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb and b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
index c8c23beae3777a53e48e5fc42d32a0044ae14826..6cdcab91715929a24d9bd7d01e8b9c052efa7dc3 100644
--- a/proj/AudioProc.xpr
+++ b/proj/AudioProc.xpr
@@ -60,7 +60,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="145"/>
+ <Option Name="WTXSimLaunchSim" Val="166"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 2f437d2a2cf95f054f9f1625902e981f04784698..767e423ac558a60f0b0960f16968b779e6ac0a28 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -50,7 +50,7 @@ ARCHITECTURE arch_operativeUnit OF operativeUnit IS
SIGNAL SR_sum : signed(30 DOWNTO 0);
SIGNAL SR_Y : signed(11 DOWNTO 0);
SIGNAL SR_readAddress : INTEGER RANGE 0 TO 94;
-
+
BEGIN
SR_coefRegisterA <= (to_signed(1554, 12),
to_signed(-897, 12)
@@ -203,7 +203,7 @@ BEGIN
END IF;
END IF;
- -- Process B
+ -- Process B
ELSIF I_sel = "01" THEN
IF I_initAddress = '1' THEN
SR_readAddress <= 0;
@@ -215,7 +215,7 @@ BEGIN
END IF;
END IF;
- -- Process A
+ -- Process A
ELSIF I_sel = "10" THEN
IF I_initAddress = '1' THEN
SR_readAddress <= 0;
@@ -227,7 +227,7 @@ BEGIN
END IF;
END IF;
- -- Process Clellan
+ -- Process Clellan
ELSIF I_sel = "11" THEN
IF I_initAddress = '1' THEN
SR_readAddress <= 0;
@@ -350,15 +350,13 @@ BEGIN
END IF;
ELSIF I_loadOutA = '1' THEN
+ SR_3(1 TO 10) <= SR_3(0 TO 9);
IF SC_addResult(9) = '1' THEN
- SR_3(1 TO 10) <= SR_3(0 TO 9);
- SR_3(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
- SR_2A(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ SR_3(0) <= signed(SC_addResult(21 DOWNTO 10)) + 1;
ELSE
- SR_3(1 TO 10) <= SR_3(0 TO 9);
SR_3(0) <= signed(SC_addResult(21 DOWNTO 10));
- SR_2A(0) <= signed(SC_addResult(21 DOWNTO 10));
END IF;
+
SR_2A(1) <= SR_2A(0);
ELSIF I_loadOutClellan = '1' THEN
IF SC_addResult(9) = '1' THEN