From 700a7fdec0d544baab30f5f8964f68432d55c17d Mon Sep 17 00:00:00 2001
From: Antonio PEREIRA <a24perei@fl-tp-br-637.imta.fr>
Date: Wed, 12 Mar 2025 09:28:32 +0100
Subject: [PATCH] minorchanges
---
proj/project_1/project_1.cache/wt/project.wpc | 3 +
proj/project_1/project_1.cache/wt/xsim.wdf | 4 +
proj/project_1/project_1.hw/project_1.lpr | 7 +
.../project_1.ip_user_files/README.txt | 1 +
.../ip/clk_wiz_0/clk_wiz_0.vho | 103 ++++
.../sim_1/behav/xsim/audioProc.tcl | 11 +
.../sim_1/behav/xsim/audioProc_behav.wdb | Bin 0 -> 72725 bytes
.../sim_1/behav/xsim/compile.bat | 27 +
.../project_1.sim/sim_1/behav/xsim/compile.sh | 24 +
.../sim_1/behav/xsim/elaborate.bat | 26 +
.../sim_1/behav/xsim/elaborate.log | 8 +
.../sim_1/behav/xsim/elaborate.sh | 22 +
.../project_1.sim/sim_1/behav/xsim/glbl.v | 84 +++
.../sim_1/behav/xsim/simulate.bat | 26 +
.../sim_1/behav/xsim/simulate.log | 0
.../sim_1/behav/xsim/simulate.sh | 22 +
.../sim_1/behav/xsim/tb_firUnit.tcl | 11 +
.../sim_1/behav/xsim/tb_firUnit_behav.wdb | Bin 0 -> 61927 bytes
.../sim_1/behav/xsim/tb_firUnit_vhdl.prj | 9 +
.../project_1.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 847 bytes
.../project_1.sim/sim_1/behav/xsim/xsim.ini | 489 ++++++++++++++++++
.../sim_1/behav/xsim/xsim.ini.bak | 489 ++++++++++++++++++
.../project_1.sim/sim_1/behav/xsim/xvhdl.log | 0
.../project_1.sim/sim_1/behav/xsim/xvhdl.pb | 4 +
.../project_1.sim/sim_1/behav/xsim/xvlog.log | 12 +
.../project_1.sim/sim_1/behav/xsim/xvlog.pb | Bin 0 -> 1640 bytes
proj/project_1/project_1.xpr | 301 +++++++++++
src/hdl/controlUnit.vhd | 14 +-
28 files changed, 1690 insertions(+), 7 deletions(-)
create mode 100644 proj/project_1/project_1.cache/wt/project.wpc
create mode 100644 proj/project_1/project_1.cache/wt/xsim.wdf
create mode 100644 proj/project_1/project_1.hw/project_1.lpr
create mode 100644 proj/project_1/project_1.ip_user_files/README.txt
create mode 100644 proj/project_1/project_1.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc.tcl
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc_behav.wdb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/compile.bat
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.bat
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/glbl.v
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.bat
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.log
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit.tcl
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.pb
create mode 100644 proj/project_1/project_1.xpr
diff --git a/proj/project_1/project_1.cache/wt/project.wpc b/proj/project_1/project_1.cache/wt/project.wpc
new file mode 100644
index 0000000..0161c5d
--- /dev/null
+++ b/proj/project_1/project_1.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:6
+eof:
diff --git a/proj/project_1/project_1.cache/wt/xsim.wdf b/proj/project_1/project_1.cache/wt/xsim.wdf
new file mode 100644
index 0000000..51d5206
--- /dev/null
+++ b/proj/project_1/project_1.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:2427094519
diff --git a/proj/project_1/project_1.hw/project_1.lpr b/proj/project_1/project_1.hw/project_1.lpr
new file mode 100644
index 0000000..afc0a86
--- /dev/null
+++ b/proj/project_1/project_1.hw/project_1.lpr
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0"/>
diff --git a/proj/project_1/project_1.ip_user_files/README.txt b/proj/project_1/project_1.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/proj/project_1/project_1.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/proj/project_1/project_1.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/proj/project_1/project_1.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100644
index 0000000..c6b126b
--- /dev/null
+++ b/proj/project_1/project_1.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,103 @@
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+
+ -- Clock in ports
+ clk_in1 => clk_in1,
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc.tcl b/proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc_behav.wdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/audioProc_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..8067c067c51a8d898ece5004ddbf6b64afcd5d9c
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.bat b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..90c0bc0
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,27 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename : compile.bat
+REM Simulator : AMD Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Sat Mar 08 19:39:29 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+call xvhdl --incr --relax -prj tb_firUnit_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
new file mode 100644
index 0000000..e918a0d
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Feb 26 12:08:10 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.bat b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..b4dbe4f
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename : elaborate.bat
+REM Simulator : AMD Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Sat Mar 08 19:39:30 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000..db78a7c
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,8 @@
+Vivado Simulator v2024.2.0
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2024.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100644
index 0000000..b001623
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Feb 26 12:08:12 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/glbl.v b/proj/project_1/project_1.sim/sim_1/behav/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.bat b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..d40839b
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename : simulate.bat
+REM Simulator : AMD Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Sat Mar 08 18:23:47 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+call xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000..e69de29
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
new file mode 100644
index 0000000..9cda091
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Feb 26 12:07:21 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit.tcl b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
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literal 0
HcmV?d00001
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
new file mode 100644
index 0000000..0107b4e
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -0,0 +1,9 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../src/hdl/firUnit.vhd" \
+"../../../../../src/hdl/tb_firUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..0e76091ce692a7c8ed1f8df69a920743b1957817
GIT binary patch
literal 847
zcmd<`<ziDUR!}YG5@3;HHZe5N;w;Y0EzL<R$uBYz;t~kUEK5wuR|tlSadUB&85tOv
z=o#r5M6sI~>l#~{n`bZ-uvD;2U}O+r;+n<C#SAtM*`!*oYUlid%A(Blj1mPyOA9ky
zBLgENg^0|Y%)AO61<$->Jq5>{9EBi|f?|cB)Z)~lveXnkE`%<S29Pcj1;>=K#JuFx
z6b0YR<f429m(;S%<kVt3rXV}7g^7zNs5CDxGcVl==51qRV`RskXXHA==xn7Aah*OS
z2=pPI)=$dJ(=W{{FG?&ZNKMf%&&)G3(aYDbNX<!1(o3yKRnXPV%u6m((A7;zO)5=S
zD5)&SOis*E(A6zU%}K0K(ACW?Q7}@_^--wE%!yA)O-n4zDapx90*Mr-CYKhaW)^_h
z6$QBpy1K=Ai3P<O`6UV^N%3i!MWK0_CGknA8Hr_Ry7dt93c5M@=?Wm{<QFBDr0Riq
zka#jNu|y6CCob{O;>^5s1=V7O;+({?RE3g^qSV9`NJ=m^H%AT<W-dk}s414lsHVsS
zmn0UIfD9@wNi4}shTEN)p9fA<#wJEcMnO$6wLmt-nM>9=Ker$!wInq~0f#Y07RYH6
zVvMn+8L~0?T%LaU3eFjcdFiPNnRyBxE<Sn+KACyhAlDTXrIuypmlo$#Dx|08rGf${
zMIk>aOCc>YC$(6iBwr!9C^fMpRUtdIC@(cffK`gw)Y1ao<tD~PApf&gutHKh9~YNv
PUW!6cYI1&2iU1=3aK-xB
literal 0
HcmV?d00001
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e2f5709
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,489 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+cpri_v8_12_0=$RDI_DATADIR/xsim/ip/cpri_v8_12_0
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+an_lt_v1_0_14=$RDI_DATADIR/xsim/ip/an_lt_v1_0_14
+axi_chip2chip_v5_0_24=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_24
+g709_fec_v2_4_11=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_11
+audio_formatter_v1_0_15=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_15
+ats_switch_v1_0_12=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_12
+xbip_pipe_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_10
+v_gamma_lut_v1_1_13=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_13
+vrf_fft_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_fft_v1_0_0
+v_hdmi_tx1_v1_0_10=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_10
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+axi_mm2s_mapper_v1_1_32=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_32
+axis_data_fifo_v1_1_34=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_34
+mailbox_v2_1_18=$RDI_DATADIR/xsim/ip/mailbox_v2_1_18
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+sdfec_ld_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/sdfec_ld_wrapper_v1_0_0
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+tcc_encoder_3gpplte_v4_0_20=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_20
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+vitis_net_p4_v2_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_2_0
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+v_frmbuf_rd_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v3_0_0
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+dfx_bitstream_monitor_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_6
+rs_toolbox_v9_0_14=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_14
+perf_axi_tg_v1_0_15=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_15
+xbip_utils_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_14
+dptx_v1_0_5=$RDI_DATADIR/xsim/ip/dptx_v1_0_5
+rs_decoder_v9_0_23=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_23
+dsp_macro_v1_0_7=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_7
+axi_vdma_v6_3_21=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_21
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+qdriv_pl_v1_0_14=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_14
+axis_data_fifo_v2_0_15=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_15
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_i3c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_2
+axi_sg_v4_1_19=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_19
+mipi_csi2_rx_ctrl_v1_0_11=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_11
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+xxv_ethernet_v4_1_13=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_13
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+ernic_v4_2_0=$RDI_DATADIR/xsim/ip/ernic_v4_2_0
+rama_v1_1_19_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_19_lib
+rfdace5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfdace5_wrapper_v1_0_0
+tsn_temac_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_12
+tri_mode_ethernet_mac_v9_0_35=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_35
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+ieee802d3_200g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_12
+fast_adapter_v1_0_10=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_10
+hdmi_gt_controller_v2_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v2_0_0
+xdfe_ofdm_v2_2_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_2_0
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+vfb_v1_0_27=$RDI_DATADIR/xsim/ip/vfb_v1_0_27
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+vcu2_v1_0_0=$RDI_DATADIR/xsim/ip/vcu2_v1_0_0
+shell_utils_addr_remap_v1_0_12=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_12
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+sim_trig_v1_0_13=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_13
+v_hdmi_phy1_v1_0_13=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_13
+displayport_v7_0_25=$RDI_DATADIR/xsim/ip/displayport_v7_0_25
+cordic_v6_0_23=$RDI_DATADIR/xsim/ip/cordic_v6_0_23
+axi_crossbar_v2_1_34=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_34
+proc_sys_reset_v5_0_16=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_16
+polar_v1_1_5=$RDI_DATADIR/xsim/ip/polar_v1_1_5
+xscl=$RDI_DATADIR/xsim/ip/xscl
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+ldpc_v2_0_16=$RDI_DATADIR/xsim/ip/ldpc_v2_0_16
+switch_core_top_v1_0_17=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_17
+v_frmbuf_wr_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_3
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+audio_clock_recovery_unit_v1_0_5=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_5
+xdfe_resampler_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_10
+sd_fec_v1_1_15=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_15
+fifo_generator_v13_2_11=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_11
+axi_timebase_wdt_v3_0_25=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_25
+psx_vip_v1_0_6=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_6
+axi_memory_init_v1_0_14=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_14
+emc_common_v3_0_8=$RDI_DATADIR/xsim/ip/emc_common_v3_0_8
+ieee802d3_rs_fec_v2_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_24
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+v_vcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_13
+v_csc_v1_1_13=$RDI_DATADIR/xsim/ip/v_csc_v1_1_13
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+zynq_ultra_ps_e_vip_v1_0_19=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_19
+axi_cdma_v4_1_33=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_33
+v_dp_axi4s_vid_out_v1_0_9=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_9
+i2s_receiver_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_9
+rld3_pl_v1_0_15=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_15
+axi_firewall_v1_2_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_8
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+cpm5n_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_9
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+axis_switch_v1_1_33=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_33
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+mipi_dphy_v4_3_13=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_13
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+iomodule_v3_1_11=$RDI_DATADIR/xsim/ip/iomodule_v3_1_11
+fc32_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_28
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+axi_hwicap_v3_0_37=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_37
+g709_rs_decoder_v2_2_15=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_15
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+tmr_voter_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_7
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mdm_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_3
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+amm_axi_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_19
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+axis_accelerator_adapter_v2_1_19=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_19
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+vrf_channelizer_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_channelizer_v1_0_0
+uhdsdi_gt_v2_1_5=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_5
+v_deinterlacer_v5_1_6=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_6
+noc_hbm_v1_0_1=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_1
+in_system_ibert_v1_0_23=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_23
+axi_pcie_v2_9_12=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_12
+axi_epu_v1_0_6=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_6
+floating_point_v7_0_24=$RDI_DATADIR/xsim/ip/floating_point_v7_0_24
+v_axi4s_vid_out_v4_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_19
+v_multi_scaler_v1_2_7=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_7
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+can_v5_1_5=$RDI_DATADIR/xsim/ip/can_v5_1_5
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+xdfe_cc_filter_v1_1_5=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_5
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+v_smpte_uhdsdi_tx_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_5
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+noc2_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_sim_v1_0_0
+tmr_sem_v1_0_27=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_27
+axi_ahblite_bridge_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_30
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+axi_uart16550_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_35
+ecc_v2_0_17=$RDI_DATADIR/xsim/ip/ecc_v2_0_17
+v_frmbuf_rd_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_12
+axi_data_fifo_v2_1_32=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_32
+xdfe_equalizer_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_10
+axi_mcdma_v1_2_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_2_0
+versal_cips_ps_vip_v1_0_11=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_11
+emb_mem_gen_v1_0_10=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_10
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+displayport_v8_1_10=$RDI_DATADIR/xsim/ip/displayport_v8_1_10
+tcc_encoder_3gpp_v5_0_23=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_23
+pcie_qdma_mailbox_v1_0_8=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_8
+v_frmbuf_rd_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_dwidth_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_32
+axi4svideo_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_19
+util_ff_v1_0_4=$RDI_DATADIR/xsim/ip/util_ff_v1_0_4
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+microblaze_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_3
+cpri_v8_11_22=$RDI_DATADIR/xsim/ip/cpri_v8_11_22
+v_vid_in_axi4s_v5_0_5=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_5
+dprx_v1_0_5=$RDI_DATADIR/xsim/ip/dprx_v1_0_5
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+axi_pcie3_v3_0_32=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_32
+v_smpte_uhdsdi_rx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_4
+axi_datamover_v5_1_35=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_35
+interlaken_v2_4_19=$RDI_DATADIR/xsim/ip/interlaken_v2_4_19
+nvmeha_v1_0_14=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_14
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+bfr_ft_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/bfr_ft_wrapper_v1_0_0
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+zynq_ultra_ps_e_v3_3_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_14
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+v_hdmi_rx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_5
+ethernet_1_10_25g_v2_7_18=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_18
+v_tpg_v8_2_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_6
+qdma_v5_0_12=$RDI_DATADIR/xsim/ip/qdma_v5_0_12
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+jesd204c_v4_3_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_3_0
+axi_timer_v2_0_35=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_35
+c_compare_v12_0_10=$RDI_DATADIR/xsim/ip/c_compare_v12_0_10
+axi_clock_converter_v2_1_32=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_32
+axi_protocol_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_33
+axi_dma_v7_1_34=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_34
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+dfx_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_11
+axi_sideband_util_v1_0_17=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_17
+tmr_manager_v1_0_13=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_13
+fec_5g_common_v1_1_5=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_5
+axi_ethernetlite_v3_0_32=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_32
+lib_bmg_v1_0_18=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_18
+high_speed_selectio_wiz_v3_6_10=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_10
+c_shift_ram_v12_0_18=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_18
+axi_pmon_v1_0_2=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_2
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+uhdsdi_gt_v2_2_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_2_0
+v_tpg_v8_1_12=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_12
+noc2_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_sim_v1_0_0
+axi_gpio_v2_0_35=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_35
+axis_interconnect_v1_1_24=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_24
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+c_addsub_v12_0_19=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_19
+sem_ultra_v3_1_27=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_27
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+v_warp_init_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+roe_framer_v3_0_9=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_9
+axi_remapper_tx_v1_0_3=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_3
+axi_traffic_gen_v3_0_19=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_19
+dfx_controller_v1_0_8=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_8
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+tmr_comparator_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_8
+rfadce5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfadce5_wrapper_v1_0_0
+axi_mmu_v2_1_31=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_31
+axi_dwidth_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_33
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+picxo_fracxo_v2_0_3=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_3
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+v_frmbuf_wr_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_12
+sd_fec_beta_v1_0_0=$RDI_DATADIR/xsim/ip/sd_fec_beta_v1_0_0
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+lmb_bram_if_cntlr_v4_0_25=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_25
+mrmac_v3_0_0=$RDI_DATADIR/xsim/ip/mrmac_v3_0_0
+tsn_endpoint_ethernet_mac_block_v1_0_18=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_18
+axis_vio_v1_0_12=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_12
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+floating_point_v7_1_19=$RDI_DATADIR/xsim/ip/floating_point_v7_1_19
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+pc_cfr_v8_0_3=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_3
+axi_amm_bridge_v1_0_23=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_23
+c_counter_binary_v12_0_20=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_20
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+axi_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_19
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+axi_msg_v1_0_12=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_12
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+xpm=$RDI_DATADIR/xsim/ip/xpm
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+gtwizard_ultrascale_v1_7_19=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_19
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mipi_rx_phy_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_1
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+dds_compiler_v6_0_26=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_26
+xdma_v4_1_31=$RDI_DATADIR/xsim/ip/xdma_v4_1_31
+axi_fifo_mm_s_v4_3_5=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_5
+l_ethernet_v3_3_13=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_13
+xdfe_nlf_v1_1_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_2
+axi_mcdma_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_14
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+xdfe_common_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_4
+axi_intc_v4_1_20=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_20
+axi_uartlite_v2_0_37=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_37
+gmii_to_rgmii_v4_1_17=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_17
+cdcam_v1_2_0=$RDI_DATADIR/xsim/ip/cdcam_v1_2_0
+blk_mem_gen_v8_4_9=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_9
+system_cache_v5_0_12=$RDI_DATADIR/xsim/ip/system_cache_v5_0_12
+cmac_usplus_v3_1_19=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_19
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_interconnect_v1_7_24=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_24
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+v_hdmi_tx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_5
+dft_v4_2_9=$RDI_DATADIR/xsim/ip/dft_v4_2_9
+ieee802d3_400g_rs_fec_v3_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_3
+srio_gen2_v4_1_20=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_20
+mipi_tx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_tx_phy_v1_0_0
+axi_epc_v2_0_36=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_36
+i2s_transmitter_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_9
+flexo_100g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_30
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+axi_emc_v3_0_33=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_33
+multi_channel_25g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_28
+axi_protocol_checker_v2_0_19=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_19
+axi_register_slice_v2_1_33=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_33
+v_letterbox_v1_1_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_13
+gtwizard_ultrascale_v1_6_17=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_17
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+axis_broadcaster_v1_1_32=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_32
+axis_clock_converter_v1_1_34=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_34
+ahblite_axi_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_28
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+sid_v8_0_22=$RDI_DATADIR/xsim/ip/sid_v8_0_22
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+ten_gig_eth_pcs_pma_v6_0_28=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_28
+axis_register_slice_v1_1_33=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_33
+clk_vip_v1_0_5=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_5
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+v_vid_sdi_tx_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_3
+processing_system7_vip_v1_0_21=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_21
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+cmac_v2_6_17=$RDI_DATADIR/xsim/ip/cmac_v2_6_17
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+mpram_v1_0_5=$RDI_DATADIR/xsim/ip/mpram_v1_0_5
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+v_hscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_13
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+axis_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_17
+xbip_multadd_v3_0_21=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_21
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+axi_vfifo_ctrl_v2_0_36=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_36
+v_warp_filter_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_5
+xfft_v9_1_13=$RDI_DATADIR/xsim/ip/xfft_v9_1_13
+axi_bram_ctrl_v4_1_11=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_11
+v_hcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_13
+v_demosaic_v1_1_13=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_13
+lte_fft_v2_1_11=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_11
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+mrmac_v2_3_2=$RDI_DATADIR/xsim/ip/mrmac_v2_3_2
+v_tc_v6_2_9=$RDI_DATADIR/xsim/ip/v_tc_v6_2_9
+div_gen_v5_1_23=$RDI_DATADIR/xsim/ip/div_gen_v5_1_23
+rs_encoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_22
+axi_utils_v2_0_10=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_10
+v_axi4s_remap_v1_1_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_12
+v_mix_v5_2_11=$RDI_DATADIR/xsim/ip/v_mix_v5_2_11
+xdfe_fft_v1_0_8=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_8
+cic_compiler_v4_0_20=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_20
+sim_clk_gen_v1_0_5=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_5
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+usxgmii_v1_2_20=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_20
+v_smpte_sdi_v3_0_12=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_12
+mipi_dsi2_rx_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_1
+mdm_v3_2_27=$RDI_DATADIR/xsim/ip/mdm_v3_2_27
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+g975_efec_i7_v2_0_24=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_24
+axis_combiner_v1_1_31=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_31
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+dcmac_v2_5_0=$RDI_DATADIR/xsim/ip/dcmac_v2_5_0
+convolution_v9_0_21=$RDI_DATADIR/xsim/ip/convolution_v9_0_21
+microblaze_v11_0_14=$RDI_DATADIR/xsim/ip/microblaze_v11_0_14
+cpm4_v1_0_17=$RDI_DATADIR/xsim/ip/cpm4_v1_0_17
+cmpy_v6_0_25=$RDI_DATADIR/xsim/ip/cmpy_v6_0_25
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+spdif_v2_0_30=$RDI_DATADIR/xsim/ip/spdif_v2_0_30
+oran_radio_if_v3_2_1=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_1
+v_hdmi_rx1_v1_0_11=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_11
+cam_v3_1_0=$RDI_DATADIR/xsim/ip/cam_v3_1_0
+emb_fifo_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_6
+axi_iic_v2_1_9=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_9
+axi_perf_mon_v5_0_35=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_35
+v_tpg_v8_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_16
+mutex_v2_1_14=$RDI_DATADIR/xsim/ip/mutex_v2_1_14
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+lib_fifo_v1_0_20=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_20
+advanced_io_wizard_v1_0_15=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_15
+c_reg_fd_v12_0_10=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_10
+axi4stream_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_19
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+ieee802d3_50g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_25
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+vid_edid_v1_0_3=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_3
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+mult_gen_v12_0_22=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_22
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+dfe_channelizer_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/dfe_channelizer_wrapper_v1_0_0
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+v_frmbuf_wr_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v3_0_0
+xdfe_cc_mixer_v2_0_5=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_5
+mipi_dsi_tx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_10
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+ieee802d3_clause74_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_19
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_tft_v2_0_29=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_29
+viterbi_v9_1_18=$RDI_DATADIR/xsim/ip/viterbi_v9_1_18
+ieee802d3_50g_rs_fec_v2_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_18
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+ilknf_v1_3_5=$RDI_DATADIR/xsim/ip/ilknf_v1_3_5
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+g975_efec_i4_v1_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_23
+c_accum_v12_0_19=$RDI_DATADIR/xsim/ip/c_accum_v12_0_19
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+ieee802d3_25g_rs_fec_v1_0_31=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_31
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+xdfe_nr_prach_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_4
+gig_ethernet_pcs_pma_v16_2_21=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_21
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+v_sdi_rx_vid_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_3
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+ldpc_5gnr_v1_0_4=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_4
+soft_ecc_proxy_v1_1_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_2
+axi_c2c_v1_0_11=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_11
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+v_smpte_uhdsdi_v1_0_12=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_12
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+fir_compiler_v7_2_23=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_23
+axi_hbicap_v1_0_8=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_8
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+canfd_v3_0_12=$RDI_DATADIR/xsim/ip/canfd_v3_0_12
+nvme_tc_v3_0_8=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_8
+axi_usb2_device_v5_0_34=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_34
+ldpc_5gnr_lite_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_3
+tmr_inject_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_7
+v_uhdsdi_audio_v2_0_9=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_9
+xsdbm_v3_0_3=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_3
+v_vscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_13
+vid_phy_controller_v2_2_19=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_19
+mem_tg_v1_0_15=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_15
+dfx_axi_shutdown_manager_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_4
+ibert_lib_v1_0_12=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_12
+ta_dma_v1_0_17=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_17
+cam_blk_lib_v1_2_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_2_0
+noc2_nps6x_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps6x_v1_0_0
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+tcc_decoder_3gppmm_v2_0_28=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_28
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+ddr4_pl_v1_0_15=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_15
+advanced_io_wizard_phy_v1_0_4=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_4
+ft_prach_v1_2_3=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_3
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+x5io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_6
+axis_subset_converter_v1_1_33=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_33
+axi_quad_spi_v3_2_32=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_32
+g709_rs_encoder_v2_2_13=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_13
+hdcp_v1_0_6=$RDI_DATADIR/xsim/ip/hdcp_v1_0_6
+v_frmbuf_rd_v2_4_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_4
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+quadsgmii_v3_5_21=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_21
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+rst_vip_v1_0_7=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_7
+ethernet_offload_v1_0_0=$RDI_DATADIR/xsim/ip/ethernet_offload_v1_0_0
+cpm5_v1_0_17=$RDI_DATADIR/xsim/ip/cpm5_v1_0_17
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+displayport_v9_0_10=$RDI_DATADIR/xsim/ip/displayport_v9_0_10
+visp_v1_0_0=$RDI_DATADIR/xsim/ip/visp_v1_0_0
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak
new file mode 100644
index 0000000..e2f5709
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -0,0 +1,489 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+cpri_v8_12_0=$RDI_DATADIR/xsim/ip/cpri_v8_12_0
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+an_lt_v1_0_14=$RDI_DATADIR/xsim/ip/an_lt_v1_0_14
+axi_chip2chip_v5_0_24=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_24
+g709_fec_v2_4_11=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_11
+audio_formatter_v1_0_15=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_15
+ats_switch_v1_0_12=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_12
+xbip_pipe_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_10
+v_gamma_lut_v1_1_13=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_13
+vrf_fft_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_fft_v1_0_0
+v_hdmi_tx1_v1_0_10=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_10
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+axi_mm2s_mapper_v1_1_32=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_32
+axis_data_fifo_v1_1_34=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_34
+mailbox_v2_1_18=$RDI_DATADIR/xsim/ip/mailbox_v2_1_18
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+sdfec_ld_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/sdfec_ld_wrapper_v1_0_0
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+tcc_encoder_3gpplte_v4_0_20=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_20
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+vitis_net_p4_v2_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_2_0
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+v_frmbuf_rd_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v3_0_0
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+dfx_bitstream_monitor_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_6
+rs_toolbox_v9_0_14=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_14
+perf_axi_tg_v1_0_15=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_15
+xbip_utils_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_14
+dptx_v1_0_5=$RDI_DATADIR/xsim/ip/dptx_v1_0_5
+rs_decoder_v9_0_23=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_23
+dsp_macro_v1_0_7=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_7
+axi_vdma_v6_3_21=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_21
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+qdriv_pl_v1_0_14=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_14
+axis_data_fifo_v2_0_15=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_15
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_i3c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_2
+axi_sg_v4_1_19=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_19
+mipi_csi2_rx_ctrl_v1_0_11=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_11
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+xxv_ethernet_v4_1_13=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_13
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+ernic_v4_2_0=$RDI_DATADIR/xsim/ip/ernic_v4_2_0
+rama_v1_1_19_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_19_lib
+rfdace5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfdace5_wrapper_v1_0_0
+tsn_temac_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_12
+tri_mode_ethernet_mac_v9_0_35=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_35
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+ieee802d3_200g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_12
+fast_adapter_v1_0_10=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_10
+hdmi_gt_controller_v2_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v2_0_0
+xdfe_ofdm_v2_2_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_2_0
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+vfb_v1_0_27=$RDI_DATADIR/xsim/ip/vfb_v1_0_27
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+vcu2_v1_0_0=$RDI_DATADIR/xsim/ip/vcu2_v1_0_0
+shell_utils_addr_remap_v1_0_12=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_12
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+sim_trig_v1_0_13=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_13
+v_hdmi_phy1_v1_0_13=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_13
+displayport_v7_0_25=$RDI_DATADIR/xsim/ip/displayport_v7_0_25
+cordic_v6_0_23=$RDI_DATADIR/xsim/ip/cordic_v6_0_23
+axi_crossbar_v2_1_34=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_34
+proc_sys_reset_v5_0_16=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_16
+polar_v1_1_5=$RDI_DATADIR/xsim/ip/polar_v1_1_5
+xscl=$RDI_DATADIR/xsim/ip/xscl
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+ldpc_v2_0_16=$RDI_DATADIR/xsim/ip/ldpc_v2_0_16
+switch_core_top_v1_0_17=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_17
+v_frmbuf_wr_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_3
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+audio_clock_recovery_unit_v1_0_5=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_5
+xdfe_resampler_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_10
+sd_fec_v1_1_15=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_15
+fifo_generator_v13_2_11=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_11
+axi_timebase_wdt_v3_0_25=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_25
+psx_vip_v1_0_6=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_6
+axi_memory_init_v1_0_14=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_14
+emc_common_v3_0_8=$RDI_DATADIR/xsim/ip/emc_common_v3_0_8
+ieee802d3_rs_fec_v2_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_24
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+v_vcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_13
+v_csc_v1_1_13=$RDI_DATADIR/xsim/ip/v_csc_v1_1_13
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+zynq_ultra_ps_e_vip_v1_0_19=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_19
+axi_cdma_v4_1_33=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_33
+v_dp_axi4s_vid_out_v1_0_9=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_9
+i2s_receiver_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_9
+rld3_pl_v1_0_15=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_15
+axi_firewall_v1_2_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_8
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+cpm5n_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_9
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+axis_switch_v1_1_33=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_33
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+mipi_dphy_v4_3_13=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_13
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+iomodule_v3_1_11=$RDI_DATADIR/xsim/ip/iomodule_v3_1_11
+fc32_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_28
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+axi_hwicap_v3_0_37=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_37
+g709_rs_decoder_v2_2_15=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_15
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+tmr_voter_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_7
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mdm_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_3
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+amm_axi_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_19
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+axis_accelerator_adapter_v2_1_19=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_19
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+vrf_channelizer_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_channelizer_v1_0_0
+uhdsdi_gt_v2_1_5=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_5
+v_deinterlacer_v5_1_6=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_6
+noc_hbm_v1_0_1=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_1
+in_system_ibert_v1_0_23=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_23
+axi_pcie_v2_9_12=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_12
+axi_epu_v1_0_6=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_6
+floating_point_v7_0_24=$RDI_DATADIR/xsim/ip/floating_point_v7_0_24
+v_axi4s_vid_out_v4_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_19
+v_multi_scaler_v1_2_7=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_7
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+can_v5_1_5=$RDI_DATADIR/xsim/ip/can_v5_1_5
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+xdfe_cc_filter_v1_1_5=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_5
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+v_smpte_uhdsdi_tx_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_5
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+noc2_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_sim_v1_0_0
+tmr_sem_v1_0_27=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_27
+axi_ahblite_bridge_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_30
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+axi_uart16550_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_35
+ecc_v2_0_17=$RDI_DATADIR/xsim/ip/ecc_v2_0_17
+v_frmbuf_rd_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_12
+axi_data_fifo_v2_1_32=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_32
+xdfe_equalizer_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_10
+axi_mcdma_v1_2_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_2_0
+versal_cips_ps_vip_v1_0_11=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_11
+emb_mem_gen_v1_0_10=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_10
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+displayport_v8_1_10=$RDI_DATADIR/xsim/ip/displayport_v8_1_10
+tcc_encoder_3gpp_v5_0_23=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_23
+pcie_qdma_mailbox_v1_0_8=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_8
+v_frmbuf_rd_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_dwidth_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_32
+axi4svideo_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_19
+util_ff_v1_0_4=$RDI_DATADIR/xsim/ip/util_ff_v1_0_4
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+microblaze_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_3
+cpri_v8_11_22=$RDI_DATADIR/xsim/ip/cpri_v8_11_22
+v_vid_in_axi4s_v5_0_5=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_5
+dprx_v1_0_5=$RDI_DATADIR/xsim/ip/dprx_v1_0_5
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+axi_pcie3_v3_0_32=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_32
+v_smpte_uhdsdi_rx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_4
+axi_datamover_v5_1_35=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_35
+interlaken_v2_4_19=$RDI_DATADIR/xsim/ip/interlaken_v2_4_19
+nvmeha_v1_0_14=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_14
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+bfr_ft_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/bfr_ft_wrapper_v1_0_0
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+zynq_ultra_ps_e_v3_3_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_14
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+v_hdmi_rx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_5
+ethernet_1_10_25g_v2_7_18=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_18
+v_tpg_v8_2_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_6
+qdma_v5_0_12=$RDI_DATADIR/xsim/ip/qdma_v5_0_12
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+jesd204c_v4_3_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_3_0
+axi_timer_v2_0_35=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_35
+c_compare_v12_0_10=$RDI_DATADIR/xsim/ip/c_compare_v12_0_10
+axi_clock_converter_v2_1_32=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_32
+axi_protocol_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_33
+axi_dma_v7_1_34=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_34
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+dfx_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_11
+axi_sideband_util_v1_0_17=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_17
+tmr_manager_v1_0_13=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_13
+fec_5g_common_v1_1_5=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_5
+axi_ethernetlite_v3_0_32=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_32
+lib_bmg_v1_0_18=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_18
+high_speed_selectio_wiz_v3_6_10=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_10
+c_shift_ram_v12_0_18=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_18
+axi_pmon_v1_0_2=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_2
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+uhdsdi_gt_v2_2_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_2_0
+v_tpg_v8_1_12=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_12
+noc2_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_sim_v1_0_0
+axi_gpio_v2_0_35=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_35
+axis_interconnect_v1_1_24=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_24
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+c_addsub_v12_0_19=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_19
+sem_ultra_v3_1_27=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_27
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+v_warp_init_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+roe_framer_v3_0_9=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_9
+axi_remapper_tx_v1_0_3=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_3
+axi_traffic_gen_v3_0_19=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_19
+dfx_controller_v1_0_8=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_8
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+tmr_comparator_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_8
+rfadce5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfadce5_wrapper_v1_0_0
+axi_mmu_v2_1_31=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_31
+axi_dwidth_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_33
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+picxo_fracxo_v2_0_3=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_3
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+v_frmbuf_wr_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_12
+sd_fec_beta_v1_0_0=$RDI_DATADIR/xsim/ip/sd_fec_beta_v1_0_0
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+lmb_bram_if_cntlr_v4_0_25=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_25
+mrmac_v3_0_0=$RDI_DATADIR/xsim/ip/mrmac_v3_0_0
+tsn_endpoint_ethernet_mac_block_v1_0_18=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_18
+axis_vio_v1_0_12=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_12
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+floating_point_v7_1_19=$RDI_DATADIR/xsim/ip/floating_point_v7_1_19
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+pc_cfr_v8_0_3=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_3
+axi_amm_bridge_v1_0_23=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_23
+c_counter_binary_v12_0_20=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_20
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+axi_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_19
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+axi_msg_v1_0_12=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_12
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+xpm=$RDI_DATADIR/xsim/ip/xpm
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+gtwizard_ultrascale_v1_7_19=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_19
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mipi_rx_phy_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_1
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+dds_compiler_v6_0_26=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_26
+xdma_v4_1_31=$RDI_DATADIR/xsim/ip/xdma_v4_1_31
+axi_fifo_mm_s_v4_3_5=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_5
+l_ethernet_v3_3_13=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_13
+xdfe_nlf_v1_1_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_2
+axi_mcdma_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_14
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+xdfe_common_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_4
+axi_intc_v4_1_20=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_20
+axi_uartlite_v2_0_37=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_37
+gmii_to_rgmii_v4_1_17=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_17
+cdcam_v1_2_0=$RDI_DATADIR/xsim/ip/cdcam_v1_2_0
+blk_mem_gen_v8_4_9=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_9
+system_cache_v5_0_12=$RDI_DATADIR/xsim/ip/system_cache_v5_0_12
+cmac_usplus_v3_1_19=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_19
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_interconnect_v1_7_24=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_24
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+v_hdmi_tx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_5
+dft_v4_2_9=$RDI_DATADIR/xsim/ip/dft_v4_2_9
+ieee802d3_400g_rs_fec_v3_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_3
+srio_gen2_v4_1_20=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_20
+mipi_tx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_tx_phy_v1_0_0
+axi_epc_v2_0_36=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_36
+i2s_transmitter_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_9
+flexo_100g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_30
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+axi_emc_v3_0_33=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_33
+multi_channel_25g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_28
+axi_protocol_checker_v2_0_19=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_19
+axi_register_slice_v2_1_33=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_33
+v_letterbox_v1_1_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_13
+gtwizard_ultrascale_v1_6_17=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_17
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+axis_broadcaster_v1_1_32=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_32
+axis_clock_converter_v1_1_34=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_34
+ahblite_axi_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_28
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+sid_v8_0_22=$RDI_DATADIR/xsim/ip/sid_v8_0_22
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+ten_gig_eth_pcs_pma_v6_0_28=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_28
+axis_register_slice_v1_1_33=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_33
+clk_vip_v1_0_5=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_5
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+v_vid_sdi_tx_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_3
+processing_system7_vip_v1_0_21=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_21
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+cmac_v2_6_17=$RDI_DATADIR/xsim/ip/cmac_v2_6_17
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+mpram_v1_0_5=$RDI_DATADIR/xsim/ip/mpram_v1_0_5
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+v_hscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_13
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+axis_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_17
+xbip_multadd_v3_0_21=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_21
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+axi_vfifo_ctrl_v2_0_36=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_36
+v_warp_filter_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_5
+xfft_v9_1_13=$RDI_DATADIR/xsim/ip/xfft_v9_1_13
+axi_bram_ctrl_v4_1_11=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_11
+v_hcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_13
+v_demosaic_v1_1_13=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_13
+lte_fft_v2_1_11=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_11
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+mrmac_v2_3_2=$RDI_DATADIR/xsim/ip/mrmac_v2_3_2
+v_tc_v6_2_9=$RDI_DATADIR/xsim/ip/v_tc_v6_2_9
+div_gen_v5_1_23=$RDI_DATADIR/xsim/ip/div_gen_v5_1_23
+rs_encoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_22
+axi_utils_v2_0_10=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_10
+v_axi4s_remap_v1_1_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_12
+v_mix_v5_2_11=$RDI_DATADIR/xsim/ip/v_mix_v5_2_11
+xdfe_fft_v1_0_8=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_8
+cic_compiler_v4_0_20=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_20
+sim_clk_gen_v1_0_5=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_5
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+usxgmii_v1_2_20=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_20
+v_smpte_sdi_v3_0_12=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_12
+mipi_dsi2_rx_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_1
+mdm_v3_2_27=$RDI_DATADIR/xsim/ip/mdm_v3_2_27
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+g975_efec_i7_v2_0_24=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_24
+axis_combiner_v1_1_31=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_31
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+dcmac_v2_5_0=$RDI_DATADIR/xsim/ip/dcmac_v2_5_0
+convolution_v9_0_21=$RDI_DATADIR/xsim/ip/convolution_v9_0_21
+microblaze_v11_0_14=$RDI_DATADIR/xsim/ip/microblaze_v11_0_14
+cpm4_v1_0_17=$RDI_DATADIR/xsim/ip/cpm4_v1_0_17
+cmpy_v6_0_25=$RDI_DATADIR/xsim/ip/cmpy_v6_0_25
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+spdif_v2_0_30=$RDI_DATADIR/xsim/ip/spdif_v2_0_30
+oran_radio_if_v3_2_1=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_1
+v_hdmi_rx1_v1_0_11=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_11
+cam_v3_1_0=$RDI_DATADIR/xsim/ip/cam_v3_1_0
+emb_fifo_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_6
+axi_iic_v2_1_9=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_9
+axi_perf_mon_v5_0_35=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_35
+v_tpg_v8_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_16
+mutex_v2_1_14=$RDI_DATADIR/xsim/ip/mutex_v2_1_14
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+lib_fifo_v1_0_20=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_20
+advanced_io_wizard_v1_0_15=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_15
+c_reg_fd_v12_0_10=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_10
+axi4stream_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_19
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+ieee802d3_50g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_25
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+vid_edid_v1_0_3=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_3
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+mult_gen_v12_0_22=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_22
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+dfe_channelizer_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/dfe_channelizer_wrapper_v1_0_0
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+v_frmbuf_wr_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v3_0_0
+xdfe_cc_mixer_v2_0_5=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_5
+mipi_dsi_tx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_10
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+ieee802d3_clause74_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_19
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_tft_v2_0_29=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_29
+viterbi_v9_1_18=$RDI_DATADIR/xsim/ip/viterbi_v9_1_18
+ieee802d3_50g_rs_fec_v2_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_18
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+ilknf_v1_3_5=$RDI_DATADIR/xsim/ip/ilknf_v1_3_5
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+g975_efec_i4_v1_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_23
+c_accum_v12_0_19=$RDI_DATADIR/xsim/ip/c_accum_v12_0_19
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+ieee802d3_25g_rs_fec_v1_0_31=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_31
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+xdfe_nr_prach_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_4
+gig_ethernet_pcs_pma_v16_2_21=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_21
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+v_sdi_rx_vid_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_3
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+ldpc_5gnr_v1_0_4=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_4
+soft_ecc_proxy_v1_1_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_2
+axi_c2c_v1_0_11=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_11
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+v_smpte_uhdsdi_v1_0_12=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_12
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+fir_compiler_v7_2_23=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_23
+axi_hbicap_v1_0_8=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_8
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+canfd_v3_0_12=$RDI_DATADIR/xsim/ip/canfd_v3_0_12
+nvme_tc_v3_0_8=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_8
+axi_usb2_device_v5_0_34=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_34
+ldpc_5gnr_lite_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_3
+tmr_inject_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_7
+v_uhdsdi_audio_v2_0_9=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_9
+xsdbm_v3_0_3=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_3
+v_vscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_13
+vid_phy_controller_v2_2_19=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_19
+mem_tg_v1_0_15=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_15
+dfx_axi_shutdown_manager_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_4
+ibert_lib_v1_0_12=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_12
+ta_dma_v1_0_17=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_17
+cam_blk_lib_v1_2_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_2_0
+noc2_nps6x_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps6x_v1_0_0
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+tcc_decoder_3gppmm_v2_0_28=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_28
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+ddr4_pl_v1_0_15=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_15
+advanced_io_wizard_phy_v1_0_4=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_4
+ft_prach_v1_2_3=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_3
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+x5io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_6
+axis_subset_converter_v1_1_33=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_33
+axi_quad_spi_v3_2_32=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_32
+g709_rs_encoder_v2_2_13=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_13
+hdcp_v1_0_6=$RDI_DATADIR/xsim/ip/hdcp_v1_0_6
+v_frmbuf_rd_v2_4_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_4
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+quadsgmii_v3_5_21=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_21
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+rst_vip_v1_0_7=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_7
+ethernet_offload_v1_0_0=$RDI_DATADIR/xsim/ip/ethernet_offload_v1_0_0
+cpm5_v1_0_17=$RDI_DATADIR/xsim/ip/cpm5_v1_0_17
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+displayport_v9_0_10=$RDI_DATADIR/xsim/ip/displayport_v9_0_10
+visp_v1_0_0=$RDI_DATADIR/xsim/ip/visp_v1_0_0
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000..e69de29
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log
new file mode 100644
index 0000000..0e6879b
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log
@@ -0,0 +1,12 @@
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a24perei/medcon/tp-filtre-etudiant-a24perei/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module clk_wiz_0_clk_wiz
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a24perei/medcon/tp-filtre-etudiant-a24perei/src/ip/clk_wiz_0/clk_wiz_0.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module clk_wiz_0
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a24perei/medcon/tp-filtre-etudiant-a24perei/src/hdl/audio_init.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module audio_init
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a24perei/medcon/tp-filtre-etudiant-a24perei/src/hdl/debounce.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module debounce
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a24perei/medcon/tp-filtre-etudiant-a24perei/src/hdl/audioProc.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module audioProc
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/a24perei/medcon/tp-filtre-etudiant-a24perei/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module glbl
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.pb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvlog.pb
new file mode 100644
index 0000000000000000000000000000000000000000..743a2f97ba63b92ce2ceccec27813ed859107401
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diff --git a/proj/project_1/project_1.xpr b/proj/project_1/project_1.xpr
new file mode 100644
index 0000000..3a6e0cc
--- /dev/null
+++ b/proj/project_1/project_1.xpr
@@ -0,0 +1,301 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/proj/project_1/project_1.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="98f33fc04d38443e92b4f879703180e1"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../medcon/tp-ecg-etudiant-a24perei/repo"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="115"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="controlUnit"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_firUnit"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 0c18c92..fa1e323 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -15,7 +15,7 @@ entity controlUnit is
O_loadSum : out std_logic;
O_loadY : out std_logic;
O_FilteredSampleValid : out std_logic;
- O_filterStage : out integer range 0 to 2 -- 🚀 Adicionado para indicar o estágio do filtro
+ O_filterStage : out integer range 0 to 2
);
end entity controlUnit;
@@ -55,20 +55,20 @@ begin
if SR_filterStage < 2 then
SR_futurState <= NEXT_FILTER;
else
- SR_futurState <= FINAL_OUTPUT; -- ✅ Após o último filtro, vai para FINAL_OUTPUT
+ SR_futurState <= FINAL_OUTPUT; -- Após o último filtro, vai para FINAL_OUTPUT
end if;
when NEXT_FILTER =>
- SR_futurState <= STORE; -- ✅ Processa o próximo filtro e volta ao PROCESSING_LOOP
+ SR_futurState <= STORE; -- Processa o próximo filtro e volta ao PROCESSING_LOOP
when FINAL_OUTPUT =>
- SR_futurState <= WAIT_END_SAMPLE; -- ✅ Estado final antes de esperar um novo input
+ SR_futurState <= WAIT_END_SAMPLE; -- Estado final antes de esperar um novo input
when WAIT_END_SAMPLE =>
if I_inputSampleValid = '1' then
- SR_futurState <= STORE; -- ✅ Só recomeça se um novo input chegar
+ SR_futurState <= STORE; -- Só recomeça se um novo input chegar
else
- SR_futurState <= WAIT_END_SAMPLE; -- ✅ Mantém a FSM parada se não houver novo input
+ SR_futurState <= WAIT_END_SAMPLE; -- Mantém a FSM parada se não houver novo input
end if;
when others =>
@@ -92,7 +92,7 @@ begin
SR_filterStage <= SR_filterStage + 1; -- 🚀 Avança para o próximo filtro
end if;
elsif SR_presentState = FINAL_OUTPUT then
- SR_filterStage <= 0; -- 🚀 Após os 3 filtros, reinicia para o primeiro
+ SR_filterStage <= 0; -- Após os 3 filtros, reinicia para o primeiro
end if;
end if;
--
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