From a6cfb042ddef7f64b54c00e4dacb4d5ad4d2bae4 Mon Sep 17 00:00:00 2001
From: Antonio Emilio <antonio_pereira@outlook.com>
Date: Tue, 18 Mar 2025 22:56:40 +0100
Subject: [PATCH] feat; working on ecg
---
proj/AudioProc.cache/wt/project.wpc | 2 +-
proj/AudioProc.cache/wt/synthesis.wdf | 52 ++
proj/AudioProc.cache/wt/synthesis_details.wdf | 3 +
proj/AudioProc.cache/wt/xsim.wdf | 4 +-
proj/AudioProc.runs/.jobs/vrs_config_1.xml | 11 +
.../synth_1/.Vivado_Synthesis.queue.rst | 0
proj/AudioProc.runs/synth_1/.vivado.begin.rst | 5 +
proj/AudioProc.runs/synth_1/.vivado.end.rst | 0
proj/AudioProc.runs/synth_1/ISEWrap.js | 270 ++++++
proj/AudioProc.runs/synth_1/ISEWrap.sh | 85 ++
.../synth_1/__synthesis_is_complete__ | 0
proj/AudioProc.runs/synth_1/controlUnit.dcp | Bin 0 -> 14483 bytes
proj/AudioProc.runs/synth_1/controlUnit.tcl | 108 +++
proj/AudioProc.runs/synth_1/controlUnit.vds | 324 ++++++++
proj/AudioProc.runs/synth_1/gen_run.xml | 122 +++
proj/AudioProc.runs/synth_1/htr.txt | 10 +
proj/AudioProc.runs/synth_1/project.wdf | 31 +
proj/AudioProc.runs/synth_1/rundef.js | 37 +
proj/AudioProc.runs/synth_1/runme.bat | 11 +
proj/AudioProc.runs/synth_1/runme.log | 315 +++++++
proj/AudioProc.runs/synth_1/runme.sh | 44 +
proj/AudioProc.runs/synth_1/vivado.jou | 24 +
proj/AudioProc.runs/synth_1/vivado.pb | Bin 0 -> 32872 bytes
.../sim_1/behav/xsim/compile.bat | 2 +-
.../sim_1/behav/xsim/compile.log | 8 +
.../sim_1/behav/xsim/elaborate.bat | 2 +-
.../sim_1/behav/xsim/elaborate.log | 13 +-
.../sim_1/behav/xsim/simulate.bat | 2 +-
.../sim_1/behav/xsim/tb_firUnit_behav.wdb | Bin 61927 -> 448 bytes
proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb | Bin 847 -> 1963 bytes
.../tb_firUnit_behav/obj/xsim_0.win64.obj | Bin 18800 -> 23178 bytes
.../xsim.dir/tb_firUnit_behav/obj/xsim_1.c | 15 +-
.../tb_firUnit_behav/obj/xsim_1.win64.obj | Bin 3564 -> 3713 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.dbg | Bin 11896 -> 14440 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.mem | Bin 3997 -> 4348 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.reloc | Bin 1240 -> 1533 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rlx | 2 +-
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rtti | Bin 935 -> 881 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.type | Bin 7400 -> 7408 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg | Bin 99120 -> 91568 bytes
.../tb_firUnit_behav/xsimSettings.ini | 10 +-
.../xsim/xsim.dir/tb_firUnit_behav/xsimk.exe | Bin 79482 -> 84320 bytes
.../xsim.dir/tb_firUnit_behav/xsimkernel.log | 6 +-
.../xsim.dir/xil_defaultlib/controlunit.vdb | Bin 12285 -> 11296 bytes
.../xsim/xsim.dir/xil_defaultlib/firunit.vdb | Bin 9487 -> 12656 bytes
.../xsim.dir/xil_defaultlib/operativeunit.vdb | Bin 39538 -> 37543 bytes
.../xsim.dir/xil_defaultlib/tb_firunit.vdb | Bin 7671 -> 6102 bytes
.../xil_defaultlib/xil_defaultlib.rlx | 6 +-
proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log | 8 +
proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb | Bin 16 -> 1094 bytes
proj/AudioProc.xpr | 21 +-
src-ref/ECG_raw_3filters-inc.pdf | Bin 3091 -> 3091 bytes
src-ref/ECG_raw_3filters.tex | 2 +-
src-ref/coeficientes_vhdl.txt | 258 +++---
src/hdl/controlUnit.vhd | 290 +++----
src/hdl/firUnit.vhd | 120 +--
src/hdl/operativeUnit.vhd | 769 +++++++++---------
src/hdl/tb_firUnit.vhd | 54 +-
58 files changed, 2229 insertions(+), 817 deletions(-)
create mode 100644 proj/AudioProc.cache/wt/synthesis.wdf
create mode 100644 proj/AudioProc.cache/wt/synthesis_details.wdf
create mode 100644 proj/AudioProc.runs/.jobs/vrs_config_1.xml
create mode 100644 proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst
create mode 100644 proj/AudioProc.runs/synth_1/.vivado.begin.rst
create mode 100644 proj/AudioProc.runs/synth_1/.vivado.end.rst
create mode 100644 proj/AudioProc.runs/synth_1/ISEWrap.js
create mode 100644 proj/AudioProc.runs/synth_1/ISEWrap.sh
create mode 100644 proj/AudioProc.runs/synth_1/__synthesis_is_complete__
create mode 100644 proj/AudioProc.runs/synth_1/controlUnit.dcp
create mode 100644 proj/AudioProc.runs/synth_1/controlUnit.tcl
create mode 100644 proj/AudioProc.runs/synth_1/controlUnit.vds
create mode 100644 proj/AudioProc.runs/synth_1/gen_run.xml
create mode 100644 proj/AudioProc.runs/synth_1/htr.txt
create mode 100644 proj/AudioProc.runs/synth_1/project.wdf
create mode 100644 proj/AudioProc.runs/synth_1/rundef.js
create mode 100644 proj/AudioProc.runs/synth_1/runme.bat
create mode 100644 proj/AudioProc.runs/synth_1/runme.log
create mode 100644 proj/AudioProc.runs/synth_1/runme.sh
create mode 100644 proj/AudioProc.runs/synth_1/vivado.jou
create mode 100644 proj/AudioProc.runs/synth_1/vivado.pb
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/compile.log
diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
index c7c2fb6..4e6ebcf 100644
--- a/proj/AudioProc.cache/wt/project.wpc
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:5
+6d6f64655f636f756e7465727c4755494d6f6465:10
eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..ff3b5e6
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
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diff --git a/proj/AudioProc.cache/wt/synthesis_details.wdf b/proj/AudioProc.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000..78f8d66
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
index 51d5206..50afb2c 100644
--- a/proj/AudioProc.cache/wt/xsim.wdf
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -1,4 +1,4 @@
version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
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-eof:2427094519
+eof:241934075
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_1.xml b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000..f0bcf81
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst b/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000..252a77f
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado.bat" Owner="Conta" Host="BOOK-IFJRPL7DU0" Pid="16568" HostCore="20" HostMemory="033897811968">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/.vivado.end.rst b/proj/AudioProc.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.js b/proj/AudioProc.runs/synth_1/ISEWrap.js
new file mode 100644
index 0000000..61806d0
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.sh b/proj/AudioProc.runs/synth_1/ISEWrap.sh
new file mode 100644
index 0000000..05d5381
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/synth_1/__synthesis_is_complete__ b/proj/AudioProc.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.runs/synth_1/controlUnit.dcp b/proj/AudioProc.runs/synth_1/controlUnit.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..be17eb1c38dd5de5a49c9b3c314ed8f35bfdaf1b
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diff --git a/proj/AudioProc.runs/synth_1/controlUnit.tcl b/proj/AudioProc.runs/synth_1/controlUnit.tcl
new file mode 100644
index 0000000..eae312a
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/controlUnit.tcl
@@ -0,0 +1,108 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1/controlUnit.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a200tsbg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.cache/wt [current_project]
+set_property parent.project_path C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_repo_paths c:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/repo [current_project]
+update_ip_catalog
+set_property ip_output_repo c:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc
+set_property used_in_implementation false [get_files C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top controlUnit -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef controlUnit.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/proj/AudioProc.runs/synth_1/controlUnit.vds b/proj/AudioProc.runs/synth_1/controlUnit.vds
new file mode 100644
index 0000000..9cd05a3
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/controlUnit.vds
@@ -0,0 +1,324 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Mar 11 23:00:46 2025
+# Process ID : 26040
+# Current directory : C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1
+# Command line : vivado.exe -log controlUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source controlUnit.tcl
+# Log file : C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1/controlUnit.vds
+# Journal file : C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1\vivado.jou
+# Running On : BOOK-IFJRPL7DU0
+# Platform : Windows Server 2016 or Windows 10
+# Operating System : 26100
+# Processor Detail : 13th Gen Intel(R) Core(TM) i7-13700H
+# CPU Frequency : 2918 MHz
+# CPU Physical cores : 14
+# CPU Logical cores : 20
+# Host memory : 33897 MB
+# Swap memory : 2147 MB
+# Total Virtual : 36045 MB
+# Available Virtual : 12725 MB
+#-----------------------------------------------------------
+source controlUnit.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2024.2/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
+Current IP cache path is c:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.cache/ip
+Command: synth_design -top controlUnit -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 42632
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1081.090 ; gain = 468.262
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd:22]
+WARNING: [Synth 8-614] signal 'SR_filterStage' is read in the process but is not in the sensitivity list [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd:34]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd:22]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1185.668 ; gain = 572.840
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1185.668 ; gain = 572.840
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1185.668 ; gain = 572.840
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1185.668 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:8]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:8]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led3'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led4'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led5'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led6'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:18]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:18]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led7'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:19]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:19]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNC'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:23]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:23]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTND'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:24]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:24]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNL'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:25]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:25]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNR'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:26]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:26]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNU'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'rstn'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:28]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:28]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:32]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:32]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw3'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:35]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:35]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw4'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:36]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:36]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw5'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:37]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:37]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw6'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:38]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:38]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw7'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:39]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:39]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_adc_sdata'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:91]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:91]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_bclk'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:92]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:92]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_dac_sdata'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:93]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:93]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_lrclk'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:94]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:94]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_mclk'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:95]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:95]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'scl'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:202]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:202]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sda'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:203]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:203]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.090 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1254.090 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 0000001 | 000
+ store | 0000010 | 001
+ processing_loop | 0000100 | 010
+ output | 0001000 | 011
+ next_filter | 0010000 | 101
+ final_output | 0100000 | 110
+ wait_end_sample | 1000000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 2 Bit Adders := 1
++---Registers :
+ 2 Bit Registers := 1
++---Muxes :
+ 7 Input 7 Bit Muxes := 1
+ 2 Input 7 Bit Muxes := 4
+ 2 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 1
+ 7 Input 1 Bit Muxes := 3
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1386.586 ; gain = 773.758
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1386.586 ; gain = 773.758
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1396.641 ; gain = 783.812
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----+------+
+| |Cell |Count |
++------+-----+------+
+|1 |BUFG | 1|
+|2 |LUT2 | 6|
+|3 |LUT3 | 3|
+|4 |LUT4 | 1|
+|5 |LUT5 | 2|
+|6 |FDCE | 8|
+|7 |FDPE | 1|
+|8 |IBUF | 4|
+|9 |OBUF | 9|
++------+-----+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 1612.969 ; gain = 931.719
+Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1612.969 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1612.969 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: f94b0336
+INFO: [Common 17-83] Releasing license: Synthesis
+18 Infos, 29 Warnings, 25 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:13 . Memory (MB): peak = 1612.969 ; gain = 1245.328
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1612.969 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1/controlUnit.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 11 23:02:03 2025...
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000..1476d2c
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1741730442">
+ <File Type="PA-TCL" Name="controlUnit.tcl"/>
+ <File Type="REPORTS-TCL" Name="controlUnit_reports.tcl"/>
+ <File Type="RDS-RDS" Name="controlUnit.vds"/>
+ <File Type="RDS-DCP" Name="controlUnit.dcp"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="controlUnit"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+</GenRun>
diff --git a/proj/AudioProc.runs/synth_1/htr.txt b/proj/AudioProc.runs/synth_1/htr.txt
new file mode 100644
index 0000000..ba6b514
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM the basic steps of a run. Note that runme.bat/sh needs
+REM to be invoked for Vivado to track run status.
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+
+vivado -log controlUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source controlUnit.tcl
diff --git a/proj/AudioProc.runs/synth_1/project.wdf b/proj/AudioProc.runs/synth_1/project.wdf
new file mode 100644
index 0000000..f1d3e11
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:466c6f775f506572664f7074696d697a65645f48696768:00:00
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+eof:2655913581
diff --git a/proj/AudioProc.runs/synth_1/rundef.js b/proj/AudioProc.runs/synth_1/rundef.js
new file mode 100644
index 0000000..fadc53b
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/rundef.js
@@ -0,0 +1,37 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "C:/Xilinx/Vitis/2024.2/bin;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2024.2/bin;";
+} else {
+ PathVal = "C:/Xilinx/Vitis/2024.2/bin;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2024.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log controlUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source controlUnit.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/synth_1/runme.bat b/proj/AudioProc.runs/synth_1/runme.bat
new file mode 100644
index 0000000..6733dc9
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
new file mode 100644
index 0000000..1df6445
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -0,0 +1,315 @@
+
+*** Running vivado
+ with args -log controlUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source controlUnit.tcl
+
+
+
+****** Vivado v2024.2 (64-bit)
+ **** SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+ **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+ **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+ **** Start of session at: Tue Mar 11 23:00:46 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source controlUnit.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2024.2/data/ip'.
+WARNING: [IP_Flow 19-4995] The host OS only allows 260 characters in a normal path. The IP cache path is more than 80 characters. If you experience issues with IP caching, please consider changing the IP cache to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
+Current IP cache path is c:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.cache/ip
+Command: synth_design -top controlUnit -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 42632
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1081.090 ; gain = 468.262
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd:22]
+WARNING: [Synth 8-614] signal 'SR_filterStage' is read in the process but is not in the sensitivity list [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd:34]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd:22]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1185.668 ; gain = 572.840
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1185.668 ; gain = 572.840
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1185.668 ; gain = 572.840
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1185.668 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:8]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:8]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led3'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:15]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:15]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led4'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:16]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:16]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led5'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:17]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:17]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led6'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:18]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:18]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'led7'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:19]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:19]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNC'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:23]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:23]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTND'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:24]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:24]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNL'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:25]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:25]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNR'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:26]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:26]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'BTNU'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'rstn'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:28]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:28]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:32]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:32]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw3'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:35]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:35]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw4'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:36]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:36]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw5'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:37]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:37]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw6'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:38]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:38]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sw7'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:39]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:39]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_adc_sdata'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:91]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:91]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_bclk'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:92]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:92]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_dac_sdata'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:93]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:93]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_lrclk'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:94]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:94]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'ac_mclk'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:95]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:95]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'scl'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:202]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:202]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'sda'. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:203]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc:203]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/constraints/NexysVideo_Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.090 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1254.090 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 0000001 | 000
+ store | 0000010 | 001
+ processing_loop | 0000100 | 010
+ output | 0001000 | 011
+ next_filter | 0010000 | 101
+ final_output | 0100000 | 110
+ wait_end_sample | 1000000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 2 Bit Adders := 1
++---Registers :
+ 2 Bit Registers := 1
++---Muxes :
+ 7 Input 7 Bit Muxes := 1
+ 2 Input 7 Bit Muxes := 4
+ 2 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 1
+ 7 Input 1 Bit Muxes := 3
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 1254.090 ; gain = 641.262
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1386.586 ; gain = 773.758
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1386.586 ; gain = 773.758
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1396.641 ; gain = 783.812
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----+------+
+| |Cell |Count |
++------+-----+------+
+|1 |BUFG | 1|
+|2 |LUT2 | 6|
+|3 |LUT3 | 3|
+|4 |LUT4 | 1|
+|5 |LUT5 | 2|
+|6 |FDCE | 8|
+|7 |FDPE | 1|
+|8 |IBUF | 4|
+|9 |OBUF | 9|
++------+-----+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:01:03 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 1612.969 ; gain = 931.719
+Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1612.969 ; gain = 1000.141
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1612.969 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1612.969 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: f94b0336
+INFO: [Common 17-83] Releasing license: Synthesis
+18 Infos, 29 Warnings, 25 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:13 . Memory (MB): peak = 1612.969 ; gain = 1245.328
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1612.969 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1/controlUnit.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Tue Mar 11 23:02:03 2025...
diff --git a/proj/AudioProc.runs/synth_1/runme.sh b/proj/AudioProc.runs/synth_1/runme.sh
new file mode 100644
index 0000000..35b6709
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+
+if [ -z "$PATH" ]; then
+ PATH=C:/Xilinx/Vitis/2024.2/bin;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2024.2/bin
+else
+ PATH=C:/Xilinx/Vitis/2024.2/bin;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2024.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2024.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log controlUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source controlUnit.tcl
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
new file mode 100644
index 0000000..16184e7
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Mar 11 23:00:46 2025
+# Process ID : 26040
+# Current directory : C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1
+# Command line : vivado.exe -log controlUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source controlUnit.tcl
+# Log file : C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1/controlUnit.vds
+# Journal file : C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/proj/AudioProc.runs/synth_1\vivado.jou
+# Running On : BOOK-IFJRPL7DU0
+# Platform : Windows Server 2016 or Windows 10
+# Operating System : 26100
+# Processor Detail : 13th Gen Intel(R) Core(TM) i7-13700H
+# CPU Frequency : 2918 MHz
+# CPU Physical cores : 14
+# CPU Logical cores : 20
+# Host memory : 33897 MB
+# Swap memory : 2147 MB
+# Total Virtual : 36045 MB
+# Available Virtual : 12725 MB
+#-----------------------------------------------------------
+source controlUnit.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat b/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat
index 90c0bc0..882944f 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.bat
@@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : AMD Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
-REM Generated by Vivado on Sat Mar 08 19:39:29 +0100 2025
+REM Generated by Vivado on Tue Mar 18 22:56:13 +0100 2025
REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.log b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000..e9b0a65
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,8 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat
index b4dbe4f..6a296df 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.bat
@@ -6,7 +6,7 @@ REM Filename : elaborate.bat
REM Simulator : AMD Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
-REM Generated by Vivado on Sat Mar 08 19:39:30 +0100 2025
+REM Generated by Vivado on Tue Mar 18 22:56:15 +0100 2025
REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
index db78a7c..515bcc8 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
@@ -5,4 +5,15 @@ Running: C:/Xilinx/Vivado/2024.2/bin/unwrapped/win64.o/xelab.exe --incr --debug
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat
index d40839b..7592180 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.bat
@@ -6,7 +6,7 @@ REM Filename : simulate.bat
REM Simulator : AMD Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
-REM Generated by Vivado on Sat Mar 08 18:23:47 +0100 2025
+REM Generated by Vivado on Tue Mar 18 22:56:16 +0100 2025
REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index 92bae6e04f64d3de695bb19e86c20b7dd4aed561..0a124f5b9dca22e3cdb98dbdbdd741af6a74cc7a 100644
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
index 2306e51..39a36f6 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -62,11 +62,11 @@ IKI_DLLESPEC extern void execute_32(char*, char *);
IKI_DLLESPEC extern void execute_33(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_40(char*, char *);
-IKI_DLLESPEC extern void execute_41(char*, char *);
IKI_DLLESPEC extern void execute_42(char*, char *);
IKI_DLLESPEC extern void execute_43(char*, char *);
IKI_DLLESPEC extern void execute_44(char*, char *);
@@ -76,16 +76,19 @@ IKI_DLLESPEC extern void execute_47(char*, char *);
IKI_DLLESPEC extern void execute_48(char*, char *);
IKI_DLLESPEC extern void execute_49(char*, char *);
IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-funcp funcTab[24] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
-const int NumRelocateId= 24;
+funcp funcTab[27] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 27;
void relocate(char *dp)
{
- iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 24);
- iki_vhdl_file_variable_register(dp + 12632);
- iki_vhdl_file_variable_register(dp + 12688);
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 27);
+ iki_vhdl_file_variable_register(dp + 14376);
+ iki_vhdl_file_variable_register(dp + 14432);
/*Populate the transaction function pointer field in the whole net structure */
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.win64.obj b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.win64.obj
index 61e0b5b2725ca1d9831705a809ae010ce5a1a3b9..77d2a211d16e84e8c90bc3f4f0dbbe675d5159d7 100644
GIT binary patch
delta 303
zcmaDO-6+eO(#FmJ2J8$B4ikCh8K+Ftl^1-#z`&5h#K2I+3YKG#o*3)Q=reJlI^&;-
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Ytw>ESElG_xHDrJ@jSx)Z$p?6K0H=yO!vFvP
delta 186
zcmZpaeIw1A(#FmJ0*BZb7;Go<$}^Ts)Rh-Jz`($e!^FT4#R`&RV33#?>&&P#aiKcn
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Sc|ETVqv7O>yeX5z__P7-`YTcZ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
index 996eb5bcef13763a5511bea1d5c6a913b58524e2..977edfdc3b090cc560d422298ee6523588da95bd 100644
GIT binary patch
literal 14440
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
index adfe195c8edf1fc716d345a74120cfdb3008fb21..054fa97f5595f310eb1ad26354c696a980802fca 100644
GIT binary patch
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
index 4936ef8..baf8869 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -1,6 +1,6 @@
{
- crc : 4059207018839603124 ,
+ crc : 7733031991265798486 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
buildDate : "Nov 8 2024" ,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
index a02389c..686fcde 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -25,11 +25,11 @@ INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
-SCOPE_NAME_COLUMN_WIDTH=365
-SCOPE_DESIGN_UNIT_COLUMN_WIDTH=390
-SCOPE_BLOCK_TYPE_COLUMN_WIDTH=160
-OBJECT_NAME_COLUMN_WIDTH=417
-OBJECT_VALUE_COLUMN_WIDTH=4027
+SCOPE_NAME_COLUMN_WIDTH=220
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=160
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=304
+OBJECT_NAME_COLUMN_WIDTH=350
+OBJECT_VALUE_COLUMN_WIDTH=92
OBJECT_DATA_TYPE_COLUMN_WIDTH=140
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe
index 3778ae9c5cfd7da7e5d7413927e85fb94b035c5b..2320308396f9a5dc2e0354164bd94a40633a5047 100644
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
index 8be5a2e..2c09a02 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -1,4 +1,4 @@
-Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 63467
+Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51894
Design successfully loaded
-Design Loading Memory Usage: 28532 KB (Peak: 28532 KB)
-Design Loading CPU Usage: 452 ms
+Design Loading Memory Usage: 28580 KB (Peak: 28580 KB)
+Design Loading CPU Usage: 468 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
index 6270efc5023fbed30bda8aba793c4dca2eea1cef..138ffec8953ffa512b6bced01e5bcf795a5ca2b2 100644
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
index 301fc9cde4c58963d1245e7b18212a30db8d8b75..8a2a74eb0d641f71e7ce3f4bc3cf98d2fa275027 100644
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index 18f33e0..f84a889 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -2,7 +2,7 @@
2020.2
Nov 8 2024
22:36:57
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1741458025,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742333722,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1741454254,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1741455408,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
-C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1741459119,vhdl,,,,tb_firunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742334967,vhdl,C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1741730766,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
index e69de29..e9b0a65 100644
--- a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,8 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Conta/Documents/GitHub/IMT/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
index b155e40f06a230303a04d2a77f07560e35c5dc93..6da5d2db73ad6dd87651bc3b4576dfb18c38f281 100644
GIT binary patch
literal 1094
zcmd<u$;hSQn3tGSS(TZWt`O$o;-iq3nUkuZq*|<`keOGKuaJ|ORFqg$si0acz$(RT
zXlAU%T~VBwTb5dsnU<Ms6vh?eY^5JsoLW?@@0_1klBn;JpIn-onpaY+@19xWQJSRh
z=^LV7QlOifoUWT%Qks&Pm{+2kXk=25T9lfpUtE-|pOKQIpPZjpQk0()nwMFkSC)}t
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jPU7>44@n`x!^MTL1Z!aMadElkr6>fYCg&HW2rvQwP)AQI
literal 16
Xcmd<$<KlA7OHl|)P0lY$5nu!W9CHKI
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
index b1f04a7..c8c23be 100644
--- a/proj/AudioProc.xpr
+++ b/proj/AudioProc.xpr
@@ -60,7 +60,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="115"/>
+ <Option Name="WTXSimLaunchSim" Val="145"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -99,24 +99,16 @@
</File>
<File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../src/hdl/firUnit.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
- <FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
<File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@@ -170,9 +162,15 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="controlUnit"/>
+ <Option Name="TopModule" Val="firUnit"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -232,7 +230,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design">
@@ -244,6 +242,7 @@
<Option Id="ShregMinSize">5</Option>
</Step>
</Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
diff --git a/src-ref/ECG_raw_3filters-inc.pdf b/src-ref/ECG_raw_3filters-inc.pdf
index 355124ca47ee75d8f7d5002187e1919781adbbb8..6bf88846efa5db29fd21993721d3e1a1d19296e7 100644
GIT binary patch
delta 18
ZcmbO%F<D|l6T6|2fw_^P!N$%mZU8mU1)Kl?
delta 18
ZcmbO%F<D|l6T5+hp}B#9(Z<d$ZU8m^1)%@{
diff --git a/src-ref/ECG_raw_3filters.tex b/src-ref/ECG_raw_3filters.tex
index 2c2602a..35ac17b 100644
--- a/src-ref/ECG_raw_3filters.tex
+++ b/src-ref/ECG_raw_3filters.tex
@@ -7,7 +7,7 @@
% Title: Figure 2
% Creator: GL2PS 1.4.2, (C) 1999-2020 C. Geuzaine
% For: Octave
-% CreationDate: Sat Mar 8 18:00:29 2025
+% CreationDate: Wed Mar 12 08:21:09 2025
\setlength{\unitlength}{1pt}
\begin{picture}(0,0)
\includegraphics[scale=1]{ECG_raw_3filters-inc}
diff --git a/src-ref/coeficientes_vhdl.txt b/src-ref/coeficientes_vhdl.txt
index e1d30f9..fc89408 100644
--- a/src-ref/coeficientes_vhdl.txt
+++ b/src-ref/coeficientes_vhdl.txt
@@ -1,134 +1,134 @@
--- Coefficients du filtre Baseline ---
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(64, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(-1, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
-to_signed(0, 8),
+to_signed(0.0161398, 8),
+to_signed(0.015271, 8),
+to_signed(0.0144957, 8),
+to_signed(0.0137641, 8),
+to_signed(0.0130196, 8),
+to_signed(0.0121989, 8),
+to_signed(0.0112324, 8),
+to_signed(0.0100452, 8),
+to_signed(0.00855703, 8),
+to_signed(0.00668368, 8),
+to_signed(0.00433731, 8),
+to_signed(0.00142748, 8),
+to_signed(-0.00213802, 8),
+to_signed(-0.00645221, 8),
+to_signed(-0.011608, 8),
+to_signed(-0.017697, 8),
+to_signed(-0.0248089, 8),
+to_signed(-0.03303, 8),
+to_signed(-0.0424426, 8),
+to_signed(-0.0531235, 8),
+to_signed(-0.0651436, 8),
+to_signed(-0.0785665, 8),
+to_signed(-0.0934478, 8),
+to_signed(-0.109834, 8),
+to_signed(-0.127762, 8),
+to_signed(-0.147259, 8),
+to_signed(-0.16834, 8),
+to_signed(-0.191009, 8),
+to_signed(-0.215257, 8),
+to_signed(-0.241064, 8),
+to_signed(-0.268396, 8),
+to_signed(-0.297208, 8),
+to_signed(-0.327439, 8),
+to_signed(-0.359018, 8),
+to_signed(-0.391859, 8),
+to_signed(-0.425867, 8),
+to_signed(-0.460931, 8),
+to_signed(-0.496931, 8),
+to_signed(-0.533736, 8),
+to_signed(-0.571204, 8),
+to_signed(-0.609185, 8),
+to_signed(-0.64752, 8),
+to_signed(-0.686042, 8),
+to_signed(-0.72458, 8),
+to_signed(-0.762955, 8),
+to_signed(-0.800987, 8),
+to_signed(-0.838492, 8),
+to_signed(-0.875284, 8),
+to_signed(-0.91118, 8),
+to_signed(-0.945994, 8),
+to_signed(-0.979548, 8),
+to_signed(-1.01166, 8),
+to_signed(-1.04217, 8),
+to_signed(-1.0709, 8),
+to_signed(-1.09771, 8),
+to_signed(-1.12243, 8),
+to_signed(-1.14494, 8),
+to_signed(-1.16512, 8),
+to_signed(-1.18284, 8),
+to_signed(-1.19801, 8),
+to_signed(-1.21054, 8),
+to_signed(-1.22036, 8),
+to_signed(-1.22741, 8),
+to_signed(-1.23166, 8),
+to_signed(63.5859, 8),
+to_signed(-1.23166, 8),
+to_signed(-1.22741, 8),
+to_signed(-1.22036, 8),
+to_signed(-1.21054, 8),
+to_signed(-1.19801, 8),
+to_signed(-1.18284, 8),
+to_signed(-1.16512, 8),
+to_signed(-1.14494, 8),
+to_signed(-1.12243, 8),
+to_signed(-1.09771, 8),
+to_signed(-1.0709, 8),
+to_signed(-1.04217, 8),
+to_signed(-1.01166, 8),
+to_signed(-0.979548, 8),
+to_signed(-0.945994, 8),
+to_signed(-0.91118, 8),
+to_signed(-0.875284, 8),
+to_signed(-0.838492, 8),
+to_signed(-0.800987, 8),
+to_signed(-0.762955, 8),
+to_signed(-0.72458, 8),
+to_signed(-0.686042, 8),
+to_signed(-0.64752, 8),
+to_signed(-0.609185, 8),
+to_signed(-0.571204, 8),
+to_signed(-0.533736, 8),
+to_signed(-0.496931, 8),
+to_signed(-0.460931, 8),
+to_signed(-0.425867, 8),
+to_signed(-0.391859, 8),
+to_signed(-0.359018, 8),
+to_signed(-0.327439, 8),
+to_signed(-0.297208, 8),
+to_signed(-0.268396, 8),
+to_signed(-0.241064, 8),
+to_signed(-0.215257, 8),
+to_signed(-0.191009, 8),
+to_signed(-0.16834, 8),
+to_signed(-0.147259, 8),
+to_signed(-0.127762, 8),
+to_signed(-0.109834, 8),
+to_signed(-0.0934478, 8),
+to_signed(-0.0785665, 8),
+to_signed(-0.0651436, 8),
+to_signed(-0.0531235, 8),
+to_signed(-0.0424426, 8),
+to_signed(-0.03303, 8),
+to_signed(-0.0248089, 8),
+to_signed(-0.017697, 8),
+to_signed(-0.011608, 8),
+to_signed(-0.00645221, 8),
+to_signed(-0.00213802, 8),
+to_signed(0.00142748, 8),
+to_signed(0.00433731, 8),
+to_signed(0.00668368, 8),
+to_signed(0.00855703, 8),
+to_signed(0.0100452, 8),
+to_signed(0.0112324, 8),
+to_signed(0.0121989, 8),
+to_signed(0.0130196, 8),
+to_signed(0.0137641, 8),
+to_signed(0.0144957, 8),
+to_signed(0.015271, 8),
+to_signed(0.0161398, 8),
--- Coefficients du filtre Notch 50Hz ---
to_signed(0, 8),
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 0c18c92..19a3236 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -1,181 +1,135 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+-- filepath: c:\Users\Conta\Documents\GitHub\IMT\tp-ecg-etudiant-a24perei\src\hdl\controlUnit.vhd
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
-entity controlUnit is
- port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSampleValid : in std_logic;
- I_processingDone : in std_logic;
- O_loadShift : out std_logic;
- O_initAddress : out std_logic;
- O_incrAddress : out std_logic;
- O_initSum : out std_logic;
- O_loadSum : out std_logic;
- O_loadY : out std_logic;
- O_FilteredSampleValid : out std_logic;
- O_filterStage : out integer range 0 to 2 -- 🚀 Adicionado para indicar o estágio do filtro
- );
-end entity controlUnit;
+ENTITY controlUnit IS
+ PORT (
+ I_clock : IN STD_LOGIC;
+ I_reset : IN STD_LOGIC;
+ I_inputSampleValid : IN STD_LOGIC;
+ I_processingDoneA : IN STD_LOGIC;
+ I_processingDoneB : IN STD_LOGIC;
+ I_processingDoneBL : IN STD_LOGIC;
+ I_processingDoneClellan : IN STD_LOGIC;
+ O_loadShift : OUT STD_LOGIC;
+ O_initAddress : OUT STD_LOGIC;
+ O_incrAddress : OUT STD_LOGIC;
+ O_initSum : OUT STD_LOGIC;
+ O_loadSum : OUT STD_LOGIC;
+ O_loadOutA : OUT STD_LOGIC;
+ O_loadOutBL : OUT STD_LOGIC;
+ O_loadOutClellan : OUT STD_LOGIC;
+ O_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ O_FilteredSampleValid : OUT STD_LOGIC
+ );
+END ENTITY controlUnit;
-architecture archi_operativeUnit of controlUnit is
+ARCHITECTURE archi_operativeUnit OF controlUnit IS
+ TYPE T_state IS (WAIT_SAMPLE, STORE, BASELINE, PROCESS_A, PROCESS_B, CLELLAN, OUTPUT, WAIT_END_SAMPLE);
+ SIGNAL SR_presentState : T_state := WAIT_SAMPLE;
+ SIGNAL SR_futurState : T_state := WAIT_SAMPLE;
+BEGIN
- type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP, OUTPUT, WAIT_END_SAMPLE, NEXT_FILTER, FINAL_OUTPUT);
- signal SR_presentState : T_state;
- signal SR_futurState : T_state;
-
- -- Controle do estágio do filtro
- signal SR_filterStage : integer range 0 to 2 := 0;
+ -- State transition process
+ PROCESS (I_reset, I_clock)
+ BEGIN
+ IF I_reset = '1' THEN
+ SR_presentState <= WAIT_SAMPLE;
+ ELSIF rising_edge(I_clock) THEN
+ SR_presentState <= SR_futurState;
+ END IF;
+ END PROCESS;
-begin
+ -- Next state logic and output control
+ PROCESS (SR_presentState, I_inputSampleValid, I_processingDoneBL, I_processingDoneClellan, I_processingDoneA, I_processingDoneB)
+ BEGIN
+ -- Default values for outputs
+ O_sel <= "00";
+ O_initAddress <= '0';
+ O_initSum <= '0';
- -- Processo para calcular o estado futuro
- process (SR_presentState, I_inputSampleValid, I_processingDone) is
- begin
- case SR_presentState is
- when WAIT_SAMPLE =>
- if I_inputSampleValid = '1' then
- SR_futurState <= STORE;
- else
- SR_futurState <= WAIT_SAMPLE;
- end if;
-
- when STORE =>
- SR_futurState <= PROCESSING_LOOP;
-
- when PROCESSING_LOOP =>
- if I_processingDone = '1' then
- SR_futurState <= OUTPUT;
- else
- SR_futurState <= PROCESSING_LOOP;
- end if;
-
- when OUTPUT =>
- if SR_filterStage < 2 then
- SR_futurState <= NEXT_FILTER;
- else
- SR_futurState <= FINAL_OUTPUT; -- ✅ Após o último filtro, vai para FINAL_OUTPUT
- end if;
-
- when NEXT_FILTER =>
- SR_futurState <= STORE; -- ✅ Processa o próximo filtro e volta ao PROCESSING_LOOP
-
- when FINAL_OUTPUT =>
- SR_futurState <= WAIT_END_SAMPLE; -- ✅ Estado final antes de esperar um novo input
-
- when WAIT_END_SAMPLE =>
- if I_inputSampleValid = '1' then
- SR_futurState <= STORE; -- ✅ Só recomeça se um novo input chegar
- else
- SR_futurState <= WAIT_END_SAMPLE; -- ✅ Mantém a FSM parada se não houver novo input
- end if;
-
- when others =>
+ -- State machine
+ CASE SR_presentState IS
+ WHEN WAIT_SAMPLE =>
+ IF I_inputSampleValid = '1' THEN
+ SR_futurState <= STORE;
+ ELSE
SR_futurState <= WAIT_SAMPLE;
- end case;
- end process;
-
-
+ END IF;
- -- Processo para atualizar o estado presente e o estágio do filtro
- process (I_clock, I_reset) is
- begin
- if I_reset = '1' then
- SR_presentState <= WAIT_SAMPLE;
- SR_filterStage <= 0; -- Reinicia o controle dos filtros
- elsif rising_edge(I_clock) then
- SR_presentState <= SR_futurState;
-
- if SR_presentState = OUTPUT and I_processingDone = '1' then
- if SR_filterStage < 2 then
- SR_filterStage <= SR_filterStage + 1; -- 🚀 Avança para o próximo filtro
- end if;
- elsif SR_presentState = FINAL_OUTPUT then
- SR_filterStage <= 0; -- 🚀 Após os 3 filtros, reinicia para o primeiro
- end if;
-
- end if;
- end process;
+ WHEN STORE =>
+ O_initAddress <= '1';
+ O_sel <= "00";
+ O_initSum <= '1';
+ SR_futurState <= BASELINE;
- -- Processo para gerar os sinais de controle
- process (SR_presentState) is
- begin
- case SR_presentState is
- when WAIT_SAMPLE =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '0';
- O_FilteredSampleValid <= '0';
-
- when STORE =>
- O_loadShift <= '1';
- O_initAddress <= '1';
- O_incrAddress <= '0';
- O_initSum <= '1';
- O_loadSum <= '0';
- O_loadY <= '0';
- O_FilteredSampleValid <= '0';
-
- when PROCESSING_LOOP =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '1';
- O_initSum <= '0';
- O_loadSum <= '1';
- O_loadY <= '0';
- O_FilteredSampleValid <= '0';
-
- when OUTPUT =>
- O_loadShift <= '0';
- O_initAddress <= '1';
- O_incrAddress <= '0';
- O_initSum <= '1';
- O_loadSum <= '1';
- O_loadY <= '1';
- O_FilteredSampleValid <= '0';
-
- when NEXT_FILTER =>
- O_loadShift <= '0';
- O_initAddress <= '1';
- O_incrAddress <= '0';
- O_initSum <= '1';
- O_loadSum <= '0';
- O_loadY <= '0';
- O_FilteredSampleValid <= '0';
+ WHEN BASELINE =>
+ O_sel <= "00";
+ IF I_processingDoneBL = '1' THEN
+ SR_futurState <= PROCESS_B;
+ O_initAddress <= '1';
+ O_initSum <= '1';
+ ELSE
+ SR_futurState <= BASELINE;
+ END IF;
- when FINAL_OUTPUT =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '1';
- O_FilteredSampleValid <= '0';
+ WHEN PROCESS_B =>
+ O_sel <= "01";
+ IF I_processingDoneB = '1' THEN
+ SR_futurState <= PROCESS_A;
+ O_initAddress <= '1';
+ ELSE
+ SR_futurState <= PROCESS_B;
+ END IF;
- when WAIT_END_SAMPLE =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '0';
- O_FilteredSampleValid <= '1';
+ WHEN PROCESS_A =>
+ O_sel <= "10";
+ IF I_processingDoneA = '1' THEN
+ SR_futurState <= CLELLAN;
+ O_initAddress <= '1';
+ O_initSum <= '1';
+ ELSE
+ SR_futurState <= PROCESS_A;
+ END IF;
+
+ WHEN CLELLAN =>
+ O_sel <= "11";
+ IF I_processingDoneClellan = '1' THEN
+ SR_futurState <= OUTPUT;
+ ELSE
+ SR_futurState <= CLELLAN;
+ END IF;
+
+ WHEN OUTPUT =>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+ WHEN WAIT_END_SAMPLE =>
+ IF I_inputSampleValid = '0' THEN
+ SR_futurState <= WAIT_SAMPLE;
+ ELSE
+ SR_futurState <= WAIT_END_SAMPLE;
+ END IF;
- when others =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '0';
- O_FilteredSampleValid <= '0';
- end case;
- end process;
+ WHEN OTHERS =>
+ SR_futurState <= WAIT_SAMPLE;
+ END CASE;
+ END PROCESS;
- O_filterStage <= SR_filterStage;
+ -- Output logic
+ O_loadShift <= '1' WHEN SR_presentState = STORE ELSE
+ '0';
+ O_incrAddress <= '1' WHEN SR_presentState = BASELINE OR SR_presentState = PROCESS_A OR SR_presentState = PROCESS_B OR SR_presentState = CLELLAN ELSE
+ '0';
+ O_loadSum <= '1' WHEN SR_presentState = BASELINE OR SR_presentState = PROCESS_A OR SR_presentState = PROCESS_B OR SR_presentState = CLELLAN ELSE
+ '0';
+ O_loadOutBL <= '1' WHEN SR_presentState = BASELINE ELSE
+ '0';
+ O_loadOutA <= '1' WHEN SR_presentState = PROCESS_A ELSE
+ '0';
+ O_loadOutClellan <= '1' WHEN SR_presentState = OUTPUT ELSE
+ '0';
+ O_FilteredSampleValid <= '1' WHEN SR_presentState = OUTPUT ELSE
+ '0';
-end architecture archi_operativeUnit;
+END ARCHITECTURE archi_operativeUnit;
\ No newline at end of file
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 7758c51..7ac25d0 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -2,15 +2,21 @@
-- Title : firUnit
-- Project :
-------------------------------------------------------------------------------
--- File : firUnit.vhd
+-- File : operativeUnit.vhd
-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
-- Company :
-- Created : 2018-04-11
--- Last update: 2025-03-08 (modificado para suportar 3 filtros FIR)
+-- Last update: 2018-04-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--- Description: 8-bit FIR filter with multiple stages
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
-------------------------------------------------------------------------------
library ieee;
@@ -22,9 +28,9 @@ entity firUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8-bit input sample
+ I_inputSample : in std_logic_vector(11 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
+ O_filteredSample : out std_logic_vector(11 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic
);
@@ -34,67 +40,83 @@ architecture archi_firUnit of firUnit is
component controlUnit is
port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSampleValid : in std_logic;
- I_processingDone : in std_logic;
- O_loadShift : out std_logic;
- O_initAddress : out std_logic;
- O_incrAddress : out std_logic;
- O_initSum : out std_logic;
- O_loadSum : out std_logic;
- O_loadY : out std_logic;
- O_FilteredSampleValid : out std_logic;
- O_filterStage : out integer range 0 to 2 -- 🚀 Adicionado para indicar o estágio do filtro
- );
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_processingDoneA : in std_logic;
+ I_processingDoneB : in std_logic;
+ I_processingDoneBL: in std_logic;
+ I_processingDoneClellan : in std_logic;
+ O_loadShift : out std_logic; -- filtered sample
+ O_initAddress : out std_logic; -- Control signal to initialize register read address
+ O_incrAddress : out std_logic; -- Control signal to increment register read address
+ O_initSum : out std_logic; -- Control signal to initialize the MAC register
+ O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadOutA : out std_logic; -- Control signal to load Y register
+ O_loadOutBL : out std_logic;
+ O_loadOutClellan : out std_logic;
+ O_sel : out std_logic_vector(1 downto 0);
+ O_FilteredSampleValid : out std_logic );
end component controlUnit;
component operativeUnit is
port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
- I_loadShift : in std_logic;
- I_initAddress : in std_logic;
- I_incrAddress : in std_logic;
- I_initSum : in std_logic;
- I_loadSum : in std_logic;
- I_loadY : in std_logic;
- I_filterStage : in integer range 0 to 2; -- 🚀 Adicionado para controlar qual filtro está ativo
- O_processingDone : out std_logic;
- O_Y : out std_logic_vector(7 downto 0)
- );
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(11 downto 0); -- 8 bit input sample
+ I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_initAddress : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress : in std_logic; -- Control signal to increment register read address
+ I_sel : in std_logic_vector(1 downto 0); -- Control signal to control the type of process
+ I_initSum : in std_logic; -- Control signal to initialize the MAC register
+ I_loadSum : in std_logic; -- Control signal to load the MAC register;
+ I_loadOutA : in std_logic; -- Control signal to load Y register coefficients A
+ I_loadOutBL : in std_logic;
+ I_loadOutClellan : in std_logic;
+ O_processingDoneA : out std_logic; -- Indicate that processing is done
+ O_processingDoneB : out std_logic; -- Indicate that processing is done
+ O_processingDoneBL: out std_logic;
+ O_processingDoneClellan : out std_logic;
+ O_total : out std_logic_vector(11 downto 0));
+
end component operativeUnit;
- signal SC_processingDone : std_logic;
+ signal SC_processingDoneA : std_logic;
+ signal SC_processingDoneB : std_logic;
+ signal SC_processingDoneBaseLine: std_logic;
+ signal SC_processingDoneLissage : std_logic;
signal SC_loadShift : std_logic;
signal SC_initAddress : std_logic;
signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic;
signal SC_loadSum : std_logic;
- signal SC_loadY : std_logic;
- signal SC_filterStage : integer range 0 to 2; -- 🚀 Novo sinal para armazenar o estágio do filtro
-
+ signal SC_loadOutA : std_logic;
+ signal SC_loadOutBaseLine: std_logic;
+ signal SC_loadOutLissage : std_logic;
+ signal SC_sel : std_logic_vector(1 downto 0);
+
begin
- -- Instância da unidade de controle
controlUnit_1 : entity work.controlUnit
port map (
I_clock => I_clock,
I_reset => I_reset,
I_inputSampleValid => I_inputSampleValid,
- I_processingDone => SC_processingDone,
+ I_processingDoneA => SC_processingDoneA,
+ I_processingDoneB => SC_processingDoneB,
+ I_processingDoneBL => SC_processingDoneBaseLine,
+ I_processingDoneClellan => SC_processingDoneLissage,
O_loadShift => SC_loadShift,
O_initAddress => SC_initAddress,
O_incrAddress => SC_incrAddress,
O_initSum => SC_initSum,
O_loadSum => SC_loadSum,
- O_loadY => SC_loadY,
- O_FilteredSampleValid => O_filteredSampleValid,
- O_filterStage => SC_filterStage -- 🚀 Agora a unidade de controle define o estágio do filtro
- );
+ O_loadOutA => SC_loadOutA,
+ O_loadOutBL => SC_loadOutBaseLine,
+ O_loadOutClellan => SC_loadOutLissage,
+ O_sel => SC_sel,
+ O_FilteredSampleValid => O_FilteredSampleValid);
- -- Instância da unidade operativa
operativeUnit_1 : entity work.operativeUnit
port map (
I_clock => I_clock,
@@ -103,12 +125,16 @@ begin
I_loadShift => SC_loadShift,
I_initAddress => SC_initAddress,
I_incrAddress => SC_incrAddress,
+ I_sel => SC_sel,
I_initSum => SC_initSum,
I_loadSum => SC_loadSum,
- I_loadY => SC_loadY,
- I_filterStage => SC_filterStage, -- 🚀 Agora a unidade operativa recebe o estágio do filtro
- O_processingDone => SC_processingDone,
- O_Y => O_filteredSample
- );
+ I_loadOutA => SC_loadOutA,
+ I_loadOutBL => SC_loadOutBaseLine,
+ I_loadOutClellan => SC_loadOutLissage,
+ O_processingDoneA => SC_processingDoneA,
+ O_processingDoneB => SC_processingDoneB,
+ O_processingDoneBL => SC_processingDoneBaseLine,
+ O_processingDoneClellan => SC_processingDoneLissage,
+ O_total => O_filteredSample );
end architecture archi_firUnit;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index ab13e7a..4314419 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -1,404 +1,375 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity operativeUnit is
- port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
- I_loadShift : in std_logic;
- I_initAddress : in std_logic;
- I_incrAddress : in std_logic;
- I_initSum : in std_logic;
- I_loadSum : in std_logic;
- I_loadY : in std_logic;
- I_filterStage : in integer range 0 to 2; -- Novo: indica qual filtro está sendo aplicado
- O_processingDone : out std_logic;
- O_Y : out std_logic_vector(7 downto 0)
- );
-end entity operativeUnit;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
-architecture arch_operativeUnit of operativeUnit is
- -- Tamanho correto de cada filtro
- type coefBaselineArray is array(0 to 128) of signed(7 downto 0);
- type coefNotch50HzArray is array(0 to 100) of signed(7 downto 0);
- type coefLowPassArray is array(0 to 10) of signed(7 downto 0);
-
- -- Registradores de coeficientes
- signal SR_coefBaseline : coefBaselineArray;
- signal SR_coefNotch50Hz : coefNotch50HzArray;
- signal SR_coefLowPass : coefLowPassArray;
-
- -- Shift register para armazenar amostras
- type shiftRegisterArray is array(0 to 128) of signed(7 downto 0);
- signal SR_shiftRegister : shiftRegisterArray;
-
- signal SC_multOperand1 : signed(7 downto 0);
- signal SC_multOperand2 : signed(7 downto 0);
- signal SC_MultResult : signed(15 downto 0);
- signal SC_addResult : signed(19 downto 0);
- signal SR_sum : signed(19 downto 0);
- signal SR_Y : signed(7 downto 0);
-
- -- Contador de leitura para cada filtro
- signal SR_readAddress : integer range 0 to 128;
-
- -- Limite do contador baseado no filtro atual
- signal SC_maxAddress : integer range 0 to 128;
-
-begin
-
- -- *** Defina os coeficientes de cada filtro aqui ***
- -- Baseline Wander Filter (129 coeficientes)
- SR_coefBaseline <= (
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(64, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8)
- );
-
- -- Notch 50Hz Filter (101 coeficientes)
- SR_coefNotch50Hz <= (
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(-1, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(1, 8),
- to_signed(1, 8),
- to_signed(1, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(0, 8),
- to_signed(1, 8),
- to_signed(1, 8),
- to_signed(2, 8),
- to_signed(2, 8),
- to_signed(1, 8),
- to_signed(-1, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-1, 8),
- to_signed(1, 8),
- to_signed(2, 8),
- to_signed(3, 8),
- to_signed(2, 8),
- to_signed(1, 8),
- to_signed(-1, 8),
- to_signed(-2, 8),
- to_signed(63, 8),
- to_signed(-2, 8),
- to_signed(-1, 8),
- to_signed(1, 8),
- to_signed(2, 8),
- to_signed(3, 8),
- to_signed(2, 8),
- to_signed(1, 8),
- to_signed(-1, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-2, 8),
- to_signed(-1, 8),
- to_signed(1, 8),
- to_signed(2, 8),
- to_signed(2, 8),
- to_signed(1, 8),
- to_signed(1, 8),
- to_signed(0, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(-1, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(1, 8),
- to_signed(1, 8),
- to_signed(1, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(-1, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8),
- to_signed(0, 8)
+ENTITY operativeUnit IS
+
+ PORT (
+ I_clock : IN STD_LOGIC;
+ I_reset : IN STD_LOGIC;
+ I_inputSample : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ I_loadShift : IN STD_LOGIC;
+ I_initAddress : IN STD_LOGIC;
+ I_incrAddress : IN STD_LOGIC;
+ I_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ I_initSum : IN STD_LOGIC;
+ I_loadSum : IN STD_LOGIC;
+ I_loadOutA : IN STD_LOGIC;
+ I_loadOutBL : IN STD_LOGIC;
+ I_loadOutClellan : IN STD_LOGIC;
+ O_processingDoneA : OUT STD_LOGIC;
+ O_processingDoneB : OUT STD_LOGIC;
+ O_processingDoneBL : OUT STD_LOGIC;
+ O_processingDoneClellan : OUT STD_LOGIC;
+ O_total : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
- -- Low-Pass Filter (Parks-McClellan) (11 coeficientes)
- SR_coefLowPass <= (
- to_signed(-13, 8),
- to_signed(13, 8),
- to_signed(16, 8),
- to_signed(21, 8),
- to_signed(25, 8),
- to_signed(26, 8),
- to_signed(25, 8),
- to_signed(21, 8),
- to_signed(16, 8),
- to_signed(13, 8),
- to_signed(-13, 8)
- );
-
- -- Definição do número de coeficientes para cada filtro
- process (I_filterStage)
- begin
- case I_filterStage is
- when 0 => SC_maxAddress <= 128; -- Baseline (129 coeficientes)
- when 1 => SC_maxAddress <= 100; -- Notch 50Hz (101 coeficientes)
- when 2 => SC_maxAddress <= 10; -- Parks-McClellan (11 coeficientes)
- when others => SC_maxAddress <= 128;
- end case;
- end process;
-
- -- Shift Register para armazenar amostras de entrada
- shift : process (I_reset, I_clock)
- begin
- if I_reset = '1' then
- SR_shiftRegister <= (others => (others => '0'));
- elsif rising_edge(I_clock) then
- if I_loadShift = '1' then
- -- Shift das amostras
- for i in SC_maxAddress downto 1 loop
- SR_shiftRegister(i) <= SR_shiftRegister(i-1);
- end loop;
- SR_shiftRegister(0) <= signed(I_inputSample);
- end if;
- end if;
- end process shift;
-
- -- Incremento do endereço de leitura para os coeficientes
- incr_address : process (I_reset, I_clock)
- begin
- if I_reset = '1' then
- SR_readAddress <= 0;
- elsif rising_edge(I_clock) then
- if I_initAddress = '1' then
+END ENTITY operativeUnit;
+
+ARCHITECTURE arch_operativeUnit OF operativeUnit IS
+ TYPE registerFileA IS ARRAY(0 TO 1) OF signed(11 DOWNTO 0);
+ SIGNAL SR_coefRegisterA : registerFileA;
+ SIGNAL SR_2A : registerFileA;
+
+ TYPE registerFileB IS ARRAY(0 TO 2) OF signed(11 DOWNTO 0);
+ SIGNAL SR_coefRegisterB : registerFileB;
+ SIGNAL SR_2 : registerFileB;
+
+ TYPE registerFileBL IS ARRAY(0 TO 94) OF signed(11 DOWNTO 0);
+ SIGNAL SR_coefRegisterBL : registerFileBL;
+ SIGNAL SR_1 : registerFileBL;
+
+ TYPE registerFileClellan IS ARRAY(0 TO 10) OF signed(11 DOWNTO 0);
+ SIGNAL SR_coefRegisterClellan : registerFileClellan;
+ SIGNAL SR_3 : registerFileClellan;
+
+ SIGNAL SC_multOperand1 : signed(11 DOWNTO 0);
+ SIGNAL SC_multOperand2 : signed(11 DOWNTO 0);
+ SIGNAL SC_MultResult : signed(23 DOWNTO 0);
+ SIGNAL SC_addResult : signed(30 DOWNTO 0);
+ SIGNAL SR_sum : signed(30 DOWNTO 0);
+ SIGNAL SR_Y : signed(11 DOWNTO 0);
+ SIGNAL SR_readAddress : INTEGER RANGE 0 TO 94;
+
+BEGIN
+ SR_coefRegisterA <= (to_signed(1554, 12),
+ to_signed(-897, 12)
+ );
+
+ SR_coefRegisterB <= (to_signed(961, 12),
+ to_signed(-1554, 12),
+ to_signed(961, 12)
+ );
+
+ SR_coefRegisterBL <= (to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-2, 12),
+ to_signed(-2, 12),
+ to_signed(-2, 12),
+ to_signed(-3, 12),
+ to_signed(-3, 12),
+ to_signed(-3, 12),
+ to_signed(-4, 12),
+ to_signed(-4, 12),
+ to_signed(-5, 12),
+ to_signed(-5, 12),
+ to_signed(-6, 12),
+ to_signed(-6, 12),
+ to_signed(-7, 12),
+ to_signed(-7, 12),
+ to_signed(-8, 12),
+ to_signed(-8, 12),
+ to_signed(-9, 12),
+ to_signed(-10, 12),
+ to_signed(-10, 12),
+ to_signed(-11, 12),
+ to_signed(-11, 12),
+ to_signed(-12, 12),
+ to_signed(-13, 12),
+ to_signed(-13, 12),
+ to_signed(-14, 12),
+ to_signed(-14, 12),
+ to_signed(-15, 12),
+ to_signed(-15, 12),
+ to_signed(-16, 12),
+ to_signed(-16, 12),
+ to_signed(-17, 12),
+ to_signed(-17, 12),
+ to_signed(-18, 12),
+ to_signed(-18, 12),
+ to_signed(-18, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(1004, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-19, 12),
+ to_signed(-18, 12),
+ to_signed(-18, 12),
+ to_signed(-18, 12),
+ to_signed(-17, 12),
+ to_signed(-17, 12),
+ to_signed(-16, 12),
+ to_signed(-16, 12),
+ to_signed(-15, 12),
+ to_signed(-15, 12),
+ to_signed(-14, 12),
+ to_signed(-14, 12),
+ to_signed(-13, 12),
+ to_signed(-13, 12),
+ to_signed(-12, 12),
+ to_signed(-11, 12),
+ to_signed(-11, 12),
+ to_signed(-10, 12),
+ to_signed(-10, 12),
+ to_signed(-9, 12),
+ to_signed(-8, 12),
+ to_signed(-8, 12),
+ to_signed(-7, 12),
+ to_signed(-7, 12),
+ to_signed(-6, 12),
+ to_signed(-6, 12),
+ to_signed(-5, 12),
+ to_signed(-5, 12),
+ to_signed(-4, 12),
+ to_signed(-4, 12),
+ to_signed(-3, 12),
+ to_signed(-3, 12),
+ to_signed(-3, 12),
+ to_signed(-2, 12),
+ to_signed(-2, 12),
+ to_signed(-2, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12),
+ to_signed(-1, 12)
+ );
+
+ SR_coefRegisterClellan <= (to_signed(-119, 12),
+ to_signed(122, 12),
+ to_signed(149, 12),
+ to_signed(191, 12),
+ to_signed(226, 12),
+ to_signed(239, 12),
+ to_signed(226, 12),
+ to_signed(191, 12),
+ to_signed(149, 12),
+ to_signed(122, 12),
+ to_signed(-119, 12)
+ );
+
+ shift : PROCESS (I_reset, I_clock) IS
+ BEGIN
+ IF I_reset = '1' THEN
+ SR_1 <= (OTHERS => (OTHERS => '0'));
+
+ ELSIF rising_edge(I_clock) THEN
+ IF I_loadShift = '1' THEN
+ IF I_sel = "00" THEN
+ SR_1(1 TO 94) <= SR_1(0 TO 93);
+ SR_1(0) <= signed(I_inputSample);
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS shift;
+
+ incr_address : PROCESS (I_reset, I_clock) IS
+ BEGIN
+ IF I_reset = '1' THEN
SR_readAddress <= 0;
- elsif I_incrAddress = '1' then
- if SR_readAddress < SC_maxAddress then
- SR_readAddress <= SR_readAddress + 1;
- end if;
- end if;
- end if;
- end process incr_address;
-
- -- Indicação de processamento concluÃdo
- O_processingDone <= '1' when SR_readAddress >= SC_maxAddress else '0';
-
- -- Multiplicação e acumulação
- process (I_filterStage, SR_readAddress)
- begin
- case I_filterStage is
- when 0 =>
- SC_multOperand1 <= SR_coefBaseline(SR_readAddress);
- when 1 =>
- SC_multOperand1 <= SR_coefNotch50Hz(SR_readAddress);
- when 2 =>
- SC_multOperand1 <= SR_coefLowPass(SR_readAddress);
- when others =>
- SC_multOperand1 <= (others => '0');
- end case;
- end process;
-
- SC_multOperand2 <= SR_shiftRegister(SR_readAddress);
- SC_MultResult <= SC_multOperand1 * SC_multOperand2;
- SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
-
- -- Acumulador de soma (MAC)
- sum_acc : process (I_reset, I_clock)
- begin
- if I_reset = '1' then
- SR_sum <= (others => '0');
- elsif rising_edge(I_clock) then
- if I_initSum = '1' then
- SR_sum <= (others => '0');
- elsif I_loadSum = '1' then
+
+ ELSIF rising_edge(I_clock) THEN
+ IF I_sel = "00" THEN
+ IF I_initAddress = '1' THEN
+ SR_readAddress <= 0;
+ ELSIF I_incrAddress = '1' THEN
+ IF SR_readAddress = 94 THEN
+ SR_readAddress <= 0;
+ ELSE
+ SR_readAddress <= SR_readAddress + 1;
+ END IF;
+ END IF;
+
+ -- Process B
+ ELSIF I_sel = "01" THEN
+ IF I_initAddress = '1' THEN
+ SR_readAddress <= 0;
+ ELSIF I_incrAddress = '1' THEN
+ IF SR_readAddress = 2 THEN
+ SR_readAddress <= 0;
+ ELSE
+ SR_readAddress <= SR_readAddress + 1;
+ END IF;
+ END IF;
+
+ -- Process A
+ ELSIF I_sel = "10" THEN
+ IF I_initAddress = '1' THEN
+ SR_readAddress <= 0;
+ ELSIF I_incrAddress = '1' THEN
+ IF SR_readAddress = 1 THEN
+ SR_readAddress <= 0;
+ ELSE
+ SR_readAddress <= SR_readAddress + 1;
+ END IF;
+ END IF;
+
+ -- Process Clellan
+ ELSIF I_sel = "11" THEN
+ IF I_initAddress = '1' THEN
+ SR_readAddress <= 0;
+ ELSIF I_incrAddress = '1' THEN
+ IF SR_readAddress = 10 THEN
+ SR_readAddress <= 0;
+ ELSE
+ SR_readAddress <= SR_readAddress + 1;
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+
+ END PROCESS incr_address;
+
+ mux_operands : PROCESS (SR_readAddress, I_sel, SR_1, SR_coefRegisterBL,
+ SR_3, SR_coefRegisterClellan, SR_2,
+ SR_coefRegisterB, SR_2A, SR_coefRegisterA) IS
+ BEGIN
+ IF I_sel = "00" THEN
+ SC_multOperand1 <= SR_1(SR_readAddress);
+ SC_multOperand2 <= SR_coefRegisterBL(SR_readAddress);
+
+ IF SR_readAddress = 94 THEN
+ O_processingDoneBL <= '1';
+ O_processingDoneA <= '0';
+ O_processingDoneB <= '0';
+ O_processingDoneClellan <= '0';
+ ELSE
+ O_processingDoneA <= '0';
+ O_processingDoneB <= '0';
+ O_processingDoneBL <= '0';
+ O_processingDoneClellan <= '0';
+ END IF;
+
+ ELSIF I_sel = "01" THEN
+ SC_multOperand1 <= SR_2(SR_readAddress);
+ SC_multOperand2 <= SR_coefRegisterB(SR_readAddress);
+
+ IF SR_readAddress = 2 THEN
+ O_processingDoneB <= '1';
+ O_processingDoneA <= '0';
+ O_processingDoneBL <= '0';
+ O_processingDoneClellan <= '0';
+ ELSE
+ O_processingDoneA <= '0';
+ O_processingDoneB <= '0';
+ O_processingDoneBL <= '0';
+ O_processingDoneClellan <= '0';
+ END IF;
+
+ ELSIF I_sel = "10" THEN
+ SC_multOperand1 <= SR_2A(SR_readAddress);
+ SC_multOperand2 <= SR_coefRegisterA(SR_readAddress);
+
+ IF SR_readAddress = 0 THEN
+ O_processingDoneA <= '1';
+ O_processingDoneB <= '0';
+ O_processingDoneBL <= '0';
+ O_processingDoneClellan <= '0';
+ ELSE
+ O_processingDoneA <= '0';
+ O_processingDoneB <= '0';
+ O_processingDoneBL <= '0';
+ O_processingDoneClellan <= '0';
+ END IF;
+
+ ELSIF I_sel = "11" THEN
+ SC_multOperand1 <= SR_3(SR_readAddress);
+ SC_multOperand2 <= SR_coefRegisterClellan(SR_readAddress);
+
+ IF SR_readAddress = 10 THEN
+ O_processingDoneClellan <= '1';
+ O_processingDoneB <= '0';
+ O_processingDoneA <= '0';
+ O_processingDoneBL <= '0';
+ ELSE
+ O_processingDoneA <= '0';
+ O_processingDoneB <= '0';
+ O_processingDoneBL <= '0';
+ O_processingDoneClellan <= '0';
+ END IF;
+ END IF;
+ END PROCESS mux_operands;
+
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2;
+ SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+
+ sum_acc : PROCESS (I_reset, I_clock) IS
+ BEGIN
+ IF I_reset = '1' THEN
+ SR_sum <= (OTHERS => '0');
+
+ ELSIF rising_edge(I_clock) THEN
+ IF I_initSum = '1' THEN
+ SR_sum <= (OTHERS => '0');
+ ELSIF I_loadSum = '1' THEN
SR_sum <= SC_addResult;
- end if;
- end if;
- end process sum_acc;
-
- -- Armazenamento do resultado final
- store_result : process (I_reset, I_clock)
- begin
- if I_reset = '1' then
- SR_Y <= (others => '0');
- elsif rising_edge(I_clock) then
- if I_loadY = '1' then
- if SC_addResult(6) = '1' then
- SR_Y <= SC_addResult(14 downto 7) + 1;
- else
- SR_Y <= SC_addResult(14 downto 7);
- end if;
- end if;
- end if;
- end process store_result;
-
- -- SaÃda final do filtro
- O_Y <= std_logic_vector(SR_Y);
-
-end architecture arch_operativeUnit;
+ END IF;
+
+ END IF;
+ END PROCESS sum_acc;
+
+ store_result : PROCESS (I_reset, I_clock) IS
+ BEGIN
+ IF I_reset = '1' THEN
+ SR_Y <= (OTHERS => '0');
+ SR_2A <= (OTHERS => (OTHERS => '0'));
+ SR_2 <= (OTHERS => (OTHERS => '0'));
+ SR_3 <= (OTHERS => (OTHERS => '0'));
+
+ ELSIF rising_edge(I_clock) THEN
+ IF I_loadOutBL = '1' THEN
+ IF SC_addResult(9) = '1' THEN
+ SR_2(1 TO 2) <= SR_2(0 TO 1);
+ SR_2(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ ELSE
+ SR_2(1 TO 2) <= SR_2(0 TO 1);
+ SR_2(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ END IF;
+
+ ELSIF I_loadOutA = '1' THEN
+ IF SC_addResult(9) = '1' THEN
+ SR_3(1 TO 10) <= SR_3(0 TO 9);
+ SR_3(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ SR_2A(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ ELSE
+ SR_3(1 TO 10) <= SR_3(0 TO 9);
+ SR_3(0) <= signed(SC_addResult(21 DOWNTO 10));
+ SR_2A(0) <= signed(SC_addResult(21 DOWNTO 10));
+ END IF;
+ SR_2A(1) <= SR_2A(0);
+ ELSIF I_loadOutClellan = '1' THEN
+ IF SC_addResult(9) = '1' THEN
+ SR_Y <= SC_addResult(21 DOWNTO 10) + 1;
+ ELSE
+ SR_Y <= SC_addResult(21 DOWNTO 10);
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS store_result;
+
+ O_total <= STD_LOGIC_VECTOR(SR_Y);
+
+END ARCHITECTURE arch_operativeUnit;
\ No newline at end of file
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index cea8698..6d885f7 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -33,17 +33,17 @@ architecture archi_tb_firUnit of tb_firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSample : in std_logic_vector(11 downto 0);
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0);
+ O_filteredSample : out std_logic_vector(11 downto 0);
O_filteredSampleValid : out std_logic);
end component firUnit;
signal SC_clock : std_logic := '0';
signal SC_reset : std_logic;
- signal SC_inputSample : std_logic_vector(7 downto 0);
+ signal SC_inputSample : std_logic_vector(11 downto 0);
signal SC_inputSampleValid : std_logic:='0';
- signal SC_filteredSample : std_logic_vector(7 downto 0);
+ signal SC_filteredSample : std_logic_vector(11 downto 0);
signal SC_filteredSampleValid : std_logic;
begin
@@ -52,41 +52,21 @@ begin
SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
-- Sample period = 20 clk period
- SC_inputSampleValid <= '0',
- '1' after 401 ns,
- '0' after 501 ns,
- '1' after 3601 ns,
- '0' after 3701 ns,
- '1' after 6201 ns,
- '0' after 6301 ns,
- '1' after 9401 ns,
- '0' after 9501 ns,
- '1' after 12601 ns,
- '0' after 12701 ns,
- '1' after 15801 ns,
- '0' after 15901 ns,
- '1' after 18001 ns,
- '0' after 18101 ns,
- '1' after 21201 ns,
- '0' after 21301 ns,
- '1' after 24401 ns,
- '0' after 24501 ns,
- '1' after 27601 ns,
- '0' after 27701 ns;
+ SC_inputSampleValid <= not SC_inputSampleValid after 1000 ns;
-- Null signal followed by a Dirac and then an arbitrary sequence
- SC_inputSample <= "00000000",
- "01111111" after 401 ns,
- "00000000" after 3601 ns,
- "00100100" after 6201 ns,
- "01100100" after 9401 ns,
- "10100010" after 12601 ns,
- "11011011" after 15801 ns,
- "00001011" after 18001 ns,
- "10000000" after 21201 ns,
- "01111111" after 24401 ns,
- "10111010" after 27601 ns;
-
+ SC_inputSample <= "000000000000",
+ "001111111111" after 3001 ns,
+ "000000000000" after 5001 ns,
+ "000000100100" after 7001 ns,
+ "000001100100" after 9001 ns,
+ "000010100010" after 11001 ns,
+ "000011011011" after 13001 ns,
+ "000000001011" after 14001 ns,
+ "000010000000" after 15001 ns,
+ "000011111111" after 16001 ns,
+ "000010111010" after 18001 ns;
+
-- the filter output on 8 bits is a sequence of signed numbers (with the assumption
-- of rounding the output, so the accuracy can be slightly different depending
--
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