From c750b1cb0faf7fd26d7ce7f4244745b9b4f5df5e Mon Sep 17 00:00:00 2001
From: Antonio PEREIRA <a24perei@fl-tp-br-637.imta.fr>
Date: Wed, 19 Mar 2025 12:14:40 +0100
Subject: [PATCH] feat
---
proj/project_1/project_1.cache/sim/ssm.db | 11 +
proj/project_1/project_1.cache/wt/project.wpc | 2 +-
proj/project_1/project_1.cache/wt/xsim.wdf | 4 +-
.../sim_1/behav/xsim/compile.log | 0
.../project_1.sim/sim_1/behav/xsim/compile.sh | 2 +-
.../sim_1/behav/xsim/elaborate.log | 6 +-
.../sim_1/behav/xsim/elaborate.sh | 2 +-
.../sim_1/behav/xsim/simulate.sh | 6 +-
.../sim_1/behav/xsim/tb_firUnit_behav.wdb | Bin 61927 -> 39488 bytes
.../sim_1/behav/xsim/tb_firUnit_vhdl.prj | 8 +-
.../project_1.sim/sim_1/behav/xsim/xelab.pb | Bin 847 -> 853 bytes
.../tb_firUnit_behav/Compile_Options.txt | 1 +
.../tb_firUnit_behav/TempBreakPointFile.txt | 1 +
.../tb_firUnit_behav/obj/xsim_0.lnx64.o | Bin 0 -> 31576 bytes
.../xsim.dir/tb_firUnit_behav/obj/xsim_1.c | 133 +
.../tb_firUnit_behav/obj/xsim_1.lnx64.o | Bin 0 -> 5776 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.dbg | Bin 0 -> 14480 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.mem | Bin 0 -> 4315 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.reloc | Bin 0 -> 1537 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rlx | 12 +
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rtti | Bin 0 -> 878 bytes
.../xsim.dir/tb_firUnit_behav/xsim.svtype | Bin 0 -> 16 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.type | Bin 0 -> 7344 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg | Bin 0 -> 91568 bytes
.../tb_firUnit_behav/xsimSettings.ini | 50 +
.../xsim.dir/tb_firUnit_behav/xsimcrash.log | 0
.../xsim/xsim.dir/tb_firUnit_behav/xsimk | Bin 0 -> 36160 bytes
.../xsim.dir/tb_firUnit_behav/xsimkernel.log | 4 +
.../xsim.dir/xil_defaultlib/controlunit.vdb | Bin 0 -> 14308 bytes
.../xsim/xsim.dir/xil_defaultlib/firunit.vdb | Bin 0 -> 15002 bytes
.../xsim.dir/xil_defaultlib/operativeunit.vdb | Bin 0 -> 47885 bytes
.../xsim.dir/xil_defaultlib/tb_firunit.vdb | Bin 0 -> 7508 bytes
.../xil_defaultlib/xil_defaultlib.rlx | 8 +
.../project_1.sim/sim_1/behav/xsim/xsim.ini | 905 +-
.../sim_1/behav/xsim/xsim.ini.bak | 905 +-
proj/project_1/project_1.xpr | 8 +-
proj/project_1/tb_firUnit_behav.wcfg | 214 +
src-ref/.nfs000000000231cfd700000038 | 11 +
src-ref/.~lock.ADCSamplesOctave.csv# | 1 +
src-ref/ADCSamplesOctave.csv | 9973 +----------------
src-ref/octaveScript.m | 67 +-
src-ref/output.txt | 155 +
src/hdl/controlUnit.vhd | 7 +
src/hdl/operativeUnit.vhd | 7 +-
44 files changed, 1595 insertions(+), 10908 deletions(-)
create mode 100644 proj/project_1/project_1.cache/sim/ssm.db
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/compile.log
mode change 100644 => 100755 proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
mode change 100644 => 100755 proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
mode change 100644 => 100755 proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
create mode 100755 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
create mode 100644 proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
create mode 100644 proj/project_1/tb_firUnit_behav.wcfg
create mode 100644 src-ref/.nfs000000000231cfd700000038
create mode 100644 src-ref/.~lock.ADCSamplesOctave.csv#
create mode 100644 src-ref/output.txt
diff --git a/proj/project_1/project_1.cache/sim/ssm.db b/proj/project_1/project_1.cache/sim/ssm.db
new file mode 100644
index 0000000..b6b91d1
--- /dev/null
+++ b/proj/project_1/project_1.cache/sim/ssm.db
@@ -0,0 +1,11 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 19 10:36:40 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,
diff --git a/proj/project_1/project_1.cache/wt/project.wpc b/proj/project_1/project_1.cache/wt/project.wpc
index 0161c5d..2599f42 100644
--- a/proj/project_1/project_1.cache/wt/project.wpc
+++ b/proj/project_1/project_1.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:6
+6d6f64655f636f756e7465727c4755494d6f6465:7
eof:
diff --git a/proj/project_1/project_1.cache/wt/xsim.wdf b/proj/project_1/project_1.cache/wt/xsim.wdf
index 51d5206..50afb2c 100644
--- a/proj/project_1/project_1.cache/wt/xsim.wdf
+++ b/proj/project_1/project_1.cache/wt/xsim.wdf
@@ -1,4 +1,4 @@
version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:2427094519
+eof:241934075
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000..e69de29
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
old mode 100644
new mode 100755
index e918a0d..2132d71
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
-# Generated by Vivado on Wed Feb 26 12:08:10 CET 2025
+# Generated by Vivado on Wed Mar 19 12:10:31 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
index db78a7c..b369c9e 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log
@@ -1,8 +1,8 @@
-Vivado Simulator v2024.2.0
+Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-Running: C:/Xilinx/Vivado/2024.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
-Using 2 slave threads.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+Using 8 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
old mode 100644
new mode 100755
index b001623..2ed28f0
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
-# Generated by Vivado on Wed Feb 26 12:08:12 CET 2025
+# Generated by Vivado on Wed Mar 19 12:10:33 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
old mode 100644
new mode 100755
index 9cda091..ff133aa
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
-# Generated by Vivado on Wed Feb 26 12:07:21 CET 2025
+# Generated by Vivado on Wed Mar 19 12:10:35 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
@@ -17,6 +17,6 @@
# ****************************************************************************
set -Eeuo pipefail
# simulate design
-echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
-xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -view /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/proj/project_1/tb_firUnit_behav.wcfg -log simulate.log"
+xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -view /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/proj/project_1/tb_firUnit_behav.wcfg -log simulate.log
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index 92bae6e04f64d3de695bb19e86c20b7dd4aed561..93b63658819aa0d028878e6792a9bd0a6ee82ae1 100644
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
index 0107b4e..c2f0070 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -1,9 +1,9 @@
# compile vhdl design source files
vhdl xil_defaultlib \
-"../../../../../src/hdl/controlUnit.vhd" \
-"../../../../../src/hdl/operativeUnit.vhd" \
-"../../../../../src/hdl/firUnit.vhd" \
-"../../../../../src/hdl/tb_firUnit.vhd" \
+"../../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../../src/hdl/firUnit.vhd" \
+"../../../../../../src/hdl/tb_firUnit.vhd" \
# Do not sort compile order
nosort
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb
index 0e76091ce692a7c8ed1f8df69a920743b1957817..69277267d44ed0eaddbb787cc9913c3355401ddc 100644
GIT binary patch
delta 115
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F2mtYzBSQcH
delta 109
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000..8a25a91
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log"
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000..39a36f6
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -0,0 +1,133 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_35(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[27] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 27;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 27);
+ iki_vhdl_file_variable_register(dp + 14376);
+ iki_vhdl_file_variable_register(dp + 14432);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_firUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_firUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_firUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
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new file mode 100644
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GIT binary patch
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
new file mode 100644
index 0000000..2e5884e
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 1677624650740528615 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_firUnit_behav/xsimk\" \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
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HcmV?d00001
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000..ea7caa5
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=117
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=84
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=162
+OBJECT_NAME_COLUMN_WIDTH=188
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
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diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
new file mode 100644
index 0000000..6ad1a32
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -0,0 +1,4 @@
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51971
+Design successfully loaded
+Design Loading Memory Usage: 20188 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 20 ms
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
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new file mode 100644
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literal 0
HcmV?d00001
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..0a2fcb5
--- /dev/null
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,8 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742382607,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1742373132,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742376828,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1742373132,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini
index e2f5709..65c1bae 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini
@@ -12,478 +12,479 @@ unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
-cpri_v8_12_0=$RDI_DATADIR/xsim/ip/cpri_v8_12_0
-sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
-axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
-an_lt_v1_0_14=$RDI_DATADIR/xsim/ip/an_lt_v1_0_14
-axi_chip2chip_v5_0_24=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_24
-g709_fec_v2_4_11=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_11
-audio_formatter_v1_0_15=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_15
-ats_switch_v1_0_12=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_12
-xbip_pipe_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_10
-v_gamma_lut_v1_1_13=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_13
-vrf_fft_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_fft_v1_0_0
-v_hdmi_tx1_v1_0_10=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_10
-pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
-axi_mm2s_mapper_v1_1_32=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_32
-axis_data_fifo_v1_1_34=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_34
-mailbox_v2_1_18=$RDI_DATADIR/xsim/ip/mailbox_v2_1_18
-lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
-sdfec_ld_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/sdfec_ld_wrapper_v1_0_0
-v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
-tcc_encoder_3gpplte_v4_0_20=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_20
-axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
-axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
-vitis_net_p4_v2_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_2_0
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
-ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
-hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
-v_frmbuf_rd_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v3_0_0
-fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
-dfx_bitstream_monitor_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_6
-rs_toolbox_v9_0_14=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_14
-perf_axi_tg_v1_0_15=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_15
-xbip_utils_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_14
-dptx_v1_0_5=$RDI_DATADIR/xsim/ip/dptx_v1_0_5
-rs_decoder_v9_0_23=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_23
-dsp_macro_v1_0_7=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_7
-axi_vdma_v6_3_21=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_21
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
-qdriv_pl_v1_0_14=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_14
-axis_data_fifo_v2_0_15=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_15
-audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
-noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
-axi_i3c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_2
-axi_sg_v4_1_19=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_19
-mipi_csi2_rx_ctrl_v1_0_11=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_11
-hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
-xxv_ethernet_v4_1_13=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_13
-hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
-ernic_v4_2_0=$RDI_DATADIR/xsim/ip/ernic_v4_2_0
-rama_v1_1_19_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_19_lib
-rfdace5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfdace5_wrapper_v1_0_0
-tsn_temac_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_12
-tri_mode_ethernet_mac_v9_0_35=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_35
-axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
-ieee802d3_200g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_12
-fast_adapter_v1_0_10=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_10
-hdmi_gt_controller_v2_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v2_0_0
-xdfe_ofdm_v2_2_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_2_0
-ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
-vfb_v1_0_27=$RDI_DATADIR/xsim/ip/vfb_v1_0_27
-blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
-vcu2_v1_0_0=$RDI_DATADIR/xsim/ip/vcu2_v1_0_0
-shell_utils_addr_remap_v1_0_12=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_12
-oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
-sim_trig_v1_0_13=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_13
-v_hdmi_phy1_v1_0_13=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_13
-displayport_v7_0_25=$RDI_DATADIR/xsim/ip/displayport_v7_0_25
-cordic_v6_0_23=$RDI_DATADIR/xsim/ip/cordic_v6_0_23
-axi_crossbar_v2_1_34=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_34
-proc_sys_reset_v5_0_16=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_16
-polar_v1_1_5=$RDI_DATADIR/xsim/ip/polar_v1_1_5
-xscl=$RDI_DATADIR/xsim/ip/xscl
-xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
-v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
-func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
-ldpc_v2_0_16=$RDI_DATADIR/xsim/ip/ldpc_v2_0_16
-switch_core_top_v1_0_17=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_17
-v_frmbuf_wr_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_3
-bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
-audio_clock_recovery_unit_v1_0_5=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_5
-xdfe_resampler_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_10
-sd_fec_v1_1_15=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_15
-fifo_generator_v13_2_11=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_11
-axi_timebase_wdt_v3_0_25=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_25
-psx_vip_v1_0_6=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_6
-axi_memory_init_v1_0_14=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_14
-emc_common_v3_0_8=$RDI_DATADIR/xsim/ip/emc_common_v3_0_8
-ieee802d3_rs_fec_v2_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_24
-axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
-v_vcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_13
-v_csc_v1_1_13=$RDI_DATADIR/xsim/ip/v_csc_v1_1_13
-axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
-zynq_ultra_ps_e_vip_v1_0_19=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_19
-axi_cdma_v4_1_33=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_33
-v_dp_axi4s_vid_out_v1_0_9=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_9
-i2s_receiver_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_9
-rld3_pl_v1_0_15=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_15
-axi_firewall_v1_2_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_8
-axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
-cpm5n_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_9
-hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
-lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
-axis_switch_v1_1_33=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_33
-axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
-mipi_dphy_v4_3_13=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_13
-msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
-msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
-iomodule_v3_1_11=$RDI_DATADIR/xsim/ip/iomodule_v3_1_11
-fc32_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_28
-mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
-aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
-axi_hwicap_v3_0_37=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_37
-g709_rs_decoder_v2_2_15=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_15
-axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
-axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
-tmr_voter_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_7
-lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
-mdm_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_3
-axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
-amm_axi_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_19
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
-axis_accelerator_adapter_v2_1_19=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_19
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
-vrf_channelizer_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_channelizer_v1_0_0
-uhdsdi_gt_v2_1_5=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_5
-v_deinterlacer_v5_1_6=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_6
-noc_hbm_v1_0_1=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_1
-in_system_ibert_v1_0_23=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_23
-axi_pcie_v2_9_12=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_12
-axi_epu_v1_0_6=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_6
-floating_point_v7_0_24=$RDI_DATADIR/xsim/ip/floating_point_v7_0_24
-v_axi4s_vid_out_v4_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_19
-v_multi_scaler_v1_2_7=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_7
-axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
-can_v5_1_5=$RDI_DATADIR/xsim/ip/can_v5_1_5
-axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
-xdfe_cc_filter_v1_1_5=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_5
-anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
-v_smpte_uhdsdi_tx_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_5
-xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
-noc2_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_sim_v1_0_0
-tmr_sem_v1_0_27=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_27
-axi_ahblite_bridge_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_30
-xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
-hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
-util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
-axi_uart16550_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_35
-ecc_v2_0_17=$RDI_DATADIR/xsim/ip/ecc_v2_0_17
-v_frmbuf_rd_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_12
-axi_data_fifo_v2_1_32=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_32
-xdfe_equalizer_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_10
-axi_mcdma_v1_2_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_2_0
-versal_cips_ps_vip_v1_0_11=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_11
-emb_mem_gen_v1_0_10=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_10
-mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
-displayport_v8_1_10=$RDI_DATADIR/xsim/ip/displayport_v8_1_10
-tcc_encoder_3gpp_v5_0_23=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_23
-pcie_qdma_mailbox_v1_0_8=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_8
-v_frmbuf_rd_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_3
-util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
-axis_dwidth_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_32
-axi4svideo_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_19
-util_ff_v1_0_4=$RDI_DATADIR/xsim/ip/util_ff_v1_0_4
-sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
-microblaze_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_3
-cpri_v8_11_22=$RDI_DATADIR/xsim/ip/cpri_v8_11_22
-v_vid_in_axi4s_v5_0_5=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_5
-dprx_v1_0_5=$RDI_DATADIR/xsim/ip/dprx_v1_0_5
-shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
-util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
-axi_pcie3_v3_0_32=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_32
-v_smpte_uhdsdi_rx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_4
-axi_datamover_v5_1_35=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_35
-interlaken_v2_4_19=$RDI_DATADIR/xsim/ip/interlaken_v2_4_19
-nvmeha_v1_0_14=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_14
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
-bfr_ft_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/bfr_ft_wrapper_v1_0_0
-axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
-zynq_ultra_ps_e_v3_3_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_14
-stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
-v_hdmi_rx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_5
-ethernet_1_10_25g_v2_7_18=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_18
-v_tpg_v8_2_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_6
-qdma_v5_0_12=$RDI_DATADIR/xsim/ip/qdma_v5_0_12
-pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
-v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
-jesd204c_v4_3_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_3_0
-axi_timer_v2_0_35=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_35
-c_compare_v12_0_10=$RDI_DATADIR/xsim/ip/c_compare_v12_0_10
-axi_clock_converter_v2_1_32=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_32
-axi_protocol_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_33
-axi_dma_v7_1_34=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_34
-pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
-dfx_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_11
-axi_sideband_util_v1_0_17=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_17
-tmr_manager_v1_0_13=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_13
-fec_5g_common_v1_1_5=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_5
-axi_ethernetlite_v3_0_32=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_32
-lib_bmg_v1_0_18=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_18
-high_speed_selectio_wiz_v3_6_10=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_10
-c_shift_ram_v12_0_18=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_18
-axi_pmon_v1_0_2=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_2
-v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
-uhdsdi_gt_v2_2_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_2_0
-v_tpg_v8_1_12=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_12
-noc2_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_sim_v1_0_0
-axi_gpio_v2_0_35=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_35
-axis_interconnect_v1_1_24=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_24
-adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
-xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
-noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
-c_addsub_v12_0_19=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_19
-sem_ultra_v3_1_27=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_27
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
-v_warp_init_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_5
-mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
-roe_framer_v3_0_9=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_9
-axi_remapper_tx_v1_0_3=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_3
-axi_traffic_gen_v3_0_19=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_19
-dfx_controller_v1_0_8=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_8
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
-tmr_comparator_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_8
-rfadce5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfadce5_wrapper_v1_0_0
-axi_mmu_v2_1_31=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_31
-axi_dwidth_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_33
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
-axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
-picxo_fracxo_v2_0_3=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_3
-dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
-v_frmbuf_wr_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_12
-sd_fec_beta_v1_0_0=$RDI_DATADIR/xsim/ip/sd_fec_beta_v1_0_0
-iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
-lmb_bram_if_cntlr_v4_0_25=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_25
-mrmac_v3_0_0=$RDI_DATADIR/xsim/ip/mrmac_v3_0_0
-tsn_endpoint_ethernet_mac_block_v1_0_18=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_18
-axis_vio_v1_0_12=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_12
-xtlm=$RDI_DATADIR/xsim/ip/xtlm
-bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
-floating_point_v7_1_19=$RDI_DATADIR/xsim/ip/floating_point_v7_1_19
-ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
-axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
-pc_cfr_v8_0_3=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_3
-axi_amm_bridge_v1_0_23=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_23
-c_counter_binary_v12_0_20=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_20
xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
-axi_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_19
-xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
-axi_msg_v1_0_12=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_12
-noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
-xpm=$RDI_DATADIR/xsim/ip/xpm
-bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
-interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
-gtwizard_ultrascale_v1_7_19=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_19
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
-mipi_rx_phy_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_1
-sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
-dds_compiler_v6_0_26=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_26
-xdma_v4_1_31=$RDI_DATADIR/xsim/ip/xdma_v4_1_31
-axi_fifo_mm_s_v4_3_5=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_5
-l_ethernet_v3_3_13=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_13
-xdfe_nlf_v1_1_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_2
-axi_mcdma_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_14
-remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
-ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
-xdfe_common_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_4
-axi_intc_v4_1_20=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_20
-axi_uartlite_v2_0_37=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_37
-gmii_to_rgmii_v4_1_17=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_17
-cdcam_v1_2_0=$RDI_DATADIR/xsim/ip/cdcam_v1_2_0
-blk_mem_gen_v8_4_9=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_9
-system_cache_v5_0_12=$RDI_DATADIR/xsim/ip/system_cache_v5_0_12
-cmac_usplus_v3_1_19=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_19
-axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
-axi_interconnect_v1_7_24=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_24
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
-sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
-v_hdmi_tx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_5
-dft_v4_2_9=$RDI_DATADIR/xsim/ip/dft_v4_2_9
-ieee802d3_400g_rs_fec_v3_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_3
-srio_gen2_v4_1_20=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_20
-mipi_tx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_tx_phy_v1_0_0
-axi_epc_v2_0_36=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_36
-i2s_transmitter_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_9
-flexo_100g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_30
-axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
-axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
-ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
-axi_emc_v3_0_33=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_33
-multi_channel_25g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_28
-axi_protocol_checker_v2_0_19=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_19
-axi_register_slice_v2_1_33=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_33
-v_letterbox_v1_1_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_13
-gtwizard_ultrascale_v1_6_17=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_17
-dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
-axis_broadcaster_v1_1_32=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_32
-axis_clock_converter_v1_1_34=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_34
-ahblite_axi_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_28
-gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
-sid_v8_0_22=$RDI_DATADIR/xsim/ip/sid_v8_0_22
-sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
-axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
-v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
-axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
-sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
-noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
-noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
-remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
-ten_gig_eth_pcs_pma_v6_0_28=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_28
-axis_register_slice_v1_1_33=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_33
-clk_vip_v1_0_5=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_5
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
-v_vid_sdi_tx_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_3
-processing_system7_vip_v1_0_21=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_21
-microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
-cmac_v2_6_17=$RDI_DATADIR/xsim/ip/cmac_v2_6_17
-pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
-mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
-mpram_v1_0_5=$RDI_DATADIR/xsim/ip/mpram_v1_0_5
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
-trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
-v_hscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_13
-ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
-axis_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_17
-xbip_multadd_v3_0_21=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_21
-axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
-axi_vfifo_ctrl_v2_0_36=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_36
-v_warp_filter_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_5
-xfft_v9_1_13=$RDI_DATADIR/xsim/ip/xfft_v9_1_13
-axi_bram_ctrl_v4_1_11=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_11
-v_hcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_13
-v_demosaic_v1_1_13=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_13
-lte_fft_v2_1_11=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_11
-xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
-mrmac_v2_3_2=$RDI_DATADIR/xsim/ip/mrmac_v2_3_2
-v_tc_v6_2_9=$RDI_DATADIR/xsim/ip/v_tc_v6_2_9
-div_gen_v5_1_23=$RDI_DATADIR/xsim/ip/div_gen_v5_1_23
-rs_encoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_22
-axi_utils_v2_0_10=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_10
-v_axi4s_remap_v1_1_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_12
-v_mix_v5_2_11=$RDI_DATADIR/xsim/ip/v_mix_v5_2_11
-xdfe_fft_v1_0_8=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_8
-cic_compiler_v4_0_20=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_20
-sim_clk_gen_v1_0_5=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_5
-qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
-lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
-dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
-hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
-usxgmii_v1_2_20=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_20
-v_smpte_sdi_v3_0_12=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_12
-mipi_dsi2_rx_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_1
-mdm_v3_2_27=$RDI_DATADIR/xsim/ip/mdm_v3_2_27
-accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
-g975_efec_i7_v2_0_24=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_24
-axis_combiner_v1_1_31=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_31
-xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
-dcmac_v2_5_0=$RDI_DATADIR/xsim/ip/dcmac_v2_5_0
-convolution_v9_0_21=$RDI_DATADIR/xsim/ip/convolution_v9_0_21
-microblaze_v11_0_14=$RDI_DATADIR/xsim/ip/microblaze_v11_0_14
-cpm4_v1_0_17=$RDI_DATADIR/xsim/ip/cpm4_v1_0_17
-cmpy_v6_0_25=$RDI_DATADIR/xsim/ip/cmpy_v6_0_25
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
-spdif_v2_0_30=$RDI_DATADIR/xsim/ip/spdif_v2_0_30
-oran_radio_if_v3_2_1=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_1
-v_hdmi_rx1_v1_0_11=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_11
-cam_v3_1_0=$RDI_DATADIR/xsim/ip/cam_v3_1_0
-emb_fifo_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_6
-axi_iic_v2_1_9=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_9
-axi_perf_mon_v5_0_35=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_35
-v_tpg_v8_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_16
-mutex_v2_1_14=$RDI_DATADIR/xsim/ip/mutex_v2_1_14
-emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
-lib_fifo_v1_0_20=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_20
-advanced_io_wizard_v1_0_15=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_15
-c_reg_fd_v12_0_10=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_10
-axi4stream_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_19
-lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
-lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
-ieee802d3_50g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_25
-icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
-noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
-vid_edid_v1_0_3=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_3
-shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
-sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
-mult_gen_v12_0_22=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_22
-timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
-dfe_channelizer_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/dfe_channelizer_wrapper_v1_0_0
-clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
-noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
-v_frmbuf_wr_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v3_0_0
-xdfe_cc_mixer_v2_0_5=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_5
-mipi_dsi_tx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_10
-axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
-ieee802d3_clause74_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_19
-sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
-axi_tft_v2_0_29=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_29
-viterbi_v9_1_18=$RDI_DATADIR/xsim/ip/viterbi_v9_1_18
-ieee802d3_50g_rs_fec_v2_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_18
-microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
-fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
-video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
-dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
-ilknf_v1_3_5=$RDI_DATADIR/xsim/ip/ilknf_v1_3_5
-rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
-g975_efec_i4_v1_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_23
-c_accum_v12_0_19=$RDI_DATADIR/xsim/ip/c_accum_v12_0_19
-aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
-ieee802d3_25g_rs_fec_v1_0_31=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_31
-smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
-noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
-xdfe_nr_prach_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_4
-gig_ethernet_pcs_pma_v16_2_21=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_21
-trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
-v_sdi_rx_vid_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_3
fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
-ldpc_5gnr_v1_0_4=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_4
-soft_ecc_proxy_v1_1_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_2
-axi_c2c_v1_0_11=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_11
-noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
-hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
-v_smpte_uhdsdi_v1_0_12=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_12
-bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
-noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
-fir_compiler_v7_2_23=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_23
-axi_hbicap_v1_0_8=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_8
-x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
-canfd_v3_0_12=$RDI_DATADIR/xsim/ip/canfd_v3_0_12
-nvme_tc_v3_0_8=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_8
-axi_usb2_device_v5_0_34=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_34
-ldpc_5gnr_lite_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_3
-tmr_inject_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_7
-v_uhdsdi_audio_v2_0_9=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_9
-xsdbm_v3_0_3=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_3
-v_vscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_13
-vid_phy_controller_v2_2_19=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_19
-mem_tg_v1_0_15=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_15
-dfx_axi_shutdown_manager_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_4
-ibert_lib_v1_0_12=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_12
-ta_dma_v1_0_17=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_17
-cam_blk_lib_v1_2_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_2_0
-noc2_nps6x_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps6x_v1_0_0
-noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
-tcc_decoder_3gppmm_v2_0_28=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_28
-noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
-ddr4_pl_v1_0_15=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_15
-advanced_io_wizard_phy_v1_0_4=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_4
-ft_prach_v1_2_3=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_3
-lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
-jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
-x5io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_6
-axis_subset_converter_v1_1_33=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_33
-axi_quad_spi_v3_2_32=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_32
-g709_rs_encoder_v2_2_13=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_13
-hdcp_v1_0_6=$RDI_DATADIR/xsim/ip/hdcp_v1_0_6
-v_frmbuf_rd_v2_4_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_4
-gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
-quadsgmii_v3_5_21=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_21
-xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
-rst_vip_v1_0_7=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_7
-ethernet_offload_v1_0_0=$RDI_DATADIR/xsim/ip/ethernet_offload_v1_0_0
-cpm5_v1_0_17=$RDI_DATADIR/xsim/ip/cpm5_v1_0_17
-processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
-debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
-xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
-vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
-axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
-displayport_v9_0_10=$RDI_DATADIR/xsim/ip/displayport_v9_0_10
-visp_v1_0_0=$RDI_DATADIR/xsim/ip/visp_v1_0_0
-bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak
index e2f5709..65c1bae 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -12,478 +12,479 @@ unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
-cpri_v8_12_0=$RDI_DATADIR/xsim/ip/cpri_v8_12_0
-sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
-axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
-an_lt_v1_0_14=$RDI_DATADIR/xsim/ip/an_lt_v1_0_14
-axi_chip2chip_v5_0_24=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_24
-g709_fec_v2_4_11=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_11
-audio_formatter_v1_0_15=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_15
-ats_switch_v1_0_12=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_12
-xbip_pipe_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_10
-v_gamma_lut_v1_1_13=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_13
-vrf_fft_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_fft_v1_0_0
-v_hdmi_tx1_v1_0_10=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_10
-pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
-axi_mm2s_mapper_v1_1_32=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_32
-axis_data_fifo_v1_1_34=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_34
-mailbox_v2_1_18=$RDI_DATADIR/xsim/ip/mailbox_v2_1_18
-lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
-sdfec_ld_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/sdfec_ld_wrapper_v1_0_0
-v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
-tcc_encoder_3gpplte_v4_0_20=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_20
-axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
-axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
-vitis_net_p4_v2_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_2_0
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
-ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
-hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
-v_frmbuf_rd_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v3_0_0
-fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
-dfx_bitstream_monitor_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_6
-rs_toolbox_v9_0_14=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_14
-perf_axi_tg_v1_0_15=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_15
-xbip_utils_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_14
-dptx_v1_0_5=$RDI_DATADIR/xsim/ip/dptx_v1_0_5
-rs_decoder_v9_0_23=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_23
-dsp_macro_v1_0_7=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_7
-axi_vdma_v6_3_21=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_21
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
-qdriv_pl_v1_0_14=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_14
-axis_data_fifo_v2_0_15=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_15
-audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
-noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
-axi_i3c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_2
-axi_sg_v4_1_19=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_19
-mipi_csi2_rx_ctrl_v1_0_11=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_11
-hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
-xxv_ethernet_v4_1_13=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_13
-hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
-ernic_v4_2_0=$RDI_DATADIR/xsim/ip/ernic_v4_2_0
-rama_v1_1_19_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_19_lib
-rfdace5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfdace5_wrapper_v1_0_0
-tsn_temac_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_12
-tri_mode_ethernet_mac_v9_0_35=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_35
-axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
-ieee802d3_200g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_12
-fast_adapter_v1_0_10=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_10
-hdmi_gt_controller_v2_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v2_0_0
-xdfe_ofdm_v2_2_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_2_0
-ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
-vfb_v1_0_27=$RDI_DATADIR/xsim/ip/vfb_v1_0_27
-blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
-vcu2_v1_0_0=$RDI_DATADIR/xsim/ip/vcu2_v1_0_0
-shell_utils_addr_remap_v1_0_12=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_12
-oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
-sim_trig_v1_0_13=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_13
-v_hdmi_phy1_v1_0_13=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_13
-displayport_v7_0_25=$RDI_DATADIR/xsim/ip/displayport_v7_0_25
-cordic_v6_0_23=$RDI_DATADIR/xsim/ip/cordic_v6_0_23
-axi_crossbar_v2_1_34=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_34
-proc_sys_reset_v5_0_16=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_16
-polar_v1_1_5=$RDI_DATADIR/xsim/ip/polar_v1_1_5
-xscl=$RDI_DATADIR/xsim/ip/xscl
-xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
-v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
-func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
-ldpc_v2_0_16=$RDI_DATADIR/xsim/ip/ldpc_v2_0_16
-switch_core_top_v1_0_17=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_17
-v_frmbuf_wr_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_3
-bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
-audio_clock_recovery_unit_v1_0_5=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_5
-xdfe_resampler_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_10
-sd_fec_v1_1_15=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_15
-fifo_generator_v13_2_11=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_11
-axi_timebase_wdt_v3_0_25=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_25
-psx_vip_v1_0_6=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_6
-axi_memory_init_v1_0_14=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_14
-emc_common_v3_0_8=$RDI_DATADIR/xsim/ip/emc_common_v3_0_8
-ieee802d3_rs_fec_v2_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_24
-axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
-v_vcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_13
-v_csc_v1_1_13=$RDI_DATADIR/xsim/ip/v_csc_v1_1_13
-axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
-zynq_ultra_ps_e_vip_v1_0_19=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_19
-axi_cdma_v4_1_33=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_33
-v_dp_axi4s_vid_out_v1_0_9=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_9
-i2s_receiver_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_9
-rld3_pl_v1_0_15=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_15
-axi_firewall_v1_2_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_8
-axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
-cpm5n_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_9
-hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
-lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
-axis_switch_v1_1_33=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_33
-axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
-mipi_dphy_v4_3_13=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_13
-msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
-msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
-iomodule_v3_1_11=$RDI_DATADIR/xsim/ip/iomodule_v3_1_11
-fc32_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_28
-mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
-aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
-axi_hwicap_v3_0_37=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_37
-g709_rs_decoder_v2_2_15=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_15
-axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
-axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
-tmr_voter_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_7
-lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
-mdm_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_3
-axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
-amm_axi_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_19
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
-axis_accelerator_adapter_v2_1_19=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_19
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
-vrf_channelizer_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_channelizer_v1_0_0
-uhdsdi_gt_v2_1_5=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_5
-v_deinterlacer_v5_1_6=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_6
-noc_hbm_v1_0_1=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_1
-in_system_ibert_v1_0_23=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_23
-axi_pcie_v2_9_12=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_12
-axi_epu_v1_0_6=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_6
-floating_point_v7_0_24=$RDI_DATADIR/xsim/ip/floating_point_v7_0_24
-v_axi4s_vid_out_v4_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_19
-v_multi_scaler_v1_2_7=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_7
-axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
-can_v5_1_5=$RDI_DATADIR/xsim/ip/can_v5_1_5
-axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
-xdfe_cc_filter_v1_1_5=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_5
-anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
-v_smpte_uhdsdi_tx_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_5
-xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
-noc2_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_sim_v1_0_0
-tmr_sem_v1_0_27=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_27
-axi_ahblite_bridge_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_30
-xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
-hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
-util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
-axi_uart16550_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_35
-ecc_v2_0_17=$RDI_DATADIR/xsim/ip/ecc_v2_0_17
-v_frmbuf_rd_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_12
-axi_data_fifo_v2_1_32=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_32
-xdfe_equalizer_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_10
-axi_mcdma_v1_2_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_2_0
-versal_cips_ps_vip_v1_0_11=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_11
-emb_mem_gen_v1_0_10=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_10
-mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
-displayport_v8_1_10=$RDI_DATADIR/xsim/ip/displayport_v8_1_10
-tcc_encoder_3gpp_v5_0_23=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_23
-pcie_qdma_mailbox_v1_0_8=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_8
-v_frmbuf_rd_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_3
-util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
-axis_dwidth_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_32
-axi4svideo_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_19
-util_ff_v1_0_4=$RDI_DATADIR/xsim/ip/util_ff_v1_0_4
-sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
-microblaze_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_3
-cpri_v8_11_22=$RDI_DATADIR/xsim/ip/cpri_v8_11_22
-v_vid_in_axi4s_v5_0_5=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_5
-dprx_v1_0_5=$RDI_DATADIR/xsim/ip/dprx_v1_0_5
-shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
-util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
-axi_pcie3_v3_0_32=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_32
-v_smpte_uhdsdi_rx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_4
-axi_datamover_v5_1_35=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_35
-interlaken_v2_4_19=$RDI_DATADIR/xsim/ip/interlaken_v2_4_19
-nvmeha_v1_0_14=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_14
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
-bfr_ft_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/bfr_ft_wrapper_v1_0_0
-axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
-zynq_ultra_ps_e_v3_3_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_14
-stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
-v_hdmi_rx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_5
-ethernet_1_10_25g_v2_7_18=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_18
-v_tpg_v8_2_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_6
-qdma_v5_0_12=$RDI_DATADIR/xsim/ip/qdma_v5_0_12
-pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
-v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
-jesd204c_v4_3_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_3_0
-axi_timer_v2_0_35=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_35
-c_compare_v12_0_10=$RDI_DATADIR/xsim/ip/c_compare_v12_0_10
-axi_clock_converter_v2_1_32=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_32
-axi_protocol_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_33
-axi_dma_v7_1_34=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_34
-pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
-dfx_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_11
-axi_sideband_util_v1_0_17=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_17
-tmr_manager_v1_0_13=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_13
-fec_5g_common_v1_1_5=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_5
-axi_ethernetlite_v3_0_32=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_32
-lib_bmg_v1_0_18=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_18
-high_speed_selectio_wiz_v3_6_10=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_10
-c_shift_ram_v12_0_18=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_18
-axi_pmon_v1_0_2=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_2
-v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
-uhdsdi_gt_v2_2_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_2_0
-v_tpg_v8_1_12=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_12
-noc2_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_sim_v1_0_0
-axi_gpio_v2_0_35=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_35
-axis_interconnect_v1_1_24=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_24
-adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
-xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
-noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
-c_addsub_v12_0_19=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_19
-sem_ultra_v3_1_27=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_27
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
-v_warp_init_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_5
-mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
-roe_framer_v3_0_9=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_9
-axi_remapper_tx_v1_0_3=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_3
-axi_traffic_gen_v3_0_19=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_19
-dfx_controller_v1_0_8=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_8
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
-tmr_comparator_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_8
-rfadce5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfadce5_wrapper_v1_0_0
-axi_mmu_v2_1_31=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_31
-axi_dwidth_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_33
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
-axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
-picxo_fracxo_v2_0_3=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_3
-dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
-v_frmbuf_wr_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_12
-sd_fec_beta_v1_0_0=$RDI_DATADIR/xsim/ip/sd_fec_beta_v1_0_0
-iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
-lmb_bram_if_cntlr_v4_0_25=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_25
-mrmac_v3_0_0=$RDI_DATADIR/xsim/ip/mrmac_v3_0_0
-tsn_endpoint_ethernet_mac_block_v1_0_18=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_18
-axis_vio_v1_0_12=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_12
-xtlm=$RDI_DATADIR/xsim/ip/xtlm
-bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
-floating_point_v7_1_19=$RDI_DATADIR/xsim/ip/floating_point_v7_1_19
-ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
-axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
-pc_cfr_v8_0_3=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_3
-axi_amm_bridge_v1_0_23=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_23
-c_counter_binary_v12_0_20=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_20
xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
-axi_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_19
-xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
-axi_msg_v1_0_12=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_12
-noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
-xpm=$RDI_DATADIR/xsim/ip/xpm
-bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
-interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
-gtwizard_ultrascale_v1_7_19=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_19
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
-mipi_rx_phy_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_1
-sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
-dds_compiler_v6_0_26=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_26
-xdma_v4_1_31=$RDI_DATADIR/xsim/ip/xdma_v4_1_31
-axi_fifo_mm_s_v4_3_5=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_5
-l_ethernet_v3_3_13=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_13
-xdfe_nlf_v1_1_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_2
-axi_mcdma_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_14
-remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
-ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
-xdfe_common_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_4
-axi_intc_v4_1_20=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_20
-axi_uartlite_v2_0_37=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_37
-gmii_to_rgmii_v4_1_17=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_17
-cdcam_v1_2_0=$RDI_DATADIR/xsim/ip/cdcam_v1_2_0
-blk_mem_gen_v8_4_9=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_9
-system_cache_v5_0_12=$RDI_DATADIR/xsim/ip/system_cache_v5_0_12
-cmac_usplus_v3_1_19=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_19
-axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
-axi_interconnect_v1_7_24=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_24
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
-sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
-v_hdmi_tx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_5
-dft_v4_2_9=$RDI_DATADIR/xsim/ip/dft_v4_2_9
-ieee802d3_400g_rs_fec_v3_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_3
-srio_gen2_v4_1_20=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_20
-mipi_tx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_tx_phy_v1_0_0
-axi_epc_v2_0_36=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_36
-i2s_transmitter_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_9
-flexo_100g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_30
-axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
-axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
-ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
-axi_emc_v3_0_33=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_33
-multi_channel_25g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_28
-axi_protocol_checker_v2_0_19=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_19
-axi_register_slice_v2_1_33=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_33
-v_letterbox_v1_1_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_13
-gtwizard_ultrascale_v1_6_17=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_17
-dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
-axis_broadcaster_v1_1_32=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_32
-axis_clock_converter_v1_1_34=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_34
-ahblite_axi_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_28
-gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
-sid_v8_0_22=$RDI_DATADIR/xsim/ip/sid_v8_0_22
-sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
-axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
-v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
-axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
-sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
-noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
-noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
-remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
-ten_gig_eth_pcs_pma_v6_0_28=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_28
-axis_register_slice_v1_1_33=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_33
-clk_vip_v1_0_5=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_5
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
-v_vid_sdi_tx_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_3
-processing_system7_vip_v1_0_21=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_21
-microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
-cmac_v2_6_17=$RDI_DATADIR/xsim/ip/cmac_v2_6_17
-pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
-mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
-mpram_v1_0_5=$RDI_DATADIR/xsim/ip/mpram_v1_0_5
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
-trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
-v_hscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_13
-ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
-axis_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_17
-xbip_multadd_v3_0_21=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_21
-axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
-axi_vfifo_ctrl_v2_0_36=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_36
-v_warp_filter_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_5
-xfft_v9_1_13=$RDI_DATADIR/xsim/ip/xfft_v9_1_13
-axi_bram_ctrl_v4_1_11=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_11
-v_hcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_13
-v_demosaic_v1_1_13=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_13
-lte_fft_v2_1_11=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_11
-xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
-mrmac_v2_3_2=$RDI_DATADIR/xsim/ip/mrmac_v2_3_2
-v_tc_v6_2_9=$RDI_DATADIR/xsim/ip/v_tc_v6_2_9
-div_gen_v5_1_23=$RDI_DATADIR/xsim/ip/div_gen_v5_1_23
-rs_encoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_22
-axi_utils_v2_0_10=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_10
-v_axi4s_remap_v1_1_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_12
-v_mix_v5_2_11=$RDI_DATADIR/xsim/ip/v_mix_v5_2_11
-xdfe_fft_v1_0_8=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_8
-cic_compiler_v4_0_20=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_20
-sim_clk_gen_v1_0_5=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_5
-qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
-lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
-dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
-hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
-usxgmii_v1_2_20=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_20
-v_smpte_sdi_v3_0_12=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_12
-mipi_dsi2_rx_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_1
-mdm_v3_2_27=$RDI_DATADIR/xsim/ip/mdm_v3_2_27
-accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
-g975_efec_i7_v2_0_24=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_24
-axis_combiner_v1_1_31=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_31
-xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
-dcmac_v2_5_0=$RDI_DATADIR/xsim/ip/dcmac_v2_5_0
-convolution_v9_0_21=$RDI_DATADIR/xsim/ip/convolution_v9_0_21
-microblaze_v11_0_14=$RDI_DATADIR/xsim/ip/microblaze_v11_0_14
-cpm4_v1_0_17=$RDI_DATADIR/xsim/ip/cpm4_v1_0_17
-cmpy_v6_0_25=$RDI_DATADIR/xsim/ip/cmpy_v6_0_25
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
-spdif_v2_0_30=$RDI_DATADIR/xsim/ip/spdif_v2_0_30
-oran_radio_if_v3_2_1=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_1
-v_hdmi_rx1_v1_0_11=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_11
-cam_v3_1_0=$RDI_DATADIR/xsim/ip/cam_v3_1_0
-emb_fifo_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_6
-axi_iic_v2_1_9=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_9
-axi_perf_mon_v5_0_35=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_35
-v_tpg_v8_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_16
-mutex_v2_1_14=$RDI_DATADIR/xsim/ip/mutex_v2_1_14
-emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
-lib_fifo_v1_0_20=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_20
-advanced_io_wizard_v1_0_15=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_15
-c_reg_fd_v12_0_10=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_10
-axi4stream_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_19
-lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
-lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
-ieee802d3_50g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_25
-icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
-noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
-vid_edid_v1_0_3=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_3
-shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
-sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
-mult_gen_v12_0_22=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_22
-timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
-dfe_channelizer_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/dfe_channelizer_wrapper_v1_0_0
-clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
-noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
-v_frmbuf_wr_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v3_0_0
-xdfe_cc_mixer_v2_0_5=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_5
-mipi_dsi_tx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_10
-axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
-ieee802d3_clause74_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_19
-sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
-axi_tft_v2_0_29=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_29
-viterbi_v9_1_18=$RDI_DATADIR/xsim/ip/viterbi_v9_1_18
-ieee802d3_50g_rs_fec_v2_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_18
-microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
-fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
-video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
-dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
-ilknf_v1_3_5=$RDI_DATADIR/xsim/ip/ilknf_v1_3_5
-rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
-g975_efec_i4_v1_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_23
-c_accum_v12_0_19=$RDI_DATADIR/xsim/ip/c_accum_v12_0_19
-aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
-ieee802d3_25g_rs_fec_v1_0_31=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_31
-smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
-noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
-xdfe_nr_prach_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_4
-gig_ethernet_pcs_pma_v16_2_21=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_21
-trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
-v_sdi_rx_vid_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_3
fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
-ldpc_5gnr_v1_0_4=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_4
-soft_ecc_proxy_v1_1_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_2
-axi_c2c_v1_0_11=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_11
-noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
-hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
-v_smpte_uhdsdi_v1_0_12=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_12
-bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
-noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
-fir_compiler_v7_2_23=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_23
-axi_hbicap_v1_0_8=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_8
-x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
-canfd_v3_0_12=$RDI_DATADIR/xsim/ip/canfd_v3_0_12
-nvme_tc_v3_0_8=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_8
-axi_usb2_device_v5_0_34=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_34
-ldpc_5gnr_lite_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_3
-tmr_inject_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_7
-v_uhdsdi_audio_v2_0_9=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_9
-xsdbm_v3_0_3=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_3
-v_vscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_13
-vid_phy_controller_v2_2_19=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_19
-mem_tg_v1_0_15=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_15
-dfx_axi_shutdown_manager_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_4
-ibert_lib_v1_0_12=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_12
-ta_dma_v1_0_17=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_17
-cam_blk_lib_v1_2_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_2_0
-noc2_nps6x_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps6x_v1_0_0
-noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
-tcc_decoder_3gppmm_v2_0_28=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_28
-noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
-ddr4_pl_v1_0_15=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_15
-advanced_io_wizard_phy_v1_0_4=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_4
-ft_prach_v1_2_3=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_3
-lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
-jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
-x5io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_6
-axis_subset_converter_v1_1_33=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_33
-axi_quad_spi_v3_2_32=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_32
-g709_rs_encoder_v2_2_13=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_13
-hdcp_v1_0_6=$RDI_DATADIR/xsim/ip/hdcp_v1_0_6
-v_frmbuf_rd_v2_4_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_4
-gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
-quadsgmii_v3_5_21=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_21
-xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
-rst_vip_v1_0_7=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_7
-ethernet_offload_v1_0_0=$RDI_DATADIR/xsim/ip/ethernet_offload_v1_0_0
-cpm5_v1_0_17=$RDI_DATADIR/xsim/ip/cpm5_v1_0_17
-processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
-debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
-xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
-vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
-axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
-displayport_v9_0_10=$RDI_DATADIR/xsim/ip/displayport_v9_0_10
-visp_v1_0_0=$RDI_DATADIR/xsim/ip/visp_v1_0_0
-bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/project_1/project_1.xpr b/proj/project_1/project_1.xpr
index 3a6e0cc..8d0cee1 100644
--- a/proj/project_1/project_1.xpr
+++ b/proj/project_1/project_1.xpr
@@ -60,7 +60,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="115"/>
+ <Option Name="WTXSimLaunchSim" Val="132"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -189,6 +189,11 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
+ <File Path="$PPRDIR/tb_firUnit_behav.wcfg">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_firUnit"/>
@@ -201,6 +206,7 @@
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
+ <Option Name="XSimWcfgFile" Val="$PPRDIR/tb_firUnit_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
diff --git a/proj/project_1/tb_firUnit_behav.wcfg b/proj/project_1/tb_firUnit_behav.wcfg
new file mode 100644
index 0000000..9f22c48
--- /dev/null
+++ b/proj/project_1/tb_firUnit_behav.wcfg
@@ -0,0 +1,214 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="tb_firUnit_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="tb_firUnit" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="3,890.000 ns"></ZoomStartTime>
+ <ZoomEndTime time="4,090.001 ns"></ZoomEndTime>
+ <Cursor1Time time="3,995.000 ns"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="243"></NameColumnWidth>
+ <ValueColumnWidth column_width="90"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="42" />
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_clock">
+ <obj_property name="ElementShortName">SC_clock</obj_property>
+ <obj_property name="ObjectShortName">SC_clock</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_reset">
+ <obj_property name="ElementShortName">SC_reset</obj_property>
+ <obj_property name="ObjectShortName">SC_reset</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/SC_inputSample">
+ <obj_property name="ElementShortName">SC_inputSample[11:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_inputSample[11:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_inputSampleValid">
+ <obj_property name="ElementShortName">SC_inputSampleValid</obj_property>
+ <obj_property name="ObjectShortName">SC_inputSampleValid</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/SC_filteredSample">
+ <obj_property name="ElementShortName">SC_filteredSample[11:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_filteredSample[11:0]</obj_property>
+ <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider8" type="divider">
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/I_inputSampleValid">
+ <obj_property name="ElementShortName">I_inputSampleValid</obj_property>
+ <obj_property name="ObjectShortName">I_inputSampleValid</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/I_processingDoneA">
+ <obj_property name="ElementShortName">I_processingDoneA</obj_property>
+ <obj_property name="ObjectShortName">I_processingDoneA</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/I_processingDoneB">
+ <obj_property name="ElementShortName">I_processingDoneB</obj_property>
+ <obj_property name="ObjectShortName">I_processingDoneB</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/I_processingDoneBL">
+ <obj_property name="ElementShortName">I_processingDoneBL</obj_property>
+ <obj_property name="ObjectShortName">I_processingDoneBL</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/I_processingDoneClellan">
+ <obj_property name="ElementShortName">I_processingDoneClellan</obj_property>
+ <obj_property name="ObjectShortName">I_processingDoneClellan</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_loadShift">
+ <obj_property name="ElementShortName">O_loadShift</obj_property>
+ <obj_property name="ObjectShortName">O_loadShift</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_initAddress">
+ <obj_property name="ElementShortName">O_initAddress</obj_property>
+ <obj_property name="ObjectShortName">O_initAddress</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_incrAddress">
+ <obj_property name="ElementShortName">O_incrAddress</obj_property>
+ <obj_property name="ObjectShortName">O_incrAddress</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_initSum">
+ <obj_property name="ElementShortName">O_initSum</obj_property>
+ <obj_property name="ObjectShortName">O_initSum</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_loadSum">
+ <obj_property name="ElementShortName">O_loadSum</obj_property>
+ <obj_property name="ObjectShortName">O_loadSum</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_loadOutA">
+ <obj_property name="ElementShortName">O_loadOutA</obj_property>
+ <obj_property name="ObjectShortName">O_loadOutA</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_loadOutBL">
+ <obj_property name="ElementShortName">O_loadOutBL</obj_property>
+ <obj_property name="ObjectShortName">O_loadOutBL</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_loadOutClellan">
+ <obj_property name="ElementShortName">O_loadOutClellan</obj_property>
+ <obj_property name="ObjectShortName">O_loadOutClellan</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_sel">
+ <obj_property name="ElementShortName">O_sel[1:0]</obj_property>
+ <obj_property name="ObjectShortName">O_sel[1:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/O_FilteredSampleValid">
+ <obj_property name="ElementShortName">O_FilteredSampleValid</obj_property>
+ <obj_property name="ObjectShortName">O_FilteredSampleValid</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/SR_presentState">
+ <obj_property name="ElementShortName">SR_presentState</obj_property>
+ <obj_property name="ObjectShortName">SR_presentState</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_firUnit/firUnit_1/controlUnit_1/SR_futurState">
+ <obj_property name="ElementShortName">SR_futurState</obj_property>
+ <obj_property name="ObjectShortName">SR_futurState</obj_property>
+ </wvobject>
+ <wvobject fp_name="divider26" type="divider">
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDoneA">
+ <obj_property name="ElementShortName">O_processingDoneA</obj_property>
+ <obj_property name="ObjectShortName">O_processingDoneA</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDoneB">
+ <obj_property name="ElementShortName">O_processingDoneB</obj_property>
+ <obj_property name="ObjectShortName">O_processingDoneB</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDoneBL">
+ <obj_property name="ElementShortName">O_processingDoneBL</obj_property>
+ <obj_property name="ObjectShortName">O_processingDoneBL</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDoneClellan">
+ <obj_property name="ElementShortName">O_processingDoneClellan</obj_property>
+ <obj_property name="ObjectShortName">O_processingDoneClellan</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand1">
+ <obj_property name="ElementShortName">SC_multOperand1[11:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_multOperand1[11:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand2">
+ <obj_property name="ElementShortName">SC_multOperand2[11:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_multOperand2[11:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
+ </wvobject>
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+ <obj_property name="ObjectShortName">SR_2A[0:1][11:0]</obj_property>
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+ <obj_property name="ObjectShortName">SR_coefRegisterB[0:2][11:0]</obj_property>
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+ <obj_property name="ObjectShortName">SR_2[0:2][11:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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+ <obj_property name="ObjectShortName">SR_coefRegisterBL[0:94][11:0]</obj_property>
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+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_1">
+ <obj_property name="ElementShortName">SR_1[0:94][11:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_1[0:94][11:0]</obj_property>
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+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_coefRegisterClellan">
+ <obj_property name="ElementShortName">SR_coefRegisterClellan[0:10][11:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_coefRegisterClellan[0:10][11:0]</obj_property>
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+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_3">
+ <obj_property name="ElementShortName">SR_3[0:10][11:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_3[0:10][11:0]</obj_property>
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+ <wvobject type="other" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_readAddress">
+ <obj_property name="ElementShortName">SR_readAddress</obj_property>
+ <obj_property name="ObjectShortName">SR_readAddress</obj_property>
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+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_sum">
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+ <obj_property name="ObjectShortName">SR_sum[30:0]</obj_property>
+ <obj_property name="Radix">SIGNEDDECRADIX</obj_property>
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new file mode 100644
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diff --git a/src-ref/.~lock.ADCSamplesOctave.csv# b/src-ref/.~lock.ADCSamplesOctave.csv#
new file mode 100644
index 0000000..8cd0338
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index 5580855..6f564ab 100644
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-9868,-8,-6
-9869,-11,-6
-9870,-12,-6
-9871,-11,-5
-9872,-10,-5
-9873,-9,-5
-9874,-6,-5
-9875,-4,-5
-9876,-3,-5
-9877,-5,-5
-9878,-8,-5
-9879,-10,-5
-9880,-8,-5
-9881,-10,-4
-9882,-9,-4
-9883,-6,-4
-9884,-6,-3
-9885,-3,-3
-9886,-3,-3
-9887,-3,-3
-9888,-3,-3
-9889,-4,-2
-9890,-8,-2
-9891,-8,-1
-9892,-7,0
-9893,-4,0
-9894,-4,1
-9895,-3,1
-9896,1,1
-9897,0,1
-9898,-4,2
-9899,-5,2
-9900,-3,2
-9901,-3,3
-9902,1,4
-9903,3,5
-9904,7,6
-9905,8,7
-9906,10,9
-9907,6,10
-9908,5,11
-9909,9,12
-9910,8,13
-9911,7,13
-9912,9,14
-9913,13,15
-9914,16,16
-9915,20,18
-9916,20,19
-9917,17,20
-9918,16,22
-9919,18,23
-9920,19,24
-9921,20,25
-9922,23,26
-9923,25,27
-9924,27,28
-9925,27,29
-9926,31,30
-9927,29,31
-9928,29,32
-9929,28,33
-9930,27,33
-9931,27,34
-9932,30,35
-9933,33,35
-9934,36,36
-9935,35,36
-9936,37,37
-9937,36,37
-9938,34,38
-9939,33,38
-9940,32,39
-9941,31,40
-9942,31,40
-9943,32,41
-9944,33,41
-9945,34,41
-9946,31,40
-9947,26,38
-9948,23,37
-9949,21,34
-9950,17,32
-9951,16,30
-9952,16,27
-9953,16,25
-9954,15,23
-9955,13,21
-9956,10,20
-9957,7,18
-9958,2,16
-9959,0,14
-9960,-3,12
-9961,-5,11
-9962,-2,9
-9963,0,8
-9964,-1,7
-9965,-2,7
-9966,-2,6
-9967,-7,5
-9968,-10,4
-9969,-12,3
-9970,-14,2
-9971,-14,1
-9972,-12,0
-9973,-11,-1
-9974,-10,-2
-9975,-9,-2
-9976,-9,-2
-9977,-15,-2
-9978,-19,-2
-9979,-17,-2
-9980,-19,-3
-9981,-17,-3
-9982,-15,-4
-9983,-13,-5
-9984,-12,-5
-9985,-11,-6
-9986,-11,-6
-9987,-16,-6
-9988,-19,-6
-9989,-21,-6
-9990,-21,-6
-9991,-19,-6
-9992,-18,-6
-9993,-14,-6
-9994,-14,-6
-9995,-11,-7
-9996,-12,-7
-9997,-13,-7
-9998,-16,-7
-9999,-16,-7
+50,-1,-12
\ No newline at end of file
diff --git a/src-ref/octaveScript.m b/src-ref/octaveScript.m
index e3f6181..05c72f5 100644
--- a/src-ref/octaveScript.m
+++ b/src-ref/octaveScript.m
@@ -5,13 +5,13 @@
Fs = 500; % Frequence d'echantillonnage
Fn = Fs/2; % Frequence de Nyquist
-%figure(1)
+figure(1)
T = csvread('./ADCSamplesOctave.csv');
-%subplot(2,3,1);plot(T(:,2));title('Raw ECG signal');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (output of an 11-bit ADC)');
+% subplot(2,3,1);plot(T(:,2));title('Raw ECG signal');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (output of an 11-bit ADC)');
% Pour Octave (à supprimer sous Matlab)
pkg load signal;
-
+fid = fopen("output.txt", "w");
% Pour les trois filtres suivants, on peut jouer sur les ordres
% donc le nombre de coefficients des filtres numériques
@@ -20,25 +20,36 @@ fBaseLine = fir1(128, 5/Fn, 'high'); % Génération du filtre
fBaseLine = round(fBaseLine * 2^10); % Normalisation et mise à l'échelle
y_minus_BL = filter(fBaseLine, [1], T(:,2)); % Application du filtre
+for i = 1:length(y_minus_BL)
+ fprintf(fid, "%f\n", y_minus_BL(i));
+end
+
% subplot(2,3,2);plot(y_minus_BL);title('Baseline wander reduced');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
% subplot(2,3,3);plot(y_minus_BL(1:1000));title('Baseline wander reduced -- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
+fprintf(fid, "----------------\n");
% Élimination du bruit à 50Hz par un coupe-bande basique (Notch FIR)
f50Hz = fir1(100, [45 55]/Fn, 'stop'); % Génération du filtre
f50Hz = round(f50Hz * 2^10); % Normalisation et mise à l'échelle
y_minus_50Hz_simple = filter(f50Hz, [1], y_minus_BL); % Application du filtre
-% subplot(2,3,4);plot(y_minus_50Hz_simple(1:1000));title('FIR1 band-cut-- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
+for i = 1:length(y_minus_50Hz_simple)
+ fprintf(fid, "%f\n", y_minus_50Hz_simple(i));
+end
+% subplot(2,3,4);plot(y_minus_50Hz_simple(1:1000));title('FIR1 band-cut-- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
+fprintf(fid, "----------------\n");
% Élimination du bruit à 50Hz par un coupe-bande plus élaboré (Pei-Tseng) IIR
[b, a] = pei_tseng_notch(50 / Fn, 10/Fn);
b = round(b * 2^10);
a = round(a * 2^10);
y_minus_50Hz_pei_tseng = filter(b, a, y_minus_BL);
-
+for i = 1:length(y_minus_50Hz_pei_tseng)
+ fprintf(fid, "%f\n", y_minus_50Hz_pei_tseng(i));
+end
% subplot(2,3,5);plot(y_minus_50Hz_pei_tseng(1:1000));title('Pei Tseng band-cut -- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
-
+fprintf(fid, "----------------\n");
% Lissage du bruit haute fréquence par filtre de Parks-McClellan (Low-pass FIR)
Fpass = 50;
Fstop = 60;
@@ -48,10 +59,11 @@ fLP = remez(10, F, A); % Génération du filtre
fLP = round(fLP * 2^10); % Normalisation et mise à l'échelle
yLP = filter(fLP, [1], y_minus_50Hz_pei_tseng); % Application du filtre
+
% subplot(2,3,6);plot(yLP(1:1000));title('Low-pass filter to suppress high-freq noise -- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
-% figure(2)
+figure(2)
% subplot(2,1,1);plot(T(:,2));title('Raw ECG signal');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
-% subplot(2,1,2);plot(yLP);title('After 3 filters');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
+subplot(2,1,2);plot(yLP);title('After 3 filters');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
% print(2, "ECG_raw_3filters.pdf", "-dpdflatexstandalone");
% figure(3)
@@ -62,34 +74,37 @@ yLP = filter(fLP, [1], y_minus_50Hz_pei_tseng); % Application du filtre
% EXPORT DES COEFFICIENTS POUR VHDL
% Conversion en entiers signés et exportation
-printf("\n--- Coefficients du filtre Baseline ---\n");
-fid = fopen("coeficientes_vhdl.txt", "w");
+%printf("\n--- Coefficients du filtre Baseline ---\n");
+
-fprintf(fid, "\n--- Coefficients du filtre Baseline ---\n");
-for i = 1:length(fBaseLine)
- fprintf(fid, "to_signed(%d, 11),\n", fBaseLine(i));
+for i = 1:length(yLP)
+ fprintf(fid, "%f\n", yLP(i));
end
+%fprintf(fid, "\n--- Coefficients du filtre Baseline ---\n");
+%for i = 1:length(fBaseLine)
+% fprintf(fid, "to_signed(%d, 11),\n", fBaseLine(i));
+%end
%fprintf(fid, "\n--- Coefficients du filtre Notch 50Hz ---\n");
%for i = 1:length(f50Hz)
% fprintf(fid, "to_signed(%d, 11),\n", f50Hz(i));
%end
-fprintf(fid, "\n--- Coefficients du filtre Pei-Tseng A ---\n");
-for i = 1:length(a)
- fprintf(fid, "to_signed(%d, 11),\n", a(i));
-end
+%fprintf(fid, "\n--- Coefficients du filtre Pei-Tseng A ---\n");
+%for i = 1:length(a)
+% fprintf(fid, "to_signed(%d, 11),\n", a(i));
+%end
-fprintf(fid, "\n--- Coefficients du filtre Pei-Tseng B ---\n");
-for i = 1:length(b)
- fprintf(fid, "to_signed(%d, 11),\n", b(i));
-end
+%fprintf(fid, "\n--- Coefficients du filtre Pei-Tseng B ---\n");
+%for i = 1:length(b)
+% fprintf(fid, "to_signed(%d, 11),\n", b(i));
+%end
-fprintf(fid, "\n--- Coefficients du filtre Parks-McClellan ---\n");
-for i = 1:length(fLP)
- fprintf(fid, "to_signed(%d, 11),\n", fLP(i));
-end
+%fprintf(fid, "\n--- Coefficients du filtre Parks-McClellan ---\n");
+%for i = 1:length(fLP)
+% fprintf(fid, "to_signed(%d, 11),\n", fLP(i));
+%end
fclose(fid);
-printf("\nThe coefficients were saved in 'coeficientes_vhdl.txt'.\n");
+printf("\nThe coefficients were saved in 'ouutput.txt'.\n");
diff --git a/src-ref/output.txt b/src-ref/output.txt
new file mode 100644
index 0000000..676bef7
--- /dev/null
+++ b/src-ref/output.txt
@@ -0,0 +1,155 @@
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
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+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+-1023.000000
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+-1059.000000
+-1159.000000
+-1321.000000
+-1540.000000
+-2574.000000
+-2702.000000
+-2993.000000
+-4302.000000
+-4455.000000
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+-5821.000000
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+-7614.000000
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+-9218.000000
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+-11165.000000
+-11579.000000
+-13030.000000
+-13626.000000
+-15066.000000
+-16670.000000
+-17076.000000
+-18706.000000
+-19163.000000
+-20848.000000
+-22376.000000
+-22815.000000
+-24486.000000
+-25107.000000
+-26763.000000
+----------------
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+-960.061523
+-864.547468
+-872.452714
+-1007.332459
+-1239.158748
+-1526.348123
+-2549.174401
+-2606.297610
+-2846.246141
+-4067.323776
+-4140.389023
+-4406.900503
+-5573.617605
+-5896.029304
+-7421.085495
+-7672.679270
+-8959.869041
+-9461.613461
+-10816.884559
+-11216.276690
+-12680.642116
+-13298.928376
+-14763.135468
+-16322.915784
+-16705.625600
+-18338.983129
+-18818.738886
+-20533.539416
+-22021.385226
+-22451.647252
+-24137.255157
+-24777.309502
+-26451.984462
+----------------
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
+0.000000
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+0.000000
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+114247.321289
+-14246.357145
+-144702.085156
+-298755.992162
+-487532.594174
+-711115.377321
+-880672.932992
+-1279887.865637
+-1676778.876275
+-2019815.453374
+-2459984.642114
+-3063931.113446
+-3605668.175116
+-4359910.585321
+-4975847.759287
+-5901455.796777
+-6565906.580186
+-7622323.465723
+-8629709.882135
+-9688511.022544
+-10815685.573006
+-12166970.780497
+-13255531.154205
+-14578966.245634
+-15929506.296283
+-17334591.013759
+-18827595.832633
+-20285559.871650
+-21715089.200852
+-23508573.761967
+-24912240.319270
+-26671912.997716
+-28123611.818423
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 19a3236..11451e8 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -72,10 +72,13 @@ BEGIN
O_initSum <= '1';
ELSE
SR_futurState <= BASELINE;
+ O_initAddress <= '0';
+ O_initSum <= '0';
END IF;
WHEN PROCESS_B =>
O_sel <= "01";
+ O_initAddress <= '0';
IF I_processingDoneB = '1' THEN
SR_futurState <= PROCESS_A;
O_initAddress <= '1';
@@ -85,20 +88,24 @@ BEGIN
WHEN PROCESS_A =>
O_sel <= "10";
+ O_initAddress <= '0';
IF I_processingDoneA = '1' THEN
SR_futurState <= CLELLAN;
O_initAddress <= '1';
O_initSum <= '1';
ELSE
SR_futurState <= PROCESS_A;
+ O_initSum <= '0';
END IF;
WHEN CLELLAN =>
O_sel <= "11";
+ O_initAddress <= '0';
IF I_processingDoneClellan = '1' THEN
SR_futurState <= OUTPUT;
ELSE
SR_futurState <= CLELLAN;
+ O_initSum <= '0';
END IF;
WHEN OUTPUT =>
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 4314419..2e86d5d 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -346,7 +346,7 @@ BEGIN
SR_2(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
ELSE
SR_2(1 TO 2) <= SR_2(0 TO 1);
- SR_2(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ SR_2(0) <= signed(SC_addResult(21 DOWNTO 10));
END IF;
ELSIF I_loadOutA = '1' THEN
@@ -370,6 +370,11 @@ BEGIN
END IF;
END PROCESS store_result;
+
+
+
+
+
O_total <= STD_LOGIC_VECTOR(SR_Y);
END ARCHITECTURE arch_operativeUnit;
\ No newline at end of file
--
GitLab