diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 30104db3d0a93037cef71602645bdad7c0783ed6..04d41050207f2f1653ac7ab0867c67b25e03d358 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -1,6 +1,6 @@
---
title: "Compte rendu Filtrage ECG"
-author: John Doe
+author: Antonio Pereira et Grazia Obuzor
geometry: margin=1cm
output: pdf_document
mainfont: sans-serif
diff --git a/proj/project_1/project_1.cache/wt/project.wpc b/proj/project_1/project_1.cache/wt/project.wpc
index 2599f423253c09ec78d9135689798dbecf72df68..d5e2b4001f9c4db17a4ca205e581a98ac102207d 100644
--- a/proj/project_1/project_1.cache/wt/project.wpc
+++ b/proj/project_1/project_1.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:7
+6d6f64655f636f756e7465727c4755494d6f6465:8
eof:
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
index efd020f8a0aa6e19722b0b0ea8334e86fb513b03..499c3828d94894c6b2b06b575b7139dd53c1c2ce 100755
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
-# Generated by Vivado on Wed Mar 19 12:17:57 CET 2025
+# Generated by Vivado on Wed Mar 26 11:56:40 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
index 4719baedd18cfa85cbec4036d82e5f11469ebab9..fe23dc1a8a5c227ead59a4e06f1923505c7e777b 100755
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
-# Generated by Vivado on Wed Mar 19 12:17:59 CET 2025
+# Generated by Vivado on Wed Mar 26 11:56:42 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
index ff133aa0a111e6c5f2e07a905d2894c53bd95f91..82547331e458d17be0b323d998fa377b70b9ef83 100755
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/simulate.sh
@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
-# Generated by Vivado on Wed Mar 19 12:10:35 CET 2025
+# Generated by Vivado on Wed Mar 26 09:31:13 CET 2025
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
index a8af8b06ea2374011d39abb4c0d2d4e29738ca4f..26161f3734521c5185699b75fad51b581a5e15fa 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
index b525d2a8c5bc7964216fd6097718956532508354..d72364e71dd2e80fd7eb757f5984fc1a1b132294 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
index 39a36f6187d919c27f1ebab4fd557768e1ecc837..d6a160cff81983e7824098fea2108a495fe0d0d3 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -67,7 +67,7 @@ IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_40(char*, char *);
-IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
IKI_DLLESPEC extern void execute_43(char*, char *);
IKI_DLLESPEC extern void execute_44(char*, char *);
IKI_DLLESPEC extern void execute_45(char*, char *);
@@ -79,16 +79,17 @@ IKI_DLLESPEC extern void execute_50(char*, char *);
IKI_DLLESPEC extern void execute_51(char*, char *);
IKI_DLLESPEC extern void execute_52(char*, char *);
IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
-funcp funcTab[27] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
-const int NumRelocateId= 27;
+funcp funcTab[28] = {(funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 28;
void relocate(char *dp)
{
- iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 27);
- iki_vhdl_file_variable_register(dp + 14376);
- iki_vhdl_file_variable_register(dp + 14432);
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 28);
+ iki_vhdl_file_variable_register(dp + 14656);
+ iki_vhdl_file_variable_register(dp + 14712);
/*Populate the transaction function pointer field in the whole net structure */
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
index fe67fb75df5711ff214bf141ee491e1ed7139cc2..752640816f42f3e991b3352775c7e734b65ec377 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
index 23a1881fd093e1a304fd812ed5b5e194ca4b6f41..de150cbd13fc0ad4c12fcf53bc906944052ece76 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
index 3f1952309329c20eac3a74309a530a40f92526e6..7bdecb7802fffa93eea75ef3fee51d33126e4473 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
index 6734ebc71e56c039cad59904a595b943da6a223c..2da91ee684f38f374d41fff03fd520f97ea12966 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
index 443009020e7658a33b20fc38f5379a923d5927f6..ff0d55c9238b7b707e447868b77fc5efe0ebc384 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -1,6 +1,6 @@
{
- crc : 1860796047234000762 ,
+ crc : 6953294578613318290 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
buildDate : "May 22 2024" ,
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
index 4628fee46f9074ed5be74eeadc7f308157bce7c1..3d3509f93c1257ce4df5d8e228c20146e09325af 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
index 6346d3fbb19c1f6c28f635a68462969c5d28a149..c81c7985a884b3ed3397168fe6c70f3ef17f4081 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
index f22e04bd8701eaa080c0afab0d143f5f92634744..4270cf904bf3c253018f41ccec247d4b2b0dce78 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
index b7c8cd7260f0e29ac9f852375b8a9f45a59b33cc..be3b30d5f5646706ec6ef3bde0d3159d937c1be3 100755
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
index 75defeda60874c1512fb09ad10467ede135d7e92..421be481e058ef4bfef81f4ae1f5cb1f3abf3637 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -1,4 +1,4 @@
-Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 33467
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 37683
Design successfully loaded
-Design Loading Memory Usage: 20188 KB (Peak: 20752 KB)
-Design Loading CPU Usage: 20 ms
+Design Loading Memory Usage: 20192 KB (Peak: 20756 KB)
+Design Loading CPU Usage: 30 ms
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
index c0f01b6cfefed94d77dd822592bd3968882a2a5c..7c4bb188894fe54a48119104e525a2da50913787 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
index e37c07e3bf2f1c9288fe46d269591a15428700dc..b03e2cc205f4176fbf3c178386de74e123fd07b2 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
index 5034304300ef6217f02a54d8c28453ea8904c7bf..5918b33dedc0f7d7f1a5c1e7ddb72b321df3f073 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
index cb3c90bfde65719280b6cce7d8f5cd3f2c841b24..24a4499d13828e5a1be3f4a5a371926382f82652 100644
Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
index 2b9362e605fc97d9af61e16ea94b24d46a868b76..df50f25d020ae877098bf8914045a766409b165c 100644
--- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -2,7 +2,7 @@
2020.2
May 22 2024
18:54:44
-/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742383073,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
-/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1742373132,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
-/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742376828,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742986595,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1742984386,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742986345,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1742373132,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/project_1/project_1.xpr b/proj/project_1/project_1.xpr
index a9628c09084928e0e1c9d795293593ae30f68064..20743aa28fb6091fb8be4d5199640df8fd0d33f2 100644
--- a/proj/project_1/project_1.xpr
+++ b/proj/project_1/project_1.xpr
@@ -60,7 +60,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
- <Option Name="WTXSimLaunchSim" Val="136"/>
+ <Option Name="WTXSimLaunchSim" Val="173"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -91,88 +91,79 @@
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
- <File Path="$PPRDIR/../../src/hdl/controlUnit.vhd">
+ <File Path="$PPRDIR/../../src/ip/clk_wiz_0/clk_wiz_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../src/hdl/operativeUnit.vhd">
+ <File Path="$PPRDIR/../../src/hdl/audio_init.v">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../src/hdl/firUnit.vhd">
+ <File Path="$PPRDIR/../../src/hdl/debounce.v">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../src/hdl/tb_firUnit.vhd">
- <FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <File Path="$PPRDIR/../../src/hdl/TWICtl.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../src/hdl/audio_init.v">
+ <File Path="$PPRDIR/../../src/hdl/controlUnit.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../src/hdl/debounce.v">
+ <File Path="$PPRDIR/../../src/hdl/operativeUnit.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../src/hdl/TWICtl.vhd">
+ <File Path="$PPRDIR/../../src/hdl/firUnit.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/hdl/fir.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/hdl/i2s_ctl.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/hdl/audioProc.v">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/../../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="controlUnit"/>
+ <Option Name="TopModule" Val="audioProc"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
diff --git a/src-ref/coeficientes_vhdl.txt b/src-ref/coeficientes_vhdl.txt
index c5fa44ba59590d7156cd0e610334816d19e92fde..73a01831972367c177b0c758c6ca6838826d3449 100644
--- a/src-ref/coeficientes_vhdl.txt
+++ b/src-ref/coeficientes_vhdl.txt
@@ -1,154 +1,154 @@
+
--- Coefficients du filtre Baseline ---
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-2, 12),
-to_signed(-2, 12),
-to_signed(-2, 12),
-to_signed(-3, 12),
-to_signed(-3, 12),
-to_signed(-3, 12),
-to_signed(-4, 12),
-to_signed(-4, 12),
-to_signed(-5, 12),
-to_signed(-5, 12),
-to_signed(-6, 12),
-to_signed(-6, 12),
-to_signed(-7, 12),
-to_signed(-7, 12),
-to_signed(-8, 12),
-to_signed(-8, 12),
-to_signed(-9, 12),
-to_signed(-10, 12),
-to_signed(-10, 12),
-to_signed(-11, 12),
-to_signed(-11, 12),
-to_signed(-12, 12),
-to_signed(-13, 12),
-to_signed(-13, 12),
-to_signed(-14, 12),
-to_signed(-14, 12),
-to_signed(-15, 12),
-to_signed(-15, 12),
-to_signed(-16, 12),
-to_signed(-16, 12),
-to_signed(-17, 12),
-to_signed(-17, 12),
-to_signed(-18, 12),
-to_signed(-18, 12),
-to_signed(-18, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(1004, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-19, 12),
-to_signed(-18, 12),
-to_signed(-18, 12),
-to_signed(-18, 12),
-to_signed(-17, 12),
-to_signed(-17, 12),
-to_signed(-16, 12),
-to_signed(-16, 12),
-to_signed(-15, 12),
-to_signed(-15, 12),
-to_signed(-14, 12),
-to_signed(-14, 12),
-to_signed(-13, 12),
-to_signed(-13, 12),
-to_signed(-12, 12),
-to_signed(-11, 12),
-to_signed(-11, 12),
-to_signed(-10, 12),
-to_signed(-10, 12),
-to_signed(-9, 12),
-to_signed(-8, 12),
-to_signed(-8, 12),
-to_signed(-7, 12),
-to_signed(-7, 12),
-to_signed(-6, 12),
-to_signed(-6, 12),
-to_signed(-5, 12),
-to_signed(-5, 12),
-to_signed(-4, 12),
-to_signed(-4, 12),
-to_signed(-3, 12),
-to_signed(-3, 12),
-to_signed(-3, 12),
-to_signed(-2, 12),
-to_signed(-2, 12),
-to_signed(-2, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(-1, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
-to_signed(0, 12),
+to_signed(0.000248934, 12),
+to_signed(0.000235534, 12),
+to_signed(0.000223576, 12),
+to_signed(0.000212292, 12),
+to_signed(0.000200809, 12),
+to_signed(0.000188151, 12),
+to_signed(0.000173245, 12),
+to_signed(0.000154933, 12),
+to_signed(0.00013198, 12),
+to_signed(0.000103086, 12),
+to_signed(6.6897e-05, 12),
+to_signed(2.20169e-05, 12),
+to_signed(-3.2976e-05, 12),
+to_signed(-9.95164e-05, 12),
+to_signed(-0.000179037, 12),
+to_signed(-0.000272952, 12),
+to_signed(-0.000382643, 12),
+to_signed(-0.000509443, 12),
+to_signed(-0.000654618, 12),
+to_signed(-0.000819357, 12),
+to_signed(-0.00100475, 12),
+to_signed(-0.00121178, 12),
+to_signed(-0.0014413, 12),
+to_signed(-0.00169404, 12),
+to_signed(-0.00197056, 12),
+to_signed(-0.00227127, 12),
+to_signed(-0.00259641, 12),
+to_signed(-0.00294604, 12),
+to_signed(-0.00332004, 12),
+to_signed(-0.00371808, 12),
+to_signed(-0.00413964, 12),
+to_signed(-0.00458402, 12),
+to_signed(-0.00505029, 12),
+to_signed(-0.00553735, 12),
+to_signed(-0.00604389, 12),
+to_signed(-0.00656841, 12),
+to_signed(-0.00710922, 12),
+to_signed(-0.00766448, 12),
+to_signed(-0.00823214, 12),
+to_signed(-0.00881004, 12),
+to_signed(-0.00939584, 12),
+to_signed(-0.0099871, 12),
+to_signed(-0.0105813, 12),
+to_signed(-0.0111756, 12),
+to_signed(-0.0117675, 12),
+to_signed(-0.0123541, 12),
+to_signed(-0.0129326, 12),
+to_signed(-0.0135001, 12),
+to_signed(-0.0140537, 12),
+to_signed(-0.0145907, 12),
+to_signed(-0.0151082, 12),
+to_signed(-0.0156035, 12),
+to_signed(-0.016074, 12),
+to_signed(-0.0165172, 12),
+to_signed(-0.0169306, 12),
+to_signed(-0.017312, 12),
+to_signed(-0.0176592, 12),
+to_signed(-0.0179703, 12),
+to_signed(-0.0182437, 12),
+to_signed(-0.0184776, 12),
+to_signed(-0.0186709, 12),
+to_signed(-0.0188223, 12),
+to_signed(-0.0189311, 12),
+to_signed(-0.0189967, 12),
+to_signed(0.980725, 12),
+to_signed(-0.0189967, 12),
+to_signed(-0.0189311, 12),
+to_signed(-0.0188223, 12),
+to_signed(-0.0186709, 12),
+to_signed(-0.0184776, 12),
+to_signed(-0.0182437, 12),
+to_signed(-0.0179703, 12),
+to_signed(-0.0176592, 12),
+to_signed(-0.017312, 12),
+to_signed(-0.0169306, 12),
+to_signed(-0.0165172, 12),
+to_signed(-0.016074, 12),
+to_signed(-0.0156035, 12),
+to_signed(-0.0151082, 12),
+to_signed(-0.0145907, 12),
+to_signed(-0.0140537, 12),
+to_signed(-0.0135001, 12),
+to_signed(-0.0129326, 12),
+to_signed(-0.0123541, 12),
+to_signed(-0.0117675, 12),
+to_signed(-0.0111756, 12),
+to_signed(-0.0105813, 12),
+to_signed(-0.0099871, 12),
+to_signed(-0.00939584, 12),
+to_signed(-0.00881004, 12),
+to_signed(-0.00823214, 12),
+to_signed(-0.00766448, 12),
+to_signed(-0.00710922, 12),
+to_signed(-0.00656841, 12),
+to_signed(-0.00604389, 12),
+to_signed(-0.00553735, 12),
+to_signed(-0.00505029, 12),
+to_signed(-0.00458402, 12),
+to_signed(-0.00413964, 12),
+to_signed(-0.00371808, 12),
+to_signed(-0.00332004, 12),
+to_signed(-0.00294604, 12),
+to_signed(-0.00259641, 12),
+to_signed(-0.00227127, 12),
+to_signed(-0.00197056, 12),
+to_signed(-0.00169404, 12),
+to_signed(-0.0014413, 12),
+to_signed(-0.00121178, 12),
+to_signed(-0.00100475, 12),
+to_signed(-0.000819357, 12),
+to_signed(-0.000654618, 12),
+to_signed(-0.000509443, 12),
+to_signed(-0.000382643, 12),
+to_signed(-0.000272952, 12),
+to_signed(-0.000179037, 12),
+to_signed(-9.95164e-05, 12),
+to_signed(-3.2976e-05, 12),
+to_signed(2.20169e-05, 12),
+to_signed(6.6897e-05, 12),
+to_signed(0.000103086, 12),
+to_signed(0.00013198, 12),
+to_signed(0.000154933, 12),
+to_signed(0.000173245, 12),
+to_signed(0.000188151, 12),
+to_signed(0.000200809, 12),
+to_signed(0.000212292, 12),
+to_signed(0.000223576, 12),
+to_signed(0.000235534, 12),
+to_signed(0.000248934, 12),
--- Coefficients du filtre Pei-Tseng A ---
-to_signed(1024, 12),
-to_signed(-1554, 12),
-to_signed(897, 12),
+to_signed(1, 12),
+to_signed(-1.518, 12),
+to_signed(0.876349, 12),
--- Coefficients du filtre Pei-Tseng B ---
-to_signed(961, 12),
-to_signed(-1554, 12),
-to_signed(961, 12),
+to_signed(0.938174, 12),
+to_signed(-1.518, 12),
+to_signed(0.938174, 12),
--- Coefficients du filtre Parks-McClellan ---
-to_signed(-119, 12),
-to_signed(122, 12),
-to_signed(149, 12),
-to_signed(191, 12),
-to_signed(226, 12),
-to_signed(239, 12),
-to_signed(226, 12),
-to_signed(191, 12),
-to_signed(149, 12),
-to_signed(122, 12),
-to_signed(-119, 12),
-
+to_signed(-0.115972, 12),
+to_signed(0.118981, 12),
+to_signed(0.145393, 12),
+to_signed(0.186638, 12),
+to_signed(0.220579, 12),
+to_signed(0.233469, 12),
+to_signed(0.220579, 12),
+to_signed(0.186638, 12),
+to_signed(0.145393, 12),
+to_signed(0.118981, 12),
+to_signed(-0.115972, 12),
diff --git a/src-ref/octaveScript.m b/src-ref/octaveScript.m
index 00936127084a36df820e26d28f31929aaf41edbe..728679ccc6a9e48424ee7599c70b9bde9cb3fd2f 100644
--- a/src-ref/octaveScript.m
+++ b/src-ref/octaveScript.m
@@ -18,7 +18,6 @@ pkg load signal;
% Suppression de la baseline (High-pass FIR)
fBaseLine = fir1(128, 5/Fn, 'high'); % Génération du filtre
-fBaseLine = round(fBaseLine * 2^10); % Normalisation et mise à l'échelle
y_minus_BL = filter(fBaseLine, [1], T(:,2)); % Application du filtre
fprintf(fid, "\n--- 1er Filtre ---\n");
for i = 1:length(y_minus_BL)
@@ -37,8 +36,6 @@ y_minus_50Hz_simple = filter(f50Hz, [1], y_minus_BL); % Application du filtre
% Élimination du bruit à 50Hz par un coupe-bande plus élaboré (Pei-Tseng) IIR
[b, a] = pei_tseng_notch(50 / Fn, 10/Fn);
-b = round(b * 2^10);
-a = round(a * 2^10);
y_minus_50Hz_pei_tseng = filter(b, a, y_minus_BL);
fprintf(fid, "\n--- 2eme Filtre ---\n");
for i = 1:length(y_minus_50Hz_pei_tseng)
@@ -53,7 +50,6 @@ Fstop = 60;
F = [0 Fpass Fstop Fn]/(Fn);
A = [1 1 0 0];
fLP = remez(10, F, A); % Génération du filtre
-fLP = round(fLP * 2^10); % Normalisation et mise à l'échelle
yLP = filter(fLP, [1], y_minus_50Hz_pei_tseng); % Application du filtre
fprintf(fid, "\n--- 3eme Filtre ---\n");
for i = 1:length(yLP)
@@ -105,4 +101,4 @@ for i = 1:length(fLP)
end
fclose(fid);
-printf("\nThe coefficients were saved in 'coeficientes_vhdl.txt'.\n");
\ No newline at end of file
+printf("\nThe coefficients were saved in 'coeficientes_vhdl.txt'.\n");
diff --git a/src-ref/output.txt b/src-ref/output.txt
index 21ce3c48dd8d315049e2d72f8c46a2959247e888..968630c9b6c42ec6026e0f6d46c726d04782ba9a 100644
--- a/src-ref/output.txt
+++ b/src-ref/output.txt
@@ -1,22 +1,4 @@
--- 1er Filtre ---
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-1023.000000
-1023.000000
-1059.000000
@@ -28,93 +10,7 @@
-2993.000000
-4302.000000
-4455.000000
--4699.000000
--5821.000000
--6097.000000
--7614.000000
--7894.000000
--9218.000000
--9767.000000
--11165.000000
--11579.000000
--13030.000000
--13626.000000
--15066.000000
--16670.000000
--17076.000000
--18706.000000
--19163.000000
--20848.000000
--22376.000000
--22815.000000
--24486.000000
--25107.000000
--26763.000000
--27235.000000
--28672.000000
--29249.000000
--30797.000000
--31295.000000
--32649.000000
--33143.000000
--33465.000000
--34981.000000
--35255.000000
--35672.000000
--35878.000000
--36196.000000
--36506.000000
-1009986.000000
--36510.000000
-227.000000
-65667.000000
-129260.000000
-187725.000000
--24898.000000
-95964.000000
-226027.000000
-155609.000000
--42624.000000
--44390.000000
--44026.000000
--45860.000000
--46468.000000
--46823.000000
--44298.000000
--41741.000000
--34058.000000
--35431.000000
--32899.000000
--30215.000000
--29766.000000
--31178.000000
--31720.000000
--28999.000000
--27477.000000
--27051.000000
--23356.000000
--21751.000000
--21176.000000
-
--- 2eme Filtre ---
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-960.061523
-864.547468
-872.452714
@@ -126,93 +22,7 @@
-2846.246141
-4067.323776
-4140.389023
--4406.900503
--5573.617605
--5896.029304
--7421.085495
--7672.679270
--8959.869041
--9461.613461
--10816.884559
--11216.276690
--12680.642116
--13298.928376
--14763.135468
--16322.915784
--16705.625600
--18338.983129
--18818.738886
--20533.539416
--22021.385226
--22451.647252
--24137.255157
--24777.309502
--26451.984462
--26945.407453
--28413.650507
--29013.299221
--30562.876450
--31048.854104
--32396.674904
--32892.561201
--33287.651091
--34850.523827
--35134.899412
--35595.680482
--35863.484079
--36243.422721
--36587.083681
-945504.429824
--134330.197257
--28628.288173
-101243.111443
-200587.752612
-257361.297455
-27909.642727
-120932.736309
-202198.667674
-93999.765719
--98498.703102
--62759.394014
--22913.429312
-2318.223906
-8259.347698
--5958.507345
--30401.698534
--56807.002377
--69767.929793
--76855.118913
--64586.840592
--42372.723257
--20683.370049
--6714.778608
--2460.172874
--6188.641831
--18783.442712
--33987.353762
--41778.182259
--43984.508697
--38936.616240
-
--- 3eme Filtre ---
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
-0.000000
114247.321289
-14246.357145
-144702.085156
@@ -223,71 +33,4 @@
-1279887.865637
-1676778.876275
-2019815.453374
--2459984.642114
--3063931.113446
--3605668.175116
--4359910.585321
--4975847.759287
--5901455.796777
--6565906.580186
--7622323.465723
--8629709.882135
--9688511.022544
--10815685.573006
--12166970.780497
--13255531.154205
--14578966.245634
--15929506.296283
--17334591.013759
--18827595.832633
--20285559.871650
--21715089.200852
--23508573.761967
--24912240.319270
--26671912.997716
--28123611.818423
--29722983.682499
--31353008.136208
--32902754.809049
--34472904.986410
--35993833.420082
--37315223.769529
--38956645.652377
--40310388.190944
--41601726.977095
--42877312.450321
--44215259.181000
--45315046.097985
--46432718.247961
--47263601.975037
--165063443.613073
-82635864.183488
-84053126.781316
-107675150.530836
-143014781.783280
-178383412.365290
-239883069.049862
-226339160.255684
-222139075.017194
-260039255.056026
-75733340.776994
-206132419.639837
-174057111.478851
-121765868.649610
-64585776.846645
-10622692.372057
-21639753.788805
--9925315.537044
--46310786.614378
--49416044.621109
--28270924.616315
--42469458.655877
--60124038.423241
--73218879.682026
--77523797.032443
--71686328.428358
--57954422.972234
--41215339.851185
--28781460.064110
--21016584.151478
--21577312.032120
\ No newline at end of file
+-2459984.642114
\ No newline at end of file
diff --git a/src-ref/values.txt b/src-ref/values.txt
new file mode 100644
index 0000000000000000000000000000000000000000..f776c5749c79258f4a1e262edea4fe4f80fdc3eb
--- /dev/null
+++ b/src-ref/values.txt
@@ -0,0 +1,294 @@
+
+--- 1er Filtre ---
+0.000000
+0.254659
+0.240952
+0.237680
+0.250547
+0.277357
+0.315152
+0.296227
+0.303160
+0.335177
+0.340133
+0.285914
+0.221107
+0.143385
+0.049808
+-0.062376
+-0.195714
+-0.352533
+-0.535413
+-0.746148
+-0.989481
+-1.267185
+-1.581678
+-1.935447
+-2.331259
+-2.770357
+-3.253755
+-3.782953
+-4.358871
+-4.981596
+-5.651633
+-6.369350
+-7.133707
+-7.943551
+-8.798338
+-9.696579
+-10.636130
+-11.613952
+-12.626899
+-13.670463
+-14.742323
+-15.838495
+-16.954176
+-18.085784
+-19.228423
+-20.377712
+-21.527787
+-22.672407
+-23.806241
+-24.922858
+-26.016814
+-27.082638
+-28.114382
+-29.106438
+-30.054815
+-30.953362
+-31.796188
+-32.578932
+-33.296745
+-33.944863
+-34.519403
+-35.016868
+-35.434672
+-35.771148
+-36.023550
+986.548367
+-36.268790
+-0.269212
+63.812770
+125.983143
+183.242268
+-24.344727
+93.068352
+220.560238
+152.179738
+-42.094194
+-43.346832
+-43.533527
+-44.656672
+-45.721622
+-45.735285
+-43.703784
+-40.631964
+-33.527439
+-34.394348
+-32.240548
+-30.072455
+-28.895738
+-30.715828
+-30.539912
+-28.374813
+-27.226408
+-26.100386
+-23.003996
+-20.941892
+-20.918707
+
+--- 2eme Filtre ---
+0.000000
+0.238915
+0.202155
+0.193633
+0.217092
+0.262718
+0.318254
+0.312600
+0.326035
+0.353146
+0.345077
+0.280718
+0.216245
+0.149371
+0.073745
+-0.018563
+-0.135004
+-0.280832
+-0.458772
+-0.668306
+-0.910409
+-1.183157
+-1.486805
+-1.823753
+-2.198505
+-2.615101
+-3.077383
+-3.588673
+-4.150194
+-4.760975
+-5.419678
+-6.124786
+-6.874102
+-7.666469
+-8.502315
+-9.381656
+-10.303874
+-11.267028
+-12.268360
+-13.303083
+-14.368059
+-15.458277
+-16.568241
+-17.694200
+-18.831606
+-19.976808
+-21.124807
+-22.270145
+-23.407892
+-24.531552
+-25.635234
+-26.712791
+-27.757669
+-28.763942
+-29.727542
+-30.642521
+-31.503476
+-32.306499
+-33.046937
+-33.719952
+-34.321316
+-34.846995
+-35.293812
+-35.659556
+-35.941189
+923.370083
+-132.230318
+-29.561827
+97.254806
+194.613010
+250.731585
+27.254335
+117.826502
+197.782890
+92.252396
+-96.864115
+-61.881664
+-23.582825
+1.952415
+7.682389
+-5.447232
+-29.471891
+-54.649883
+-67.907873
+-74.684838
+-63.351745
+-42.257873
+-20.335714
+-7.003274
+-1.944215
+-5.891804
+-18.361907
+-32.487668
+-40.729324
+-42.570347
+-38.346013
+
+--- 3eme Filtre ---
+0.000000
+-0.027707
+0.004982
+0.036333
+0.071844
+0.113944
+0.162423
+0.222936
+0.276962
+0.326497
+0.381124
+0.386919
+0.419694
+0.437563
+0.434232
+0.407084
+0.355001
+0.291214
+0.202308
+0.084239
+-0.058197
+-0.222804
+-0.422032
+-0.660250
+-0.939864
+-1.262267
+-1.628481
+-2.039989
+-2.499375
+-3.010511
+-3.577163
+-4.203398
+-4.892473
+-5.646155
+-6.464541
+-7.346939
+-8.292083
+-9.298471
+-10.364711
+-11.489804
+-12.672181
+-13.910098
+-15.201229
+-16.541986
+-17.927798
+-19.353210
+-20.812477
+-22.299658
+-23.808534
+-25.333279
+-26.867377
+-28.404332
+-29.937490
+-31.459405
+-32.962188
+-34.437911
+-35.878618
+-37.276302
+-38.623212
+-39.912145
+-41.136025
+-42.288122
+-43.362029
+-44.351564
+-45.250762
+-157.330050
+78.537243
+79.952945
+102.602535
+135.617139
+169.231066
+227.351267
+214.698596
+210.384598
+246.534802
+71.469836
+195.917420
+165.745137
+115.824914
+61.377840
+9.722329
+20.067901
+-10.049809
+-44.573806
+-47.464148
+-26.883722
+-40.218340
+-56.990862
+-69.563066
+-73.864904
+-68.442221
+-55.383611
+-39.674623
+-27.569247
+-20.173520
+-20.402409
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 32222792b4fe7edb725590c8a51690feff59987e..63bf1c9ce3e747972fdb1ff18c7b5675841032bc 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -18,6 +18,7 @@ ENTITY controlUnit IS
O_initSum : OUT STD_LOGIC;
O_loadSum : OUT STD_LOGIC;
O_loadOutA : OUT STD_LOGIC;
+ O_loadOutB : OUT STD_LOGIC;
O_loadOutBL : OUT STD_LOGIC;
O_loadOutClellan : OUT STD_LOGIC;
O_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -82,9 +83,11 @@ BEGIN
IF I_processingDoneB = '1' THEN
SR_futurState <= PROCESS_A;
O_initAddress <= '1';
+ O_initSum <= '1';
ELSE
SR_futurState <= PROCESS_B;
O_initAddress <= '0';
+ O_initSum <= '0';
END IF;
WHEN PROCESS_A =>
@@ -105,6 +108,7 @@ BEGIN
O_initAddress <= '0';
IF I_processingDoneClellan = '1' THEN
SR_futurState <= OUTPUT;
+ O_initSum <= '1';
ELSE
SR_futurState <= CLELLAN;
O_initSum <= '0';
@@ -136,6 +140,8 @@ BEGIN
'0';
O_loadOutA <= '1' WHEN SR_presentState = PROCESS_A ELSE
'0';
+ O_loadOutB <= '1' WHEN SR_presentState = PROCESS_B ELSE
+ '0';
O_loadOutClellan <= '1' WHEN SR_presentState = OUTPUT ELSE
'0';
O_FilteredSampleValid <= '1' WHEN SR_presentState = OUTPUT ELSE
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 7ac25d014af2c2598435ad169a85cec99231ebbf..311dfa7cb12511f8344ea84e08ae3d33b5979eb8 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -52,6 +52,7 @@ architecture archi_firUnit of firUnit is
O_incrAddress : out std_logic; -- Control signal to increment register read address
O_initSum : out std_logic; -- Control signal to initialize the MAC register
O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadOutB : out std_logic; -- Control signal to load 2A register
O_loadOutA : out std_logic; -- Control signal to load Y register
O_loadOutBL : out std_logic;
O_loadOutClellan : out std_logic;
@@ -71,6 +72,7 @@ architecture archi_firUnit of firUnit is
I_initSum : in std_logic; -- Control signal to initialize the MAC register
I_loadSum : in std_logic; -- Control signal to load the MAC register;
I_loadOutA : in std_logic; -- Control signal to load Y register coefficients A
+ I_loadOutB : in std_logic;
I_loadOutBL : in std_logic;
I_loadOutClellan : in std_logic;
O_processingDoneA : out std_logic; -- Indicate that processing is done
@@ -91,6 +93,7 @@ architecture archi_firUnit of firUnit is
signal SC_initSum : std_logic;
signal SC_loadSum : std_logic;
signal SC_loadOutA : std_logic;
+ signal SC_loadOutB : std_logic;
signal SC_loadOutBaseLine: std_logic;
signal SC_loadOutLissage : std_logic;
signal SC_sel : std_logic_vector(1 downto 0);
@@ -112,6 +115,7 @@ begin
O_initSum => SC_initSum,
O_loadSum => SC_loadSum,
O_loadOutA => SC_loadOutA,
+ O_loadOutB => SC_loadOutB,
O_loadOutBL => SC_loadOutBaseLine,
O_loadOutClellan => SC_loadOutLissage,
O_sel => SC_sel,
@@ -129,6 +133,7 @@ begin
I_initSum => SC_initSum,
I_loadSum => SC_loadSum,
I_loadOutA => SC_loadOutA,
+ I_loadOutB => SC_loadOutB,
I_loadOutBL => SC_loadOutBaseLine,
I_loadOutClellan => SC_loadOutLissage,
O_processingDoneA => SC_processingDoneA,
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 767e423ac558a60f0b0960f16968b779e6ac0a28..e417b2871df7d34da1879d33e20abdccefb636e3 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -15,6 +15,7 @@ ENTITY operativeUnit IS
I_initSum : IN STD_LOGIC;
I_loadSum : IN STD_LOGIC;
I_loadOutA : IN STD_LOGIC;
+ I_loadOutB : IN STD_LOGIC;
I_loadOutBL : IN STD_LOGIC;
I_loadOutClellan : IN STD_LOGIC;
O_processingDoneA : OUT STD_LOGIC;
@@ -27,7 +28,7 @@ ENTITY operativeUnit IS
END ENTITY operativeUnit;
ARCHITECTURE arch_operativeUnit OF operativeUnit IS
- TYPE registerFileA IS ARRAY(0 TO 1) OF signed(11 DOWNTO 0);
+ TYPE registerFileA IS ARRAY(0 TO 2) OF signed(11 DOWNTO 0);
SIGNAL SR_coefRegisterA : registerFileA;
SIGNAL SR_2A : registerFileA;
@@ -52,7 +53,8 @@ ARCHITECTURE arch_operativeUnit OF operativeUnit IS
SIGNAL SR_readAddress : INTEGER RANGE 0 TO 94;
BEGIN
- SR_coefRegisterA <= (to_signed(1554, 12),
+ SR_coefRegisterA <= (to_signed(-1024, 12),
+ to_signed(1554, 12),
to_signed(-897, 12)
);
@@ -220,7 +222,7 @@ BEGIN
IF I_initAddress = '1' THEN
SR_readAddress <= 0;
ELSIF I_incrAddress = '1' THEN
- IF SR_readAddress = 1 THEN
+ IF SR_readAddress = 2 THEN
SR_readAddress <= 0;
ELSE
SR_readAddress <= SR_readAddress + 1;
@@ -349,6 +351,15 @@ BEGIN
SR_2(0) <= signed(SC_addResult(21 DOWNTO 10));
END IF;
+ ELSIF I_loadOutB = '1' THEN
+ IF SC_addResult(9) = '1' THEN
+ SR_2A(1 TO 2) <= SR_2A(0 TO 1);
+ SR_2A(0) <= signed(SC_addResult(21 DOWNTO 10) + 1);
+ ELSE
+ SR_2A(1 TO 2) <= SR_2A(0 TO 1);
+ SR_2A(0) <= signed(SC_addResult(21 DOWNTO 10));
+ END IF;
+
ELSIF I_loadOutA = '1' THEN
SR_3(1 TO 10) <= SR_3(0 TO 9);
IF SC_addResult(9) = '1' THEN
@@ -356,8 +367,7 @@ BEGIN
ELSE
SR_3(0) <= signed(SC_addResult(21 DOWNTO 10));
END IF;
-
- SR_2A(1) <= SR_2A(0);
+
ELSIF I_loadOutClellan = '1' THEN
IF SC_addResult(9) = '1' THEN
SR_Y <= SC_addResult(21 DOWNTO 10) + 1;