diff --git a/proj/project_1/project_1.cache/wt/xsim.wdf b/proj/project_1/project_1.cache/wt/xsim.wdf index 50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af..51d5206f7011f2f0764fb661278617e58456141a 100644 --- a/proj/project_1/project_1.cache/wt/xsim.wdf +++ b/proj/project_1/project_1.cache/wt/xsim.wdf @@ -1,4 +1,4 @@ version:1 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 -eof:241934075 +eof:2427094519 diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.log deleted file mode 100644 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000 diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh index 2132d719e2e57fed5e2041430402fee65c188b27..efd020f8a0aa6e19722b0b0ea8334e86fb513b03 100755 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Wed Mar 19 12:10:31 CET 2025 +# Generated by Vivado on Wed Mar 19 12:17:57 CET 2025 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log index b369c9ef3036e148fe1daa403d0d1151d89b30b6..14b10ae3242e717166337534eaa6636a2bc93613 100644 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log @@ -5,4 +5,15 @@ Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr Using 8 slave threads. Starting static elaboration Completed static elaboration -INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default] +Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default] +Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default] +Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit +Built simulation snapshot tb_firUnit_behav diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh index 2ed28f0e2e0f595522bcb167c8452eb320591b01..4719baedd18cfa85cbec4036d82e5f11469ebab9 100755 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Wed Mar 19 12:10:33 CET 2025 +# Generated by Vivado on Wed Mar 19 12:17:59 CET 2025 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb index 93b63658819aa0d028878e6792a9bd0a6ee82ae1..a8af8b06ea2374011d39abb4c0d2d4e29738ca4f 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb index 69277267d44ed0eaddbb787cc9913c3355401ddc..18bc397722d8cbecf2c3bcb3c901fc360d316f1d 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o index 0c467ec22647fa3bbd2f72f3eadc8780fb02b4d3..b525d2a8c5bc7964216fd6097718956532508354 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg index ac351a38954928972aaf8ca72f9e675ddbb45a68..23a1881fd093e1a304fd812ed5b5e194ca4b6f41 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem index 43cfbf4930e3bcc5f08da9c7ce1a07826d608eb1..3f1952309329c20eac3a74309a530a40f92526e6 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx index 2e5884e2c55ab5351c58bb9acf75facb1cea0e2d..443009020e7658a33b20fc38f5379a923d5927f6 100644 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 1677624650740528615 , + crc : 1860796047234000762 , ccp_crc : 0 , cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" , buildDate : "May 22 2024" , diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti index fef07f60bb962f26dbca922c1b545eb6708ab919..4628fee46f9074ed5be74eeadc7f308157bce7c1 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type index bdd39fd0b54539fd10556fd56cf6ab9635e774cb..6346d3fbb19c1f6c28f635a68462969c5d28a149 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg index 91704886bfc93829631863bfaf3623765f098c99..f22e04bd8701eaa080c0afab0d143f5f92634744 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk index e5014e9fac0425ab0e2da5c32a21d9f57d119834..b7c8cd7260f0e29ac9f852375b8a9f45a59b33cc 100755 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log index 6ad1a324f3ce0cbaca10f08f446924417823f344..75defeda60874c1512fb09ad10467ede135d7e92 100644 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log @@ -1,4 +1,4 @@ -Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51971 +Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 33467 Design successfully loaded Design Loading Memory Usage: 20188 KB (Peak: 20752 KB) Design Loading CPU Usage: 20 ms diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb index c0f6ce1fa55f360160a80f78b9dfda3aa9f8d3b9..c0f01b6cfefed94d77dd822592bd3968882a2a5c 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb index 99af87d485bccdfbce35764888c400a19a752c0e..e37c07e3bf2f1c9288fe46d269591a15428700dc 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb index 8da4fc2cebf8d1b9c7a8b85cd582a1b0c291fc8d..cb3c90bfde65719280b6cce7d8f5cd3f2c841b24 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index 0a2fcb5531c0c85489359778427afa640c09435b..2b9362e605fc97d9af61e16ea94b24d46a868b76 100644 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -2,7 +2,7 @@ 2020.2 May 22 2024 18:54:44 -/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742382607,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,, +/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742383073,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,, /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1742373132,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,, /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742376828,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,, /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1742373132,vhdl,,,,tb_firunit,,,,,,,, diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c1836d071b0defdbda3f718b6ae776ce75ce6910 100644 --- a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log +++ b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,6 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'controlUnit' +INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'firUnit' +INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit' diff --git a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb index b155e40f06a230303a04d2a77f07560e35c5dc93..ea4261478203304b1112b86f0e763def504cdba7 100644 Binary files a/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb and b/proj/project_1/project_1.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/proj/project_1/project_1.xpr b/proj/project_1/project_1.xpr index 8d0cee185762efa6ac715779f484aefb76a499cc..a9628c09084928e0e1c9d795293593ae30f68064 100644 --- a/proj/project_1/project_1.xpr +++ b/proj/project_1/project_1.xpr @@ -60,7 +60,7 @@ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="EnableBDX" Val="FALSE"/> - <Option Name="WTXSimLaunchSim" Val="132"/> + <Option Name="WTXSimLaunchSim" Val="136"/> <Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/> diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd index 11451e877885d4e76b942569953f1042ee98c32a..32222792b4fe7edb725590c8a51690feff59987e 100644 --- a/src/hdl/controlUnit.vhd +++ b/src/hdl/controlUnit.vhd @@ -84,11 +84,13 @@ BEGIN O_initAddress <= '1'; ELSE SR_futurState <= PROCESS_B; + O_initAddress <= '0'; END IF; WHEN PROCESS_A => - O_sel <= "10"; O_initAddress <= '0'; + O_sel <= "10"; + IF I_processingDoneA = '1' THEN SR_futurState <= CLELLAN; O_initAddress <= '1'; diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd index 2e86d5d5b84e92bd244a42abbc1a9297849b51b0..abb24b1bc24512c5ae4cfcce3ff6e7e9542e8359 100644 --- a/src/hdl/operativeUnit.vhd +++ b/src/hdl/operativeUnit.vhd @@ -283,7 +283,7 @@ BEGIN SC_multOperand1 <= SR_2A(SR_readAddress); SC_multOperand2 <= SR_coefRegisterA(SR_readAddress); - IF SR_readAddress = 0 THEN + IF SR_readAddress = 1 THEN O_processingDoneA <= '1'; O_processingDoneB <= '0'; O_processingDoneBL <= '0';