From 86178efa058dd2f7eb6b9c46fa6b6d233f0cafaf Mon Sep 17 00:00:00 2001
From: Charles MASSONG <c24masso@fl-tp-br-604.imta.fr>
Date: Wed, 26 Feb 2025 16:31:06 +0100
Subject: [PATCH] Travail tp filtre
---
AudioProc.xpr | 218 ++
docs/img/FSM.drawio.png | Bin 0 -> 129377 bytes
docs/img/FSM.png | Bin 117251 -> 0 bytes
.../0/e/0edd54b7fee8338b/0edd54b7fee8338b.xci | 298 ++
.../2024.1/0/e/0edd54b7fee8338b/clk_wiz_0.dcp | Bin 0 -> 13273 bytes
.../0edd54b7fee8338b/clk_wiz_0_sim_netlist.v | 291 ++
.../clk_wiz_0_sim_netlist.vhdl | 216 ++
.../0/e/0edd54b7fee8338b/clk_wiz_0_stub.v | 31 +
.../0/e/0edd54b7fee8338b/clk_wiz_0_stub.vhdl | 35 +
proj/AudioProc.cache/sim/ssm.db | 11 +
proj/AudioProc.cache/wt/project.wpc | 3 +
proj/AudioProc.cache/wt/synthesis.wdf | 52 +
proj/AudioProc.cache/wt/xsim.wdf | 4 +
proj/AudioProc.hw/AudioProc.lpr | 7 +
proj/AudioProc.ip_user_files/README.txt | 1 +
.../ip/clk_wiz_0/clk_wiz_0.vho | 100 +
.../ip/clk_wiz_0/clk_wiz_0_stub.v | 31 +
.../ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 35 +
.../ipstatic/mmcm_pll_drp_func_7s_mmcm.vh | 680 ++++
.../ipstatic/mmcm_pll_drp_func_7s_pll.vh | 542 +++
.../ipstatic/mmcm_pll_drp_func_us_mmcm.vh | 680 ++++
.../ipstatic/mmcm_pll_drp_func_us_pll.vh | 555 +++
.../mmcm_pll_drp_func_us_plus_mmcm.vh | 886 +++++
.../ipstatic/mmcm_pll_drp_func_us_plus_pll.vh | 561 +++
.../clk_wiz_0/activehdl/README.txt | 50 +
.../clk_wiz_0/activehdl/clk_wiz_0.sh | 258 ++
.../clk_wiz_0/activehdl/clk_wiz_0.udo | 0
.../clk_wiz_0/activehdl/compile.do | 25 +
.../clk_wiz_0/activehdl/file_info.txt | 5 +
.../sim_scripts/clk_wiz_0/activehdl/glbl.v | 84 +
.../clk_wiz_0/activehdl/simulate.do | 14 +
.../sim_scripts/clk_wiz_0/modelsim/README.txt | 50 +
.../clk_wiz_0/modelsim/clk_wiz_0.sh | 287 ++
.../clk_wiz_0/modelsim/clk_wiz_0.udo | 0
.../sim_scripts/clk_wiz_0/modelsim/compile.do | 22 +
.../clk_wiz_0/modelsim/file_info.txt | 5 +
.../sim_scripts/clk_wiz_0/modelsim/glbl.v | 84 +
.../clk_wiz_0/modelsim/simulate.do | 19 +
.../sim_scripts/clk_wiz_0/modelsim/wave.do | 2 +
.../sim_scripts/clk_wiz_0/questa/README.txt | 50 +
.../sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh | 297 ++
.../clk_wiz_0/questa/clk_wiz_0.udo | 0
.../sim_scripts/clk_wiz_0/questa/compile.do | 22 +
.../sim_scripts/clk_wiz_0/questa/elaborate.do | 1 +
.../clk_wiz_0/questa/file_info.txt | 5 +
.../sim_scripts/clk_wiz_0/questa/glbl.v | 84 +
.../sim_scripts/clk_wiz_0/questa/simulate.do | 19 +
.../sim_scripts/clk_wiz_0/questa/wave.do | 2 +
.../sim_scripts/clk_wiz_0/riviera/README.txt | 50 +
.../clk_wiz_0/riviera/clk_wiz_0.sh | 264 ++
.../clk_wiz_0/riviera/clk_wiz_0.udo | 0
.../sim_scripts/clk_wiz_0/riviera/compile.do | 25 +
.../clk_wiz_0/riviera/file_info.txt | 5 +
.../sim_scripts/clk_wiz_0/riviera/glbl.v | 84 +
.../sim_scripts/clk_wiz_0/riviera/simulate.do | 14 +
.../sim_scripts/clk_wiz_0/vcs/README.txt | 50 +
.../sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh | 345 ++
.../sim_scripts/clk_wiz_0/vcs/file_info.txt | 5 +
.../sim_scripts/clk_wiz_0/vcs/glbl.v | 84 +
.../sim_scripts/clk_wiz_0/vcs/simulate.do | 2 +
.../sim_scripts/clk_wiz_0/xcelium/README.txt | 50 +
.../clk_wiz_0/xcelium/clk_wiz_0.sh | 351 ++
.../clk_wiz_0/xcelium/file_info.txt | 5 +
.../sim_scripts/clk_wiz_0/xcelium/glbl.v | 84 +
.../sim_scripts/clk_wiz_0/xcelium/hdl.var | 0
.../sim_scripts/clk_wiz_0/xcelium/simulate.do | 7 +
.../sim_scripts/clk_wiz_0/xsim/README.txt | 50 +
.../sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh | 330 ++
.../sim_scripts/clk_wiz_0/xsim/cmd.tcl | 12 +
.../sim_scripts/clk_wiz_0/xsim/file_info.txt | 3 +
.../sim_scripts/clk_wiz_0/xsim/glbl.v | 84 +
.../sim_scripts/clk_wiz_0/xsim/vlog.prj | 8 +
proj/AudioProc.runs/.jobs/vrs_config_1.xml | 12 +
.../.Vivado_Synthesis.queue.rst | 0
.../.Xil/clk_wiz_0_propImpl.xdc | 4 +
.../clk_wiz_0_synth_1/.vivado.begin.rst | 5 +
.../clk_wiz_0_synth_1/.vivado.end.rst | 0
.../clk_wiz_0_synth_1/ISEWrap.js | 270 ++
.../clk_wiz_0_synth_1/ISEWrap.sh | 85 +
.../__synthesis_is_complete__ | 0
.../clk_wiz_0_synth_1/clk_wiz_0.dcp | Bin 0 -> 13383 bytes
.../clk_wiz_0_synth_1/clk_wiz_0.tcl | 234 ++
.../clk_wiz_0_synth_1/clk_wiz_0.vds | 272 ++
.../clk_wiz_0_utilization_synth.pb | Bin 0 -> 276 bytes
.../clk_wiz_0_utilization_synth.rpt | 176 +
.../clk_wiz_0_synth_1/dont_touch.xdc | 32 +
.../clk_wiz_0_synth_1/gen_run.xml | 50 +
proj/AudioProc.runs/clk_wiz_0_synth_1/htr.txt | 10 +
.../clk_wiz_0_synth_1/project.wdf | 32 +
.../clk_wiz_0_synth_1/rundef.js | 41 +
.../clk_wiz_0_synth_1/runme.bat | 12 +
.../clk_wiz_0_synth_1/runme.log | 262 ++
.../AudioProc.runs/clk_wiz_0_synth_1/runme.sh | 40 +
.../clk_wiz_0_synth_1/vivado.jou | 24 +
.../clk_wiz_0_synth_1/vivado.pb | Bin 0 -> 28572 bytes
.../AudioProc.sim/sim_1/behav/xsim/compile.sh | 28 +
.../sim_1/behav/xsim/elaborate.log | 21 +
.../sim_1/behav/xsim/elaborate.sh | 22 +
proj/AudioProc.sim/sim_1/behav/xsim/glbl.v | 84 +
.../sim_1/behav/xsim/simulate.log | 1 +
.../sim_1/behav/xsim/simulate.sh | 22 +
.../sim_1/behav/xsim/tb_firUnit.tcl | 11 +
.../sim_1/behav/xsim/tb_firUnit_behav.wdb | Bin 0 -> 53384 bytes
.../sim_1/behav/xsim/tb_firUnit_vhdl.prj | 9 +
.../sim_1/behav/xsim/tb_firUnit_vlog.prj | 7 +
proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 2199 bytes
.../tb_firUnit_behav/Compile_Options.txt | 1 +
.../tb_firUnit_behav/TempBreakPointFile.txt | 1 +
.../tb_firUnit_behav/obj/xsim_0.lnx64.o | Bin 0 -> 25536 bytes
.../xsim.dir/tb_firUnit_behav/obj/xsim_1.c | 142 +
.../tb_firUnit_behav/obj/xsim_1.lnx64.o | Bin 0 -> 6392 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.dbg | Bin 0 -> 15928 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.mem | Bin 0 -> 4535 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.reloc | Bin 0 -> 2004 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rlx | 12 +
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rtti | Bin 0 -> 753 bytes
.../xsim.dir/tb_firUnit_behav/xsim.svtype | Bin 0 -> 47 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.type | Bin 0 -> 7048 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg | Bin 0 -> 13064 bytes
.../tb_firUnit_behav/xsimSettings.ini | 50 +
.../xsim.dir/tb_firUnit_behav/xsimcrash.log | 0
.../xsim/xsim.dir/tb_firUnit_behav/xsimk | Bin 0 -> 32824 bytes
.../xsim.dir/tb_firUnit_behav/xsimkernel.log | 7 +
.../xsim.dir/xil_defaultlib/controlunit.vdb | Bin 0 -> 8400 bytes
.../xsim/xsim.dir/xil_defaultlib/firunit.vdb | Bin 0 -> 10393 bytes
.../xsim/xsim.dir/xil_defaultlib/glbl.sdb | Bin 0 -> 5679 bytes
.../xsim.dir/xil_defaultlib/operativeunit.vdb | Bin 0 -> 14228 bytes
.../xsim.dir/xil_defaultlib/tb_firunit.vdb | Bin 0 -> 7470 bytes
.../xil_defaultlib/xil_defaultlib.rlx | 9 +
proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini | 490 +++
.../sim_1/behav/xsim/xsim.ini.bak | 490 +++
proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log | 6 +
proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb | Bin 0 -> 859 bytes
proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log | 0
proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb | 4 +
proj/AudioProc.xpr | 348 ++
proj/ip_upgrade.log | 27 +
proj/tb_firUnit_behav.wcfg | 95 +
proj/vivado.jou | 83 +
proj/vivado.log | 1724 +++++++++
src/hdl/controlUnit.vhd | 82 +-
src/hdl/operativeUnit.vhd | 50 +-
src/ip/clk_wiz_0/clk_wiz_0.dcp | Bin 12528 -> 13383 bytes
src/ip/clk_wiz_0/clk_wiz_0.v | 52 +-
src/ip/clk_wiz_0/clk_wiz_0.vho | 49 +-
src/ip/clk_wiz_0/clk_wiz_0.xci | 1253 +++---
src/ip/clk_wiz_0/clk_wiz_0.xdc | 34 +-
src/ip/clk_wiz_0/clk_wiz_0.xml | 3448 +++++++++--------
src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 65 +-
src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc | 31 +-
src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v | 51 +-
src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl | 32 +-
src/ip/clk_wiz_0/clk_wiz_0_stub.v | 31 +-
src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 18 +-
.../clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt | 115 -
.../clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt | 323 ++
src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh | 680 ++++
src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh | 542 +++
src/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh | 680 ++++
src/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh | 555 +++
.../mmcm_pll_drp_func_us_plus_mmcm.vh | 886 +++++
.../mmcm_pll_drp_func_us_plus_pll.vh | 561 +++
vivado.jou | 25 +
vivado.log | 97 +
164 files changed, 21073 insertions(+), 2376 deletions(-)
create mode 100644 AudioProc.xpr
create mode 100644 docs/img/FSM.drawio.png
delete mode 100644 docs/img/FSM.png
create mode 100644 proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/0edd54b7fee8338b.xci
create mode 100644 proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0.dcp
create mode 100755 proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.v
create mode 100755 proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.vhdl
create mode 100755 proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.v
create mode 100755 proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.vhdl
create mode 100644 proj/AudioProc.cache/sim/ssm.db
create mode 100644 proj/AudioProc.cache/wt/project.wpc
create mode 100644 proj/AudioProc.cache/wt/synthesis.wdf
create mode 100644 proj/AudioProc.cache/wt/xsim.wdf
create mode 100644 proj/AudioProc.hw/AudioProc.lpr
create mode 100644 proj/AudioProc.ip_user_files/README.txt
create mode 100755 proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
create mode 100644 proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v
create mode 100644 proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
create mode 100755 proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
create mode 100755 proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
create mode 100755 proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
create mode 100755 proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
create mode 100755 proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
create mode 100755 proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
create mode 100755 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
create mode 100644 proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
create mode 100644 proj/AudioProc.runs/.jobs/vrs_config_1.xml
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.begin.rst
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.end.rst
create mode 100755 proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.js
create mode 100755 proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.sh
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/__synthesis_is_complete__
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/htr.txt
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/project.wdf
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/rundef.js
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/runme.bat
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/runme.log
create mode 100755 proj/AudioProc.runs/clk_wiz_0_synth_1/runme.sh
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.jou
create mode 100644 proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.pb
create mode 100755 proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
create mode 100755 proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
create mode 100755 proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
create mode 100755 proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
create mode 100644 proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
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diff --git a/AudioProc.xpr b/AudioProc.xpr
new file mode 100644
index 0000000..573f8c6
--- /dev/null
+++ b/AudioProc.xpr
@@ -0,0 +1,218 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/AudioProc.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="e38929706f6f4a97b2a2b7a6dd753304"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
+ <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
+ </StratHandle>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+ <Desc>Vivado Implementation Defaults</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
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diff --git a/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/0edd54b7fee8338b.xci b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/0edd54b7fee8338b.xci
new file mode 100644
index 0000000..647b9d9
--- /dev/null
+++ b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/0edd54b7fee8338b.xci
@@ -0,0 +1,298 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
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diff --git a/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0.dcp b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0.dcp
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NLye77%H0eNYynwq;-~-s
literal 0
HcmV?d00001
diff --git a/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.v b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.v
new file mode 100755
index 0000000..2a0c546
--- /dev/null
+++ b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.v
@@ -0,0 +1,291 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date : Wed Feb 26 11:54:27 2025
+// Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
+// Design : clk_wiz_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+ (clk_out1,
+ clk_out2,
+ clk_out3,
+ clk_out4,
+ reset,
+ locked,
+ clk_in1);
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+ input clk_in1;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire clk_out2;
+ wire clk_out3;
+ wire clk_out4;
+ wire locked;
+ wire reset;
+
+ decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .clk_out2(clk_out2),
+ .clk_out3(clk_out3),
+ .clk_out4(clk_out4),
+ .locked(locked),
+ .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
+ (clk_out1,
+ clk_out2,
+ clk_out3,
+ clk_out4,
+ reset,
+ locked,
+ clk_in1);
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+ input clk_in1;
+
+ wire clk_in1;
+ wire clk_in1_clk_wiz_0;
+ wire clk_out1;
+ wire clk_out1_clk_wiz_0;
+ wire clk_out2;
+ wire clk_out2_clk_wiz_0;
+ wire clk_out3;
+ wire clk_out3_clk_wiz_0;
+ wire clk_out4;
+ wire clk_out4_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfbout_clk_wiz_0;
+ wire locked;
+ wire reset;
+ wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+ wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_clk_wiz_0),
+ .O(clkfbout_buf_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_clk_wiz_0),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout2_buf
+ (.I(clk_out2_clk_wiz_0),
+ .O(clk_out2));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout3_buf
+ (.I(clk_out3_clk_wiz_0),
+ .O(clk_out3));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout4_buf
+ (.I(clk_out4_clk_wiz_0),
+ .O(clk_out4));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ MMCME2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(6.000000),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKFBOUT_USE_FINE_PS("FALSE"),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE_F(6.000000),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT0_USE_FINE_PS("FALSE"),
+ .CLKOUT1_DIVIDE(3),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT1_USE_FINE_PS("FALSE"),
+ .CLKOUT2_DIVIDE(50),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT2_USE_FINE_PS("FALSE"),
+ .CLKOUT3_DIVIDE(12),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT3_USE_FINE_PS("FALSE"),
+ .CLKOUT4_CASCADE("FALSE"),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT4_USE_FINE_PS("FALSE"),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .CLKOUT5_USE_FINE_PS("FALSE"),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.500000),
+ .CLKOUT6_PHASE(0.000000),
+ .CLKOUT6_USE_FINE_PS("FALSE"),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PSEN_INVERTED(1'b0),
+ .IS_PSINCDEC_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .SS_EN("FALSE"),
+ .SS_MODE("CENTER_HIGH"),
+ .SS_MOD_PERIOD(10000),
+ .STARTUP_WAIT("FALSE"))
+ mmcm_adv_inst
+ (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+ .CLKFBOUT(clkfbout_clk_wiz_0),
+ .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+ .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+ .CLKIN1(clk_in1_clk_wiz_0),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+ .CLKOUT0(clk_out1_clk_wiz_0),
+ .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+ .CLKOUT1(clk_out2_clk_wiz_0),
+ .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+ .CLKOUT2(clk_out3_clk_wiz_0),
+ .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+ .CLKOUT3(clk_out4_clk_wiz_0),
+ .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+ .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+ .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(locked),
+ .PSCLK(1'b0),
+ .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .PWRDWN(1'b0),
+ .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.vhdl b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.vhdl
new file mode 100755
index 0000000..a8125e2
--- /dev/null
+++ b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_sim_netlist.vhdl
@@ -0,0 +1,216 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Feb 26 11:54:28 2025
+-- Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
+-- Design : clk_wiz_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
+ signal clk_in1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out2_clk_wiz_0 : STD_LOGIC;
+ signal clk_out3_clk_wiz_0 : STD_LOGIC;
+ signal clk_out4_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_clk_wiz_0 : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_clk_wiz_0,
+ O => clkfbout_buf_clk_wiz_0
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_clk_wiz_0
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_clk_wiz_0,
+ O => clk_out1
+ );
+clkout2_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out2_clk_wiz_0,
+ O => clk_out2
+ );
+clkout3_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out3_clk_wiz_0,
+ O => clk_out3
+ );
+clkout4_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out4_clk_wiz_0,
+ O => clk_out4
+ );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 6.000000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => false,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 6.000000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => false,
+ CLKOUT1_DIVIDE => 3,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => false,
+ CLKOUT2_DIVIDE => 50,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => false,
+ CLKOUT3_DIVIDE => 12,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => false,
+ CLKOUT4_CASCADE => false,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => false,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => false,
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => false,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => false
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_clk_wiz_0,
+ CLKFBOUT => clkfbout_clk_wiz_0,
+ CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1_clk_wiz_0,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_clk_wiz_0,
+ CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => clk_out2_clk_wiz_0,
+ CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => clk_out3_clk_wiz_0,
+ CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => clk_out4_clk_wiz_0,
+ CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PSCLK => '0',
+ PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => reset
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ port (
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ locked => locked,
+ reset => reset
+ );
+end STRUCTURE;
diff --git a/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.v b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.v
new file mode 100755
index 0000000..34b708c
--- /dev/null
+++ b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.v
@@ -0,0 +1,31 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date : Wed Feb 26 11:54:27 2025
+// Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, clk_out2, clk_out3, clk_out4, reset,
+ locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */
+/* synthesis syn_force_seq_prim="clk_out2" */
+/* synthesis syn_force_seq_prim="clk_out3" */
+/* synthesis syn_force_seq_prim="clk_out4" */;
+ output clk_out1 /* synthesis syn_isclock = 1 */;
+ output clk_out2 /* synthesis syn_isclock = 1 */;
+ output clk_out3 /* synthesis syn_isclock = 1 */;
+ output clk_out4 /* synthesis syn_isclock = 1 */;
+ input reset;
+ output locked;
+ input clk_in1;
+endmodule
diff --git a/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.vhdl b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.vhdl
new file mode 100755
index 0000000..c1b53b0
--- /dev/null
+++ b/proj/AudioProc.cache/ip/2024.1/0/e/0edd54b7fee8338b/clk_wiz_0_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Feb 26 11:54:27 2025
+-- Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,reset,locked,clk_in1";
+begin
+end;
diff --git a/proj/AudioProc.cache/sim/ssm.db b/proj/AudioProc.cache/sim/ssm.db
new file mode 100644
index 0000000..593ba29
--- /dev/null
+++ b/proj/AudioProc.cache/sim/ssm.db
@@ -0,0 +1,11 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Feb 26 12:03:32 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,rtl
diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
new file mode 100644
index 0000000..9b34209
--- /dev/null
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..d385d80
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
+version:1
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+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937322e3133334d42:00:00
+eof:3734131713
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
new file mode 100644
index 0000000..51d5206
--- /dev/null
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:2427094519
diff --git a/proj/AudioProc.hw/AudioProc.lpr b/proj/AudioProc.hw/AudioProc.lpr
new file mode 100644
index 0000000..afc0a86
--- /dev/null
+++ b/proj/AudioProc.hw/AudioProc.lpr
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0"/>
diff --git a/proj/AudioProc.ip_user_files/README.txt b/proj/AudioProc.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100755
index 0000000..b02ca8e
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,100 @@
+
+-- (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1__100.00000______0.000______50.0______151.366____132.063
+-- clk_out2__200.00000______0.000______50.0______132.221____132.063
+-- clk_out3__12.00000______0.000______50.0______231.952____132.063
+-- clk_out4__50.00000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v
new file mode 100644
index 0000000..88530c7
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -0,0 +1,31 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date : Wed Feb 26 11:54:28 2025
+// Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+// Command : write_verilog -force -mode synth_stub
+// /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_out1, clk_out2, clk_out3, clk_out4, reset,
+ locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */
+/* synthesis syn_force_seq_prim="clk_out2" */
+/* synthesis syn_force_seq_prim="clk_out3" */
+/* synthesis syn_force_seq_prim="clk_out4" */;
+ output clk_out1 /* synthesis syn_isclock = 1 */;
+ output clk_out2 /* synthesis syn_isclock = 1 */;
+ output clk_out3 /* synthesis syn_isclock = 1 */;
+ output clk_out4 /* synthesis syn_isclock = 1 */;
+ input reset;
+ output locked;
+ input clk_in1;
+endmodule
diff --git a/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
new file mode 100644
index 0000000..04dfc6c
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -0,0 +1,35 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Feb 26 11:54:28 2025
+-- Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+-- Command : write_vhdl -force -mode synth_stub
+-- /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,reset,locked,clk_in1";
+begin
+end;
diff --git a/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000..6c4981a
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1011_00,
+ 10'b0010_1101_00,
+ 10'b0010_0011_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0100_1111_00,
+ 10'b0101_1011_00,
+ 10'b0111_0111_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_1001_00,
+ 10'b1101_0001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0111_0001_00,
+ 10'b0111_0001_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0110_0001_00,
+ 10'b0110_0001_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0100_1010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000..b662a3e
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,542 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+`ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+`ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+`endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+`ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+`ifdef DEBUG
+ $display("temp: %h", temp);
+`endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1101_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0011_0111_00,
+ 10'b0011_0111_00,
+ 10'b0101_1111_00,
+ 10'b0111_1111_00,
+ 10'b0111_1011_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_1101_00,
+ 10'b1111_0111_00,
+ 10'b1111_1011_00,
+ 10'b1111_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+`endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+`ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
diff --git a/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000..154c81f
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_0011_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_1001_11,
+ 10'b0010_1001_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1011_11,
+ 10'b0011_1111_11,
+ 10'b0100_1111_11,
+ 10'b0100_1111_11,
+ 10'b0101_1111_11,
+ 10'b0110_1111_11,
+ 10'b0111_1111_11,
+ 10'b0111_1111_11,
+ 10'b1100_1111_11,
+ 10'b1101_1111_11,
+ 10'b1110_1111_11,
+ 10'b1111_1111_11,
+ 10'b1111_1111_11,
+ 10'b1110_0111_11,
+ 10'b1110_1011_11,
+ 10'b1111_0111_11,
+ 10'b1111_1011_11,
+ 10'b1111_1011_11,
+ 10'b1110_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000..ff369d1
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,555 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: AMD
+// Engineer: Jim Tatsukawa
+// Date: 6/15/2015
+// Design Name: PLLE3 DRP
+// Module Name: plle3_drp_func.h
+// Version: 1.10
+// Target Devices: UltraScale Architecture
+// Tool versions: 2015.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// PM_Rise bits have been removed for PLLE3
+//
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [759:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001 //19
+
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 19
+ );
+
+ reg [639:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0010_1111_01, //1
+ 10'b0010_0011_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0010_0001_11, //4
+ 10'b0010_0110_11, //5
+ 10'b0010_1010_11, //6
+ 10'b0010_1010_11, //7
+ 10'b0011_0110_11, //8
+ 10'b0010_1100_11, //9
+ 10'b0010_1100_11, //10
+ 10'b0010_1100_11, //11
+ 10'b0010_0010_11, //12
+ 10'b0011_1100_11, //13
+ 10'b0011_1100_11, //14
+ 10'b0011_1100_11, //15
+ 10'b0011_1100_11, //16
+ 10'b0011_0010_11, //17
+ 10'b0011_0010_11, //18
+ 10'b0011_0010_11 //19
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
+
diff --git a/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000..fd26211
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,886 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: AMD
+// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
+// Date: 7/30/2014
+// Design Name: MMCME4 DRP
+// Module Name: mmcme4_drp_func.h
+// Version: 1.31
+// Target Devices: UltraScale Plus Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for UltraScal+ MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function
+// 2/28/17 - Updated for Ultrascale Plus
+//
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [7:0] divide // Max M divide is 128 in UltrascalePlus
+ );
+
+ reg [5119:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=2
+ 40'b01000_01000_1111101000_1111101001_0000000001, // M=3
+ 40'b01011_01011_1111101000_1111101001_0000000001, // M=4
+ 40'b01110_01110_1111101000_1111101001_0000000001, // M=5
+ 40'b10001_10001_1111101000_1111101001_0000000001, // M=6
+ 40'b10011_10011_1111101000_1111101001_0000000001, // M=7
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001, // M=127
+ 40'b11111_11111_0011111010_1111101001_0000000001 // M=128
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [1279:0] lookup_low;
+ reg [1279:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0011_1111_11, // M=1 - not legal
+ 10'b0011_1111_11, // M=2
+ 10'b0011_1101_11, // M=3
+ 10'b0011_0101_11, // M=4
+ 10'b0011_1001_11, // M=5
+ 10'b0011_1110_11, // M=6
+ 10'b0011_1110_11, // M=7
+ 10'b0011_0001_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0100_0110_11,
+ 10'b0011_1100_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11, // M=127
+ 10'b1101_1000_11 // M=128
+};
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0111_1111_11, // M=1 - not legal
+ 10'b0111_1111_11, // M=2
+ 10'b1110_1111_11, // M=3
+ 10'b1111_1111_11, // M=4
+ 10'b1111_1011_11, // M=5
+ 10'b1111_1101_11, // M=6
+ 10'b1111_0011_11, // M=7
+ 10'b1110_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1110_0110_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11 // M=128
+};
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000..0899943
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,561 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: AMD
+// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
+// Date: 6/15/2015
+// Design Name: PLLE4 DRP
+// Module Name: plle4_drp_func.h
+// Version: 2.0
+// Target Devices: UltraScale+ Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// M_Rise bits have been removed for PLLE3
+// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
+// Ultrascale+ and for max M of 21
+//
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [839:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001, //19
+ 40'b11111_11111_0111110100_1111101001_0000000001, //20
+ 40'b11111_11111_0111011011_1111101001_0000000001 //21
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [209:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0011_0111_11, //1 not legal in Ultrascale+
+ 10'b0011_0111_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0011_1001_11, //4
+ 10'b0011_0001_11, //5
+ 10'b0100_1110_11, //6
+ 10'b0011_0110_11, //7
+ 10'b0011_1010_11, //8
+ 10'b0111_1001_11, //9
+ 10'b0111_1001_11, //10
+ 10'b0101_0110_11, //11
+ 10'b1100_0101_11, //12
+ 10'b0101_1010_11, //13
+ 10'b0110_0110_11, //14
+ 10'b0110_1010_11, //15
+ 10'b0111_0110_11, //16
+ 10'b1111_0101_11, //17
+ 10'b1100_0110_11, //18
+ 10'b1110_0001_11, //19
+ 10'b1101_0110_11, //20
+ 10'b1111_0001_11 //21
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
+// will need to divide the doubled clock VCO clock frequency by
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
new file mode 100755
index 0000000..74d9461
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
@@ -0,0 +1,258 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Aldec Active-HDL Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+# switch with the directory path where the library is created while generating the script
+# with export_simulation.
+#
+# Alternatively, you can set the library path by setting the following project property:-
+#
+# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+# You can also point to the simulation library by either setting the 'lib_map_path' global
+# variable in this script or specify it with the '-lib_map_path' switch while executing this
+# script (type 'clk_wiz_0.sh -help' for more information).
+#
+# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+# generated script, but if design is targetted for system simulation containing SystemC/C++/C
+# sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous design library mappings
+ true
+ else
+ # map simulator index file
+ map_setup_file
+ fi
+}
+
+# map library.cfg file
+map_setup_file()
+{
+ file="library.cfg"
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ vmap -link $lib_map_path
+ fi
+ fi
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
new file mode 100644
index 0000000..c65c1fc
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
@@ -0,0 +1,25 @@
+transcript off
+onbreak {quit -force}
+onerror {quit -force}
+transcript on
+
+vlib work
+vlib activehdl/xpm
+vlib activehdl/xil_defaultlib
+
+vmap xpm activehdl/xpm
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xpm -sv2k12 "+incdir+../../../ipstatic" -l xpm -l xil_defaultlib \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm - \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" -l xpm -l xil_defaultlib \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
new file mode 100644
index 0000000..b33b916
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
new file mode 100644
index 0000000..2bd90be
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
@@ -0,0 +1,14 @@
+transcript off
+onbreak {quit -force}
+onerror {quit -force}
+transcript on
+
+asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O2 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+do {clk_wiz_0.udo}
+
+run
+
+endsim
+
+quit -force
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
new file mode 100755
index 0000000..8939ec5
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
@@ -0,0 +1,287 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Siemens ModelSim Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+# switch with the directory path where the library is created while generating the script
+# with export_simulation.
+#
+# Alternatively, you can set the library path by setting the following project property:-
+#
+# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+# You can also point to the simulation library by either setting the 'lib_map_path' global
+# variable in this script or specify it with the '-lib_map_path' switch while executing this
+# script (type 'clk_wiz_0.sh -help' for more information).
+#
+# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+# generated script, but if design is targetted for system simulation containing SystemC/C++/C
+# sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous simulator index file
+ true
+ else
+ # copy simulator index file to current directory
+ copy_setup_file
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ ref_lib_dir=$lib_map_path
+ fi
+
+ if [[ ($b_keep_index == 1) ]]; then
+ # do not recreate design library directories
+ true
+ else
+ # create design library directories
+ create_lib_dir
+ fi
+}
+
+# copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ cp $src_file .
+ fi
+ fi
+}
+
+# create design library directory
+create_lib_dir()
+{
+ lib_dir="modelsim_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $lib_dir
+ fi
+ mkdir $lib_dir
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
new file mode 100644
index 0000000..270653b
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
@@ -0,0 +1,22 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xpm modelsim_lib/msim/xpm
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../ipstatic" \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../ipstatic" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
new file mode 100644
index 0000000..b33b916
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
new file mode 100644
index 0000000..157ea1c
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_0.udo}
+
+run 1000ns
+
+quit -force
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
new file mode 100755
index 0000000..eaab4da
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
@@ -0,0 +1,297 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Siemens Questa Advanced Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+# switch with the directory path where the library is created while generating the script
+# with export_simulation.
+#
+# Alternatively, you can set the library path by setting the following project property:-
+#
+# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+# You can also point to the simulation library by either setting the 'lib_map_path' global
+# variable in this script or specify it with the '-lib_map_path' switch while executing this
+# script (type 'clk_wiz_0.sh -help' for more information).
+#
+# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+# generated script, but if design is targetted for system simulation containing SystemC/C++/C
+# sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "elaborate" )
+ elaborate
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ elaborate
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ source elaborate.do 2>&1 | tee elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous simulator index file
+ true
+ else
+ # copy simulator index file to current directory
+ copy_setup_file
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ ref_lib_dir=$lib_map_path
+ fi
+
+ if [[ ($b_keep_index == 1) ]]; then
+ # do not recreate design library directories
+ true
+ else
+ # create design library directories
+ create_lib_dir
+ fi
+}
+
+# copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ cp $src_file .
+ fi
+ fi
+}
+
+# create design library directory
+create_lib_dir()
+{
+ lib_dir="questa_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $lib_dir
+ fi
+ mkdir $lib_dir
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
new file mode 100644
index 0000000..2e71be8
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
@@ -0,0 +1,22 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xpm questa_lib/msim/xpm
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../ipstatic" \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../ipstatic" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
new file mode 100644
index 0000000..327f0a7
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 -l elaborate.log +acc=npr -suppress 10016 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
new file mode 100644
index 0000000..b33b916
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
new file mode 100644
index 0000000..81ab20f
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib clk_wiz_0_opt
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_0.udo}
+
+run 1000ns
+
+quit -force
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
new file mode 100644
index 0000000..70157b0
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
new file mode 100755
index 0000000..843cf62
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
@@ -0,0 +1,264 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Aldec Riviera-PRO Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+# switch with the directory path where the library is created while generating the script
+# with export_simulation.
+#
+# Alternatively, you can set the library path by setting the following project property:-
+#
+# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+# You can also point to the simulation library by either setting the 'lib_map_path' global
+# variable in this script or specify it with the '-lib_map_path' switch while executing this
+# script (type 'clk_wiz_0.sh -help' for more information).
+#
+# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+# generated script, but if design is targetted for system simulation containing SystemC/C++/C
+# sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous design library mappings
+ true
+ else
+ # map simulator index file
+ map_setup_file
+ fi
+}
+
+# map library.cfg file
+map_setup_file()
+{
+ file="library.cfg"
+ if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ vmap -link $lib_map_path
+ fi
+ fi
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
new file mode 100644
index 0000000..28c4c2b
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
@@ -0,0 +1,25 @@
+transcript off
+onbreak {quit -force}
+onerror {quit -force}
+transcript on
+
+vlib work
+vlib riviera/xpm
+vlib riviera/xil_defaultlib
+
+vmap xpm riviera/xpm
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xpm -incr "+incdir+../../../ipstatic" -l xpm -l xil_defaultlib \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 -incr \
+"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -incr -v2k5 "+incdir+../../../ipstatic" -l xpm -l xil_defaultlib \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
new file mode 100644
index 0000000..b33b916
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
new file mode 100644
index 0000000..972cc59
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
@@ -0,0 +1,14 @@
+transcript off
+onbreak {quit -force}
+onerror {quit -force}
+transcript on
+
+asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+do {clk_wiz_0.udo}
+
+run 1000ns
+
+endsim
+
+quit -force
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
new file mode 100755
index 0000000..35bbf8c
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
@@ -0,0 +1,345 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Synopsys Verilog Compiler Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+# switch with the directory path where the library is created while generating the script
+# with export_simulation.
+#
+# Alternatively, you can set the library path by setting the following project property:-
+#
+# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+# You can also point to the simulation library by either setting the 'lib_map_path' global
+# variable in this script or specify it with the '-lib_map_path' switch while executing this
+# script (type 'clk_wiz_0.sh -help' for more information).
+#
+# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+# generated script, but if design is targetted for system simulation containing SystemC/C++/C
+# sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# set vhdlan compile options
+vhdlan_opts="-full64 -l .tmp_log"
+
+# set vlogan compile options
+vlogan_opts="-full64 -l .tmp_log"
+
+# set vcs elaboration options
+vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log"
+
+# set vcs simulation options
+vcs_sim_opts="-ucli -licqueue -l simulate.log "
+
+# set design libraries
+design_libs=(xpm xil_defaultlib)
+
+# simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "elaborate" )
+ elaborate
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ elaborate
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ vlogan -work xpm $vlogan_opts -sverilog +incdir+"../../../ipstatic" \
+ "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+ 2>&1 | tee compile.log; cat .tmp_log > vlogan.log 2>/dev/null
+
+ vhdlan -work xpm $vhdlan_opts \
+ "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
+ 2>&1 | tee -a compile.log; cat .tmp_log > vhdlan.log 2>/dev/null
+
+ vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../ipstatic" \
+ "../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+ "../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+ 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
+
+ vlogan -work xil_defaultlib $vlogan_opts +v2k \
+ glbl.v \
+ 2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous design library mappings
+ true
+ else
+ # define design library mappings
+ create_lib_mappings
+ fi
+
+ if [[ ($b_keep_index == 1) ]]; then
+ # do not recreate design library directories
+ true
+ else
+ # create design library directories
+ create_lib_dir
+ fi
+}
+
+# define design library mappings
+create_lib_mappings()
+{
+ file="synopsys_sim.setup"
+ if [[ -e $file ]]; then
+ if [[ ($lib_map_path == "") ]]; then
+ return
+ else
+ rm -rf $file
+ fi
+ fi
+
+ touch $file
+
+ if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ mapping="$lib:$sim_lib_dir/$lib"
+ echo $mapping >> $file
+ done
+
+ if [[ ($lib_map_path != "") ]]; then
+ incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+ echo $incl_ref >> $file
+ fi
+}
+
+# create design library directory
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log lib_sc.so 64 AN.DB csrc clk_wiz_0_simv.daidir vcs_lib c.obj)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
new file mode 100644
index 0000000..b33b916
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
new file mode 100644
index 0000000..b77c6f1
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
@@ -0,0 +1,2 @@
+run 1000ns
+quit
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh
new file mode 100755
index 0000000..ed97de1
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh
@@ -0,0 +1,351 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Cadence Xcelium Parallel Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+# switch with the directory path where the library is created while generating the script
+# with export_simulation.
+#
+# Alternatively, you can set the library path by setting the following project property:-
+#
+# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+# You can also point to the simulation library by either setting the 'lib_map_path' global
+# variable in this script or specify it with the '-lib_map_path' switch while executing this
+# script (type 'clk_wiz_0.sh -help' for more information).
+#
+# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+# generated script, but if design is targetted for system simulation containing SystemC/C++/C
+# sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# set xmvhdl compile options
+xmvhdl_opts="-64bit -messages -relax -logfile .tmp_log -update"
+
+# set xmvlog compile options
+xmvlog_opts="-64bit -messages -logfile .tmp_log -update"
+
+# set xmelab elaboration options
+xmelab_opts="-64bit -relax -access +rwc -namemap_mixgen -messages -logfile elaborate.log"
+
+# set xmsim simulation options
+xmsim_opts="-64bit -logfile simulate.log"
+
+# set design libraries for elaboration
+design_libs_elab="-libname xpm -libname xil_defaultlib -libname unisims_ver -libname unimacro_ver -libname secureip"
+
+# set design libraries
+design_libs=(simprims_ver xpm xil_defaultlib)
+
+# simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "elaborate" )
+ elaborate
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ elaborate
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ xmvlog -work xpm $xmvlog_opts -sv +incdir+"../../../ipstatic" \
+ "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+ 2>&1 | tee compile.log; cat .tmp_log > xmvlog.log 2>/dev/null
+
+ xmvhdl -work xpm -V93 $xmvhdl_opts \
+ "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd" \
+ 2>&1 | tee -a compile.log; cat .tmp_log > xmvhdl.log 2>/dev/null
+
+ xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../ipstatic" \
+ "../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+ "../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+ 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
+
+ xmvlog -work xil_defaultlib $xmvlog_opts \
+ glbl.v \
+ 2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ xmelab $xmelab_opts $design_libs_elab xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ xmsim $xmsim_opts xil_defaultlib.clk_wiz_0 -input simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous design library mappings
+ true
+ else
+ # define design library mappings
+ create_lib_mappings
+ fi
+
+ if [[ ($b_keep_index == 1) ]]; then
+ # do not recreate design library directories
+ true
+ else
+ # create design library directories
+ create_lib_dir
+ fi
+}
+
+# define design library mappings
+create_lib_mappings()
+{
+ file="hdl.var"
+ touch $file
+
+ file="cds.lib"
+ if [[ -e $file ]]; then
+ if [[ ($lib_map_path == "") ]]; then
+ return
+ else
+ rm -rf $file
+ fi
+ fi
+
+ touch $file
+
+ if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ incl_ref="INCLUDE $lib_map_path/cds.lib"
+ echo $incl_ref >> $file
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ mapping="DEFINE $lib $sim_lib_dir/$lib"
+ echo $mapping >> $file
+ done
+}
+
+# create design library directory
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log clk_wiz_0_sc.so .tmp_log xcelium_lib waves.shm c.obj)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log .tmp_log)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt
new file mode 100644
index 0000000..b33b916
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/hdl.var
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do
new file mode 100644
index 0000000..baf3d48
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do
@@ -0,0 +1,7 @@
+set pack_assert_off {numeric_std std_logic_arith}
+
+database -open waves -into waves.shm -default
+catch {probe -create -shm -all -variables -depth 1} msg
+
+run 1000ns
+exit
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
new file mode 100644
index 0000000..e749064
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2024.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and how to fetch design source file details
+# from the file_info.txt file.
+#
+# Generated by export_simulation on Wed Feb 26 11:53:03 CET 2025
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './clk_wiz_0.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
new file mode 100755
index 0000000..9881fce
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
@@ -0,0 +1,330 @@
+#!/usr/bin/env bash
+#**********************************************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Script generated by Vivado on Wed Feb 26 11:53:03 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# Filename : clk_wiz_0.sh
+# Simulator : AMD Vivado Simulator
+# Description : Simulation script generated by export_simulation Tcl command
+# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+# design. The script will copy the library mapping file from the compiled library directory,
+# create design library directories and library mappings in the mapping file.
+#
+# Usage : clk_wiz_0.sh
+# clk_wiz_0.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+# clk_wiz_0.sh [-reset_run]
+# clk_wiz_0.sh [-reset_log]
+# clk_wiz_0.sh [-help]
+#
+# * The -noclean_files switch is deprecated and will not peform any function (by default, the
+# simulator generated files will not be removed unless -reset_run switch is used)
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# set xvlog options
+xvlog_opts="--incr --relax "
+
+# script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+ check_args $*
+ setup
+ if [[ ($b_step == 1) ]]; then
+ case $step in
+ "compile" )
+ init_lib
+ compile
+ ;;
+ "elaborate" )
+ elaborate
+ ;;
+ "simulate" )
+ simulate
+ ;;
+ * )
+ echo -e "ERROR: Invalid or missing step '$step' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ esac
+ else
+ init_lib
+ compile
+ elaborate
+ simulate
+ fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ # delete previous files for a clean rerun
+ if [[ ($b_reset_run == 1) ]]; then
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ fi
+
+ # delete previous log files
+ if [[ ($b_reset_log == 1) ]]; then
+ reset_log
+ echo -e "INFO: Simulation run log files deleted.\n"
+ exit 0
+ fi
+
+ # add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+ if [[ ($b_keep_index == 1) ]]; then
+ # keep previous simulator index file
+ true
+ else
+ # copy simulator index file to current directory
+ copy_setup_file
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ ref_lib_dir=$lib_map_path
+ fi
+}
+
+# copy xsim.ini file
+copy_setup_file()
+{
+ file="xsim.ini"
+
+ if [[ ($lib_map_path == "") ]]; then
+ lib_map_path="/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim"
+ fi
+
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ cp $src_file .
+ fi
+
+ # map local design libraries to xsim.ini
+ map_local_libs
+ fi
+}
+
+# map local design libraries
+map_local_libs()
+{
+ updated_mappings=()
+ local_mappings=()
+
+ # local design libraries
+ local_libs=(xil_defaultlib)
+
+ if [[ 0 == ${#local_libs[@]} ]]; then
+ return
+ fi
+
+ file="xsim.ini"
+ file_backup="xsim.ini.bak"
+
+ if [[ -e $file ]]; then
+ rm -f $file_backup
+
+ # create a backup copy of the xsim.ini file
+ cp $file $file_backup
+
+ # read libraries from backup file and search in local library collection
+ while read -r line
+ do
+ IN=$line
+
+ # split mapping entry with '=' delimiter to fetch library name and mapping
+ read lib_name mapping <<<$(IFS="="; echo $IN)
+
+ # if local library found, then construct the local mapping and add to local mapping collection
+ if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ local_mappings+=("$lib_name")
+ fi
+
+ # add to updated library mapping collection
+ updated_mappings+=("$line")
+ done < "$file_backup"
+
+ # append local libraries not found originally from xsim.ini
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ updated_mappings+=("$line")
+ fi
+ done
+
+ # write updated mappings in xsim.ini
+ rm -f $file
+ for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+ lib_name="${updated_mappings[i]}"
+ echo $lib_name >> $file
+ done
+ else
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ mapping="$lib_name=xsim.dir/$lib_name"
+ echo $mapping >> $file
+ done
+ fi
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir libdpi.so)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+ files_to_remove=(xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# check switch argument value
+check_arg_value()
+{
+ if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+ echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# check command line arguments
+check_args()
+{
+ arg_count=$#
+ if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+ usage
+ fi
+ while [[ "$#" -gt 0 ]]; do
+ case $1 in
+ -step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
+ -lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+ -gen_bypass) b_gen_bypass=1 ;;
+ -reset_run) b_reset_run=1 ;;
+ -reset_log) b_reset_log=1 ;;
+ -keep_index) b_keep_index=1 ;;
+ -noclean_files) b_noclean_files=1 ;;
+ -help|-h) ;;
+ *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+ esac
+ shift
+ done
+
+ # -reset_run is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+ echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -reset_log is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+ echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -keep_index is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+ echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ # -noclean_files is not applicable with other switches
+ if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+ echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+ exit 1
+ fi
+}
+
+# script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-step]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-reset_log]\n\
+Usage: clk_wiz_0.sh [-keep_index]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+ echo -e $msg
+ exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_reset_run=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
new file mode 100644
index 0000000..6ac0dc8
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
+quit
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
new file mode 100644
index 0000000..a75fafc
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
@@ -0,0 +1,3 @@
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../../src/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
new file mode 100644
index 0000000..52f6000
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
@@ -0,0 +1,8 @@
+verilog xil_defaultlib --include "../../../ipstatic" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../../src/ip/clk_wiz_0/clk_wiz_0.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_1.xml b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000..d39edd1
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="clk_wiz_0_synth_1" LaunchDir="/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst b/proj/AudioProc.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc b/proj/AudioProc.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
new file mode 100644
index 0000000..5fe727d
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
@@ -0,0 +1,4 @@
+set_property SRC_FILE_INFO {cfile:/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../../src/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design]
+current_instance inst
+set_property src_info {type:SCOPED_XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.begin.rst b/proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.begin.rst
new file mode 100644
index 0000000..e298042
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="c24masso" Host="fl-tp-br-604" Pid="36790" HostCore="12" HostMemory="16081508">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.end.rst b/proj/AudioProc.runs/clk_wiz_0_synth_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.js b/proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.js
new file mode 100755
index 0000000..61806d0
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.sh b/proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.sh
new file mode 100755
index 0000000..05d5381
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ b/proj/AudioProc.runs/clk_wiz_0_synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp
new file mode 100644
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diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
new file mode 100644
index 0000000..65a7b6c
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
@@ -0,0 +1,234 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "clk_wiz_0_synth_1" START { ROLLUP_AUTO }
+set_param project.vivado.isBlockSynthRun true
+set_msg_config -msgmgr_mode ooc_run
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a200tsbg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/wt [current_project]
+set_property parent.project_path /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_repo_paths /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo [current_project]
+update_ip_catalog
+set_property ip_output_repo /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_ip -quiet /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc dont_touch.xdc
+set_property used_in_implementation false [get_files dont_touch.xdc]
+set_param ips.enableIPCacheLiteLoad 1
+OPTRACE "Configure IP Cache" START { }
+
+set cacheID [config_ip_cache -export -no_bom -dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1 -new_name clk_wiz_0 -ip [get_ips clk_wiz_0]]
+
+OPTRACE "Configure IP Cache" END { }
+if { $cacheID == "" } {
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top clk_wiz_0 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
+OPTRACE "synth_design" END { }
+OPTRACE "Write IP Cache" START { }
+
+#---------------------------------------------------------
+# Generate Checkpoint/Stub/Simulation Files For IP Cache
+#---------------------------------------------------------
+# disable binary constraint mode for IPCache checkpoints
+set_param constraints.enableBinaryConstraints false
+
+catch {
+ write_checkpoint -force -noxdef -rename_prefix clk_wiz_0_ clk_wiz_0.dcp
+
+ set ipCachedFiles {}
+ write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
+ lappend ipCachedFiles clk_wiz_0_stub.v
+
+ write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl
+ lappend ipCachedFiles clk_wiz_0_stub.vhdl
+
+ write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
+ lappend ipCachedFiles clk_wiz_0_sim_netlist.v
+
+ write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
+ lappend ipCachedFiles clk_wiz_0_sim_netlist.vhdl
+ set TIME_taken [expr [clock seconds] - $TIME_start]
+
+ if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
+ config_ip_cache -add -dcp clk_wiz_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips clk_wiz_0]
+ }
+OPTRACE "Write IP Cache" END { }
+}
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+rename_ref -prefix_all clk_wiz_0_
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef clk_wiz_0.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+
+if { [catch {
+ file copy -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.dcp
+} _RESULT ] } {
+ send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+ error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+ write_verilog -force -mode synth_stub /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_vhdl -force -mode synth_stub /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_verilog -force -mode funcsim /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_vhdl -force -mode funcsim /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+
+} else {
+
+
+if { [catch {
+ file copy -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.dcp
+} _RESULT ] } {
+ send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+ error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+ file rename -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+close [open .end.used_ip_cache.rst w]
+}; # end if cacheID
+
+if {[file isdir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/ip/clk_wiz_0]} {
+ catch {
+ file copy -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.v /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/ip/clk_wiz_0
+ }
+}
+
+if {[file isdir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/ip/clk_wiz_0]} {
+ catch {
+ file copy -force /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/ip/clk_wiz_0
+ }
+}
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "clk_wiz_0_synth_1" END { }
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.vds b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
new file mode 100644
index 0000000..f00f5a8
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
@@ -0,0 +1,272 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 11:53:05 2025
+# Process ID: 36861
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1
+# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4248.581 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :15254 MB
+#-----------------------------------------------------------
+source clk_wiz_0.tcl -notrace
+create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 1680.684 ; gain = 327.840 ; free physical = 5579 ; free virtual = 14118
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+Command: synth_design -top clk_wiz_0 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 37082
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2501.867 ; gain = 420.523 ; free physical = 4412 ; free virtual = 12955
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.v:68]
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388]
+ Parameter BANDWIDTH bound to: OPTIMIZED - type: string
+ Parameter CLKFBOUT_MULT_F bound to: 6.000000 - type: double
+ Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
+ Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
+ Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: double
+ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer
+ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT2_DIVIDE bound to: 50 - type: integer
+ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT3_DIVIDE bound to: 12 - type: integer
+ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
+ Parameter COMPENSATION bound to: ZHOLD - type: string
+ Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
+ Parameter STARTUP_WAIT bound to: FALSE - type: string
+INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.v:68]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2578.805 ; gain = 497.461 ; free physical = 4294 ; free virtual = 12848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2596.617 ; gain = 515.273 ; free physical = 4291 ; free virtual = 12849
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2596.617 ; gain = 515.273 ; free physical = 4291 ; free virtual = 12849
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2602.555 ; gain = 0.000 ; free physical = 4291 ; free virtual = 12849
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.555 ; gain = 0.000 ; free physical = 4268 ; free virtual = 12827
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2669.555 ; gain = 0.000 ; free physical = 4268 ; free virtual = 12827
+INFO: [Designutils 20-5008] Incremental synthesis strategy off
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2669.555 ; gain = 588.211 ; free physical = 4286 ; free virtual = 12848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4286 ; free virtual = 12848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4300 ; free virtual = 12861
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4298 ; free virtual = 12862
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4299 ; free virtual = 12862
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4288 ; free virtual = 12863
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4288 ; free virtual = 12863
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4287 ; free virtual = 12863
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----------+------+
+| |Cell |Count |
++------+-----------+------+
+|1 |BUFG | 5|
+|2 |MMCME2_ADV | 1|
+|3 |IBUF | 1|
++------+-----------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 2677.559 ; gain = 523.277 ; free physical = 4277 ; free virtual = 12864
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.566 ; gain = 596.215 ; free physical = 4277 ; free virtual = 12864
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2677.566 ; gain = 0.000 ; free physical = 4277 ; free virtual = 12864
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2677.566 ; gain = 0.000 ; free physical = 4553 ; free virtual = 13141
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: 2bb42201
+INFO: [Common 17-83] Releasing license: Synthesis
+33 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 2677.566 ; gain = 981.039 ; free physical = 4553 ; free virtual = 13141
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2253.438; main = 1881.028; forked = 419.174
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3782.270; main = 2677.562; forked = 1104.707
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2701.570 ; gain = 0.000 ; free physical = 4580 ; free virtual = 13168
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 0edd54b7fee8338b
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.598 ; gain = 0.000 ; free physical = 4578 ; free virtual = 13170
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 11:54:28 2025...
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..cb1c83687cfae52aa803755d175323d25126deae
GIT binary patch
literal 276
zcmd;LGcqtT(KDRHtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp-
z<zZl8V3^CxP}J=4lo!N)D+D6<3NsWjd$fvx*u9b<@~$L9g^Bx8DG+<DJOe|6{a<;8
zhCb(`3cAZS+nrSfiO*GIXxQfbR1L)LH3E@$jTjg#U6vYy*lR5q7#2AEwP0Xia5`$q
zz)<Bl$%?}%)Xm*FB*^Ei9mvSJ_6!UPj!(hlTNjX~y{;gURyPp4*BeCM^=4pba9HXC
iVt?}Cbq@(}HHvrkaP;$Y^;sJT68#$pGV5p%hz$V0Fh)WE
literal 0
HcmV?d00001
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
new file mode 100644
index 0000000..d002006
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
@@ -0,0 +1,176 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:54:28 2025
+| Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+| Design : clk_wiz_0
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Logic | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Flip Flop | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 0 | Yes | - | Set |
+| 0 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 0 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 1 | 0 | 0 | 285 | 0.35 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 0 | 10 | 10.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| BUFG | 5 | Clock |
+| MMCME2_ADV | 1 | Clock |
+| IBUF | 1 | IO |
++------------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc b/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc
new file mode 100644
index 0000000..e20d5ae
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc
@@ -0,0 +1,32 @@
+# This file is automatically generated.
+# It contains project source information necessary for synthesis and implementation.
+
+# IP: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci
+# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# IP: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci
+# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml b/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml
new file mode 100644
index 0000000..7133487
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml
@@ -0,0 +1,50 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="clk_wiz_0_synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1740567182">
+ <File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_0_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="clk_wiz_0.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="clk_wiz_0_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="clk_wiz_0_utilization_synth.rpt"/>
+ <File Type="VDS-TIMING-PB" Name="clk_wiz_0_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="clk_wiz_0.tcl"/>
+ <File Type="REPORTS-TCL" Name="clk_wiz_0_reports.tcl"/>
+ <File Type="RDS-RDS" Name="clk_wiz_0.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="clk_wiz_0_drc_synth.rpt"/>
+ <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0" RelGenDir="$PGENDIR/clk_wiz_0">
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0" RelGenDir="$PGENDIR/clk_wiz_0">
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+</GenRun>
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/htr.txt b/proj/AudioProc.runs/clk_wiz_0_synth_1/htr.txt
new file mode 100644
index 0000000..94a0b3d
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/project.wdf b/proj/AudioProc.runs/clk_wiz_0_synth_1/project.wdf
new file mode 100644
index 0000000..e347b49
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:466c6f775f506572664f7074696d697a65645f48696768:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
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+70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f31345c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3430316638303238363638613434623761383162376161656563363734373430:506172656e742050412070726f6a656374204944:00
+eof:14405968
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/rundef.js b/proj/AudioProc.runs/clk_wiz_0_synth_1/rundef.js
new file mode 100644
index 0000000..d930527
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.bat b/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.bat
new file mode 100644
index 0000000..637899f
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.log b/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.log
new file mode 100644
index 0000000..66e639b
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.log
@@ -0,0 +1,262 @@
+
+*** Running vivado
+ with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 26 11:53:05 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source clk_wiz_0.tcl -notrace
+create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 1680.684 ; gain = 327.840 ; free physical = 5579 ; free virtual = 14118
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+Command: synth_design -top clk_wiz_0 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 37082
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2501.867 ; gain = 420.523 ; free physical = 4412 ; free virtual = 12955
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.v:68]
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388]
+ Parameter BANDWIDTH bound to: OPTIMIZED - type: string
+ Parameter CLKFBOUT_MULT_F bound to: 6.000000 - type: double
+ Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
+ Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
+ Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: double
+ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer
+ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT2_DIVIDE bound to: 50 - type: integer
+ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT3_DIVIDE bound to: 12 - type: integer
+ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
+ Parameter COMPENSATION bound to: ZHOLD - type: string
+ Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
+ Parameter STARTUP_WAIT bound to: FALSE - type: string
+INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.v:68]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2578.805 ; gain = 497.461 ; free physical = 4294 ; free virtual = 12848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2596.617 ; gain = 515.273 ; free physical = 4291 ; free virtual = 12849
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2596.617 ; gain = 515.273 ; free physical = 4291 ; free virtual = 12849
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2602.555 ; gain = 0.000 ; free physical = 4291 ; free virtual = 12849
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.555 ; gain = 0.000 ; free physical = 4268 ; free virtual = 12827
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2669.555 ; gain = 0.000 ; free physical = 4268 ; free virtual = 12827
+INFO: [Designutils 20-5008] Incremental synthesis strategy off
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2669.555 ; gain = 588.211 ; free physical = 4286 ; free virtual = 12848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4286 ; free virtual = 12848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4300 ; free virtual = 12861
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4298 ; free virtual = 12862
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4299 ; free virtual = 12862
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4288 ; free virtual = 12863
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4288 ; free virtual = 12863
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4287 ; free virtual = 12863
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----------+------+
+| |Cell |Count |
++------+-----------+------+
+|1 |BUFG | 5|
+|2 |MMCME2_ADV | 1|
+|3 |IBUF | 1|
++------+-----------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.559 ; gain = 596.215 ; free physical = 4289 ; free virtual = 12865
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 2677.559 ; gain = 523.277 ; free physical = 4277 ; free virtual = 12864
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2677.566 ; gain = 596.215 ; free physical = 4277 ; free virtual = 12864
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2677.566 ; gain = 0.000 ; free physical = 4277 ; free virtual = 12864
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2677.566 ; gain = 0.000 ; free physical = 4553 ; free virtual = 13141
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: 2bb42201
+INFO: [Common 17-83] Releasing license: Synthesis
+33 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 2677.566 ; gain = 981.039 ; free physical = 4553 ; free virtual = 13141
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2253.438; main = 1881.028; forked = 419.174
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3782.270; main = 2677.562; forked = 1104.707
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2701.570 ; gain = 0.000 ; free physical = 4580 ; free virtual = 13168
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 0edd54b7fee8338b
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2757.598 ; gain = 0.000 ; free physical = 4578 ; free virtual = 13170
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 11:54:28 2025...
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.sh b/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.sh
new file mode 100755
index 0000000..e2b3f0f
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.jou b/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.jou
new file mode 100644
index 0000000..a97cbf1
--- /dev/null
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 11:53:05 2025
+# Process ID: 36861
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1
+# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4248.581 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :15254 MB
+#-----------------------------------------------------------
+source clk_wiz_0.tcl -notrace
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.pb b/proj/AudioProc.runs/clk_wiz_0_synth_1/vivado.pb
new file mode 100644
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000..15435ca
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Feb 26 12:25:18 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj tb_firUnit_vlog.prj"
+xvlog --incr --relax -prj tb_firUnit_vlog.prj 2>&1 | tee compile.log
+
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee -a compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000..43f9ab9
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,21 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling module xil_defaultlib.glbl
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000..629e137
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Feb 26 12:25:21 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
new file mode 100755
index 0000000..ed3b249
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000..3a14ee6
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000..e6d1d1c
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Feb 26 12:18:18 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..d0b4d93baa959cb7c0df7f33dd774ebc51d719ca
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
new file mode 100644
index 0000000..0107b4e
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -0,0 +1,9 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../src/hdl/firUnit.vhd" \
+"../../../../../src/hdl/tb_firUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
new file mode 100644
index 0000000..76b7b44
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
@@ -0,0 +1,7 @@
+# compile verilog/system verilog design source files
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..43a1def838315285f5ced7ff416a763f33fc462d
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000..2965ab3
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" "xil_defaultlib.glbl" -log "elaborate.log"
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
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HcmV?d00001
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000..71dfa28
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -0,0 +1,142 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_2(char*, char *);
+IKI_DLLESPEC extern void execute_3(char*, char *);
+IKI_DLLESPEC extern void execute_4(char*, char *);
+IKI_DLLESPEC extern void execute_5(char*, char *);
+IKI_DLLESPEC extern void execute_6(char*, char *);
+IKI_DLLESPEC extern void execute_7(char*, char *);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_56(char*, char *);
+IKI_DLLESPEC extern void execute_57(char*, char *);
+IKI_DLLESPEC extern void execute_58(char*, char *);
+IKI_DLLESPEC extern void execute_59(char*, char *);
+IKI_DLLESPEC extern void execute_60(char*, char *);
+IKI_DLLESPEC extern void execute_61(char*, char *);
+IKI_DLLESPEC extern void execute_62(char*, char *);
+IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[36] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 36;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 36);
+ iki_vhdl_file_variable_register(dp + 14184);
+ iki_vhdl_file_variable_register(dp + 14240);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_firUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_firUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_firUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
new file mode 100644
index 0000000..1198a3c
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 15088705700611705432 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl" ,
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+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_firUnit_behav/xsimk\" \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000..cb0db76
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=181
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=209
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
+OBJECT_NAME_COLUMN_WIDTH=183
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
new file mode 100644
index 0000000..dd6b8e0
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51495
+Design successfully loaded
+Design Loading Memory Usage: 20184 KB (Peak: 20756 KB)
+Design Loading CPU Usage: 20 ms
+Simulation completed
+Simulation Memory Usage: 101920 KB (Peak: 159452 KB)
+Simulation CPU Usage: 50 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
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diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
new file mode 100644
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new file mode 100644
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GIT binary patch
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literal 0
HcmV?d00001
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..264db57
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,9 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v,1708598507,verilog,,,,glbl,,,,,,,,
+/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd,1740567123,vhdl,/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd,1740559580,vhdl,/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd,1740569105,vhdl,/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/tb_firUnit.vhd,1740559580,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..65c1bae
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,490 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak
new file mode 100644
index 0000000..65c1bae
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -0,0 +1,490 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000..c80084a
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..123cc48f4be058465ccf604a8505bc71e22ce897
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log
new file mode 100644
index 0000000..e69de29
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
new file mode 100644
index 0000000..8228398
--- /dev/null
+++ b/proj/AudioProc.xpr
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="401f8028668a44b7a81b7aaeec674740"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="17"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="1"/>
+ <Option Name="WTModelSimExportSim" Val="1"/>
+ <Option Name="WTQuestaExportSim" Val="1"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="1"/>
+ <Option Name="WTRivieraExportSim" Val="1"/>
+ <Option Name="WTActivehdlExportSim" Val="1"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <File Path="$PPRDIR/tb_firUnit_behav.wcfg">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_firUnit"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ <Option Name="XSimWcfgFile" Val="$PPRDIR/tb_firUnit_behav.wcfg"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="clk_wiz_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0" RelGenDir="$PGENDIR/clk_wiz_0">
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
+ <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
+ </StratHandle>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="clk_wiz_0_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_0" Part="xc7a200tsbg484-1" ConstrsSet="clk_wiz_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clk_wiz_0_synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+ <Desc>Vivado Implementation Defaults</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/proj/ip_upgrade.log b/proj/ip_upgrade.log
new file mode 100644
index 0000000..844ce36
--- /dev/null
+++ b/proj/ip_upgrade.log
@@ -0,0 +1,27 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:52:51 2025
+| Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+| Command : upgrade_ip
+| Device : xc7a200tsbg484-1
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'clk_wiz_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of clk_wiz_0 from xilinx.com:ip:clk_wiz:5.2 to xilinx.com:ip:clk_wiz:6.0 (Rev. 14)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'clk_wiz_0'. These changes may impact your design.
+
+
+-Upgraded port order differs after port 'reset'
+
+
diff --git a/proj/tb_firUnit_behav.wcfg b/proj/tb_firUnit_behav.wcfg
new file mode 100644
index 0000000..f90eed5
--- /dev/null
+++ b/proj/tb_firUnit_behav.wcfg
@@ -0,0 +1,95 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="tb_firUnit_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="glbl" />
+ <top_module name="tb_firUnit" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+ <ZoomEndTime time="325.501 ns"></ZoomEndTime>
+ <Cursor1Time time="141.500 ns"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="195"></NameColumnWidth>
+ <ValueColumnWidth column_width="60"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="18" />
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_clock">
+ <obj_property name="ElementShortName">SC_clock</obj_property>
+ <obj_property name="ObjectShortName">SC_clock</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_reset">
+ <obj_property name="ElementShortName">SC_reset</obj_property>
+ <obj_property name="ObjectShortName">SC_reset</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/SC_inputSample">
+ <obj_property name="ElementShortName">SC_inputSample[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_inputSample[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_inputSampleValid">
+ <obj_property name="ElementShortName">SC_inputSampleValid</obj_property>
+ <obj_property name="ObjectShortName">SC_inputSampleValid</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/SC_filteredSample">
+ <obj_property name="ElementShortName">SC_filteredSample[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_filteredSample[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/SC_filteredSampleValid">
+ <obj_property name="ElementShortName">SC_filteredSampleValid</obj_property>
+ <obj_property name="ObjectShortName">SC_filteredSampleValid</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDone">
+ <obj_property name="ElementShortName">O_processingDone</obj_property>
+ <obj_property name="ObjectShortName">O_processingDone</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/O_Y">
+ <obj_property name="ElementShortName">O_Y[7:0]</obj_property>
+ <obj_property name="ObjectShortName">O_Y[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_coefRegister">
+ <obj_property name="ElementShortName">SR_coefRegister[0:15][7:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_coefRegister[0:15][7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_shiftRegister">
+ <obj_property name="ElementShortName">SR_shiftRegister[0:15][7:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_shiftRegister[0:15][7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand1">
+ <obj_property name="ElementShortName">SC_multOperand1[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_multOperand1[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand2">
+ <obj_property name="ElementShortName">SC_multOperand2[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_multOperand2[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SC_MultResult">
+ <obj_property name="ElementShortName">SC_MultResult[15:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_MultResult[15:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SC_addResult">
+ <obj_property name="ElementShortName">SC_addResult[19:0]</obj_property>
+ <obj_property name="ObjectShortName">SC_addResult[19:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_sum">
+ <obj_property name="ElementShortName">SR_sum[19:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_sum[19:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_Y">
+ <obj_property name="ElementShortName">SR_Y[7:0]</obj_property>
+ <obj_property name="ObjectShortName">SR_Y[7:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/I_loadY">
+ <obj_property name="ElementShortName">I_loadY</obj_property>
+ <obj_property name="ObjectShortName">I_loadY</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/tb_firUnit/firUnit_1/operativeUnit_1/SR_readAddress">
+ <obj_property name="ElementShortName">SR_readAddress</obj_property>
+ <obj_property name="ObjectShortName">SR_readAddress</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/proj/vivado.jou b/proj/vivado.jou
new file mode 100644
index 0000000..d54a508
--- /dev/null
+++ b/proj/vivado.jou
@@ -0,0 +1,83 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 09:59:54 2025
+# Process ID: 10833
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj
+# Command line: vivado
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/vivado.log
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :1998.882 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :17455 MB
+#-----------------------------------------------------------
+start_gui
+source ./create_project.tcl
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_ip_catalog -rebuild -scan_changes
+report_ip_status -name ip_status
+upgrade_ip -vlnv xilinx.com:ip:clk_wiz:6.0 [get_ips clk_wiz_0] -log ip_upgrade.log
+export_ip_user_files -of_objects [get_ips clk_wiz_0] -no_script -sync -force -quiet
+generate_target all [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci]
+catch { config_ip_cache -export [get_ips -all clk_wiz_0] }
+export_ip_user_files -of_objects [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci] -no_script -sync -force -quiet
+create_ip_run [get_files -of_objects [get_fileset sources_1] /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci]
+launch_runs clk_wiz_0_synth_1 -jobs 2
+wait_on_run clk_wiz_0_synth_1
+export_simulation -of_objects [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci] -directory /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/sim_scripts -ip_user_files_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files -ipstatic_source_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/ipstatic -lib_map_path [list {modelsim=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/modelsim} {questa=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/questa} {xcelium=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/xcelium} {vcs=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/vcs} {riviera=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_firUnit [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+report_ip_status -name ip_status
+launch_simulation
+source tb_firUnit.tcl
+run 10 us
+run 10 us
+run 10 us
+run 10 us
+run 10 us
+run 10 us
+relaunch_sim
+close_sim
+launch_simulation
+source tb_firUnit.tcl
+relaunch_sim
+current_wave_config {Untitled 2}
+add_wave {{/tb_firUnit/firUnit_1/controlUnit_1/SR_presentState}}
+relaunch_sim
+run 10 us
+current_wave_config {Untitled 2}
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_readAddress}}
+relaunch_sim
+close_sim
+launch_simulation
+source tb_firUnit.tcl
+current_wave_config {Untitled 3}
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDone}} {{/tb_firUnit/firUnit_1/operativeUnit_1/O_Y}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_coefRegister}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_shiftRegister}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand1}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand2}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_MultResult}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_addResult}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_sum}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_Y}}
+relaunch_sim
+current_wave_config {Untitled 3}
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/I_loadY}}
+relaunch_sim
+relaunch_sim
+current_wave_config {Untitled 3}
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_readAddress}}
+restart
+run 10 us
+save_wave_config {/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/tb_firUnit_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/tb_firUnit_behav.wcfg
+set_property xsim.view /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/tb_firUnit_behav.wcfg [get_filesets sim_1]
+close_sim
diff --git a/proj/vivado.log b/proj/vivado.log
new file mode 100644
index 0000000..0f12558
--- /dev/null
+++ b/proj/vivado.log
@@ -0,0 +1,1724 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 09:59:54 2025
+# Process ID: 10833
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj
+# Command line: vivado
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/vivado.log
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :1998.882 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :17455 MB
+#-----------------------------------------------------------
+start_gui
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+source ./create_project.tcl
+# if {[info exists ::create_path]} {
+# set dest_dir $::create_path
+# } else {
+# set dest_dir [pwd]
+# }
+# puts "INFO: Creating new project in $dest_dir"
+INFO: Creating new project in /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj
+# set proj_name "AudioProc"
+# set origin_dir ".."
+# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+# set src_dir $origin_dir/src
+# set repo_dir $origin_dir/repo
+# set part_num "xc7a200tsbg484-1"
+# create_project $proj_name $dest_dir
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+# set proj_dir [get_property directory [current_project]]
+# set obj [get_projects $proj_name]
+# set_property "default_lib" "xil_defaultlib" $obj
+# set_property "part" "$part_num" $obj
+# set_property "simulator_language" "Mixed" $obj
+# set_property "target_language" "VHDL" $obj
+# if {[string equal [get_filesets -quiet sources_1] ""]} {
+# create_fileset -srcset sources_1
+# }
+# if {[string equal [get_filesets -quiet constrs_1] ""]} {
+# create_fileset -constrset constrs_1
+# }
+# set obj [get_filesets sources_1]
+# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
+# add_files -quiet $src_dir/hdl
+# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
+# add_files -fileset constrs_1 -quiet $src_dir/constraints
+# if {[string equal [get_runs -quiet synth_1] ""]} {
+# create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
+# } else {
+# set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
+# set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
+# }
+# set obj [get_runs synth_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.synth_design.args.fanout_limit" "400" $obj
+# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
+# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
+# set_property "steps.synth_design.args.resource_sharing" "off" $obj
+# set_property "steps.synth_design.args.no_lc" "1" $obj
+# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
+# current_run -synthesis [get_runs synth_1]
+# if {[string equal [get_runs -quiet impl_1] ""]} {
+# create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+# } else {
+# set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+# set_property flow "Vivado Implementation 2014" [get_runs impl_1]
+# }
+# set obj [get_runs impl_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.write_bitstream.args.bin_file" "1" $obj
+# current_run -implementation [get_runs impl_1]
+impl_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_ip_catalog -rebuild -scan_changes
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+report_ip_status -name ip_status
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+upgrade_ip -vlnv xilinx.com:ip:clk_wiz:6.0 [get_ips clk_wiz_0] -log ip_upgrade.log
+Upgrading 'clk_wiz_0'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [IP_Flow 19-1972] Upgraded clk_wiz_0 from Clocking Wizard 5.2 to Clocking Wizard 6.0
+WARNING: [IP_Flow 19-4707] Upgraded port order differs after port 'reset'
+WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'clk_wiz_0'. These changes may impact your design.
+INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_0'...
+CRITICAL WARNING: [Coretcl 2-1279] The upgrade of 'clk_wiz_0' has identified issues that may require user intervention. Please review the upgrade log '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/ip_upgrade.log', and verify that the upgraded IP is correctly configured.
+INFO: [Coretcl 2-1525] Wrote upgrade log to '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/ip_upgrade.log'.
+upgrade_ip: Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 10092.996 ; gain = 336.473 ; free physical = 6200 ; free virtual = 14742
+export_ip_user_files -of_objects [get_ips clk_wiz_0] -no_script -sync -force -quiet
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+generate_target all [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci]
+INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_0'...
+INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_0'...
+INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_0'...
+INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_0'...
+catch { config_ip_cache -export [get_ips -all clk_wiz_0] }
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+export_ip_user_files -of_objects [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci] -no_script -sync -force -quiet
+create_ip_run [get_files -of_objects [get_fileset sources_1] /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci]
+launch_runs clk_wiz_0_synth_1 -jobs 2
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+[Wed Feb 26 11:53:03 2025] Launched clk_wiz_0_synth_1...
+Run output will be captured here: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/clk_wiz_0_synth_1/runme.log
+export_simulation -of_objects [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci] -directory /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/sim_scripts -ip_user_files_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files -ipstatic_source_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.ip_user_files/ipstatic -lib_map_path [list {modelsim=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/modelsim} {questa=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/questa} {xcelium=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/xcelium} {vcs=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/vcs} {riviera=/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+set_property top tb_firUnit [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/processingUnitIP.v:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/processingUnitIP.v:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/processingUnitIP.v:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+report_ip_status -name ip_status
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/processingUnitIP.v:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/processingUnitIP.v:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/processingUnitIP.v:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_firUnit' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+INFO: [VRFC 10-2263] Analyzing Verilog file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
+INFO: [VRFC 10-311] analyzing module glbl
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+execute_script: Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 10376.637 ; gain = 0.000 ; free physical = 6026 ; free virtual = 14704
+INFO: [USF-XSim-69] 'compile' step finished in '12' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling module xil_defaultlib.glbl
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
+execute_script: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 10376.637 ; gain = 0.000 ; free physical = 5984 ; free virtual = 14728
+INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch {tb_firUnit.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_firUnit.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_firUnit_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:25 . Memory (MB): peak = 10405.938 ; gain = 29.301 ; free physical = 5906 ; free virtual = 14714
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_firUnit' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 10405.938 ; gain = 0.000 ; free physical = 5864 ; free virtual = 14635
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_firUnit' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch {tb_firUnit.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_firUnit.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_firUnit_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 10405.938 ; gain = 0.000 ; free physical = 5844 ; free virtual = 14658
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+Time resolution is 1 ps
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 10435.938 ; gain = 0.000 ; free physical = 5855 ; free virtual = 14627
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/tb_firUnit/firUnit_1/controlUnit_1/SR_presentState}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 10435.938 ; gain = 0.000 ; free physical = 5858 ; free virtual = 14634
+run 10 us
+ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
+current_wave_config {Untitled 2}
+Untitled 2
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_readAddress}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 10435.938 ; gain = 0.000 ; free physical = 5855 ; free virtual = 14628
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [USF-XSim-7] Finding pre-compiled libraries...
+INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-54] Inspecting design source files for 'tb_firUnit' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling module xil_defaultlib.glbl
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch {tb_firUnit.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source tb_firUnit.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_firUnit_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 10475.977 ; gain = 0.000 ; free physical = 5280 ; free virtual = 14605
+current_wave_config {Untitled 3}
+Untitled 3
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/O_processingDone}} {{/tb_firUnit/firUnit_1/operativeUnit_1/O_Y}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_coefRegister}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_shiftRegister}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand1}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_multOperand2}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_MultResult}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SC_addResult}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_sum}} {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_Y}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+Time resolution is 1 ps
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 10475.977 ; gain = 0.000 ; free physical = 5358 ; free virtual = 14631
+current_wave_config {Untitled 3}
+Untitled 3
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/I_loadY}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+Time resolution is 1 ps
+ERROR: Index 16 out of bound 0 to 15
+Time: 275 ns Iteration: 1 Process: /tb_firUnit/firUnit_1/operativeUnit_1/line__119
+ File: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+
+HDL Line: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:119
+relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 10475.977 ; gain = 0.000 ; free physical = 5219 ; free virtual = 14494
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xvlog --incr --relax -prj tb_firUnit_vlog.prj
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'operativeUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'tb_firUnit'
+INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling module xil_defaultlib.glbl
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 10493.980 ; gain = 0.000 ; free physical = 5240 ; free virtual = 14560
+current_wave_config {Untitled 3}
+Untitled 3
+add_wave {{/tb_firUnit/firUnit_1/operativeUnit_1/SR_readAddress}}
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 10 us
+save_wave_config {/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/tb_firUnit_behav.wcfg}
+add_files -fileset sim_1 -norecurse /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/tb_firUnit_behav.wcfg
+set_property xsim.view /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/tb_firUnit_behav.wcfg [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 12:29:33 2025...
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 705905d..c5cc141 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -49,34 +49,62 @@ architecture archi_operativeUnit of controlUnit is
begin
- process (_BLANK_) is
- begin
- if I_reset = '1' then -- asynchronous reset (active high)
- SR_presentState <= _BLANK_
- elsif rising_edge(I_clock) then -- rising clock edge
- _BLANK_
- end if;
- end process;
-
- process (_BLANK_) is
- begin
- case SR_presentState is
-
- when WAIT_SAMPLE =>
- _BLANK_
-
- when others => null;
- end case;
- end process;
-
- O_loadShift <= '1' when _BLANK_ ;
- O_initAddress <= '1' when _BLANK_ ;
- O_incrAddress <= '1' when _BLANK_ ;
- O_initSum <= '1' when _BLANK_ ;
- O_loadSum <= '1' when _BLANK_ ;
- O_loadY <= '1' when _BLANK_ ;
- O_FilteredSampleValid <= '1' when _BLANK_ ;
+ process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_presentState <= WAIT_SAMPLE;
+ elsif rising_edge(I_clock) then -- rising clock edge
+ SR_presentState <= SR_futurState;
+ end if;
+ end process;
+
+
+ -- Next state logic process
+ process (SR_presentState, I_inputSampleValid, I_processingDone) is
+ begin
+ case SR_presentState is
+
+ when WAIT_SAMPLE =>
+ if I_inputSampleValid = '1' then
+ SR_futurState <= STORE;
+ else
+ SR_futurState <= WAIT_SAMPLE;
+ end if;
+
+ when STORE =>
+ SR_futurState <= PROCESSING_LOOP;
+
+ when PROCESSING_LOOP =>
+ if I_processingDone = '1' then
+ SR_futurState <= OUTPUT;
+ else
+ SR_futurState <= PROCESSING_LOOP;
+ end if;
+
+ when OUTPUT =>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+ when WAIT_END_SAMPLE =>
+ if I_inputSampleValid = '0' then
+ SR_futurState <= WAIT_SAMPLE;
+ else
+ SR_futurState <= WAIT_END_SAMPLE;
+ end if;
+
+ when others =>
+ SR_futurState <= WAIT_SAMPLE;
+ end case;
+ end process;
+
+ -- Output logic
+ O_loadShift <= '1' when SR_presentState = STORE else '0';
+ O_initAddress <= '1' when SR_presentState = STORE else '0';
+ O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP else '0';
+ O_initSum <= '1' when SR_presentState = STORE else '0';
+ O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP else '0';
+ O_loadY <= '1' when SR_presentState = OUTPUT else '0';
+ --O_FilteredSampleValid <= _BLANK_;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 1286aff..fe1c926 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -85,42 +85,62 @@ begin
to_signed(2, 8)
);
- shift : process (_BLANK_) is
+ shift : process (I_reset, I_clock) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));
- elsif _BLANK_
-
+ elsif Rising_edge(I_clock) then
+ if I_loadShift = '1' then
+ for i in 1 to 15 loop
+ SR_shiftRegister(i) <= SR_shiftRegister(i-1);
+ end loop;
+ SR_shiftRegister(0) <= signed(I_inputSample);
+ end if;
end if;
- end process shift;
+ end process shift ;
+
+
- incr_address : process (_BLANK_) is
+ incr_address : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0;
- elsif _BLANK_
-
+ elsif Rising_edge(I_clock) then
+ if I_initAddress = '1' then
+ SR_readAddress <= 0;
+ elsif I_incrAddress = '1' and SR_readAddress <= 15 then
+ SR_readAddress <= SR_readAddress + 1;
+ end if;
end if;
end process incr_address;
- O_processingDone <= '1' when _BLANK_ ;
+ O_processingDone <= '1' when SR_readAddress = 14 else '0';
- SC_multOperand1 <= _BLANK_ ; -- 8 bits
- SC_multOperand2 <= _BLANK_ ; -- 8 bits
- SC_MultResult <= _BLANK_ ; -- 16 bits
+ SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 8 bits
+ SC_multOperand2 <= SR_coefRegister(SR_readAddress); -- 8 bits
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 16 bits
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
- sum_acc : process (_BLANK_) is
+ sum_acc : process (I_reset, I_clock) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_sum <= (others => '0');
- elsif _BLANK_
+ elsif Rising_edge(I_clock) then
+ if I_initSum = '1' then
+ SR_sum <= (others => '0');
+ elsif I_loadSum = '1' then
+ SR_sum <= SC_addResult;
+ end if;
end if;
end process sum_acc;
- store_result : process (_BLANK_) is
+ store_result : process (I_clock) is
begin
- _BLANK_
+ if Rising_edge(I_clock) then
+ if I_loadY = '1' then
+ SR_Y <= signed(resize(SC_addResult, SR_Y'length));
+ end if;
+ end if;
end process store_result;
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.dcp b/src/ip/clk_wiz_0/clk_wiz_0.dcp
index 1df5ec10a4ff9e7c1b2e8c55ee8f41698941ff5f..f726fa3af1501226fc8fa1c14219391554de4aa4 100644
GIT binary patch
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diff --git a/src/ip/clk_wiz_0/clk_wiz_0.v b/src/ip/clk_wiz_0/clk_wiz_0.v
index 2e3a203..088af81 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0.v
+++ b/src/ip/clk_wiz_0/clk_wiz_0.v
@@ -1,23 +1,22 @@
+
// file: clk_wiz_0.v
-//
-// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
-//
+// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
+// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
+// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
@@ -26,11 +25,11 @@
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
+// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
-//
+//
// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
+// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
@@ -39,13 +38,12 @@
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
+// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
-//
+//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
-//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
@@ -55,10 +53,10 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
-// CLK_OUT1___100.000______0.000______50.0______151.366____132.063
-// CLK_OUT2___200.000______0.000______50.0______132.221____132.063
-// CLK_OUT3____12.000______0.000______50.0______231.952____132.063
-// CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+// clk_out1__100.00000______0.000______50.0______151.366____132.063
+// clk_out2__200.00000______0.000______50.0______132.221____132.063
+// clk_out3__12.00000______0.000______50.0______231.952____132.063
+// clk_out4__50.00000______0.000______50.0______174.353____132.063
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -67,12 +65,10 @@
`timescale 1ps/1ps
-(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_14_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
- // Clock in ports
- input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
@@ -80,13 +76,13 @@ module clk_wiz_0
output clk_out4,
// Status and control signals
input reset,
- output locked
+ output locked,
+ // Clock in ports
+ input clk_in1
);
clk_wiz_0_clk_wiz inst
(
- // Clock in ports
- .clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
@@ -94,7 +90,9 @@ module clk_wiz_0
.clk_out4(clk_out4),
// Status and control signals
.reset(reset),
- .locked(locked)
+ .locked(locked),
+ // Clock in ports
+ .clk_in1(clk_in1)
);
endmodule
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.vho b/src/ip/clk_wiz_0/clk_wiz_0.vho
index c6b126b..b02ca8e 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0.vho
+++ b/src/ip/clk_wiz_0/clk_wiz_0.vho
@@ -1,22 +1,21 @@
---
--- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
---
+
+-- (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+--
-- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
+-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
+-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
@@ -25,11 +24,11 @@
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
+-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
---
+--
-- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
+-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
@@ -38,13 +37,12 @@
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
+-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
---
+--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
---
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
@@ -54,10 +52,10 @@
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
--- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
--- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
--- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
--- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+-- clk_out1__100.00000______0.000______50.0______151.366____132.063
+-- clk_out2__200.00000______0.000______50.0______132.221____132.063
+-- clk_out3__12.00000______0.000______50.0______231.952____132.063
+-- clk_out4__50.00000______0.000______50.0______174.353____132.063
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
@@ -70,7 +68,6 @@
component clk_wiz_0
port
(-- Clock in ports
- clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
@@ -78,7 +75,8 @@ port
clk_out4 : out std_logic;
-- Status and control signals
reset : in std_logic;
- locked : out std_logic
+ locked : out std_logic;
+ clk_in1 : in std_logic
);
end component;
@@ -88,9 +86,6 @@ end component;
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : clk_wiz_0
port map (
-
- -- Clock in ports
- clk_in1 => clk_in1,
-- Clock out ports
clk_out1 => clk_out1,
clk_out2 => clk_out2,
@@ -98,6 +93,8 @@ your_instance_name : clk_wiz_0
clk_out4 => clk_out4,
-- Status and control signals
reset => reset,
- locked => locked
+ locked => locked,
+ -- Clock in ports
+ clk_in1 => clk_in1
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.xci b/src/ip/clk_wiz_0/clk_wiz_0.xci
index 79f1c0a..8735bea 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0.xci
+++ b/src/ip/clk_wiz_0/clk_wiz_0.xci
@@ -1,525 +1,728 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>clk_wiz_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">200.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">12.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">12.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">6.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">6.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______151.366____132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______132.221____132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____12.000______0.000______50.0______231.952____132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4____50.000______0.000______50.0______174.353____132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">151.366</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">132.221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">231.952</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">12.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">174.353</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">132.063</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">6.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">6.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">sbg484</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- <spirit:vendorExtensions>
- <xilinx:componentInstanceExtensions>
- <xilinx:configElementInfos>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
- </xilinx:configElementInfos>
- </xilinx:componentInstanceExtensions>
- </spirit:vendorExtensions>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
+{
+ "schema": "xilinx.com:schema:json_instance:1.0",
+ "ip_inst": {
+ "xci_name": "clk_wiz_0",
+ "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+ "ip_revision": "14",
+ "gen_directory": ".",
+ "parameters": {
+ "component_parameters": {
+ "Component_Name": [ { "value": "clk_wiz_0", "resolve_type": "user", "usage": "all" } ],
+ "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+ "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+ "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+ "PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+ "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+ "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+ "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+ "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+ "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+ "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+ "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+ "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+ "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+ "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+ "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+ "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+ "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+ "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+ "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+ "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+ "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "50.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+ "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+ "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+ "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+ "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+ "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+ "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+ "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+ "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+ "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKIN1_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT1_DIVIDE": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT2_DIVIDE": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT3_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+ "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+ "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+ "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_JITTER": [ { "value": "151.366", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_PHASE_ERROR": [ { "value": "132.063", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_JITTER": [ { "value": "132.221", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_PHASE_ERROR": [ { "value": "132.063", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_JITTER": [ { "value": "231.952", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_PHASE_ERROR": [ { "value": "132.063", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_JITTER": [ { "value": "174.353", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_PHASE_ERROR": [ { "value": "132.063", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+ "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+ "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+ },
+ "model_parameters": {
+ "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "c_component_name": [ { "value": "clk_wiz_0", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW1": [ { "value": "__primary_________100.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__100.00000______0.000______50.0______151.366____132.063", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__200.00000______0.000______50.0______132.221____132.063", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__12.00000______0.000______50.0______231.952____132.063", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__50.00000______0.000______50.0______174.353____132.063", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_OUT_FREQ": [ { "value": "12.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "50", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+ "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+ "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+ "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+ "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+ "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+ "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+ "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+ "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+ "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+ "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE2_AUTO": [ { "value": "0.5", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE3_AUTO": [ { "value": "8.333333333333334", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE4_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE5_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE6_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE7_AUTO": [ { "value": "0.16666666666666666", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "12.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+ },
+ "project_parameters": {
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "" } ],
+ "BOARD_CONNECTIONS": [ { "value": "" } ],
+ "DEVICE": [ { "value": "xc7a200t" } ],
+ "NEXTGEN_VERSAL": [ { "value": "0" } ],
+ "PACKAGE": [ { "value": "sbg484" } ],
+ "PREFHDL": [ { "value": "VHDL" } ],
+ "SILICON_REVISION": [ { "value": "" } ],
+ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
+ "STATIC_POWER": [ { "value": "" } ],
+ "TEMPERATURE_GRADE": [ { "value": "" } ]
+ },
+ "runtime_parameters": {
+ "IPCONTEXT": [ { "value": "IP_Flow" } ],
+ "IPREVISION": [ { "value": "14" } ],
+ "MANAGED": [ { "value": "TRUE" } ],
+ "OUTPUTDIR": [ { "value": "." } ],
+ "SELECTEDSIMMODEL": [ { "value": "" } ],
+ "SHAREDDIR": [ { "value": "." } ],
+ "SWVERSION": [ { "value": "2024.1" } ],
+ "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+ }
+ },
+ "boundary": {
+ "ports": {
+ "reset": [ { "direction": "in", "driver_value": "0" } ],
+ "clk_in1": [ { "direction": "in" } ],
+ "clk_out1": [ { "direction": "out" } ],
+ "clk_out2": [ { "direction": "out" } ],
+ "clk_out3": [ { "direction": "out" } ],
+ "clk_out4": [ { "direction": "out" } ],
+ "locked": [ { "direction": "out" } ]
+ },
+ "interfaces": {
+ "reset": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "RST": [ { "physical_name": "reset" } ]
+ }
+ },
+ "clock_CLK_IN1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+ }
+ },
+ "clock_CLK_OUT1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+ }
+ },
+ "clock_CLK_OUT2": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
+ }
+ },
+ "clock_CLK_OUT3": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT3": [ { "physical_name": "clk_out3" } ]
+ }
+ },
+ "clock_CLK_OUT4": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT4": [ { "physical_name": "clk_out4" } ]
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.xdc b/src/ip/clk_wiz_0/clk_wiz_0.xdc
index 420a6de..b41c9c9 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0.xdc
+++ b/src/ip/clk_wiz_0/clk_wiz_0.xdc
@@ -1,23 +1,22 @@
+
# file: clk_wiz_0.xdc
-#
-# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
-#
+# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+#
# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
+# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
+# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
@@ -26,11 +25,11 @@
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
+# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
-#
+#
# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
+# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
@@ -39,13 +38,12 @@
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
+# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
-#
+#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
-#
# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system. If required
@@ -53,7 +51,7 @@
#----------------------------------------------------------------
# Connect to input port when clock capable pin is selected for input
create_clock -period 10.0 [get_ports clk_in1]
-set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.10000000000000001
-
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
diff --git a/src/ip/clk_wiz_0/clk_wiz_0.xml b/src/ip/clk_wiz_0/clk_wiz_0.xml
index 66fd124..50ae032 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0.xml
+++ b/src/ip/clk_wiz_0/clk_wiz_0.xml
@@ -149,6 +149,287 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PROTOCOL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ID_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ADDR_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AWUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ARUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>READ_WRITE_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_LOCK</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_PROT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_CACHE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_QOS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_REGION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_WSTRB</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_BRESP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_RRESP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MAX_BURST_LENGTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_THREADS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_THREADS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
@@ -180,7 +461,61 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
@@ -192,87 +527,173 @@
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>s_axi_resetn</spirit:name>
- <spirit:displayName>S_AXI_RESETN</spirit:displayName>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:name>ref_clk</spirit:name>
+ <spirit:displayName>ref_clk</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>RST</spirit:name>
+ <spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>s_axi_aresetn</spirit:name>
+ <spirit:name>ref_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.ASSOCIATED_RESET">aresetn</spirit:value>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_resetn" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ref_clk" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>intr</spirit:name>
- <spirit:displayName>Intr</spirit:displayName>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
- <spirit:master/>
+ <spirit:name>s_axi_resetn</spirit:name>
+ <spirit:displayName>S_AXI_RESETN</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>INTERRUPT</spirit:name>
+ <spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>ip2intc_irpt</spirit:name>
+ <spirit:name>s_axi_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.ASSOCIATED_RESET">aresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.intr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_resetn" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_IN1</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
+ <spirit:name>intr</spirit:name>
+ <spirit:displayName>Intr</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+ <spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_in1</spirit:name>
+ <spirit:name>interrupt</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.BOARD.ASSOCIATED_PARAM">CLK_IN1_BOARD_INTERFACE</spirit:value>
+ <spirit:name>SENSITIVITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.INTR.SENSITIVITY">EDGE_RISING</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PortWidth</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:presence>required</xilinx:presence>
- </xilinx:enablement>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
@@ -280,7 +701,7 @@
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_IN1" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Single_ended_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Single_ended_non_clock_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="No_buffer") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Global_buffer"))">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.intr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
@@ -322,39 +743,21 @@
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_IN1_D" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_non_clock_pin"))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clock_CLK_IN2</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk_in2</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
<spirit:parameter>
- <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN2.BOARD.ASSOCIATED_PARAM">CLK_IN2_BOARD_INTERFACE</spirit:value>
+ <spirit:name>CAN_DEBUG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:presence>required</xilinx:presence>
- </xilinx:enablement>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
@@ -362,7 +765,7 @@
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_IN2" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Single_ended_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Single_ended_non_clock_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="No_buffer") or (spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Global_buffer")) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER'))=1))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_IN1_D" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_non_clock_pin"))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
@@ -404,6 +807,24 @@
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CAN_DEBUG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
@@ -413,29 +834,6 @@
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clock_CLKFB_IN</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clkfb_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLKFB_IN" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))!=1) or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO_OFFCHIP") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))!="DIFF")))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
<spirit:busInterface>
<spirit:name>CLKFB_IN_D</spirit:name>
<spirit:displayName>CLKFB_IN_D</spirit:displayName>
@@ -461,458 +859,665 @@
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>CAN_DEBUG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLKFB_IN_D" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF")))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLKFB_IN_D" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP")) and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF") and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_OUT1</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:name>CLKFB_OUT_D</spirit:name>
+ <spirit:displayName>CLKFB_OUT_D</spirit:displayName>
+ <spirit:description>Differential Feeback Clock Output</spirit:description>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>CLK_N</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out1</spirit:name>
+ <spirit:name>clkfb_out_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clock_CLK_OUT2</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>CLK_P</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out2</spirit:name>
+ <spirit:name>clkfb_out_p</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:value>
+ <spirit:name>CAN_DEBUG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_OUT2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_USED'))=1)">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLKFB_OUT_D" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP")) and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF") and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_OUT3</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
+ <spirit:name>reset</spirit:name>
+ <spirit:displayName>reset</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out3</spirit:name>
+ <spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:value>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_OUT3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_USED'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0)">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=0) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_OUT4</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
+ <spirit:name>resetn</spirit:name>
+ <spirit:displayName>resetn</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out4</spirit:name>
+ <spirit:name>resetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.FREQ_HZ">100000000</spirit:value>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_OUT4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_USED'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0)">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.resetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=1) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_OUT5</spirit:name>
+ <spirit:name>clock_CLK_IN1</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
- <spirit:master/>
+ <spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>CLK_IN1</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out5</spirit:name>
+ <spirit:name>clk_in1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT5.FREQ_HZ">100000000</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT5.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
+ <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.BOARD.ASSOCIATED_PARAM">CLK_IN1_BOARD_INTERFACE</spirit:value>
</spirit:parameter>
</spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_OUT5" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_USED'))=1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_OUT6</spirit:name>
+ <spirit:name>clock_CLK_OUT1</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>CLK_OUT1</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out6</spirit:name>
+ <spirit:name>clk_out1</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT6.FREQ_HZ">100000000</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT6.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_OUT6" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_USED'))=1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLK_OUT7</spirit:name>
+ <spirit:name>clock_CLK_OUT2</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>CLK_OUT2</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clk_out7</spirit:name>
+ <spirit:name>clk_out2</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT7.FREQ_HZ">100000000</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_BUSIF"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_RESET"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>ASSOCIATED_MMCM_LOCK</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT7.ASSOCIATED_MMCM_LOCK">locked</spirit:value>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLK_OUT7" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_USED'))=1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>clock_CLKFB_OUT</spirit:name>
+ <spirit:name>clock_CLK_OUT3</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK</spirit:name>
+ <spirit:name>CLK_OUT3</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clkfb_out</spirit:name>
+ <spirit:name>clk_out3</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.clock_CLKFB_OUT" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))!=1) or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO_OFFCHIP") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))!="DIFF")))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_BUSIF"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_RESET"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
- <spirit:name>CLKFB_OUT_D</spirit:name>
- <spirit:displayName>CLKFB_OUT_D</spirit:displayName>
- <spirit:description>Differential Feeback Clock Output</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+ <spirit:name>clock_CLK_OUT4</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
- <spirit:name>CLK_N</spirit:name>
+ <spirit:name>CLK_OUT4</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
- <spirit:name>clkfb_out_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CLK_P</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clkfb_out_p</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLKFB_OUT_D" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF")))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:displayName>reset</spirit:displayName>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>reset</spirit:name>
+ <spirit:name>clk_out4</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=0) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>resetn</spirit:name>
- <spirit:displayName>resetn</spirit:displayName>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>resetn</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
<spirit:parameter>
- <spirit:name>POLARITY</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.ASSOCIATED_BUSIF"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.ASSOCIATED_RESET"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT4.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.resetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=1) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>s_drp</spirit:name>
- <spirit:displayName>s_drp</spirit:displayName>
- <spirit:description>Slave DRP Port</spirit:description>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DADDR</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>daddr</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DEN</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>den</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DI</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>din</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DO</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>dout</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DRDY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>drdy</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DWE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>dwe</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_drp" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
- <spirit:name>xilinx_vhdlinstantiationtemplate</spirit:name>
- <spirit:displayName>VHDL Instantiation Template</spirit:displayName>
- <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
- <spirit:language>vhdl</spirit:language>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:modelName>clk_wiz_v6_0_14</spirit:modelName>
<spirit:fileSetRef>
- <spirit:localName>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:localName>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>df5bfb27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Wed Feb 26 10:52:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:19cc2464</spirit:value>
</spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesimulationwrapper</spirit:name>
+ <spirit:displayName>Simulation Wrapper</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:modelName>clk_wiz_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:32 UTC 2016</spirit:value>
+ <spirit:value>Wed Feb 26 10:52:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:19cc2464</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -920,33 +1525,18 @@
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:modelName>clk_wiz_v6_0_14</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
- <spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>df5bfb27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:33 UTC 2016</spirit:value>
+ <spirit:value>Wed Feb 26 10:52:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -954,101 +1544,47 @@
<spirit:name>xilinx_anylanguagesynthesiswrapper</spirit:name>
<spirit:displayName>Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+ <spirit:modelName>clk_wiz_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
- <spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>df5bfb27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:33 UTC 2016</spirit:value>
+ <spirit:value>Wed Feb 26 10:52:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
- <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
- <spirit:displayName>Simulation</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
- <spirit:fileSetRef>
- <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
- </spirit:fileSetRef>
+ <spirit:name>xilinx_elaborateports</spirit:name>
+ <spirit:displayName>Elaborate Ports</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>b7329546</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:33 UTC 2016</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:8ebd4ae1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
- <spirit:name>xilinx_anylanguagesimulationwrapper</spirit:name>
- <spirit:displayName>Simulation Wrapper</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:name>xilinx_externalfiles</spirit:name>
+ <spirit:displayName>External Files</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
- <spirit:localName>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:localName>
+ <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
- <spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>b7329546</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:33 UTC 2016</spirit:value>
+ <spirit:value>Wed Feb 26 10:54:28 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1061,28 +1597,23 @@
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>df5bfb27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Wed Feb 26 10:53:00 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:33 UTC 2016</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_synthesisconstraints</spirit:name>
+ <spirit:displayName>Synthesis Constraints</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+ <spirit:parameters>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1094,63 +1625,33 @@
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
- <spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>df5bfb27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:11:33 UTC 2016</spirit:value>
+ <spirit:value>Wed Feb 26 10:53:00 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
- <spirit:name>xilinx_externalfiles</spirit:name>
- <spirit:displayName>External Files</spirit:displayName>
- <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+ <spirit:name>xilinx_vhdlinstantiationtemplate</spirit:name>
+ <spirit:displayName>VHDL Instantiation Template</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>clk_wiz_v6_0_14</spirit:modelName>
<spirit:fileSetRef>
- <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+ <spirit:localName>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
- <spirit:parameter>
- <spirit:name>customizationCRC</spirit:name>
- <spirit:value>df5bfb27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>customizationCRCversion</spirit:name>
- <spirit:value>5</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRC</spirit:name>
- <spirit:value>893de65f</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>boundaryCRCversion</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Fri Jan 22 01:13:26 UTC 2016</spirit:value>
+ <spirit:value>Wed Feb 26 10:52:50 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
- <spirit:name>StaleAtRelink</spirit:name>
- <spirit:value>false</spirit:value>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:72f46ee5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1180,705 +1681,7 @@
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>s_axi_aresetn</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_aresetn" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>s_axi_awaddr</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH')) - 1)">10</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awaddr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in2_n" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Differential_non_clock_pin")) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER'))=1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>clk_in_sel</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in_sel" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER'))=1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>clkfb_in</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))!=1) or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO_OFFCHIP") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))!="DIFF")))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>clkfb_in_p</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in_p" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF")))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>clkfb_in_n</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in_n" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF")))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>daddr</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">6</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.daddr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>dclk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
- </spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dclk" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>den</spirit:name>
+ <spirit:name>s_axi_aresetn</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -1895,17 +1698,17 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.den" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_aresetn" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>din</spirit:name>
+ <spirit:name>s_axi_awaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
- <spirit:left spirit:format="long">15</spirit:left>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH')) - 1)">10</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -1922,37 +1725,36 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.din" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awaddr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>dout</spirit:name>
+ <spirit:name>s_axi_awvalid</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">15</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
- </spirit:vector>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
+ <spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dout" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awvalid" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>drdy</spirit:name>
+ <spirit:name>s_axi_awready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -1966,18 +1768,22 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drdy" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awready" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>dwe</spirit:name>
+ <spirit:name>s_axi_wdata</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
@@ -1989,18 +1795,22 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dwe" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_RECONFIG')) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wdata" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>psclk</spirit:name>
+ <spirit:name>s_axi_wstrb</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH')) div 8) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
@@ -2012,13 +1822,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.psclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wstrb" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>psen</spirit:name>
+ <spirit:name>s_axi_wvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2035,15 +1845,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.psen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wvalid" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>psincdec</spirit:name>
+ <spirit:name>s_axi_wready</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2051,25 +1861,26 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.psincdec" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wready" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>psdone</spirit:name>
+ <spirit:name>s_axi_bresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
@@ -2078,13 +1889,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.psdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bresp" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out1</spirit:name>
+ <spirit:name>s_axi_bvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -2095,9 +1906,16 @@
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
+ <spirit:vendorExtensions>
+ <xilinx:portInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bvalid" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:portInfo>
+ </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out1_ce</spirit:name>
+ <spirit:name>s_axi_bready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2114,18 +1932,22 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out1_ce" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT1_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT1_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT1_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bready" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out1_clr</spirit:name>
+ <spirit:name>s_axi_araddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH')) - 1)">10</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
@@ -2137,15 +1959,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out1_clr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT1_DRIVES'))="BUFR")">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_araddr" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out2</spirit:name>
+ <spirit:name>s_axi_arvalid</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2153,19 +1975,22 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_USED'))=1)">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arvalid" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out2_ce</spirit:name>
+ <spirit:name>s_axi_arready</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2173,48 +1998,50 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out2_ce" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out2_clr</spirit:name>
+ <spirit:name>s_axi_rdata</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out2_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_DRIVES'))="BUFR") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT2_USED'))=1))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out3</spirit:name>
+ <spirit:name>s_axi_rresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
@@ -2223,15 +2050,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_USED'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0)">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out3_ce</spirit:name>
+ <spirit:name>s_axi_rvalid</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2239,20 +2066,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out3_ce" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out3_clr</spirit:name>
+ <spirit:name>s_axi_rready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2269,15 +2093,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out3_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_DRIVES'))="BUFR") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT3_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out4</spirit:name>
+ <spirit:name>clk_in1_p</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2285,17 +2109,20 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_USED'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0)">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in1_p" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_non_clock_pin"))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out4_ce</spirit:name>
+ <spirit:name>clk_in1_n</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2312,13 +2139,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out4_ce" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in1_n" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_PRIM_SOURCE'))="Differential_non_clock_pin"))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out4_clr</spirit:name>
+ <spirit:name>clk_in2_p</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2335,15 +2162,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out4_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_DRIVES'))="BUFR") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT4_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in2_p" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Differential_non_clock_pin")) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER'))=1))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out5</spirit:name>
+ <spirit:name>clk_in2_n</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2351,17 +2178,20 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out5" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_USED'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in2_n" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Differential_clock_capable_pin") or (spirit:decode(id('MODELPARAM_VALUE.C_SECONDARY_SOURCE'))="Differential_non_clock_pin")) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER'))=1))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out5_ce</spirit:name>
+ <spirit:name>clkfb_in_p</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2378,13 +2208,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out5_ce" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in_p" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP")) and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF") and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out5_clr</spirit:name>
+ <spirit:name>clkfb_in_n</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2401,13 +2231,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out5_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_DRIVES'))="BUFR") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT5_USED'))=1))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in_n" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP")) and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF") and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out6</spirit:name>
+ <spirit:name>clkfb_out_p</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -2421,15 +2251,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out6" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_USED'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out_p" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP")) and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF") and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out6_ce</spirit:name>
+ <spirit:name>clkfb_out_n</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2437,20 +2267,17 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out6_ce" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out_n" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP")) and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF") and ((spirit:decode(id('MODELPARAM_VALUE.C_MMCM_COMPENSATION'))!="INTERNAL"))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out6_clr</spirit:name>
+ <spirit:name>reset</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2467,15 +2294,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out6_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_DRIVES'))="BUFR") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT6_USED'))=1))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=0) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out7</spirit:name>
+ <spirit:name>resetn</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2483,17 +2310,20 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out7" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_USED'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.resetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=1) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out7_ce</spirit:name>
+ <spirit:name>ref_clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2510,18 +2340,22 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out7_ce" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_DRIVES'))="BUFGCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_DRIVES'))="BUFHCE") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_DRIVES'))="BUFR")) and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_USED'))=1)) and (spirit:decode(id('MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP'))=0)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ref_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clk_out7_clr</spirit:name>
+ <spirit:name>clk_stop</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
@@ -2533,33 +2367,40 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_out7_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_DRIVES'))="BUFR") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKOUT7_USED'))=1))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_stop" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clkfb_out</spirit:name>
+ <spirit:name>clk_glitch</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))!=1) or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO_OFFCHIP") or (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))!="DIFF")))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_glitch" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clkfb_out_p</spirit:name>
+ <spirit:name>interrupt</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -2569,37 +2410,47 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out_p" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF")))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clkfb_out_n</spirit:name>
+ <spirit:name>clk_oor</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out_n" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and ((spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))!="FDBK_AUTO") or (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) or ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP"))) and ((spirit:decode(id('MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_FEEDBACK_SOURCE'))="FDBK_AUTO_OFFCHIP") and (spirit:decode(id('MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING'))="DIFF")))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_oor" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>reset</spirit:name>
+ <spirit:name>user_clk0</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2616,13 +2467,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=0) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">true</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_Enable_PLL0'))=0)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>resetn</spirit:name>
+ <spirit:name>user_clk1</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2639,13 +2490,13 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.resetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_RESET'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_RESET_LOW'))=1) and (not spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION')))">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_Enable_PLL1'))=0)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>power_down</spirit:name>
+ <spirit:name>user_clk2</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
@@ -2662,15 +2513,15 @@
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.power_down" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_POWER_DOWN'))=1)">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>input_clk_stopped</spirit:name>
+ <spirit:name>user_clk3</spirit:name>
<spirit:wire>
- <spirit:direction>out</spirit:direction>
+ <spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2678,17 +2529,33 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
</spirit:wire>
<spirit:vendorExtensions>
<xilinx:portInfo>
<xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.input_clk_stopped" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_INCLK_STOPPED'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_PRIMITIVE'))="MMCM")">false</xilinx:isEnabled>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:portInfo>
</spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>clkfb_stopped</spirit:name>
+ <spirit:name>clk_in1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>clk_out1</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -2699,16 +2566,9 @@
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_stopped" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_CLKFB_STOPPED'))=1) and (spirit:decode(id('MODELPARAM_VALUE.C_PRIMITIVE'))="MMCM")">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>locked</spirit:name>
+ <spirit:name>clk_out2</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -2719,16 +2579,9 @@
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.locked" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_USE_LOCKED'))=1)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>cddcdone</spirit:name>
+ <spirit:name>clk_out3</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -2739,18 +2592,24 @@
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cddcdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_HAS_CDDC'))=1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
</spirit:port>
<spirit:port>
- <spirit:name>cddcreq</spirit:name>
+ <spirit:name>clk_out4</spirit:name>
<spirit:wire>
- <spirit:direction>in</spirit:direction>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_logic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>locked</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
@@ -2758,17 +2617,7 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
- <spirit:driver>
- <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
- </spirit:driver>
</spirit:wire>
- <spirit:vendorExtensions>
- <xilinx:portInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cddcreq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_HAS_CDDC'))=1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:portInfo>
- </spirit:vendorExtensions>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
@@ -2776,6 +2625,62 @@
<spirit:name>C_CLKOUT2_USED</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_USED" spirit:order="194">1</spirit:value>
</spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USER_CLK_FREQ0</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ0" spirit:order="1194">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="string">
+ <spirit:name>C_AUTO_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUTO_PRIMITIVE" spirit:order="1195">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USER_CLK_FREQ1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ1" spirit:order="1195">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USER_CLK_FREQ2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ2" spirit:order="1196">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USER_CLK_FREQ3</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ3" spirit:order="1197">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLOCK_MONITOR</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR" spirit:order="1200">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_USER_CLOCK0</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0" spirit:order="1201">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_USER_CLOCK1</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1" spirit:order="1202">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_USER_CLOCK2</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2" spirit:order="1203">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_USER_CLOCK3</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3" spirit:order="1204">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_Enable_PLL0</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_Enable_PLL0" spirit:order="1205">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_Enable_PLL1</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_Enable_PLL1" spirit:order="1206">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_REF_CLK_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REF_CLK_FREQ" spirit:order="1209">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PRECISION</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRECISION" spirit:order="1209">1</spirit:value>
+ </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="INTEGER">
<spirit:name>C_CLKOUT3_USED</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_USED" spirit:order="195">1</spirit:value>
@@ -2856,6 +2761,10 @@
<spirit:name>C_USE_DYN_PHASE_SHIFT</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT" spirit:order="213">0</spirit:value>
</spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN" spirit:order="214">0</spirit:value>
+ </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="INTEGER">
<spirit:name>C_USE_INCLK_SWITCHOVER</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER" spirit:order="214">0</spirit:value>
@@ -2908,6 +2817,10 @@
<spirit:name>C_PRIM_SOURCE</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_SOURCE" spirit:order="224">Single_ended_clock_capable_pin</spirit:value>
</spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PHASESHIFT_MODE" spirit:order="2240">WAVEFORM</spirit:value>
+ </spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_SECONDARY_SOURCE</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_SOURCE" spirit:order="225">Single_ended_clock_capable_pin</spirit:value>
@@ -3003,19 +2916,19 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">CLK_OUT1___100.000______0.000______50.0______151.366____132.063</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">clk_out1__100.00000______0.000______50.0______151.366____132.063</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">CLK_OUT2___200.000______0.000______50.0______132.221____132.063</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">clk_out2__200.00000______0.000______50.0______132.221____132.063</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">CLK_OUT3____12.000______0.000______50.0______231.952____132.063</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">clk_out3__12.00000______0.000______50.0______231.952____132.063</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">CLK_OUT4____50.000______0.000______50.0______174.353____132.063</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">clk_out4__50.00000______0.000______50.0______174.353____132.063</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
@@ -3115,19 +3028,19 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">100.000</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">100.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">200.000</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">200.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">12.000</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">12.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">50.000</spirit:value>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">50.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
@@ -3279,33 +3192,33 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">6.000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">3</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">50</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">12</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
</spirit:modelParameter>
@@ -3526,198 +3439,463 @@
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_SECONDARY_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ <spirit:name>C_SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">reset</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_HAS_CDDC</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_REG</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_REG" spirit:order="409">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_2" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_2" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT1_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ <spirit:name>C_CLKFBOUT_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_1" spirit:order="410">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT2_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ <spirit:name>C_CLKFBOUT_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_2" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT3_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ <spirit:name>C_DIVCLK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVCLK" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT4_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ <spirit:name>C_LOCK_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_1" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT5_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ <spirit:name>C_LOCK_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_2" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT6_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ <spirit:name>C_LOCK_3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_3" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_OUT7_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ <spirit:name>C_FILTER_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_1" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_RESET_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">reset</spirit:value>
+ <spirit:name>C_FILTER_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_2" spirit:order="411">0000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_LOCKED_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ <spirit:name>C_DIVIDE1_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE1_AUTO" spirit:order="411">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_IN_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ <spirit:name>C_DIVIDE2_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.5</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ <spirit:name>C_DIVIDE3_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE3_AUTO" spirit:order="411">8.333333333333334</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ <spirit:name>C_DIVIDE4_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE4_AUTO" spirit:order="411">2.0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ <spirit:name>C_DIVIDE5_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE5_AUTO" spirit:order="411">0.16666666666666666</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ <spirit:name>C_DIVIDE6_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE6_AUTO" spirit:order="411">0.16666666666666666</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ <spirit:name>C_DIVIDE7_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE7_AUTO" spirit:order="411">0.16666666666666666</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_POWER_DOWN_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ <spirit:name>C_PLLBUFGCEDIV</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DADDR_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DCLK_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ <spirit:name>C_PLLBUFGCEDIV1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV1" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DRDY_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ <spirit:name>C_PLLBUFGCEDIV2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV2" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DWE_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ <spirit:name>C_PLLBUFGCEDIV3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV3" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DIN_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ <spirit:name>C_PLLBUFGCEDIV4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV4" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DOUT_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_DEN_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PSCLK_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PSEN_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PSINCDEC_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PSDONE_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_VALID_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ <spirit:name>C_MMCMBUFGCEDIV7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_STATUS_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ <spirit:name>C_CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ <spirit:name>C_CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ <spirit:name>C_CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ <spirit:name>C_CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ <spirit:name>C_CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ <spirit:name>C_CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PRIMITIVE</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ <spirit:name>C_CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_SS_MODE</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ <spirit:name>C_CLKOUT0_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ" spirit:order="711">100.00000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_SS_MOD_PERIOD</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">200.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_SS_MOD_TIME</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ <spirit:name>C_CLKOUT2_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ" spirit:order="713">12.00000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_HAS_CDDC</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ" spirit:order="714">50.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CDDCDONE_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ <spirit:name>C_CLKOUT4_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ" spirit:order="715">100.000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CDDCREQ_PORT</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ <spirit:name>C_CLKOUT5_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ" spirit:order="716">100.000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ <spirit:name>C_CLKOUT6_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ" spirit:order="717">100.000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_M_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MAX" spirit:order="403">64.000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_INTERFACE_SELECTION</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_M_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MIN" spirit:order="403">2.000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
- <spirit:displayName>C S Axi Addr Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_D_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MAX" spirit:order="403">80.000</spirit:value>
</spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
- <spirit:displayName>C S Axi Data Width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_D_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MIN" spirit:order="403">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_O_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MAX" spirit:order="403">128.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_O_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MIN" spirit:order="403">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_VCO_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MIN" spirit:order="403">600.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_VCO_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MAX" spirit:order="403">1200.000</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_1d3de01d</spirit:name>
+ <spirit:enumeration>WAVEFORM</spirit:enumeration>
+ <spirit:enumeration>LATENCY</spirit:enumeration>
+ </spirit:choice>
<spirit:choice>
<spirit:name>choice_list_876bfc32</spirit:name>
<spirit:enumeration>UI</spirit:enumeration>
@@ -3769,6 +3947,12 @@
<spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
<spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
</spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_340369e0</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys clock">sys_clock</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_3c2d3ec7</spirit:name>
<spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
@@ -3789,6 +3973,12 @@
<spirit:enumeration spirit:text="BUFHCE">BUFHCE</spirit:enumeration>
<spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
</spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_77d3d587</spirit:name>
+ <spirit:enumeration spirit:text="MMCM">MMCM</spirit:enumeration>
+ <spirit:enumeration spirit:text="PLL">PLL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE DIV">BUFGCE_DIV</spirit:enumeration>
+ </spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_8b28f1f7</spirit:name>
<spirit:enumeration spirit:text="AXI4Lite">Enable_AXI</spirit:enumeration>
@@ -3835,10 +4025,59 @@
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
- <spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>clk_wiz_0.vho</spirit:name>
- <spirit:userFileType>vhdlTemplate</spirit:userFileType>
+ <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -3859,46 +4098,51 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
- <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
</spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
</spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
</spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
</spirit:file>
- </spirit:fileSet>
- <spirit:fileSet>
- <spirit:name>xilinx_implementation_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>clk_wiz_0_board.xdc</spirit:name>
- <spirit:userFileType>xdc</spirit:userFileType>
- <spirit:userFileType>USED_IN_board</spirit:userFileType>
- <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
- <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_14</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
- <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+ <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>doc/clk_wiz_v5_2_changelog.txt</spirit:name>
- <spirit:userFileType>text</spirit:userFileType>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -3937,6 +4181,30 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_board.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_board</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>doc/clk_wiz_v6_0_changelog.txt</spirit:name>
+ <spirit:userFileType>text</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.vho</spirit:name>
+ <spirit:userFileType>vhdlTemplate</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
</spirit:fileSets>
<spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.</spirit:description>
<spirit:parameters>
@@ -3944,6 +4212,76 @@
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clk_wiz_0</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ0</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ0" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ1</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ1" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ2</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ2" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ3</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ3" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLOCK_MONITOR</spirit:name>
+ <spirit:displayName>Enable Clock Monitoring</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLOCK_MONITOR" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
+ <spirit:displayName>Optimize Clocking Structure</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK2</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK2" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK3</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK3" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REF_CLK_FREQ</spirit:name>
+ <spirit:displayName>Reference Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.REF_CLK_FREQ" spirit:order="15300" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRECISION</spirit:name>
+ <spirit:displayName>Tolerance(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRECISION" spirit:order="15400" spirit:minimum="1" spirit:maximum="100">1</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>PRIMITIVE</spirit:name>
<spirit:displayName>Primitive</spirit:displayName>
@@ -3999,6 +4337,10 @@
<spirit:name>IN_FREQ_UNITS</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHASESHIFT_MODE" spirit:choiceRef="choice_list_1d3de01d" spirit:order="116" spirit:configGroups="0 NoDisplay">WAVEFORM</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>IN_JITTER_UNITS</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
@@ -4283,6 +4625,34 @@
<spirit:name>USE_MIN_O_JITTER</spirit:name>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING" spirit:order="984" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING" spirit:order="985" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING" spirit:order="986" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING" spirit:order="987" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING" spirit:order="988" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING" spirit:order="989" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING" spirit:order="990" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>PRIM_SOURCE</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
@@ -4445,7 +4815,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="106" spirit:rangeType="long">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_BANDWIDTH</spirit:name>
@@ -4513,7 +4883,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">3</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
@@ -4529,7 +4899,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">50</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay">50</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
@@ -4545,7 +4915,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">12</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay">12</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
@@ -4561,7 +4931,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
@@ -4577,7 +4947,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
@@ -4593,7 +4963,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
@@ -4767,11 +5137,11 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.8">Custom</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.8">Custom</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.9">Custom</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.9">Custom</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
@@ -4781,6 +5151,10 @@
<spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AUTO_PRIMITIVE" spirit:choiceRef="choice_pairs_77d3d587" spirit:order="13212">MMCM</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
@@ -4877,42 +5251,66 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>INPUT_MODE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="14.4">frequency</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="7.8">frequency</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INTERFACE_SELECTION</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AXI_DRP</spirit:name>
+ <spirit:displayName>Write DRP registers</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_DRP" spirit:order="11.12">false</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE_DUTY_CONFIG</spirit:name>
<spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PHASE_DUTY_CONFIG">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>Clocking Wizard</xilinx:displayName>
- <xilinx:coreRevision>0</xilinx:coreRevision>
+ <xilinx:xpmLibraries>
+ <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+ </xilinx:xpmLibraries>
+ <xilinx:coreRevision>14</xilinx:coreRevision>
<xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
@@ -4922,12 +5320,12 @@
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2015.3</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="69bff2c8"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3a523104"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="a5d35bf6"/>
- <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="18e8d175"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="09870f83"/>
+ <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52494094"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f72112df"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4f3d3737"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c11c59cd"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="63dcade9"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
index e47643a..eb66c80 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
+++ b/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
@@ -1,23 +1,22 @@
+
// file: clk_wiz_0.v
-//
-// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
-//
+// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
+// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
+// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
@@ -26,11 +25,11 @@
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
+// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
-//
+//
// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
+// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
@@ -39,13 +38,12 @@
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
+// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
-//
+//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
-//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
@@ -55,10 +53,10 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
-// CLK_OUT1___100.000______0.000______50.0______151.366____132.063
-// CLK_OUT2___200.000______0.000______50.0______132.221____132.063
-// CLK_OUT3____12.000______0.000______50.0______231.952____132.063
-// CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+// clk_out1__100.00000______0.000______50.0______151.366____132.063
+// clk_out2__200.00000______0.000______50.0______132.221____132.063
+// clk_out3__12.00000______0.000______50.0______231.952____132.063
+// clk_out4__50.00000______0.000______50.0______174.353____132.063
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -68,8 +66,8 @@
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
+
(// Clock in ports
- input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
@@ -77,23 +75,35 @@ module clk_wiz_0_clk_wiz
output clk_out4,
// Status and control signals
input reset,
- output locked
+ output locked,
+ input clk_in1
);
-
// Input buffering
//------------------------------------
+wire clk_in1_clk_wiz_0;
+wire clk_in2_clk_wiz_0;
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
+
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
+
+ wire clk_out1_clk_wiz_0;
+ wire clk_out2_clk_wiz_0;
+ wire clk_out3_clk_wiz_0;
+ wire clk_out4_clk_wiz_0;
+ wire clk_out5_clk_wiz_0;
+ wire clk_out6_clk_wiz_0;
+ wire clk_out7_clk_wiz_0;
+
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
@@ -179,12 +189,12 @@ module clk_wiz_0_clk_wiz
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
-
assign reset_high = reset;
assign locked = locked_int;
-
- // Output buffering
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
//-----------------------------------
BUFG clkf_buf
@@ -193,6 +203,9 @@ module clk_wiz_0_clk_wiz
+
+
+
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
index 41c79d7..773dcfa 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+++ b/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
@@ -1,23 +1,22 @@
+
# file: clk_wiz_0_ooc.xdc
-#
-# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
-#
+# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+#
# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
+# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
+# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
@@ -26,11 +25,11 @@
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
+# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
-#
+#
# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
+# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
@@ -39,13 +38,12 @@
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
+# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
-#
+#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
-#
#################
#DEFAULT CLOCK CONSTRAINTS
@@ -54,3 +52,4 @@
# Clock Period Constraints #
############################################################
#create_clock -period 10.0 [get_ports clk_in1]
+
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
index e0a8184..65edb90 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+++ b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
@@ -1,9 +1,11 @@
-// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-// Date : Thu Jan 21 17:13:26 2016
-// Host : WK86 running 64-bit Service Pack 1 (build 7601)
-// Command : write_verilog -force -mode funcsim C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date : Wed Feb 26 11:54:28 2025
+// Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+// Command : write_verilog -force -mode funcsim
+// /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -11,23 +13,22 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
-(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_0
- (clk_in1,
- clk_out1,
+ (clk_out1,
clk_out2,
clk_out3,
clk_out4,
reset,
- locked);
- input clk_in1;
+ locked,
+ clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
input reset;
output locked;
+ input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
@@ -37,7 +38,7 @@ module clk_wiz_0
wire locked;
wire reset;
- clk_wiz_0_clk_wiz_0_clk_wiz inst
+ clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
@@ -47,22 +48,21 @@ module clk_wiz_0
.reset(reset));
endmodule
-(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
-module clk_wiz_0_clk_wiz_0_clk_wiz
- (clk_in1,
- clk_out1,
+module clk_wiz_0_clk_wiz
+ (clk_out1,
clk_out2,
clk_out3,
clk_out4,
reset,
- locked);
- input clk_in1;
+ locked,
+ clk_in1);
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
input reset;
output locked;
+ input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
@@ -214,12 +214,15 @@ module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
+ wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
@@ -232,6 +235,7 @@ module glbl ();
reg GSR_int;
reg GTS_int;
reg PRLD_int;
+ reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
@@ -256,9 +260,10 @@ module glbl ();
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
- assign (weak1, weak0) GSR = GSR_int;
- assign (weak1, weak0) GTS = GTS_int;
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
@@ -274,5 +279,13 @@ module glbl ();
GTS_int = 1'b0;
end
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
endmodule
`endif
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
index 84ae83d..1ca8b0e 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+++ b/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
@@ -1,9 +1,11 @@
--- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
--- Date : Thu Jan 21 17:13:26 2016
--- Host : WK86 running 64-bit Service Pack 1 (build 7601)
--- Command : write_vhdl -force -mode funcsim C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Feb 26 11:54:28 2025
+-- Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+-- Command : write_vhdl -force -mode funcsim
+-- /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -13,21 +15,19 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-entity clk_wiz_0_clk_wiz_0_clk_wiz is
+entity clk_wiz_0_clk_wiz is
port (
- clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
reset : in STD_LOGIC;
- locked : out STD_LOGIC
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
);
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
-end clk_wiz_0_clk_wiz_0_clk_wiz;
+end clk_wiz_0_clk_wiz;
-architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
+architecture STRUCTURE of clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clk_out2_clk_wiz_0 : STD_LOGIC;
@@ -189,23 +189,21 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
- clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
reset : in STD_LOGIC;
- locked : out STD_LOGIC
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_0 : entity is true;
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_0;
architecture STRUCTURE of clk_wiz_0 is
begin
-inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
+inst: entity work.clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_stub.v b/src/ip/clk_wiz_0/clk_wiz_0_stub.v
index 3e730b7..88530c7 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+++ b/src/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -1,9 +1,11 @@
-// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
-// Date : Thu Jan 21 17:13:26 2016
-// Host : WK86 running 64-bit Service Pack 1 (build 7601)
-// Command : write_verilog -force -mode synth_stub C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date : Wed Feb 26 11:54:28 2025
+// Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+// Command : write_verilog -force -mode synth_stub
+// /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
@@ -12,13 +14,18 @@
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
-module clk_wiz_0(clk_in1, clk_out1, clk_out2, clk_out3, clk_out4, reset, locked)
-/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,clk_out2,clk_out3,clk_out4,reset,locked" */;
- input clk_in1;
- output clk_out1;
- output clk_out2;
- output clk_out3;
- output clk_out4;
+module clk_wiz_0(clk_out1, clk_out2, clk_out3, clk_out4, reset,
+ locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */
+/* synthesis syn_force_seq_prim="clk_out2" */
+/* synthesis syn_force_seq_prim="clk_out3" */
+/* synthesis syn_force_seq_prim="clk_out4" */;
+ output clk_out1 /* synthesis syn_isclock = 1 */;
+ output clk_out2 /* synthesis syn_isclock = 1 */;
+ output clk_out3 /* synthesis syn_isclock = 1 */;
+ output clk_out4 /* synthesis syn_isclock = 1 */;
input reset;
output locked;
+ input clk_in1;
endmodule
diff --git a/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
index 262c691..04dfc6c 100644
--- a/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+++ b/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -1,9 +1,11 @@
--- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
--- Date : Thu Jan 21 17:13:26 2016
--- Host : WK86 running 64-bit Service Pack 1 (build 7601)
--- Command : write_vhdl -force -mode synth_stub C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date : Wed Feb 26 11:54:28 2025
+-- Host : fl-tp-br-604 running 64-bit Ubuntu 24.04.1 LTS
+-- Command : write_vhdl -force -mode synth_stub
+-- /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
-- Design : clk_wiz_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
@@ -13,13 +15,13 @@ use IEEE.STD_LOGIC_1164.ALL;
entity clk_wiz_0 is
Port (
- clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
reset : in STD_LOGIC;
- locked : out STD_LOGIC
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
);
end clk_wiz_0;
@@ -28,6 +30,6 @@ architecture stub of clk_wiz_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,clk_out2,clk_out3,clk_out4,reset,locked";
+attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,reset,locked,clk_in1";
begin
end;
diff --git a/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt b/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
deleted file mode 100644
index c88739c..0000000
--- a/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-2015.3:
- * Version 5.2
- * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
- * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
- * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
- * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
- * Example design and simulation files are delivered in verilog only
-
-2015.2.1:
- * Version 5.1 (Rev. 6)
- * No changes
-
-2015.2:
- * Version 5.1 (Rev. 6)
- * No changes
-
-2015.1:
- * Version 5.1 (Rev. 6)
- * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
- * Supported devices and production status are now determined automatically, to simplify support for future devices
-
-2014.4.1:
- * Version 5.1 (Rev. 5)
- * No changes
-
-2014.4:
- * Version 5.1 (Rev. 5)
- * Internal device family change, no functional changes
- * updates related to the source selection based on board interface for zed board
-
-2014.3:
- * Version 5.1 (Rev. 4)
- * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
-
-2014.2:
- * Version 5.1 (Rev. 3)
- * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
-
-2014.1:
- * Version 5.1 (Rev. 2)
- * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
- * Internal device family name change, no functional changes
-
-2013.4:
- * Version 5.1 (Rev. 1)
- * Added support for Ultrascale devices
- * Updated Board Flow GUI to select the clock interfaces
- * Fixed issue with Stub file parameter error for BUFR output driver
-
-2013.3:
- * Version 5.1
- * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
- * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
- * Fixed precision issues between displayed and actual frequencies
- * Added tool tips to GUI
- * Added Jitter and Phase error values to IP properties
- * Added support for Cadence IES and Synopsys VCS simulators
- * Reduced warnings in synthesis and simulation
- * Enhanced support for IP Integrator
-
-2013.2:
- * Version 5.0 (Rev. 1)
- * Fixed issue with clock constraints for multiple instances of clocking wizard
- * Updated Life-Cycle status of devices
-
-2013.1:
- * Version 5.0
- * Lower case ports for Verilog
- * Added Safe Clock Startup and Clock Sequencing
-
-(c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
diff --git a/src/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/src/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt
new file mode 100755
index 0000000..7c91ba6
--- /dev/null
+++ b/src/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt
@@ -0,0 +1,323 @@
+2024.1:
+ * Version 6.0 (Rev. 14)
+ * General: IP packaging adjustments to address warnings from IP Packager integrity check
+
+2023.2.2:
+ * Version 6.0 (Rev. 13)
+ * No changes
+
+2023.2.1:
+ * Version 6.0 (Rev. 13)
+ * No changes
+
+2023.2:
+ * Version 6.0 (Rev. 13)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2023.1.2:
+ * Version 6.0 (Rev. 12)
+ * No changes
+
+2023.1.1:
+ * Version 6.0 (Rev. 12)
+ * No changes
+
+2023.1:
+ * Version 6.0 (Rev. 12)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2022.2.2:
+ * Version 6.0 (Rev. 11)
+ * No changes
+
+2022.2.1:
+ * Version 6.0 (Rev. 11)
+ * No changes
+
+2022.2:
+ * Version 6.0 (Rev. 11)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2022.1.2:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1.1:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1:
+ * Version 6.0 (Rev. 10)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.2.2:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2.1:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2:
+ * Version 6.0 (Rev. 9)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.1.1:
+ * Version 6.0 (Rev. 8)
+ * No changes
+
+2021.1:
+ * Version 6.0 (Rev. 8)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.3:
+ * Version 6.0 (Rev. 7)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.2.2:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2.1:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2:
+ * Version 6.0 (Rev. 6)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.1.1:
+ * Version 6.0 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 6.0 (Rev. 5)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.2.2:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2.1:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2:
+ * Version 6.0 (Rev. 4)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.1.3:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 6.0 (Rev. 3)
+ * Bug Fix: Internal GUI fixes
+ * Other: New family support added
+
+2018.3.1:
+ * Version 6.0 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 6.0 (Rev. 2)
+ * Bug Fix: Made input source independent for primary and secondary clock
+ * Other: New family support added
+
+2018.2:
+ * Version 6.0 (Rev. 1)
+ * Bug Fix: Removed vco freq check when Primitive is None
+ * Other: New family support added
+
+2018.1:
+ * Version 6.0
+ * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
+ * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
+ * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
+ * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
+ * Other: DRCs added for invalid input values in Override mode
+
+2017.4:
+ * Version 5.4 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
+ * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
+
+2017.3:
+ * Version 5.4 (Rev. 2)
+ * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
+
+2017.2:
+ * Version 5.4 (Rev. 1)
+ * General: Internal GUI changes. No effect on the customer design.
+
+2017.1:
+ * Version 5.4
+ * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
+ * Other: Added support for new zynq ultrascale plus devices.
+
+2016.4:
+ * Version 5.3 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed.
+
+2016.3:
+ * Version 5.3 (Rev. 2)
+ * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
+ * Feature Enhancement: Added Matched Routing Option for better timing solutions.
+ * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Other: Added support for Spartan7 devices.
+
+2016.2:
+ * Version 5.3 (Rev. 1)
+ * Internal register bit update, no effect on customer designs.
+
+2016.1:
+ * Version 5.3
+ * Added Clock Monitor Feature as part of clocking wizard
+ * DRP registers can be directly written through AXI without resource utilization
+ * Changes to HDL library management to support Vivado IP simulation library
+
+2015.4.2:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 5.2 (Rev. 1)
+ * Internal device family change, no functional changes
+
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2024 Advanced Micro Devices, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of AMD and is protected under U.S. and international copyright
+and other intellectual property laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+AMD, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) AMD shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or AMD had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+AMD products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of AMD products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000..6c4981a
--- /dev/null
+++ b/src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1011_00,
+ 10'b0010_1101_00,
+ 10'b0010_0011_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0100_1111_00,
+ 10'b0101_1011_00,
+ 10'b0111_0111_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_1001_00,
+ 10'b1101_0001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0111_0001_00,
+ 10'b0111_0001_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0110_0001_00,
+ 10'b0110_0001_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0100_1010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000..b662a3e
--- /dev/null
+++ b/src/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,542 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+`ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+`ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+`endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+`ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+`ifdef DEBUG
+ $display("temp: %h", temp);
+`endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1101_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0011_0111_00,
+ 10'b0011_0111_00,
+ 10'b0101_1111_00,
+ 10'b0111_1111_00,
+ 10'b0111_1011_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_1101_00,
+ 10'b1111_0111_00,
+ 10'b1111_1011_00,
+ 10'b1111_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+`endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+`ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
diff --git a/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000..154c81f
--- /dev/null
+++ b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
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+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
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+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_0011_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_1001_11,
+ 10'b0010_1001_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1011_11,
+ 10'b0011_1111_11,
+ 10'b0100_1111_11,
+ 10'b0100_1111_11,
+ 10'b0101_1111_11,
+ 10'b0110_1111_11,
+ 10'b0111_1111_11,
+ 10'b0111_1111_11,
+ 10'b1100_1111_11,
+ 10'b1101_1111_11,
+ 10'b1110_1111_11,
+ 10'b1111_1111_11,
+ 10'b1111_1111_11,
+ 10'b1110_0111_11,
+ 10'b1110_1011_11,
+ 10'b1111_0111_11,
+ 10'b1111_1011_11,
+ 10'b1111_1011_11,
+ 10'b1110_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000..ff369d1
--- /dev/null
+++ b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,555 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: AMD
+// Engineer: Jim Tatsukawa
+// Date: 6/15/2015
+// Design Name: PLLE3 DRP
+// Module Name: plle3_drp_func.h
+// Version: 1.10
+// Target Devices: UltraScale Architecture
+// Tool versions: 2015.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// PM_Rise bits have been removed for PLLE3
+//
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [759:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001 //19
+
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 19
+ );
+
+ reg [639:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0010_1111_01, //1
+ 10'b0010_0011_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0010_0001_11, //4
+ 10'b0010_0110_11, //5
+ 10'b0010_1010_11, //6
+ 10'b0010_1010_11, //7
+ 10'b0011_0110_11, //8
+ 10'b0010_1100_11, //9
+ 10'b0010_1100_11, //10
+ 10'b0010_1100_11, //11
+ 10'b0010_0010_11, //12
+ 10'b0011_1100_11, //13
+ 10'b0011_1100_11, //14
+ 10'b0011_1100_11, //15
+ 10'b0011_1100_11, //16
+ 10'b0011_0010_11, //17
+ 10'b0011_0010_11, //18
+ 10'b0011_0010_11 //19
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
+
diff --git a/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000..fd26211
--- /dev/null
+++ b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,886 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: AMD
+// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
+// Date: 7/30/2014
+// Design Name: MMCME4 DRP
+// Module Name: mmcme4_drp_func.h
+// Version: 1.31
+// Target Devices: UltraScale Plus Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for UltraScal+ MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function
+// 2/28/17 - Updated for Ultrascale Plus
+//
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [7:0] divide // Max M divide is 128 in UltrascalePlus
+ );
+
+ reg [5119:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=2
+ 40'b01000_01000_1111101000_1111101001_0000000001, // M=3
+ 40'b01011_01011_1111101000_1111101001_0000000001, // M=4
+ 40'b01110_01110_1111101000_1111101001_0000000001, // M=5
+ 40'b10001_10001_1111101000_1111101001_0000000001, // M=6
+ 40'b10011_10011_1111101000_1111101001_0000000001, // M=7
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001, // M=127
+ 40'b11111_11111_0011111010_1111101001_0000000001 // M=128
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [1279:0] lookup_low;
+ reg [1279:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0011_1111_11, // M=1 - not legal
+ 10'b0011_1111_11, // M=2
+ 10'b0011_1101_11, // M=3
+ 10'b0011_0101_11, // M=4
+ 10'b0011_1001_11, // M=5
+ 10'b0011_1110_11, // M=6
+ 10'b0011_1110_11, // M=7
+ 10'b0011_0001_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0100_0110_11,
+ 10'b0011_1100_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11, // M=127
+ 10'b1101_1000_11 // M=128
+};
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0111_1111_11, // M=1 - not legal
+ 10'b0111_1111_11, // M=2
+ 10'b1110_1111_11, // M=3
+ 10'b1111_1111_11, // M=4
+ 10'b1111_1011_11, // M=5
+ 10'b1111_1101_11, // M=6
+ 10'b1111_0011_11, // M=7
+ 10'b1110_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1110_0110_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11 // M=128
+};
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000..0899943
--- /dev/null
+++ b/src/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,561 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: AMD
+// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
+// Date: 6/15/2015
+// Design Name: PLLE4 DRP
+// Module Name: plle4_drp_func.h
+// Version: 2.0
+// Target Devices: UltraScale+ Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// M_Rise bits have been removed for PLLE3
+// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
+// Ultrascale+ and for max M of 21
+//
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [839:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001, //19
+ 40'b11111_11111_0111110100_1111101001_0000000001, //20
+ 40'b11111_11111_0111011011_1111101001_0000000001 //21
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [209:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0011_0111_11, //1 not legal in Ultrascale+
+ 10'b0011_0111_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0011_1001_11, //4
+ 10'b0011_0001_11, //5
+ 10'b0100_1110_11, //6
+ 10'b0011_0110_11, //7
+ 10'b0011_1010_11, //8
+ 10'b0111_1001_11, //9
+ 10'b0111_1001_11, //10
+ 10'b0101_0110_11, //11
+ 10'b1100_0101_11, //12
+ 10'b0101_1010_11, //13
+ 10'b0110_0110_11, //14
+ 10'b0110_1010_11, //15
+ 10'b0111_0110_11, //16
+ 10'b1111_0101_11, //17
+ 10'b1100_0110_11, //18
+ 10'b1110_0001_11, //19
+ 10'b1101_0110_11, //20
+ 10'b1111_0001_11 //21
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
+// will need to divide the doubled clock VCO clock frequency by
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/vivado.jou b/vivado.jou
new file mode 100644
index 0000000..4057a4e
--- /dev/null
+++ b/vivado.jou
@@ -0,0 +1,25 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 09:51:27 2025
+# Process ID: 9416
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
+# Command line: vivado
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.log
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4294.632 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :17504 MB
+#-----------------------------------------------------------
+start_gui
+source ./proj/create_project.tcl
diff --git a/vivado.log b/vivado.log
new file mode 100644
index 0000000..5171770
--- /dev/null
+++ b/vivado.log
@@ -0,0 +1,97 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 09:51:27 2025
+# Process ID: 9416
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
+# Command line: vivado
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.log
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4294.632 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :17504 MB
+#-----------------------------------------------------------
+start_gui
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+source ./proj/create_project.tcl
+# if {[info exists ::create_path]} {
+# set dest_dir $::create_path
+# } else {
+# set dest_dir [pwd]
+# }
+# puts "INFO: Creating new project in $dest_dir"
+INFO: Creating new project in /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
+# set proj_name "AudioProc"
+# set origin_dir ".."
+# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+# set src_dir $origin_dir/src
+# set repo_dir $origin_dir/repo
+# set part_num "xc7a200tsbg484-1"
+# create_project $proj_name $dest_dir
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+create_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 8079.234 ; gain = 197.969 ; free physical = 7226 ; free virtual = 15602
+# set proj_dir [get_property directory [current_project]]
+# set obj [get_projects $proj_name]
+# set_property "default_lib" "xil_defaultlib" $obj
+# set_property "part" "$part_num" $obj
+# set_property "simulator_language" "Mixed" $obj
+# set_property "target_language" "VHDL" $obj
+# if {[string equal [get_filesets -quiet sources_1] ""]} {
+# create_fileset -srcset sources_1
+# }
+# if {[string equal [get_filesets -quiet constrs_1] ""]} {
+# create_fileset -constrset constrs_1
+# }
+# set obj [get_filesets sources_1]
+# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
+# add_files -quiet $src_dir/hdl
+# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
+# add_files -fileset constrs_1 -quiet $src_dir/constraints
+# if {[string equal [get_runs -quiet synth_1] ""]} {
+# create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
+# } else {
+# set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
+# set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
+# }
+# set obj [get_runs synth_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.synth_design.args.fanout_limit" "400" $obj
+# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
+# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
+# set_property "steps.synth_design.args.resource_sharing" "off" $obj
+# set_property "steps.synth_design.args.no_lc" "1" $obj
+# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
+# current_run -synthesis [get_runs synth_1]
+# if {[string equal [get_runs -quiet impl_1] ""]} {
+# create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+# } else {
+# set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+# set_property flow "Vivado Implementation 2014" [get_runs impl_1]
+# }
+# set obj [get_runs impl_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.write_bitstream.args.bin_file" "1" $obj
+# current_run -implementation [get_runs impl_1]
+impl_1
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 09:59:12 2025...
--
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