diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
index 9b342093142bd1b298b4af63bdebdead3a3ef56e..c7c2fb6900fc092f4c13bd3f83a7b96eb456e558 100644
--- a/proj/AudioProc.cache/wt/project.wpc
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4755494d6f6465:5
eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
index d385d80e33b79d1726f7b3e260f12fc2eafbdfe6..645111d071acd881702c462534e62aa54cf8e8b0 100644
--- a/proj/AudioProc.cache/wt/synthesis.wdf
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -1,7 +1,7 @@
version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:636c6b5f77697a5f30:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:617564696f50726f63:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@@ -12,7 +12,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@@ -20,16 +20,16 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:5b7370656369666965645d:00:00
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-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
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+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:6f6e655f686f74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:6f6666:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
@@ -46,7 +46,7 @@ version:1
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323173:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323637372e3536364d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937322e3133334d42:00:00
-eof:3734131713
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333473:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323634362e3231314d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313034392e3934314d42:00:00
+eof:3095229760
diff --git a/proj/AudioProc.cache/wt/synthesis_details.wdf b/proj/AudioProc.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/proj/AudioProc.cache/wt/webtalk_pa.xml b/proj/AudioProc.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..cccb4e2fc39116253e584f4e7dd90e453db0a39a
--- /dev/null
+++ b/proj/AudioProc.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Mar 5 14:11:06 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="c08af246695d4f33a252c51c1b53f205" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Flow_PerfOptimized_High" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/proj/AudioProc.hw/AudioProc.lpr b/proj/AudioProc.hw/AudioProc.lpr
index afc0a86cf8f820e635f040c3869b4b647d11ec04..aa18adc095c6432a86aa8a7a331502559213b706 100644
--- a/proj/AudioProc.hw/AudioProc.lpr
+++ b/proj/AudioProc.hw/AudioProc.lpr
@@ -4,4 +4,6 @@
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
-<labtools version="1" minor="0"/>
+<labtools version="1" minor="0">
+ <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/proj/AudioProc.hw/hw_1/hw.xml b/proj/AudioProc.hw/hw_1/hw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2cc8b5c9dbf896cee7f203c4cfa2a0fccaedffa0
--- /dev/null
+++ b/proj/AudioProc.hw/hw_1/hw.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<hwsession version="1" minor="2">
+ <device name="xc7a200t_0" gui_info=""/>
+ <ObjectList object_type="hw_device" gui_info="">
+ <Object name="xc7a200t_0" gui_info="">
+ <Properties Property="FULL_PROBES.FILE" value=""/>
+ <Properties Property="PROBES.FILE" value=""/>
+ <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/audioProc.bit"/>
+ <Properties Property="SLR.COUNT" value="1"/>
+ </Object>
+ </ObjectList>
+ <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_2.xml b/proj/AudioProc.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000000000000000000000000000000000000..3a7cdf79fa357dc28e0bbdfc9a7c2ef612e39f5a
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml b/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml
index 71334874c8cca75f5a1bd3a1160b6f578c2496e4..b95e30e4c764164b5b1da059016a4b0b2f24a664 100644
--- a/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml
+++ b/proj/AudioProc.runs/clk_wiz_0_synth_1/gen_run.xml
@@ -1,14 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="clk_wiz_0_synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1740567182">
- <File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_0_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="clk_wiz_0.dcp"/>
<File Type="RDS-UTIL-PB" Name="clk_wiz_0_utilization_synth.pb"/>
- <File Type="RDS-UTIL" Name="clk_wiz_0_utilization_synth.rpt"/>
- <File Type="VDS-TIMING-PB" Name="clk_wiz_0_timing_summary_synth.pb"/>
<File Type="PA-TCL" Name="clk_wiz_0.tcl"/>
+ <File Type="RDS-UTIL" Name="clk_wiz_0_utilization_synth.rpt"/>
<File Type="REPORTS-TCL" Name="clk_wiz_0_reports.tcl"/>
<File Type="RDS-RDS" Name="clk_wiz_0.vds"/>
- <File Type="RDS-PROPCONSTRS" Name="clk_wiz_0_drc_synth.rpt"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0" RelGenDir="$PGENDIR/clk_wiz_0">
<File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
<FileInfo>
@@ -42,9 +39,7 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
diff --git a/proj/AudioProc.runs/impl_1/.Vivado_Implementation.queue.rst b/proj/AudioProc.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.init_design.begin.rst b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7b0499891446e3e8c863122380d480f837389e29
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="c24masso" Host="" Pid="90623">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.init_design.end.rst b/proj/AudioProc.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7b0499891446e3e8c863122380d480f837389e29
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="c24masso" Host="" Pid="90623">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.end.rst b/proj/AudioProc.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.place_design.begin.rst b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7b0499891446e3e8c863122380d480f837389e29
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="c24masso" Host="" Pid="90623">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.place_design.end.rst b/proj/AudioProc.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.route_design.begin.rst b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7b0499891446e3e8c863122380d480f837389e29
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="c24masso" Host="" Pid="90623">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.route_design.end.rst b/proj/AudioProc.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.vivado.begin.rst b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..ac0471eb0f76d43839967bbd3f0d3e65c6f4eb5f
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="c24masso" Host="fl-tp-br-641" Pid="90550" HostCore="4" HostMemory="16257800">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.vivado.end.rst b/proj/AudioProc.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7b0499891446e3e8c863122380d480f837389e29
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="c24masso" Host="" Pid="90623">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.end.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/ISEWrap.js b/proj/AudioProc.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/impl_1/ISEWrap.sh b/proj/AudioProc.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bin b/proj/AudioProc.runs/impl_1/audioProc.bin
new file mode 100644
index 0000000000000000000000000000000000000000..749188e2e6421a3b0cf5846df5a12871d975b393
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc.bin differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bit b/proj/AudioProc.runs/impl_1/audioProc.bit
new file mode 100644
index 0000000000000000000000000000000000000000..4d7964890d45a333d58b9904e15b29bffb899bfe
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc.bit differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.tcl b/proj/AudioProc.runs/impl_1/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d3e132a4190c0065f4bface1f6cfdf1cb0427c79
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc.tcl
@@ -0,0 +1,286 @@
+namespace eval ::optrace {
+ variable script "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param chipscope.maxJobs 1
+ set_param runs.launchOptions { -jobs 2 }
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7a200tsbg484-1
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/wt [current_project]
+ set_property parent.project_path /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.xpr [current_project]
+ set_property ip_repo_paths /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo [current_project]
+ update_ip_catalog
+ set_property ip_output_repo /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+ set_property XPM_LIBRARIES XPM_CDC [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/audioProc.dcp
+ read_ip -quiet /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci
+OPTRACE "read constraints: implementation" START { }
+ read_xdc /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ link_design -top audioProc -part xc7a200tsbg484-1
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx" }
+ set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_io -file audioProc_io_placed.rpt" "report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb" "report_control_sets -verbose -file audioProc_control_sets_placed.rpt" }
+ set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx" "report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx" "report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx" "report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb" "report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt" "report_clock_utilization -file audioProc_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx" }
+ set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+ write_checkpoint -force audioProc_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ set_property XPM_LIBRARIES XPM_CDC [current_project]
+ catch { write_mem_info -force -no_partial_mmi audioProc.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force audioProc.bit -bin_file
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force audioProc}
+ catch {file copy -force audioProc.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/proj/AudioProc.runs/impl_1/audioProc.vdi b/proj/AudioProc.runs/impl_1/audioProc.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..b081471ab2a067c461acfe175cf4882b7ba7f8aa
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -0,0 +1,763 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Mar 5 14:12:22 2025
+# Process ID: 90623
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-641
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3100.043 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :17651 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1571.520 ; gain = 204.840 ; free physical = 6283 ; free virtual = 16059
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1990.426 ; gain = 0.000 ; free physical = 5960 ; free virtual = 15720
+INFO: [Netlist 29-17] Analyzing 92 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc:54]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc:54]
+get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2707.918 ; gain = 624.898 ; free physical = 5455 ; free virtual = 15269
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2707.918 ; gain = 0.000 ; free physical = 5451 ; free virtual = 15265
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2707.918 ; gain = 1117.586 ; free physical = 5451 ; free virtual = 15265
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2707.918 ; gain = 0.000 ; free physical = 5428 ; free virtual = 15244
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2727.762 ; gain = 19.844 ; free physical = 5428 ; free virtual = 15244
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5113 ; free virtual = 14928
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5113 ; free virtual = 14928
+Phase 1 Initialization | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5113 ; free virtual = 14928
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5112 ; free virtual = 14928
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5112 ; free virtual = 14928
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5112 ; free virtual = 14928
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 18b6c7825
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5110 ; free virtual = 14926
+Retarget | Checksum: 18b6c7825
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 1970ed4ba
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5108 ; free virtual = 14924
+Constant propagation | Checksum: 1970ed4ba
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Sweep | Checksum: 1fa5c0332
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+BUFG optimization | Checksum: 1fa5c0332
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Shift Register Optimization | Checksum: 1fa5c0332
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Post Processing Netlist | Checksum: 1fa5c0332
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Phase 9 Finalization | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 2 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Ending Netlist Obfuscation Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+INFO: [Common 17-83] Releasing license: Implementation
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14908
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14908
+Write Physdb Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5091 ; free virtual = 14908
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5094 ; free virtual = 14910
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17b1be318
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5094 ; free virtual = 14910
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5094 ; free virtual = 14910
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f1d75507
+
+Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5076 ; free virtual = 14895
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e01ae09e
+
+Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e01ae09e
+
+Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+Phase 1 Placer Initialization | Checksum: 1e01ae09e
+
+Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 15c659040
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1f06dbb3b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f06dbb3b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 177563483
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 134 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 58 nets or LUTs. Breaked 0 LUT, combined 58 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
+INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5072 ; free virtual = 14899
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 58 | 58 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 58 | 58 | 0 | 9 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 16fcc0717
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5069 ; free virtual = 14897
+Phase 2.4 Global Placement Core | Checksum: 1ab2b8c90
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5069 ; free virtual = 14897
+Phase 2 Global Placement | Checksum: 1ab2b8c90
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5069 ; free virtual = 14897
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 148f50c4f
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c9d6d086
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 10158e9a0
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 11913573e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.5 Fast Optimization
+Phase 3.5 Fast Optimization | Checksum: fce9bc41
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5081 ; free virtual = 14910
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1a65a55ff
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5084 ; free virtual = 14909
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 121f35092
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5084 ; free virtual = 14909
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 158b76b67
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5084 ; free virtual = 14909
+
+Phase 3.9 Fast Optimization
+Phase 3.9 Fast Optimization | Checksum: 1cc1d718d
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5093 ; free virtual = 14918
+Phase 3 Detail Placement | Checksum: 1cc1d718d
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5093 ; free virtual = 14918
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 236b07470
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.182 | TNS=-0.269 |
+Phase 1 Physical Synthesis Initialization | Checksum: 20308c1ff
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 2dd9727f8
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+Phase 4.1.1.1 BUFG Insertion | Checksum: 236b07470
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.522. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5046 ; free virtual = 14871
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5046 ; free virtual = 14871
+Phase 4.1 Post Commit Optimization | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5046 ; free virtual = 14871
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+Phase 4.3 Placer Reporting | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20c662c6b
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+Ending Placer Task | Checksum: 13ced0ba0
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+76 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5026 ; free virtual = 14850
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.25 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14845
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14844
+Wrote PlaceDB: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5017 ; free virtual = 14843
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14842
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14842
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14843
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14843
+Write Physdb Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14843
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 109e7e37 ConstDB: 0 ShapeSum: 9433a205 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 18fdecac | NumContArr: 5b39c82f | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 1f989aa15
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:41 . Memory (MB): peak = 3300.426 ; gain = 198.918 ; free physical = 4818 ; free virtual = 14647
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 1f989aa15
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:41 . Memory (MB): peak = 3300.426 ; gain = 198.918 ; free physical = 4818 ; free virtual = 14647
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 1f989aa15
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:41 . Memory (MB): peak = 3300.426 ; gain = 198.918 ; free physical = 4818 ; free virtual = 14647
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1bd2412ab
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:42 . Memory (MB): peak = 3349.402 ; gain = 247.895 ; free physical = 4767 ; free virtual = 14597
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.526 | TNS=0.000 | WHS=-0.120 | THS=-18.709|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 1012
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 1012
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 1e1ac6fca
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:42 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4759 ; free virtual = 14589
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 1e1ac6fca
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:42 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4759 ; free virtual = 14589
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 1e50d8e52
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:43 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4772 ; free virtual = 14602
+Phase 4 Initial Routing | Checksum: 1e50d8e52
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:43 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4772 ; free virtual = 14602
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 384
+ Number of Nodes with overlaps = 184
+ Number of Nodes with overlaps = 126
+ Number of Nodes with overlaps = 62
+ Number of Nodes with overlaps = 37
+ Number of Nodes with overlaps = 11
+ Number of Nodes with overlaps = 7
+ Number of Nodes with overlaps = 4
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.175 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 2e259928b
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4760 ; free virtual = 14590
+Phase 5 Rip-up And Reroute | Checksum: 2e259928b
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4760 ; free virtual = 14590
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4768 ; free virtual = 14598
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.268 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 6.1 Delay CleanUp | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4777 ; free virtual = 14607
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+Phase 6 Delay and Skew Optimization | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.268 | TNS=0.000 | WHS=0.135 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+Phase 7 Post Hold Fix | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.081324 %
+ Global Horizontal Routing Utilization = 0.0987442 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 230747a87
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 230747a87
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.268 | TNS=0.000 | WHS=0.135 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 230747a87
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+Total Elapsed time in route_design: 46.56 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 14e55bb2d
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 14e55bb2d
+
+Time (s): cpu = 00:00:59 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+95 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:01:00 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 4 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+115 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4736 ; free virtual = 14567
+Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4724 ; free virtual = 14557
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4741 ; free virtual = 14574
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4744 ; free virtual = 14577
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4744 ; free virtual = 14577
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4744 ; free virtual = 14577
+Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4743 ; free virtual = 14577
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+Command: write_bitstream -force audioProc.bit -bin_file
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./audioProc.bit...
+Writing bitstream ./audioProc.bin...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+126 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 3732.207 ; gain = 319.387 ; free physical = 4410 ; free virtual = 14260
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 5 14:14:25 2025...
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..95c7a0b5a4a2cdaee2d0453198407ef151b08d15
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:14:06 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..a5ff748bf07eea21cc03f30eb74a7716bc278fc6
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..965ab5c47abebd7f7d02c97cfab2561182fcb98a
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
@@ -0,0 +1,252 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:14:07 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Device Cell Placement Summary for Global Clock g1
+8. Device Cell Placement Summary for Global Clock g2
+9. Device Cell Placement Summary for Global Clock g3
+10. Clock Region Cell Placement per Global Clock: Region X1Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 120 | 0 | 0 | 0 |
+| BUFIO | 0 | 40 | 0 | 0 | 0 |
+| BUFMR | 0 | 20 | 0 | 0 | 0 |
+| BUFR | 0 | 40 | 0 | 0 | 0 |
+| MMCM | 1 | 10 | 0 | 0 | 0 |
+| PLL | 0 | 10 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 469 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1 |
+| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 1 | 120 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/clkout4_buf/O | clk_1/inst/clk_out4 |
+| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/clkf_buf/O | clk_1/inst/clkfbout_buf_clk_wiz_0 |
+| g3 | src3 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 0 | 1 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/clkout3_buf/O | clk_1/inst/clk_out3 |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT0 | clk_1/inst/clk_out1_clk_wiz_0 |
+| src1 | g1 | MMCME2_ADV/CLKOUT3 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT3 | clk_1/inst/clk_out4_clk_wiz_0 |
+| src2 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKFBOUT | clk_1/inst/clkfbout_clk_wiz_0 |
+| src3 | g3 | MMCME2_ADV/CLKOUT2 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT2 | clk_1/inst/clk_out3_clk_wiz_0 |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
+| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y2 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 589 | 4000 | 184 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
+| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y4 | 0 | 0 |
+| Y3 | 0 | 0 |
+| Y2 | 0 | 0 |
+| Y1 | 0 | 0 |
+| Y0 | 0 | 0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+| g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 10.000 | {0.000 5.000} | 469 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 469 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+7. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| g1 | BUFG/O | n/a | clk_out4_clk_wiz_0 | 20.000 | {0.000 10.000} | 120 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 120 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+8. Device Cell Placement Summary for Global Clock g2
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+| g2 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | 0 | 0 | 1 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+9. Device Cell Placement Summary for Global Clock g3
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| g3 | BUFG/O | n/a | clk_out3_clk_wiz_0 | 83.333 | {0.000 41.667} | 0 | 1 | 0 | 0 | clk_1/inst/clk_out3 |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+10. Clock Region Cell Placement per Global Clock: Region X1Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+| g0 | n/a | BUFG/O | None | 469 | 0 | 469 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
+| g1 | n/a | BUFG/O | None | 120 | 0 | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
+| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
+| g3 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out3 |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y3 [get_cells clk_1/inst/clkf_buf]
+set_property LOC BUFGCTRL_X0Y2 [get_cells clk_1/inst/clkout4_buf]
+set_property LOC BUFGCTRL_X0Y0 [get_cells clk_1/inst/clkout3_buf]
+set_property LOC BUFGCTRL_X0Y1 [get_cells clk_1/inst/clkout1_buf]
+
+# Location of IO Primitives which is load of clock spine
+set_property LOC IOB_X1Y118 [get_cells ac_mclk_OBUF_inst]
+
+# Location of clock ports
+set_property LOC IOB_X1Y124 [get_ports CLK100MHZ]
+
+# Clock net "clk_1/inst/clk_out4" driven by instance "clk_1/inst/clkout4_buf" located at site "BUFGCTRL_X0Y2"
+#startgroup
+create_pblock {CLKAG_clk_1/inst/clk_out4}
+add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out4"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
+
+# Clock net "clk_1/inst/clk_out1" driven by instance "clk_1/inst/clkout1_buf" located at site "BUFGCTRL_X0Y1"
+#startgroup
+create_pblock {CLKAG_clk_1/inst/clk_out1}
+add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out1"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
diff --git a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c7f49d69cf88431371958443c36afd7350b7dec3
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
@@ -0,0 +1,107 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:13:15 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+| Design : audioProc
+| Device : xc7a200t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 29 |
+| Minimum number of control sets | 29 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 67 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 29 |
+| >= 0 to < 4 | 1 |
+| >= 4 to < 6 | 7 |
+| >= 6 to < 8 | 5 |
+| >= 8 to < 10 | 3 |
+| >= 10 to < 12 | 1 |
+| >= 12 to < 14 | 1 |
+| >= 14 to < 16 | 0 |
+| >= 16 | 11 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 24 | 16 |
+| No | No | Yes | 10 | 4 |
+| No | Yes | No | 44 | 15 |
+| Yes | No | No | 79 | 29 |
+| Yes | No | Yes | 304 | 105 |
+| Yes | Yes | No | 128 | 39 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++----------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++----------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| clk_1/inst/clk_out1 | dbuttons/IV[2]_i_1_n_0 | | 1 | 1 | 1.00 |
+| clk_1/inst/clk_out1 | lrclkcnt[3]_i_2_n_0 | lrclkcnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | initialize_audio/initWord[23]_i_1_n_0 | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0 | | 3 | 4 | 1.33 |
+| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[5]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out1 | audio_inout/BCLK_Fall_int | rightFir/firUnit_1/operativeUnit_1/AR[0] | 2 | 5 | 2.50 |
+| clk_1/inst/clk_out1 | | audio_inout/Cnt_Bclk[4]_i_1_n_0 | 2 | 5 | 2.50 |
+| clk_1/inst/clk_out4 | rstn_IBUF | | 3 | 6 | 2.00 |
+| clk_1/inst/clk_out1 | | | 4 | 6 | 1.50 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/state_reg[3][0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0 | initialize_audio/twi_controller/sclCnt0 | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | | initialize_audio/twi_controller/busFreeCnt0 | 4 | 7 | 1.75 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[2] | | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/dataByte[7]_i_1_n_0 | | 2 | 8 | 4.00 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[2] | | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out1 | | rightFir/firUnit_1/operativeUnit_1/AR[0] | 4 | 10 | 2.50 |
+| clk_1/inst/clk_out1 | dbuttons/cnt2 | dbuttons/cnt2[12]_i_1_n_0 | 4 | 13 | 3.25 |
+| clk_1/inst/clk_out4 | | | 12 | 18 | 1.50 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | | 6 | 19 | 3.17 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 11 | 24 | 2.18 |
+| clk_1/inst/clk_out1 | audio_inout/D_L_O_int | rightFir/firUnit_1/operativeUnit_1/AR[0] | 5 | 24 | 4.80 |
+| clk_1/inst/clk_out1 | audio_inout/D_R_O_int[23]_i_1_n_0 | rightFir/firUnit_1/operativeUnit_1/AR[0] | 8 | 24 | 3.00 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/E[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 14 | 24 | 1.71 |
+| clk_1/inst/clk_out1 | audio_inout/Data_Out_int[31]_i_1_n_0 | | 8 | 25 | 3.12 |
+| clk_1/inst/clk_out4 | | initialize_audio/delaycnt0 | 9 | 32 | 3.56 |
+| clk_1/inst/clk_out1 | audio_inout/p_4_in | audio_inout/Data_In_int[31]_i_1_n_0 | 8 | 32 | 4.00 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 43 | 128 | 2.98 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[0] | rightFir/firUnit_1/operativeUnit_1/AR[0] | 37 | 128 | 3.46 |
++----------------------+-----------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..0ee433d552131074c75a044dc1f26398343b8c55
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:13:05 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..f0c1cb2d00d7347420959479be2b38f9c51da16f
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..60864fa88882b9f548d72dd961951ddd63b51da0
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:14:05 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..c0b51dfdab76dab16b0053f9fb42b0b967be1f7f
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f34f610c53c7c78e48bc61c56b09b2698708c523
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
@@ -0,0 +1,526 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:13:16 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_io -file audioProc_io_placed.rpt
+| Design : audioProc
+| Device : xc7a200t
+| Speed File : -1
+| Package : sbg484
+| Package Version : FINAL 2012-06-12
+| Package Pin Delay Version : VERS. 2.0 2012-06-12
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 25 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA21 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B22 | BTNC | High Range | IO_L20N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| C2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| C22 | BTNL | High Range | IO_L20P_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D14 | BTNR | High Range | IO_L6P_T0_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D22 | BTND | High Range | IO_L22N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E22 | sw | High Range | IO_L22P_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
+| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F15 | BTNU | High Range | IO_0_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | rstn | High Range | IO_L12N_T1_MRCC_35 | INPUT | LVCMOS15 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| G22 | sw3 | High Range | IO_L24N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| H17 | sw4 | High Range | IO_L6P_T0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | sw5 | High Range | IO_0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | sw6 | High Range | IO_L19P_T3_A22_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M17 | sw7 | High Range | IO_25_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| P19 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | CLK100MHZ | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | ac_adc_sdata | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| T5 | ac_bclk | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T20 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U5 | ac_lrclk | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U6 | ac_mclk | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U16 | led3 | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U21 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V5 | sda | High Range | IO_L16N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V15 | led4 | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W5 | scl | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W6 | ac_dac_sdata | High Range | IO_L15P_T2_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W15 | led6 | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W16 | led5 | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y13 | led7 | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9c1940f692d079955d8d6f2a1f9012c01f049381
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c85dcd012a00889aeba3206b8bd3b3b042bc7aee
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
@@ -0,0 +1,90 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:14:06 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 11
++-----------+----------+-------------------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+----------+-------------------------------+------------+
+| TIMING-18 | Warning | Missing input or output delay | 11 |
++-----------+----------+-------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-18#1 Warning
+Missing input or output delay
+An input delay is missing on BTNC relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay
+An input delay is missing on ac_adc_sdata relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay
+An input delay is missing on rstn relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay
+An input delay is missing on sw3 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay
+An input delay is missing on sw4 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay
+An input delay is missing on sw5 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay
+An input delay is missing on sw6 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#8 Warning
+Missing input or output delay
+An input delay is missing on sw7 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#9 Warning
+Missing input or output delay
+An output delay is missing on ac_bclk relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#10 Warning
+Missing input or output delay
+An output delay is missing on ac_dac_sdata relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#11 Warning
+Missing input or output delay
+An output delay is missing on ac_lrclk relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..1e7aa79dd1f8a03403ae9fc8cc1d4bf520ce65f4
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..1c92b04dec42fd945da4325ccf3a3af8079f40e8
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..7875783ec854a0770114b022c6122506e73b48fc
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5446ed0dba62f7461653b911544d1777f14cdaff
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
@@ -0,0 +1,161 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:14:07 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 0.251 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 0.099 |
+| Device Static (W) | 0.151 |
+| Effective TJA (C/W) | 3.3 |
+| Max Ambient (C) | 84.2 |
+| Junction Temperature (C) | 25.8 |
+| Confidence Level | Low |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks | 0.003 | 7 | --- | --- |
+| Slice Logic | 0.002 | 1350 | --- | --- |
+| LUT as Logic | 0.002 | 585 | 133800 | 0.44 |
+| CARRY4 | <0.001 | 40 | 33450 | 0.12 |
+| Register | <0.001 | 589 | 267600 | 0.22 |
+| F7/F8 Muxes | <0.001 | 49 | 133800 | 0.04 |
+| Others | 0.000 | 19 | --- | --- |
+| Signals | 0.002 | 1012 | --- | --- |
+| MMCM | 0.085 | 1 | 10 | 10.00 |
+| I/O | 0.006 | 20 | 285 | 7.02 |
+| Static Power | 0.151 | | | |
+| Total | 0.251 | | | |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.039 | 0.009 | 0.031 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.078 | 0.047 | 0.031 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | High | User specified more than 95% of clocks | |
+| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Low | | |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 3.3 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++--------------------+-------------------------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++--------------------+-------------------------------+-----------------+
+| CLK100MHZ | CLK100MHZ | 10.0 |
+| clk_out1_clk_wiz_0 | clk_1/inst/clk_out1_clk_wiz_0 | 10.0 |
+| clk_out3_clk_wiz_0 | clk_1/inst/clk_out3_clk_wiz_0 | 83.3 |
+| clk_out4_clk_wiz_0 | clk_1/inst/clk_out4_clk_wiz_0 | 20.0 |
+| clkfbout_clk_wiz_0 | clk_1/inst/clkfbout_clk_wiz_0 | 10.0 |
++--------------------+-------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-----------------------+-----------+
+| Name | Power (W) |
++-----------------------+-----------+
+| audioProc | 0.099 |
+| clk_1 | 0.086 |
+| inst | 0.086 |
+| initialize_audio | 0.001 |
+| leftFir | 0.002 |
+| firUnit_1 | 0.002 |
+| operativeUnit_1 | 0.002 |
+| rightFir | 0.002 |
+| firUnit_1 | 0.002 |
+| operativeUnit_1 | 0.002 |
++-----------------------+-----------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..8dfed8421aa91541b4fc70a1d31d752851d95d6f
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a125d006012c7ba5bc5dcbbc0d068ecfaaa79f59
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..7fac92490525df949dfddcab0ff4d810b8d8696c
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..eac7e255a4f6d4a8076a25e8533a788e491f051e
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 1513 :
+ # of nets not needing routing.......... : 490 :
+ # of internally routed nets........ : 490 :
+ # of routable nets..................... : 1023 :
+ # of fully routed nets............. : 1023 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..8d4ee631f01e147de66b63192cf090a61c4e8d4c
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..6751886aa97361585ba73d65637d205e9526c760
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3eabd69bd6be208de5823189c130183163934522
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
@@ -0,0 +1,3126 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:14:06 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+ Inter-SLR Compensation : Conservative
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule Severity Description Violations
+--------- -------- ----------------------------- ----------
+TIMING-18 Warning Missing input or output delay 11
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (0)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (0)
+5. checking no_input_delay (10)
+6. checking no_output_delay (5)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (0)
+------------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (0)
+------------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (10)
+-------------------------------
+ There are 10 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (5)
+-------------------------------
+ There are 5 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 0.286 0.000 0 1194 0.138 0.000 0 1194 3.000 0.000 0 599
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+CLK100MHZ {0.000 5.000} 10.000 100.000
+ clk_out1_clk_wiz_0 {0.000 5.000} 10.000 100.000
+ clk_out3_clk_wiz_0 {0.000 41.667} 83.333 12.000
+ clk_out4_clk_wiz_0 {0.000 10.000} 20.000 50.000
+ clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+CLK100MHZ 3.000 0.000 0 1
+ clk_out1_clk_wiz_0 0.286 0.000 0 969 0.138 0.000 0 969 4.500 0.000 0 471
+ clk_out3_clk_wiz_0 81.178 0.000 0 2
+ clk_out4_clk_wiz_0 14.812 0.000 0 225 0.153 0.000 0 225 9.500 0.000 0 122
+ clkfbout_clk_wiz_0 7.845 0.000 0 3
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: CLK100MHZ
+ To Clock: CLK100MHZ
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: CLK100MHZ
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { CLK100MHZ }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0
+ To Clock: clk_out1_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 0.286ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.138ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.286ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.629ns (logic 4.854ns (50.408%) route 4.775ns (49.592%))
+ Logic Levels: 13 (CARRY4=6 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.030ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.592ns = ( 8.408 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y124 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/Q
+ net (fo=2, routed) 1.292 0.739 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_2[2]
+ SLICE_X157Y124 LUT6 (Prop_lut6_I1_O) 0.124 0.863 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0/O
+ net (fo=1, routed) 0.000 0.863 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0_n_0
+ SLICE_X157Y124 MUXF7 (Prop_muxf7_I0_O) 0.238 1.101 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0/O
+ net (fo=1, routed) 0.000 1.101 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0_n_0
+ SLICE_X157Y124 MUXF8 (Prop_muxf8_I0_O) 0.104 1.205 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15__0/O
+ net (fo=7, routed) 0.760 1.965 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X158Y125 LUT5 (Prop_lut5_I0_O) 0.342 2.307 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0/O
+ net (fo=4, routed) 0.490 2.797 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0_n_0
+ SLICE_X160Y124 LUT3 (Prop_lut3_I1_O) 0.355 3.152 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.570 3.722 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X161Y126 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.526 4.248 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.248 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X161Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.582 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.732 5.314 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X160Y127 LUT4 (Prop_lut4_I3_O) 0.303 5.617 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0/O
+ net (fo=1, routed) 0.000 5.617 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0_n_0
+ SLICE_X160Y127 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 6.015 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.015 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X160Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.349 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.641 6.990 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X159Y128 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.705 7.695 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.695 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X159Y129 CARRY4 (Prop_carry4_CI_O[3])
+ 0.329 8.024 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[3]
+ net (fo=2, routed) 0.291 8.315 rightFir/firUnit_1/operativeUnit_1/SC_addResult[19]
+ SLICE_X157Y129 LUT2 (Prop_lut2_I0_O) 0.306 8.621 r rightFir/firUnit_1/operativeUnit_1/SR_sum[19]_i_1__0/O
+ net (fo=1, routed) 0.000 8.621 rightFir/firUnit_1/operativeUnit_1/p_1_in[19]
+ SLICE_X157Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.700 8.408 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X157Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]/C
+ clock pessimism 0.554 8.961
+ clock uncertainty -0.084 8.878
+ SLICE_X157Y129 FDCE (Setup_fdce_C_D) 0.029 8.907 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]
+ -------------------------------------------------------------------
+ required time 8.907
+ arrival time -8.621
+ -------------------------------------------------------------------
+ slack 0.286
+
+Slack (MET) : 0.288ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.630ns (logic 4.856ns (50.427%) route 4.774ns (49.573%))
+ Logic Levels: 13 (CARRY4=6 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.030ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.592ns = ( 8.408 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y124 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/Q
+ net (fo=2, routed) 1.292 0.739 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_2[2]
+ SLICE_X157Y124 LUT6 (Prop_lut6_I1_O) 0.124 0.863 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0/O
+ net (fo=1, routed) 0.000 0.863 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0_n_0
+ SLICE_X157Y124 MUXF7 (Prop_muxf7_I0_O) 0.238 1.101 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0/O
+ net (fo=1, routed) 0.000 1.101 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0_n_0
+ SLICE_X157Y124 MUXF8 (Prop_muxf8_I0_O) 0.104 1.205 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15__0/O
+ net (fo=7, routed) 0.760 1.965 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X158Y125 LUT5 (Prop_lut5_I0_O) 0.342 2.307 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0/O
+ net (fo=4, routed) 0.490 2.797 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0_n_0
+ SLICE_X160Y124 LUT3 (Prop_lut3_I1_O) 0.355 3.152 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.570 3.722 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X161Y126 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.526 4.248 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.248 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X161Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.582 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.732 5.314 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X160Y127 LUT4 (Prop_lut4_I3_O) 0.303 5.617 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0/O
+ net (fo=1, routed) 0.000 5.617 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0_n_0
+ SLICE_X160Y127 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 6.015 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.015 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X160Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.349 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.641 6.990 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X159Y128 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.705 7.695 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.695 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X159Y129 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 8.029 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[1]
+ net (fo=1, routed) 0.289 8.318 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[17]
+ SLICE_X157Y129 LUT2 (Prop_lut2_I0_O) 0.303 8.621 r rightFir/firUnit_1/operativeUnit_1/SR_sum[17]_i_1__0/O
+ net (fo=1, routed) 0.000 8.621 rightFir/firUnit_1/operativeUnit_1/p_1_in[17]
+ SLICE_X157Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.700 8.408 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X157Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]/C
+ clock pessimism 0.554 8.961
+ clock uncertainty -0.084 8.878
+ SLICE_X157Y129 FDCE (Setup_fdce_C_D) 0.031 8.909 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]
+ -------------------------------------------------------------------
+ required time 8.909
+ arrival time -8.621
+ -------------------------------------------------------------------
+ slack 0.288
+
+Slack (MET) : 0.296ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.613ns (logic 4.671ns (48.590%) route 4.942ns (51.410%))
+ Logic Levels: 13 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.038ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.666ns = ( 8.334 - 10.000 )
+ Source Clock Delay (SCD): -1.075ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.744 -1.075 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y131 FDCE (Prop_fdce_C_Q) 0.456 -0.619 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.494 0.875 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+ SLICE_X150Y124 LUT6 (Prop_lut6_I2_O) 0.124 0.999 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33/O
+ net (fo=1, routed) 0.000 0.999 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33_n_0
+ SLICE_X150Y124 MUXF7 (Prop_muxf7_I1_O) 0.214 1.213 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21/O
+ net (fo=1, routed) 0.000 1.213 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21_n_0
+ SLICE_X150Y124 MUXF8 (Prop_muxf8_I1_O) 0.088 1.301 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15/O
+ net (fo=7, routed) 0.786 2.087 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X153Y124 LUT5 (Prop_lut5_I0_O) 0.345 2.432 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15/O
+ net (fo=3, routed) 0.877 3.310 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15_n_0
+ SLICE_X154Y124 LUT6 (Prop_lut6_I2_O) 0.326 3.636 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7/O
+ net (fo=1, routed) 0.000 3.636 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7_n_0
+ SLICE_X154Y124 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 4.279 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[3]
+ net (fo=4, routed) 0.871 5.149 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_4
+ SLICE_X154Y127 LUT4 (Prop_lut4_I1_O) 0.307 5.456 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8/O
+ net (fo=1, routed) 0.000 5.456 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8_n_0
+ SLICE_X154Y127 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 5.969 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.969 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X154Y128 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 6.284 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[3]
+ net (fo=1, routed) 0.619 6.904 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[14]
+ SLICE_X153Y129 LUT2 (Prop_lut2_I1_O) 0.307 7.211 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3/O
+ net (fo=1, routed) 0.000 7.211 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3_n_0
+ SLICE_X153Y129 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 7.609 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.609 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X153Y130 CARRY4 (Prop_carry4_CI_O[3])
+ 0.329 7.938 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[3]
+ net (fo=2, routed) 0.295 8.232 leftFir/firUnit_1/operativeUnit_1/SC_addResult[19]
+ SLICE_X153Y131 LUT2 (Prop_lut2_I0_O) 0.306 8.538 r leftFir/firUnit_1/operativeUnit_1/SR_sum[19]_i_1/O
+ net (fo=1, routed) 0.000 8.538 leftFir/firUnit_1/operativeUnit_1/p_1_in[19]
+ SLICE_X153Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.626 8.334 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]/C
+ clock pessimism 0.554 8.887
+ clock uncertainty -0.084 8.804
+ SLICE_X153Y131 FDCE (Setup_fdce_C_D) 0.031 8.835 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[19]
+ -------------------------------------------------------------------
+ required time 8.835
+ arrival time -8.538
+ -------------------------------------------------------------------
+ slack 0.296
+
+Slack (MET) : 0.332ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.627ns (logic 4.673ns (48.538%) route 4.954ns (51.462%))
+ Logic Levels: 13 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.038ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.666ns = ( 8.334 - 10.000 )
+ Source Clock Delay (SCD): -1.075ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.744 -1.075 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y131 FDCE (Prop_fdce_C_Q) 0.456 -0.619 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.494 0.875 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+ SLICE_X150Y124 LUT6 (Prop_lut6_I2_O) 0.124 0.999 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33/O
+ net (fo=1, routed) 0.000 0.999 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33_n_0
+ SLICE_X150Y124 MUXF7 (Prop_muxf7_I1_O) 0.214 1.213 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21/O
+ net (fo=1, routed) 0.000 1.213 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21_n_0
+ SLICE_X150Y124 MUXF8 (Prop_muxf8_I1_O) 0.088 1.301 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15/O
+ net (fo=7, routed) 0.786 2.087 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X153Y124 LUT5 (Prop_lut5_I0_O) 0.345 2.432 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15/O
+ net (fo=3, routed) 0.877 3.310 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15_n_0
+ SLICE_X154Y124 LUT6 (Prop_lut6_I2_O) 0.326 3.636 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7/O
+ net (fo=1, routed) 0.000 3.636 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7_n_0
+ SLICE_X154Y124 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 4.279 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[3]
+ net (fo=4, routed) 0.871 5.149 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_4
+ SLICE_X154Y127 LUT4 (Prop_lut4_I1_O) 0.307 5.456 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8/O
+ net (fo=1, routed) 0.000 5.456 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8_n_0
+ SLICE_X154Y127 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 5.969 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.969 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X154Y128 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 6.284 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[3]
+ net (fo=1, routed) 0.619 6.904 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[14]
+ SLICE_X153Y129 LUT2 (Prop_lut2_I1_O) 0.307 7.211 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3/O
+ net (fo=1, routed) 0.000 7.211 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3_n_0
+ SLICE_X153Y129 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 7.609 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.609 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X153Y130 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 7.943 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[1]
+ net (fo=1, routed) 0.307 8.250 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[17]
+ SLICE_X152Y131 LUT2 (Prop_lut2_I0_O) 0.303 8.553 r leftFir/firUnit_1/operativeUnit_1/SR_sum[17]_i_1/O
+ net (fo=1, routed) 0.000 8.553 leftFir/firUnit_1/operativeUnit_1/p_1_in[17]
+ SLICE_X152Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.626 8.334 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]/C
+ clock pessimism 0.554 8.887
+ clock uncertainty -0.084 8.804
+ SLICE_X152Y131 FDCE (Setup_fdce_C_D) 0.081 8.885 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[17]
+ -------------------------------------------------------------------
+ required time 8.885
+ arrival time -8.553
+ -------------------------------------------------------------------
+ slack 0.332
+
+Slack (MET) : 0.357ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.608ns (logic 4.760ns (49.541%) route 4.848ns (50.459%))
+ Logic Levels: 13 (CARRY4=6 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.030ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.592ns = ( 8.408 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y124 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/Q
+ net (fo=2, routed) 1.292 0.739 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_2[2]
+ SLICE_X157Y124 LUT6 (Prop_lut6_I1_O) 0.124 0.863 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0/O
+ net (fo=1, routed) 0.000 0.863 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0_n_0
+ SLICE_X157Y124 MUXF7 (Prop_muxf7_I0_O) 0.238 1.101 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0/O
+ net (fo=1, routed) 0.000 1.101 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0_n_0
+ SLICE_X157Y124 MUXF8 (Prop_muxf8_I0_O) 0.104 1.205 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15__0/O
+ net (fo=7, routed) 0.760 1.965 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X158Y125 LUT5 (Prop_lut5_I0_O) 0.342 2.307 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0/O
+ net (fo=4, routed) 0.490 2.797 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0_n_0
+ SLICE_X160Y124 LUT3 (Prop_lut3_I1_O) 0.355 3.152 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.570 3.722 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X161Y126 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.526 4.248 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.248 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X161Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.582 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.732 5.314 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X160Y127 LUT4 (Prop_lut4_I3_O) 0.303 5.617 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0/O
+ net (fo=1, routed) 0.000 5.617 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0_n_0
+ SLICE_X160Y127 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 6.015 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.015 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X160Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.349 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.641 6.990 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X159Y128 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.705 7.695 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.695 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X159Y129 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 7.934 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[2]
+ net (fo=1, routed) 0.363 8.297 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[18]
+ SLICE_X158Y129 LUT2 (Prop_lut2_I0_O) 0.302 8.599 r rightFir/firUnit_1/operativeUnit_1/SR_sum[18]_i_1__0/O
+ net (fo=1, routed) 0.000 8.599 rightFir/firUnit_1/operativeUnit_1/p_1_in[18]
+ SLICE_X158Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.700 8.408 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]/C
+ clock pessimism 0.554 8.961
+ clock uncertainty -0.084 8.878
+ SLICE_X158Y129 FDCE (Setup_fdce_C_D) 0.079 8.957 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]
+ -------------------------------------------------------------------
+ required time 8.957
+ arrival time -8.599
+ -------------------------------------------------------------------
+ slack 0.357
+
+Slack (MET) : 0.387ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.578ns (logic 4.740ns (49.486%) route 4.838ns (50.514%))
+ Logic Levels: 13 (CARRY4=6 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.030ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.592ns = ( 8.408 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y124 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/Q
+ net (fo=2, routed) 1.292 0.739 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_2[2]
+ SLICE_X157Y124 LUT6 (Prop_lut6_I1_O) 0.124 0.863 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0/O
+ net (fo=1, routed) 0.000 0.863 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0_n_0
+ SLICE_X157Y124 MUXF7 (Prop_muxf7_I0_O) 0.238 1.101 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0/O
+ net (fo=1, routed) 0.000 1.101 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0_n_0
+ SLICE_X157Y124 MUXF8 (Prop_muxf8_I0_O) 0.104 1.205 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15__0/O
+ net (fo=7, routed) 0.760 1.965 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X158Y125 LUT5 (Prop_lut5_I0_O) 0.342 2.307 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0/O
+ net (fo=4, routed) 0.490 2.797 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0_n_0
+ SLICE_X160Y124 LUT3 (Prop_lut3_I1_O) 0.355 3.152 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.570 3.722 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X161Y126 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.526 4.248 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.248 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X161Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.582 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.732 5.314 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X160Y127 LUT4 (Prop_lut4_I3_O) 0.303 5.617 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0/O
+ net (fo=1, routed) 0.000 5.617 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0_n_0
+ SLICE_X160Y127 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 6.015 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.015 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X160Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.349 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.641 6.990 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X159Y128 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.705 7.695 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.695 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X159Y129 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 7.917 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[0]
+ net (fo=1, routed) 0.354 8.271 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[16]
+ SLICE_X158Y129 LUT2 (Prop_lut2_I0_O) 0.299 8.570 r rightFir/firUnit_1/operativeUnit_1/SR_sum[16]_i_1__0/O
+ net (fo=1, routed) 0.000 8.570 rightFir/firUnit_1/operativeUnit_1/p_1_in[16]
+ SLICE_X158Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.700 8.408 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y129 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]/C
+ clock pessimism 0.554 8.961
+ clock uncertainty -0.084 8.878
+ SLICE_X158Y129 FDCE (Setup_fdce_C_D) 0.079 8.957 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]
+ -------------------------------------------------------------------
+ required time 8.957
+ arrival time -8.570
+ -------------------------------------------------------------------
+ slack 0.387
+
+Slack (MET) : 0.397ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.567ns (logic 4.599ns (48.070%) route 4.968ns (51.930%))
+ Logic Levels: 13 (CARRY4=6 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.031ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.593ns = ( 8.407 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y124 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/Q
+ net (fo=2, routed) 1.292 0.739 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_2[2]
+ SLICE_X157Y124 LUT6 (Prop_lut6_I1_O) 0.124 0.863 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0/O
+ net (fo=1, routed) 0.000 0.863 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0_n_0
+ SLICE_X157Y124 MUXF7 (Prop_muxf7_I0_O) 0.238 1.101 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0/O
+ net (fo=1, routed) 0.000 1.101 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0_n_0
+ SLICE_X157Y124 MUXF8 (Prop_muxf8_I0_O) 0.104 1.205 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15__0/O
+ net (fo=7, routed) 0.760 1.965 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X158Y125 LUT5 (Prop_lut5_I0_O) 0.342 2.307 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0/O
+ net (fo=4, routed) 0.490 2.797 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0_n_0
+ SLICE_X160Y124 LUT3 (Prop_lut3_I1_O) 0.355 3.152 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.570 3.722 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X161Y126 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.526 4.248 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.248 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X161Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.582 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.732 5.314 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X160Y127 LUT4 (Prop_lut4_I3_O) 0.303 5.617 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0/O
+ net (fo=1, routed) 0.000 5.617 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0_n_0
+ SLICE_X160Y127 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 6.015 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.015 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X160Y128 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 6.237 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[0]
+ net (fo=2, routed) 0.628 6.865 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[11]
+ SLICE_X159Y127 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.560 7.425 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1/CO[3]
+ net (fo=1, routed) 0.000 7.425 rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__1_n_0
+ SLICE_X159Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 7.759 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[1]
+ net (fo=1, routed) 0.496 8.256 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[13]
+ SLICE_X158Y128 LUT2 (Prop_lut2_I0_O) 0.303 8.559 r rightFir/firUnit_1/operativeUnit_1/SR_sum[13]_i_1__0/O
+ net (fo=1, routed) 0.000 8.559 rightFir/firUnit_1/operativeUnit_1/p_1_in[13]
+ SLICE_X158Y128 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.699 8.407 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y128 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]/C
+ clock pessimism 0.554 8.960
+ clock uncertainty -0.084 8.877
+ SLICE_X158Y128 FDCE (Setup_fdce_C_D) 0.079 8.956 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[13]
+ -------------------------------------------------------------------
+ required time 8.956
+ arrival time -8.559
+ -------------------------------------------------------------------
+ slack 0.397
+
+Slack (MET) : 0.421ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.539ns (logic 4.577ns (47.982%) route 4.962ns (52.018%))
+ Logic Levels: 13 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.038ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.666ns = ( 8.334 - 10.000 )
+ Source Clock Delay (SCD): -1.075ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.744 -1.075 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y131 FDCE (Prop_fdce_C_Q) 0.456 -0.619 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.494 0.875 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+ SLICE_X150Y124 LUT6 (Prop_lut6_I2_O) 0.124 0.999 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33/O
+ net (fo=1, routed) 0.000 0.999 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33_n_0
+ SLICE_X150Y124 MUXF7 (Prop_muxf7_I1_O) 0.214 1.213 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21/O
+ net (fo=1, routed) 0.000 1.213 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21_n_0
+ SLICE_X150Y124 MUXF8 (Prop_muxf8_I1_O) 0.088 1.301 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15/O
+ net (fo=7, routed) 0.786 2.087 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X153Y124 LUT5 (Prop_lut5_I0_O) 0.345 2.432 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15/O
+ net (fo=3, routed) 0.877 3.310 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15_n_0
+ SLICE_X154Y124 LUT6 (Prop_lut6_I2_O) 0.326 3.636 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7/O
+ net (fo=1, routed) 0.000 3.636 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7_n_0
+ SLICE_X154Y124 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 4.279 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[3]
+ net (fo=4, routed) 0.871 5.149 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_4
+ SLICE_X154Y127 LUT4 (Prop_lut4_I1_O) 0.307 5.456 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8/O
+ net (fo=1, routed) 0.000 5.456 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8_n_0
+ SLICE_X154Y127 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 5.969 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.969 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X154Y128 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 6.284 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[3]
+ net (fo=1, routed) 0.619 6.904 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[14]
+ SLICE_X153Y129 LUT2 (Prop_lut2_I1_O) 0.307 7.211 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3/O
+ net (fo=1, routed) 0.000 7.211 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3_n_0
+ SLICE_X153Y129 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 7.609 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.609 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X153Y130 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 7.848 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[2]
+ net (fo=1, routed) 0.314 8.162 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[18]
+ SLICE_X154Y130 LUT2 (Prop_lut2_I0_O) 0.302 8.464 r leftFir/firUnit_1/operativeUnit_1/SR_sum[18]_i_1/O
+ net (fo=1, routed) 0.000 8.464 leftFir/firUnit_1/operativeUnit_1/p_1_in[18]
+ SLICE_X154Y130 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.626 8.334 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X154Y130 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]/C
+ clock pessimism 0.554 8.887
+ clock uncertainty -0.084 8.804
+ SLICE_X154Y130 FDCE (Setup_fdce_C_D) 0.081 8.885 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[18]
+ -------------------------------------------------------------------
+ required time 8.885
+ arrival time -8.464
+ -------------------------------------------------------------------
+ slack 0.421
+
+Slack (MET) : 0.426ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.535ns (logic 4.557ns (47.794%) route 4.978ns (52.206%))
+ Logic Levels: 13 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.037ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.665ns = ( 8.335 - 10.000 )
+ Source Clock Delay (SCD): -1.075ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.744 -1.075 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X147Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X147Y131 FDCE (Prop_fdce_C_Q) 0.456 -0.619 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=78, routed) 1.494 0.875 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg_n_0_[1]
+ SLICE_X150Y124 LUT6 (Prop_lut6_I2_O) 0.124 0.999 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33/O
+ net (fo=1, routed) 0.000 0.999 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_33_n_0
+ SLICE_X150Y124 MUXF7 (Prop_muxf7_I1_O) 0.214 1.213 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21/O
+ net (fo=1, routed) 0.000 1.213 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_21_n_0
+ SLICE_X150Y124 MUXF8 (Prop_muxf8_I1_O) 0.088 1.301 f leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15/O
+ net (fo=7, routed) 0.786 2.087 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X153Y124 LUT5 (Prop_lut5_I0_O) 0.345 2.432 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15/O
+ net (fo=3, routed) 0.877 3.310 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_15_n_0
+ SLICE_X154Y124 LUT6 (Prop_lut6_I2_O) 0.326 3.636 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7/O
+ net (fo=1, routed) 0.000 3.636 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_7_n_0
+ SLICE_X154Y124 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 4.279 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/O[3]
+ net (fo=4, routed) 0.871 5.149 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_4
+ SLICE_X154Y127 LUT4 (Prop_lut4_I1_O) 0.307 5.456 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8/O
+ net (fo=1, routed) 0.000 5.456 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_8_n_0
+ SLICE_X154Y127 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.513 5.969 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 5.969 leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X154Y128 CARRY4 (Prop_carry4_CI_O[3])
+ 0.315 6.284 r leftFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[3]
+ net (fo=1, routed) 0.619 6.904 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[14]
+ SLICE_X153Y129 LUT2 (Prop_lut2_I1_O) 0.307 7.211 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3/O
+ net (fo=1, routed) 0.000 7.211 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_i_3_n_0
+ SLICE_X153Y129 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 7.609 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/CO[3]
+ net (fo=1, routed) 0.000 7.609 leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2_n_0
+ SLICE_X153Y130 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 7.831 r leftFir/firUnit_1/operativeUnit_1/SC_addResult_carry__3/O[0]
+ net (fo=1, routed) 0.330 8.161 leftFir/firUnit_1/operativeUnit_1/SC_addResult__0[16]
+ SLICE_X154Y131 LUT2 (Prop_lut2_I0_O) 0.299 8.460 r leftFir/firUnit_1/operativeUnit_1/SR_sum[16]_i_1/O
+ net (fo=1, routed) 0.000 8.460 leftFir/firUnit_1/operativeUnit_1/p_1_in[16]
+ SLICE_X154Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.627 8.335 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X154Y131 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]/C
+ clock pessimism 0.554 8.888
+ clock uncertainty -0.084 8.805
+ SLICE_X154Y131 FDCE (Setup_fdce_C_D) 0.081 8.886 leftFir/firUnit_1/operativeUnit_1/SR_sum_reg[16]
+ -------------------------------------------------------------------
+ required time 8.886
+ arrival time -8.460
+ -------------------------------------------------------------------
+ slack 0.426
+
+Slack (MET) : 0.436ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.528ns (logic 4.614ns (48.424%) route 4.914ns (51.576%))
+ Logic Levels: 12 (CARRY4=5 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.031ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.593ns = ( 8.407 - 10.000 )
+ Source Clock Delay (SCD): -1.009ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.810 -1.009 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y124 FDCE (Prop_fdce_C_Q) 0.456 -0.553 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][2]/Q
+ net (fo=2, routed) 1.292 0.739 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]_2[2]
+ SLICE_X157Y124 LUT6 (Prop_lut6_I1_O) 0.124 0.863 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0/O
+ net (fo=1, routed) 0.000 0.863 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_30__0_n_0
+ SLICE_X157Y124 MUXF7 (Prop_muxf7_I0_O) 0.238 1.101 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0/O
+ net (fo=1, routed) 0.000 1.101 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_20__0_n_0
+ SLICE_X157Y124 MUXF8 (Prop_muxf8_I0_O) 0.104 1.205 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_15__0/O
+ net (fo=7, routed) 0.760 1.965 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]__119[2]
+ SLICE_X158Y125 LUT5 (Prop_lut5_I0_O) 0.342 2.307 f rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0/O
+ net (fo=4, routed) 0.490 2.797 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry_i_8__0_n_0
+ SLICE_X160Y124 LUT3 (Prop_lut3_I1_O) 0.355 3.152 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0/O
+ net (fo=1, routed) 0.570 3.722 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_i_4__0_n_0
+ SLICE_X161Y126 CARRY4 (Prop_carry4_DI[0]_CO[3])
+ 0.526 4.248 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0/CO[3]
+ net (fo=1, routed) 0.000 4.248 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__0_n_0
+ SLICE_X161Y127 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 4.582 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1/O[1]
+ net (fo=3, routed) 0.732 5.314 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__0_carry__1_n_6
+ SLICE_X160Y127 LUT4 (Prop_lut4_I3_O) 0.303 5.617 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0/O
+ net (fo=1, routed) 0.000 5.617 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_i_6__0_n_0
+ SLICE_X160Y127 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.398 6.015 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0/CO[3]
+ net (fo=1, routed) 0.000 6.015 rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__0_n_0
+ SLICE_X160Y128 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.349 r rightFir/firUnit_1/operativeUnit_1/SC_MultResult__57_carry__1/O[1]
+ net (fo=2, routed) 0.641 6.990 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[12]
+ SLICE_X159Y128 CARRY4 (Prop_carry4_DI[0]_O[3])
+ 0.794 7.784 r rightFir/firUnit_1/operativeUnit_1/SC_addResult_carry__2/O[3]
+ net (fo=1, routed) 0.430 8.214 rightFir/firUnit_1/operativeUnit_1/SC_addResult__0[15]
+ SLICE_X158Y128 LUT2 (Prop_lut2_I0_O) 0.306 8.520 r rightFir/firUnit_1/operativeUnit_1/SR_sum[15]_i_1__0/O
+ net (fo=1, routed) 0.000 8.520 rightFir/firUnit_1/operativeUnit_1/p_1_in[15]
+ SLICE_X158Y128 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 1.699 8.407 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y128 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]/C
+ clock pessimism 0.554 8.960
+ clock uncertainty -0.084 8.877
+ SLICE_X158Y128 FDCE (Setup_fdce_C_D) 0.079 8.956 rightFir/firUnit_1/operativeUnit_1/SR_sum_reg[15]
+ -------------------------------------------------------------------
+ required time 8.956
+ arrival time -8.520
+ -------------------------------------------------------------------
+ slack 0.436
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.138ns (arrival time - required time)
+ Source: audio_inout/Data_Out_int_reg[18]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[19]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.243ns (logic 0.186ns (76.391%) route 0.057ns (23.609%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.255ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.643 -0.657 audio_inout/clk_out1
+ SLICE_X157Y135 FDRE r audio_inout/Data_Out_int_reg[18]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y135 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r audio_inout/Data_Out_int_reg[18]/Q
+ net (fo=1, routed) 0.057 -0.458 audio_inout/Data_Out_int_reg_n_0_[18]
+ SLICE_X156Y135 LUT6 (Prop_lut6_I4_O) 0.045 -0.413 r audio_inout/Data_Out_int[19]_i_1/O
+ net (fo=1, routed) 0.000 -0.413 audio_inout/Data_Out_int[19]_i_1_n_0
+ SLICE_X156Y135 FDRE r audio_inout/Data_Out_int_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.915 -0.899 audio_inout/clk_out1
+ SLICE_X156Y135 FDRE r audio_inout/Data_Out_int_reg[19]/C
+ clock pessimism 0.255 -0.644
+ SLICE_X156Y135 FDRE (Hold_fdre_C_D) 0.092 -0.552 audio_inout/Data_Out_int_reg[19]
+ -------------------------------------------------------------------
+ required time 0.552
+ arrival time -0.413
+ -------------------------------------------------------------------
+ slack 0.138
+
+Slack (MET) : 0.148ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.207ns (logic 0.141ns (68.087%) route 0.066ns (31.913%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.906ns
+ Source Clock Delay (SCD): -0.662ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.638 -0.662 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X160Y122 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y122 FDCE (Prop_fdce_C_Q) 0.141 -0.521 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12][3]/Q
+ net (fo=2, routed) 0.066 -0.455 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[12]_12[3]
+ SLICE_X161Y122 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.908 -0.906 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y122 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]/C
+ clock pessimism 0.257 -0.649
+ SLICE_X161Y122 FDCE (Hold_fdce_C_D) 0.046 -0.603 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]
+ -------------------------------------------------------------------
+ required time 0.603
+ arrival time -0.455
+ -------------------------------------------------------------------
+ slack 0.148
+
+Slack (MET) : 0.164ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.254ns (logic 0.141ns (55.468%) route 0.113ns (44.532%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.903ns
+ Source Clock Delay (SCD): -0.660ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.640 -0.660 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X163Y130 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X163Y130 FDCE (Prop_fdce_C_Q) 0.141 -0.519 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][4]/Q
+ net (fo=2, routed) 0.113 -0.406 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7]_7[4]
+ SLICE_X161Y130 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.911 -0.903 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y130 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]/C
+ clock pessimism 0.257 -0.646
+ SLICE_X161Y130 FDCE (Hold_fdce_C_D) 0.076 -0.570 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]
+ -------------------------------------------------------------------
+ required time 0.570
+ arrival time -0.406
+ -------------------------------------------------------------------
+ slack 0.164
+
+Slack (MET) : 0.170ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[4][1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.271ns (logic 0.141ns (51.948%) route 0.130ns (48.052%))
+ Logic Levels: 0
+ Clock Path Skew: 0.035ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.910ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.635 -0.665 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X160Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y124 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][1]/Q
+ net (fo=2, routed) 0.130 -0.393 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3]_3[1]
+ SLICE_X159Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[4][1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.904 -0.910 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[4][1]/C
+ clock pessimism 0.280 -0.630
+ SLICE_X159Y124 FDCE (Hold_fdce_C_D) 0.066 -0.564 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[4][1]
+ -------------------------------------------------------------------
+ required time 0.564
+ arrival time -0.393
+ -------------------------------------------------------------------
+ slack 0.170
+
+Slack (MET) : 0.172ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.232ns (logic 0.164ns (70.680%) route 0.068ns (29.320%))
+ Logic Levels: 0
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.934ns
+ Source Clock Delay (SCD): -0.689ns
+ Clock Pessimism Removal (CPR): -0.245ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.611 -0.689 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y122 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X152Y122 FDCE (Prop_fdce_C_Q) 0.164 -0.525 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0][1]/Q
+ net (fo=2, routed) 0.068 -0.457 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[0]_0[1]
+ SLICE_X152Y122 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.880 -0.934 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y122 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]/C
+ clock pessimism 0.245 -0.689
+ SLICE_X152Y122 FDCE (Hold_fdce_C_D) 0.060 -0.629 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[1][1]
+ -------------------------------------------------------------------
+ required time 0.629
+ arrival time -0.457
+ -------------------------------------------------------------------
+ slack 0.172
+
+Slack (MET) : 0.174ns (arrival time - required time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][6]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][6]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.265ns (logic 0.141ns (53.133%) route 0.124ns (46.867%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.929ns
+ Source Clock Delay (SCD): -0.684ns
+ Clock Pessimism Removal (CPR): -0.258ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.616 -0.684 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y133 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y133 FDCE (Prop_fdce_C_Q) 0.141 -0.543 r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][6]/Q
+ net (fo=2, routed) 0.124 -0.418 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13]_13[6]
+ SLICE_X153Y132 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.885 -0.929 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y132 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][6]/C
+ clock pessimism 0.258 -0.671
+ SLICE_X153Y132 FDCE (Hold_fdce_C_D) 0.078 -0.593 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][6]
+ -------------------------------------------------------------------
+ required time 0.593
+ arrival time -0.418
+ -------------------------------------------------------------------
+ slack 0.174
+
+Slack (MET) : 0.179ns (arrival time - required time)
+ Source: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/D
+ (rising edge-triggered cell FDPE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.283ns (logic 0.186ns (65.775%) route 0.097ns (34.225%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.909ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.635 -0.665 leftFir/firUnit_1/controlUnit_1/clk_out1
+ SLICE_X156Y126 FDCE r leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y126 FDCE (Prop_fdce_C_Q) 0.141 -0.524 r leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/Q
+ net (fo=2, routed) 0.097 -0.427 leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg_n_0_[4]
+ SLICE_X157Y126 LUT3 (Prop_lut3_I2_O) 0.045 -0.382 r leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState[0]_i_1/O
+ net (fo=1, routed) 0.000 -0.382 leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState[0]_i_1_n_0
+ SLICE_X157Y126 FDPE r leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.905 -0.909 leftFir/firUnit_1/controlUnit_1/clk_out1
+ SLICE_X157Y126 FDPE r leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/C
+ clock pessimism 0.257 -0.652
+ SLICE_X157Y126 FDPE (Hold_fdpe_C_D) 0.091 -0.561 leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]
+ -------------------------------------------------------------------
+ required time 0.561
+ arrival time -0.382
+ -------------------------------------------------------------------
+ slack 0.179
+
+Slack (MET) : 0.179ns (arrival time - required time)
+ Source: audio_inout/D_R_O_int_reg[13]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[20]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.308ns (logic 0.186ns (60.298%) route 0.122ns (39.702%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.037ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.644 -0.656 audio_inout/clk_out1
+ SLICE_X160Y135 FDRE r audio_inout/D_R_O_int_reg[13]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y135 FDRE (Prop_fdre_C_Q) 0.141 -0.515 r audio_inout/D_R_O_int_reg[13]/Q
+ net (fo=1, routed) 0.122 -0.392 audio_inout/in_audioR[13]
+ SLICE_X156Y135 LUT6 (Prop_lut6_I2_O) 0.045 -0.347 r audio_inout/Data_Out_int[20]_i_1/O
+ net (fo=1, routed) 0.000 -0.347 audio_inout/Data_Out_int[20]_i_1_n_0
+ SLICE_X156Y135 FDRE r audio_inout/Data_Out_int_reg[20]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.915 -0.899 audio_inout/clk_out1
+ SLICE_X156Y135 FDRE r audio_inout/Data_Out_int_reg[20]/C
+ clock pessimism 0.280 -0.619
+ SLICE_X156Y135 FDRE (Hold_fdre_C_D) 0.092 -0.527 audio_inout/Data_Out_int_reg[20]
+ -------------------------------------------------------------------
+ required time 0.527
+ arrival time -0.347
+ -------------------------------------------------------------------
+ slack 0.179
+
+Slack (MET) : 0.181ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.266ns (logic 0.141ns (52.950%) route 0.125ns (47.050%))
+ Logic Levels: 0
+ Clock Path Skew: 0.010ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.909ns
+ Source Clock Delay (SCD): -0.662ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.638 -0.662 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y122 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y122 FDCE (Prop_fdce_C_Q) 0.141 -0.521 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13][3]/Q
+ net (fo=2, routed) 0.125 -0.396 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[13]_13[3]
+ SLICE_X161Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.905 -0.909 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y124 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]/C
+ clock pessimism 0.257 -0.652
+ SLICE_X161Y124 FDCE (Hold_fdce_C_D) 0.075 -0.577 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][3]
+ -------------------------------------------------------------------
+ required time 0.577
+ arrival time -0.396
+ -------------------------------------------------------------------
+ slack 0.181
+
+Slack (MET) : 0.182ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.293ns (logic 0.164ns (55.964%) route 0.129ns (44.036%))
+ Logic Levels: 0
+ Clock Path Skew: 0.039ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.906ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.635 -0.665 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y123 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X158Y123 FDCE (Prop_fdce_C_Q) 0.164 -0.501 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14][1]/Q
+ net (fo=2, routed) 0.129 -0.372 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[14]_14[1]
+ SLICE_X160Y122 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=469, routed) 0.908 -0.906 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X160Y122 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][1]/C
+ clock pessimism 0.280 -0.626
+ SLICE_X160Y122 FDCE (Hold_fdce_C_D) 0.072 -0.554 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[15][1]
+ -------------------------------------------------------------------
+ required time 0.554
+ arrival time -0.372
+ -------------------------------------------------------------------
+ slack 0.182
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out1_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT0 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_1/inst/clkout1_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X156Y121 lrclkD1_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X155Y120 lrclkD2_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X153Y120 lrclkcnt_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X153Y120 lrclkcnt_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X154Y120 lrclkcnt_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X154Y120 lrclkcnt_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X155Y120 pulse48kHz_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X158Y133 audio_inout/BCLK_int_reg/C
+Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X156Y121 lrclkD1_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X156Y121 lrclkD1_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X155Y120 lrclkD2_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X155Y120 lrclkD2_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X154Y120 lrclkcnt_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X154Y120 lrclkcnt_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X156Y121 lrclkD1_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X156Y121 lrclkD1_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X155Y120 lrclkD2_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X155Y120 lrclkD2_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X153Y120 lrclkcnt_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X154Y120 lrclkcnt_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X154Y120 lrclkcnt_reg[2]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out3_clk_wiz_0
+ To Clock: clk_out3_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 81.178ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out3_clk_wiz_0
+Waveform(ns): { 0.000 41.667 }
+Period(ns): 83.333
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT2 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 83.333 81.178 BUFGCTRL_X0Y0 clk_1/inst/clkout3_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT2 n/a 1.249 83.333 82.084 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT2
+Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 83.333 130.027 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT2
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out4_clk_wiz_0
+ To Clock: clk_out4_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 14.812ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.153ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 14.812ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[4]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.923ns (logic 0.952ns (19.337%) route 3.971ns (80.663%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.034ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.489 3.858 initialize_audio/twi_controller_n_8
+ SLICE_X161Y113 FDRE r initialize_audio/initA_reg[4]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/clk_out4
+ SLICE_X161Y113 FDRE r initialize_audio/initA_reg[4]/C
+ clock pessimism 0.554 18.969
+ clock uncertainty -0.094 18.875
+ SLICE_X161Y113 FDRE (Setup_fdre_C_CE) -0.205 18.670 initialize_audio/initA_reg[4]
+ -------------------------------------------------------------------
+ required time 18.670
+ arrival time -3.858
+ -------------------------------------------------------------------
+ slack 14.812
+
+Slack (MET) : 14.812ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[5]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.923ns (logic 0.952ns (19.337%) route 3.971ns (80.663%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.034ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.489 3.858 initialize_audio/twi_controller_n_8
+ SLICE_X161Y113 FDRE r initialize_audio/initA_reg[5]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/clk_out4
+ SLICE_X161Y113 FDRE r initialize_audio/initA_reg[5]/C
+ clock pessimism 0.554 18.969
+ clock uncertainty -0.094 18.875
+ SLICE_X161Y113 FDRE (Setup_fdre_C_CE) -0.205 18.670 initialize_audio/initA_reg[5]
+ -------------------------------------------------------------------
+ required time 18.670
+ arrival time -3.858
+ -------------------------------------------------------------------
+ slack 14.812
+
+Slack (MET) : 14.817ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[6]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.918ns (logic 0.952ns (19.357%) route 3.966ns (80.643%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.034ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.484 3.853 initialize_audio/twi_controller_n_8
+ SLICE_X160Y113 FDRE r initialize_audio/initA_reg[6]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/initA_reg[6]/C
+ clock pessimism 0.554 18.969
+ clock uncertainty -0.094 18.875
+ SLICE_X160Y113 FDRE (Setup_fdre_C_CE) -0.205 18.670 initialize_audio/initA_reg[6]
+ -------------------------------------------------------------------
+ required time 18.670
+ arrival time -3.853
+ -------------------------------------------------------------------
+ slack 14.817
+
+Slack (MET) : 14.852ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[0]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.918ns (logic 0.952ns (19.356%) route 3.966ns (80.644%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.033ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.484 3.853 initialize_audio/twi_controller_n_8
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[0]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.707 18.415 initialize_audio/clk_out4
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[0]/C
+ clock pessimism 0.554 18.968
+ clock uncertainty -0.094 18.874
+ SLICE_X158Y112 FDRE (Setup_fdre_C_CE) -0.169 18.705 initialize_audio/initA_reg[0]
+ -------------------------------------------------------------------
+ required time 18.705
+ arrival time -3.853
+ -------------------------------------------------------------------
+ slack 14.852
+
+Slack (MET) : 14.852ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[1]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.918ns (logic 0.952ns (19.356%) route 3.966ns (80.644%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.033ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.484 3.853 initialize_audio/twi_controller_n_8
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[1]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.707 18.415 initialize_audio/clk_out4
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[1]/C
+ clock pessimism 0.554 18.968
+ clock uncertainty -0.094 18.874
+ SLICE_X158Y112 FDRE (Setup_fdre_C_CE) -0.169 18.705 initialize_audio/initA_reg[1]
+ -------------------------------------------------------------------
+ required time 18.705
+ arrival time -3.853
+ -------------------------------------------------------------------
+ slack 14.852
+
+Slack (MET) : 14.852ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[2]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.918ns (logic 0.952ns (19.356%) route 3.966ns (80.644%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.033ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.484 3.853 initialize_audio/twi_controller_n_8
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[2]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.707 18.415 initialize_audio/clk_out4
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[2]/C
+ clock pessimism 0.554 18.968
+ clock uncertainty -0.094 18.874
+ SLICE_X158Y112 FDRE (Setup_fdre_C_CE) -0.169 18.705 initialize_audio/initA_reg[2]
+ -------------------------------------------------------------------
+ required time 18.705
+ arrival time -3.853
+ -------------------------------------------------------------------
+ slack 14.852
+
+Slack (MET) : 14.852ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[3]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.918ns (logic 0.952ns (19.356%) route 3.966ns (80.644%))
+ Logic Levels: 4 (LUT4=2 LUT5=2)
+ Clock Path Skew: 0.033ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
+ Source Clock Delay (SCD): -1.065ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.754 -1.065 initialize_audio/clk_out4
+ SLICE_X153Y110 FDRE r initialize_audio/delaycnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X153Y110 FDRE (Prop_fdre_C_Q) 0.456 -0.609 f initialize_audio/delaycnt_reg[2]/Q
+ net (fo=3, routed) 0.993 0.384 initialize_audio/delaycnt_reg_n_0_[2]
+ SLICE_X152Y113 LUT4 (Prop_lut4_I1_O) 0.124 0.508 f initialize_audio/initA[6]_i_14/O
+ net (fo=1, routed) 0.447 0.955 initialize_audio/initA[6]_i_14_n_0
+ SLICE_X152Y115 LUT5 (Prop_lut5_I4_O) 0.124 1.079 f initialize_audio/initA[6]_i_10/O
+ net (fo=1, routed) 0.811 1.891 initialize_audio/initA[6]_i_10_n_0
+ SLICE_X152Y114 LUT4 (Prop_lut4_I2_O) 0.124 2.015 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 1.230 3.245 initialize_audio/twi_controller/initEn_reg
+ SLICE_X157Y113 LUT5 (Prop_lut5_I1_O) 0.124 3.369 r initialize_audio/twi_controller/initA[6]_i_2/O
+ net (fo=7, routed) 0.484 3.853 initialize_audio/twi_controller_n_8
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[3]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.707 18.415 initialize_audio/clk_out4
+ SLICE_X158Y112 FDRE r initialize_audio/initA_reg[3]/C
+ clock pessimism 0.554 18.968
+ clock uncertainty -0.094 18.874
+ SLICE_X158Y112 FDRE (Setup_fdre_C_CE) -0.169 18.705 initialize_audio/initA_reg[3]
+ -------------------------------------------------------------------
+ required time 18.705
+ arrival time -3.853
+ -------------------------------------------------------------------
+ slack 14.852
+
+Slack (MET) : 14.915ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.763ns (logic 0.952ns (19.986%) route 3.811ns (80.014%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=4, routed) 1.008 0.468 initialize_audio/twi_controller/rSda_reg_0
+ SLICE_X163Y117 LUT3 (Prop_lut3_I0_O) 0.124 0.592 r initialize_audio/twi_controller/FSM_gray_state[3]_i_7/O
+ net (fo=6, routed) 1.096 1.688 initialize_audio/twi_controller/FSM_gray_state[3]_i_7_n_0
+ SLICE_X161Y117 LUT5 (Prop_lut5_I0_O) 0.124 1.812 r initialize_audio/twi_controller/FSM_gray_state[3]_i_11/O
+ net (fo=1, routed) 0.658 2.471 initialize_audio/twi_controller/FSM_gray_state[3]_i_11_n_0
+ SLICE_X162Y117 LUT6 (Prop_lut6_I5_O) 0.124 2.595 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.658 3.253 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X162Y116 LUT6 (Prop_lut6_I3_O) 0.124 3.377 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.391 3.768 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X163Y116 FDRE (Setup_fdre_C_CE) -0.205 18.682 initialize_audio/twi_controller/FSM_gray_state_reg[1]
+ -------------------------------------------------------------------
+ required time 18.682
+ arrival time -3.768
+ -------------------------------------------------------------------
+ slack 14.915
+
+Slack (MET) : 14.915ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.763ns (logic 0.952ns (19.986%) route 3.811ns (80.014%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=4, routed) 1.008 0.468 initialize_audio/twi_controller/rSda_reg_0
+ SLICE_X163Y117 LUT3 (Prop_lut3_I0_O) 0.124 0.592 r initialize_audio/twi_controller/FSM_gray_state[3]_i_7/O
+ net (fo=6, routed) 1.096 1.688 initialize_audio/twi_controller/FSM_gray_state[3]_i_7_n_0
+ SLICE_X161Y117 LUT5 (Prop_lut5_I0_O) 0.124 1.812 r initialize_audio/twi_controller/FSM_gray_state[3]_i_11/O
+ net (fo=1, routed) 0.658 2.471 initialize_audio/twi_controller/FSM_gray_state[3]_i_11_n_0
+ SLICE_X162Y117 LUT6 (Prop_lut6_I5_O) 0.124 2.595 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.658 3.253 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X162Y116 LUT6 (Prop_lut6_I3_O) 0.124 3.377 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.391 3.768 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[2]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[2]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X163Y116 FDRE (Setup_fdre_C_CE) -0.205 18.682 initialize_audio/twi_controller/FSM_gray_state_reg[2]
+ -------------------------------------------------------------------
+ required time 18.682
+ arrival time -3.768
+ -------------------------------------------------------------------
+ slack 14.915
+
+Slack (MET) : 14.972ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/rSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.706ns (logic 0.952ns (20.230%) route 3.754ns (79.770%))
+ Logic Levels: 4 (LUT3=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.023ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.823 -0.996 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y117 FDRE r initialize_audio/twi_controller/rSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y117 FDRE (Prop_fdre_C_Q) 0.456 -0.540 r initialize_audio/twi_controller/rSda_reg/Q
+ net (fo=4, routed) 1.008 0.468 initialize_audio/twi_controller/rSda_reg_0
+ SLICE_X163Y117 LUT3 (Prop_lut3_I0_O) 0.124 0.592 r initialize_audio/twi_controller/FSM_gray_state[3]_i_7/O
+ net (fo=6, routed) 1.096 1.688 initialize_audio/twi_controller/FSM_gray_state[3]_i_7_n_0
+ SLICE_X161Y117 LUT5 (Prop_lut5_I0_O) 0.124 1.812 r initialize_audio/twi_controller/FSM_gray_state[3]_i_11/O
+ net (fo=1, routed) 0.658 2.471 initialize_audio/twi_controller/FSM_gray_state[3]_i_11_n_0
+ SLICE_X162Y117 LUT6 (Prop_lut6_I5_O) 0.124 2.595 r initialize_audio/twi_controller/FSM_gray_state[3]_i_4/O
+ net (fo=1, routed) 0.658 3.253 initialize_audio/twi_controller/FSM_gray_state[3]_i_4_n_0
+ SLICE_X162Y116 LUT6 (Prop_lut6_I3_O) 0.124 3.377 r initialize_audio/twi_controller/FSM_gray_state[3]_i_1/O
+ net (fo=4, routed) 0.333 3.710 initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0
+ SLICE_X161Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[3]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[3]/C
+ clock pessimism 0.568 18.981
+ clock uncertainty -0.094 18.887
+ SLICE_X161Y116 FDRE (Setup_fdre_C_CE) -0.205 18.682 initialize_audio/twi_controller/FSM_gray_state_reg[3]
+ -------------------------------------------------------------------
+ required time 18.682
+ arrival time -3.710
+ -------------------------------------------------------------------
+ slack 14.972
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.153ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[8]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.258ns (logic 0.209ns (80.975%) route 0.049ns (19.025%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.255ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/clk_out4
+ SLICE_X158Y114 FDRE r initialize_audio/initWord_reg[8]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X158Y114 FDRE (Prop_fdre_C_Q) 0.164 -0.493 r initialize_audio/initWord_reg[8]/Q
+ net (fo=1, routed) 0.049 -0.444 initialize_audio/data2[0]
+ SLICE_X159Y114 LUT6 (Prop_lut6_I3_O) 0.045 -0.399 r initialize_audio/data_i[0]_i_1/O
+ net (fo=1, routed) 0.000 -0.399 initialize_audio/data_i[0]_i_1_n_0
+ SLICE_X159Y114 FDRE r initialize_audio/data_i_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/clk_out4
+ SLICE_X159Y114 FDRE r initialize_audio/data_i_reg[0]/C
+ clock pessimism 0.255 -0.644
+ SLICE_X159Y114 FDRE (Hold_fdre_C_D) 0.092 -0.552 initialize_audio/data_i_reg[0]
+ -------------------------------------------------------------------
+ required time 0.552
+ arrival time -0.399
+ -------------------------------------------------------------------
+ slack 0.153
+
+Slack (MET) : 0.156ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/dataByte_reg[3]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.260ns (logic 0.209ns (80.352%) route 0.051ns (19.648%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.901ns
+ Source Clock Delay (SCD): -0.658ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.642 -0.658 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X158Y116 FDRE (Prop_fdre_C_Q) 0.164 -0.494 r initialize_audio/twi_controller/dataByte_reg[3]/Q
+ net (fo=1, routed) 0.051 -0.443 initialize_audio/twi_controller/dataByte[3]
+ SLICE_X159Y116 LUT4 (Prop_lut4_I3_O) 0.045 -0.398 r initialize_audio/twi_controller/dataByte[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.398 initialize_audio/twi_controller/p_1_in[4]
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.913 -0.901 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[4]/C
+ clock pessimism 0.256 -0.645
+ SLICE_X159Y116 FDRE (Hold_fdre_C_D) 0.091 -0.554 initialize_audio/twi_controller/dataByte_reg[4]
+ -------------------------------------------------------------------
+ required time 0.554
+ arrival time -0.398
+ -------------------------------------------------------------------
+ slack 0.156
+
+Slack (MET) : 0.169ns (arrival time - required time)
+ Source: initialize_audio/data_i_reg[6]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[6]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.296ns (logic 0.186ns (62.828%) route 0.110ns (37.172%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.035ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.901ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/clk_out4
+ SLICE_X160Y115 FDRE r initialize_audio/data_i_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y115 FDRE (Prop_fdre_C_Q) 0.141 -0.515 r initialize_audio/data_i_reg[6]/Q
+ net (fo=1, routed) 0.110 -0.405 initialize_audio/twi_controller/Q[2]
+ SLICE_X159Y116 LUT4 (Prop_lut4_I0_O) 0.045 -0.360 r initialize_audio/twi_controller/dataByte[6]_i_1/O
+ net (fo=1, routed) 0.000 -0.360 initialize_audio/twi_controller/p_1_in[6]
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.913 -0.901 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
+ clock pessimism 0.280 -0.621
+ SLICE_X159Y116 FDRE (Hold_fdre_C_D) 0.092 -0.529 initialize_audio/twi_controller/dataByte_reg[6]
+ -------------------------------------------------------------------
+ required time 0.529
+ arrival time -0.360
+ -------------------------------------------------------------------
+ slack 0.169
+
+Slack (MET) : 0.174ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/dataByte_reg[6]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[7]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.308ns (logic 0.186ns (60.369%) route 0.122ns (39.631%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.901ns
+ Source Clock Delay (SCD): -0.658ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.642 -0.658 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y116 FDRE (Prop_fdre_C_Q) 0.141 -0.517 r initialize_audio/twi_controller/dataByte_reg[6]/Q
+ net (fo=1, routed) 0.122 -0.395 initialize_audio/twi_controller/dataByte[6]
+ SLICE_X158Y116 LUT4 (Prop_lut4_I3_O) 0.045 -0.350 r initialize_audio/twi_controller/dataByte[7]_i_2/O
+ net (fo=1, routed) 0.000 -0.350 initialize_audio/twi_controller/p_1_in[7]
+ SLICE_X158Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.913 -0.901 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/C
+ clock pessimism 0.256 -0.645
+ SLICE_X158Y116 FDRE (Hold_fdre_C_D) 0.121 -0.524 initialize_audio/twi_controller/dataByte_reg[7]
+ -------------------------------------------------------------------
+ required time 0.524
+ arrival time -0.350
+ -------------------------------------------------------------------
+ slack 0.174
+
+Slack (MET) : 0.197ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/FSM_gray_state_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.330ns (logic 0.186ns (56.423%) route 0.144ns (43.577%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.900ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.256ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X163Y116 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r initialize_audio/twi_controller/FSM_gray_state_reg[1]/Q
+ net (fo=28, routed) 0.144 -0.372 initialize_audio/twi_controller/state[1]
+ SLICE_X162Y116 LUT6 (Prop_lut6_I4_O) 0.045 -0.327 r initialize_audio/twi_controller/FSM_gray_state[0]_i_1/O
+ net (fo=1, routed) 0.000 -0.327 initialize_audio/twi_controller/FSM_gray_state[0]_i_1_n_0
+ SLICE_X162Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.914 -0.900 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y116 FDRE r initialize_audio/twi_controller/FSM_gray_state_reg[0]/C
+ clock pessimism 0.256 -0.644
+ SLICE_X162Y116 FDRE (Hold_fdre_C_D) 0.120 -0.524 initialize_audio/twi_controller/FSM_gray_state_reg[0]
+ -------------------------------------------------------------------
+ required time 0.524
+ arrival time -0.327
+ -------------------------------------------------------------------
+ slack 0.197
+
+Slack (MET) : 0.198ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[9]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[1]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.304ns (logic 0.209ns (68.711%) route 0.095ns (31.289%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/clk_out4
+ SLICE_X158Y113 FDRE r initialize_audio/initWord_reg[9]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X158Y113 FDRE (Prop_fdre_C_Q) 0.164 -0.493 r initialize_audio/initWord_reg[9]/Q
+ net (fo=1, routed) 0.095 -0.398 initialize_audio/data2[1]
+ SLICE_X157Y113 LUT6 (Prop_lut6_I2_O) 0.045 -0.353 r initialize_audio/data_i[1]_i_1/O
+ net (fo=1, routed) 0.000 -0.353 initialize_audio/data_i[1]_i_1_n_0
+ SLICE_X157Y113 FDRE r initialize_audio/data_i_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/clk_out4
+ SLICE_X157Y113 FDRE r initialize_audio/data_i_reg[1]/C
+ clock pessimism 0.257 -0.642
+ SLICE_X157Y113 FDRE (Hold_fdre_C_D) 0.091 -0.551 initialize_audio/data_i_reg[1]
+ -------------------------------------------------------------------
+ required time 0.551
+ arrival time -0.353
+ -------------------------------------------------------------------
+ slack 0.198
+
+Slack (MET) : 0.213ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[21]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[5]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.342ns (logic 0.186ns (54.425%) route 0.156ns (45.575%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.037ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/clk_out4
+ SLICE_X161Y114 FDRE r initialize_audio/initWord_reg[21]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y114 FDRE (Prop_fdre_C_Q) 0.141 -0.515 r initialize_audio/initWord_reg[21]/Q
+ net (fo=2, routed) 0.156 -0.359 initialize_audio/data1[5]
+ SLICE_X159Y114 LUT6 (Prop_lut6_I0_O) 0.045 -0.314 r initialize_audio/data_i[5]_i_2/O
+ net (fo=1, routed) 0.000 -0.314 initialize_audio/data_i[5]_i_2_n_0
+ SLICE_X159Y114 FDRE r initialize_audio/data_i_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/clk_out4
+ SLICE_X159Y114 FDRE r initialize_audio/data_i_reg[5]/C
+ clock pessimism 0.280 -0.619
+ SLICE_X159Y114 FDRE (Hold_fdre_C_D) 0.092 -0.527 initialize_audio/data_i_reg[5]
+ -------------------------------------------------------------------
+ required time 0.527
+ arrival time -0.314
+ -------------------------------------------------------------------
+ slack 0.213
+
+Slack (MET) : 0.213ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/busFreeCnt_reg[0]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/busFreeCnt_reg[2]/D
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.318ns (logic 0.186ns (58.452%) route 0.132ns (41.548%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.894ns
+ Source Clock Delay (SCD): -0.653ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.647 -0.653 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y109 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y109 FDSE (Prop_fdse_C_Q) 0.141 -0.512 r initialize_audio/twi_controller/busFreeCnt_reg[0]/Q
+ net (fo=7, routed) 0.132 -0.380 initialize_audio/twi_controller/sel0[0]
+ SLICE_X160Y109 LUT3 (Prop_lut3_I2_O) 0.045 -0.335 r initialize_audio/twi_controller/busFreeCnt[2]_i_1/O
+ net (fo=1, routed) 0.000 -0.335 initialize_audio/twi_controller/busFreeCnt00_in[2]
+ SLICE_X160Y109 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.920 -0.894 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y109 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[2]/C
+ clock pessimism 0.254 -0.640
+ SLICE_X160Y109 FDSE (Hold_fdse_C_D) 0.092 -0.548 initialize_audio/twi_controller/busFreeCnt_reg[2]
+ -------------------------------------------------------------------
+ required time 0.548
+ arrival time -0.335
+ -------------------------------------------------------------------
+ slack 0.213
+
+Slack (MET) : 0.213ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/busFreeCnt_reg[0]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/busFreeCnt_reg[1]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.317ns (logic 0.186ns (58.636%) route 0.131ns (41.364%))
+ Logic Levels: 1 (LUT2=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.894ns
+ Source Clock Delay (SCD): -0.653ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.647 -0.653 initialize_audio/twi_controller/clk_out4
+ SLICE_X161Y109 FDSE r initialize_audio/twi_controller/busFreeCnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y109 FDSE (Prop_fdse_C_Q) 0.141 -0.512 r initialize_audio/twi_controller/busFreeCnt_reg[0]/Q
+ net (fo=7, routed) 0.131 -0.381 initialize_audio/twi_controller/sel0[0]
+ SLICE_X160Y109 LUT2 (Prop_lut2_I0_O) 0.045 -0.336 r initialize_audio/twi_controller/busFreeCnt[1]_i_1/O
+ net (fo=1, routed) 0.000 -0.336 initialize_audio/twi_controller/busFreeCnt[1]_i_1_n_0
+ SLICE_X160Y109 FDRE r initialize_audio/twi_controller/busFreeCnt_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.920 -0.894 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y109 FDRE r initialize_audio/twi_controller/busFreeCnt_reg[1]/C
+ clock pessimism 0.254 -0.640
+ SLICE_X160Y109 FDRE (Hold_fdre_C_D) 0.091 -0.549 initialize_audio/twi_controller/busFreeCnt_reg[1]
+ -------------------------------------------------------------------
+ required time 0.549
+ arrival time -0.336
+ -------------------------------------------------------------------
+ slack 0.213
+
+Slack (MET) : 0.224ns (arrival time - required time)
+ Source: initialize_audio/data_i_reg[5]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[5]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.329ns (logic 0.186ns (56.464%) route 0.143ns (43.536%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.901ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/clk_out4
+ SLICE_X159Y114 FDRE r initialize_audio/data_i_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y114 FDRE (Prop_fdre_C_Q) 0.141 -0.516 r initialize_audio/data_i_reg[5]/Q
+ net (fo=1, routed) 0.143 -0.372 initialize_audio/twi_controller/dataByte_reg[5]_0
+ SLICE_X159Y116 LUT4 (Prop_lut4_I0_O) 0.045 -0.327 r initialize_audio/twi_controller/dataByte[5]_i_1/O
+ net (fo=1, routed) 0.000 -0.327 initialize_audio/twi_controller/p_1_in[5]
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.913 -0.901 initialize_audio/twi_controller/clk_out4
+ SLICE_X159Y116 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/C
+ clock pessimism 0.257 -0.644
+ SLICE_X159Y116 FDRE (Hold_fdre_C_D) 0.092 -0.552 initialize_audio/twi_controller/dataByte_reg[5]
+ -------------------------------------------------------------------
+ required time 0.552
+ arrival time -0.327
+ -------------------------------------------------------------------
+ slack 0.224
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out4_clk_wiz_0
+Waveform(ns): { 0.000 10.000 }
+Period(ns): 20.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT3 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y2 clk_1/inst/clkout4_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT3 n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X157Y113 initialize_audio/data_i_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y115 initialize_audio/data_i_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X159Y114 initialize_audio/data_i_reg[5]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y115 initialize_audio/data_i_reg[6]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X157Y114 initialize_audio/data_i_reg[7]/C
+Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 20.000 193.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X157Y113 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X157Y113 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y115 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y115 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X157Y113 initialize_audio/data_i_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X157Y113 initialize_audio/data_i_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y114 initialize_audio/data_i_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y115 initialize_audio/data_i_reg[3]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X159Y115 initialize_audio/data_i_reg[3]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y115 initialize_audio/data_i_reg[4]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clkfbout_clk_wiz_0
+ To Clock: clkfbout_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clkfbout_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKFBOUT }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y3 clk_1/inst/clkf_buf/I
+Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBOUT
+Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBOUT
+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..9d642c2ca4456073ed12d9ed0a81977f2d2dd9b3
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9b83aba7c3d63b0ee0c5d53304d7eb21deba98dd
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..071217230f454ef50b759fd1c3d2552ab53fca9d
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
@@ -0,0 +1,226 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:13:15 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs | 585 | 0 | 800 | 133800 | 0.44 |
+| LUT as Logic | 585 | 0 | 800 | 133800 | 0.44 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register as Flip Flop | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register as Latch | 0 | 0 | 1600 | 267600 | 0.00 |
+| F7 Muxes | 33 | 0 | 400 | 66900 | 0.05 |
+| F8 Muxes | 16 | 0 | 200 | 33450 | 0.05 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 312 | Yes | - | Reset |
+| 20 | Yes | Set | - |
+| 255 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice | 252 | 0 | 200 | 33450 | 0.75 |
+| SLICEL | 171 | 0 | | | |
+| SLICEM | 81 | 0 | | | |
+| LUT as Logic | 585 | 0 | 800 | 133800 | 0.44 |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 517 | | | | |
+| using O5 and O6 | 68 | | | | |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| LUT as Distributed RAM | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| LUT as Shift Register | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| Slice Registers | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register driven from within the Slice | 268 | | | | |
+| Register driven from outside the Slice | 321 | | | | |
+| LUT in front of the register is unused | 271 | | | | |
+| LUT in front of the register is used | 50 | | | | |
+| Unique Control Sets | 29 | | 200 | 33450 | 0.09 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 20 | 20 | 0 | 285 | 7.02 |
+| IOB Master Pads | 8 | | | | |
+| IOB Slave Pads | 10 | | | | |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 0 | 10 | 10.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| FDCE | 312 | Flop & Latch |
+| FDRE | 255 | Flop & Latch |
+| LUT6 | 250 | LUT |
+| LUT2 | 131 | LUT |
+| LUT5 | 98 | LUT |
+| LUT4 | 67 | LUT |
+| LUT3 | 64 | LUT |
+| LUT1 | 43 | LUT |
+| CARRY4 | 40 | CarryLogic |
+| MUXF7 | 33 | MuxFx |
+| FDSE | 20 | Flop & Latch |
+| MUXF8 | 16 | MuxFx |
+| IBUF | 11 | IO |
+| OBUF | 9 | IO |
+| BUFG | 4 | Clock |
+| OBUFT | 2 | IO |
+| FDPE | 2 | Flop & Latch |
+| MMCME2_ADV | 1 | Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/clockInfo.txt b/proj/AudioProc.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000000000000000000000000000000000000..860371da413a626dd48787b332f6671eba0614ad
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.1
+| Date : Wed Mar 5 14:13:08 2025
+| Host : fl-tp-br-641
+| Design : design_1
+| Device : xc7a200t-sbg484-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/proj/AudioProc.runs/impl_1/gen_run.xml b/proj/AudioProc.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..8d032686f8e3db1a926fc8462bfa07823d169c18
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/gen_run.xml
@@ -0,0 +1,187 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1741180266">
+ <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS" Name="audioProc_postroute_physopted.rqs"/>
+ <File Type="ROUTE-RQS" Name="audioProc_routed.rqs"/>
+ <File Type="RBD_FILE" Name="audioProc.rbd"/>
+ <File Type="NPI_FILE" Name="audioProc.npi"/>
+ <File Type="RNPI_FILE" Name="audioProc.rnpi"/>
+ <File Type="CFI_FILE" Name="audioProc.cfi"/>
+ <File Type="RCFI_FILE" Name="audioProc.rcfi"/>
+ <File Type="PL-PDI-FILE" Name="audioProc_pld.pdi"/>
+ <File Type="BOOT-PDI-FILE" Name="audioProc_boot.pdi"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="audioProc_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-RPX" Name="audioProc_drc_routed.rpx"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="audioProc_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="audioProc_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="audioProc_bus_skew_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="audioProc_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="audioProc_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="audioProc_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="audioProc_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="audioProc_postroute_physopt.dcp"/>
+ <File Type="PHYSOPT-DCP" Name="audioProc_physopt.dcp"/>
+ <File Type="PLACE-IO" Name="audioProc_io_placed.rpt"/>
+ <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="audioProc.ltx"/>
+ <File Type="BITSTR-SYSDEF" Name="audioProc.sysdef"/>
+ <File Type="BITSTR-MMI" Name="audioProc.mmi"/>
+ <File Type="BITSTR-BMM" Name="audioProc_bd.bmm"/>
+ <File Type="PLACE-UTIL-PB" Name="audioProc_utilization_placed.pb"/>
+ <File Type="BG-BGN" Name="audioProc.bgn"/>
+ <File Type="OPT-DCP" Name="audioProc_opt.dcp"/>
+ <File Type="OPT-HWDEF" Name="audioProc.hwdef"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+ <File Type="BG-BIT" Name="audioProc.bit"/>
+ <File Type="ROUTE-BUS-SKEW" Name="audioProc_bus_skew_routed.rpt"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="PLACE-UTIL" Name="audioProc_utilization_placed.rpt"/>
+ <File Type="BG-DRC" Name="audioProc.drc"/>
+ <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
+ <File Type="PDI-FILE" Name="audioProc.pdi"/>
+ <File Type="RDI-RDI" Name="audioProc.vdi"/>
+ <File Type="BG-BIN" Name="audioProc.bin"/>
+ <File Type="PLACE-DCP" Name="audioProc_placed.dcp"/>
+ <File Type="BITSTR-MSK" Name="audioProc.msk"/>
+ <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
+ <File Type="BITSTR-RBT" Name="audioProc.rbt"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="audioProc_postplace_pwropt.dcp"/>
+ <File Type="BITSTR-NKY" Name="audioProc.nky"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="audioProc_incremental_reuse_pre_placed.rpt"/>
+ <File Type="ROUTE-DRC" Name="audioProc_drc_routed.rpt"/>
+ <File Type="ROUTE-DRC-PB" Name="audioProc_drc_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="audioProc_power_routed.rpt"/>
+ <File Type="ROUTE-PWR-SUM" Name="audioProc_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR-RPX" Name="audioProc_power_routed.rpx"/>
+ <File Type="ROUTE-STATUS" Name="audioProc_route_status.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="audioProc_route_status.pb"/>
+ <File Type="ROUTE-DCP" Name="audioProc_routed.dcp"/>
+ <File Type="ROUTE-ERROR-DCP" Name="audioProc_routed_error.dcp"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="audioProc_routed_bb.dcp"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="audioProc_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-TIMING-PB" Name="audioProc_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMING-RPX" Name="audioProc_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-SIMILARITY" Name="audioProc_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="audioProc_clock_utilization_routed.rpt"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="audioProc_bus_skew_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="audioProc_bus_skew_routed.rpx"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ <Step Id="write_device_image"/>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
+</GenRun>
diff --git a/proj/AudioProc.runs/impl_1/htr.txt b/proj/AudioProc.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2498e464293307c0340b7226ed1775e71d1403fc
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/init_design.pb b/proj/AudioProc.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..03dedae6ef56ce8c7817e71703b9916f2d6b351b
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/init_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/opt_design.pb b/proj/AudioProc.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4cf647aa36cc64ab256e1b9c569c257d7c3cafd0
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/opt_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/place_design.pb b/proj/AudioProc.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ed2c9a23af4df02d9eab45696cf7dfda61268f45
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/place_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/project.wdf b/proj/AudioProc.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..449116682dfa7be006882addcedb17746e37a015
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00
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+eof:1910590704
diff --git a/proj/AudioProc.runs/impl_1/route_design.pb b/proj/AudioProc.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..322d5964b4c788aea7bce8c05350c54093a0102d
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/route_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/rundef.js b/proj/AudioProc.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..71fd88a2c461cdb1b7866d73d7d4f095836dc76b
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/rundef.js
@@ -0,0 +1,45 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/impl_1/runme.bat b/proj/AudioProc.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/impl_1/runme.log b/proj/AudioProc.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..7c3a885b9d6ccadb57ffb90d00bea207e8df51a3
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.log
@@ -0,0 +1,753 @@
+
+*** Running vivado
+ with args -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Mar 5 14:12:22 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1571.520 ; gain = 204.840 ; free physical = 6283 ; free virtual = 16059
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1990.426 ; gain = 0.000 ; free physical = 5960 ; free virtual = 15720
+INFO: [Netlist 29-17] Analyzing 92 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc:54]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc:54]
+get_clocks: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2707.918 ; gain = 624.898 ; free physical = 5455 ; free virtual = 15269
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2707.918 ; gain = 0.000 ; free physical = 5451 ; free virtual = 15265
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2707.918 ; gain = 1117.586 ; free physical = 5451 ; free virtual = 15265
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2707.918 ; gain = 0.000 ; free physical = 5428 ; free virtual = 15244
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2727.762 ; gain = 19.844 ; free physical = 5428 ; free virtual = 15244
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5113 ; free virtual = 14928
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5113 ; free virtual = 14928
+Phase 1 Initialization | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5113 ; free virtual = 14928
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5112 ; free virtual = 14928
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5112 ; free virtual = 14928
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2042ec06d
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5112 ; free virtual = 14928
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 18b6c7825
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5110 ; free virtual = 14926
+Retarget | Checksum: 18b6c7825
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 1970ed4ba
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5108 ; free virtual = 14924
+Constant propagation | Checksum: 1970ed4ba
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Sweep | Checksum: 1fa5c0332
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+BUFG optimization | Checksum: 1fa5c0332
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Shift Register Optimization | Checksum: 1fa5c0332
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 1fa5c0332
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Post Processing Netlist | Checksum: 1fa5c0332
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Phase 9 Finalization | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 2 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+Ending Netlist Obfuscation Task | Checksum: 2773fae47
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3029.660 ; gain = 0.000 ; free physical = 5104 ; free virtual = 14920
+INFO: [Common 17-83] Releasing license: Implementation
+33 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14907
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14908
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5092 ; free virtual = 14908
+Write Physdb Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5091 ; free virtual = 14908
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5094 ; free virtual = 14910
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17b1be318
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5094 ; free virtual = 14910
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5094 ; free virtual = 14910
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f1d75507
+
+Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5076 ; free virtual = 14895
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e01ae09e
+
+Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e01ae09e
+
+Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.44 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+Phase 1 Placer Initialization | Checksum: 1e01ae09e
+
+Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 15c659040
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1f06dbb3b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.56 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1f06dbb3b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5075 ; free virtual = 14896
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 177563483
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 134 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 58 nets or LUTs. Breaked 0 LUT, combined 58 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
+INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5072 ; free virtual = 14899
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 58 | 58 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 58 | 58 | 0 | 9 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 16fcc0717
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5069 ; free virtual = 14897
+Phase 2.4 Global Placement Core | Checksum: 1ab2b8c90
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5069 ; free virtual = 14897
+Phase 2 Global Placement | Checksum: 1ab2b8c90
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5069 ; free virtual = 14897
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 148f50c4f
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c9d6d086
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 10158e9a0
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 11913573e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5068 ; free virtual = 14897
+
+Phase 3.5 Fast Optimization
+Phase 3.5 Fast Optimization | Checksum: fce9bc41
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5081 ; free virtual = 14910
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1a65a55ff
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5084 ; free virtual = 14909
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 121f35092
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5084 ; free virtual = 14909
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 158b76b67
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5084 ; free virtual = 14909
+
+Phase 3.9 Fast Optimization
+Phase 3.9 Fast Optimization | Checksum: 1cc1d718d
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5093 ; free virtual = 14918
+Phase 3 Detail Placement | Checksum: 1cc1d718d
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5093 ; free virtual = 14918
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 236b07470
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.182 | TNS=-0.269 |
+Phase 1 Physical Synthesis Initialization | Checksum: 20308c1ff
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 2dd9727f8
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+Phase 4.1.1.1 BUFG Insertion | Checksum: 236b07470
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5064 ; free virtual = 14889
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.522. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5046 ; free virtual = 14871
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5046 ; free virtual = 14871
+Phase 4.1 Post Commit Optimization | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5046 ; free virtual = 14871
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+Phase 4.3 Placer Reporting | Checksum: 229da698f
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20c662c6b
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+Ending Placer Task | Checksum: 13ced0ba0
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+76 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5042 ; free virtual = 14867
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5026 ; free virtual = 14850
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.25 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5020 ; free virtual = 14845
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5019 ; free virtual = 14844
+Wrote PlaceDB: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5017 ; free virtual = 14843
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14842
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14842
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14843
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14843
+Write Physdb Complete: Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3085.688 ; gain = 0.000 ; free physical = 5016 ; free virtual = 14843
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 109e7e37 ConstDB: 0 ShapeSum: 9433a205 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 18fdecac | NumContArr: 5b39c82f | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 1f989aa15
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:41 . Memory (MB): peak = 3300.426 ; gain = 198.918 ; free physical = 4818 ; free virtual = 14647
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 1f989aa15
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:41 . Memory (MB): peak = 3300.426 ; gain = 198.918 ; free physical = 4818 ; free virtual = 14647
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 1f989aa15
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:41 . Memory (MB): peak = 3300.426 ; gain = 198.918 ; free physical = 4818 ; free virtual = 14647
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1bd2412ab
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:42 . Memory (MB): peak = 3349.402 ; gain = 247.895 ; free physical = 4767 ; free virtual = 14597
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.526 | TNS=0.000 | WHS=-0.120 | THS=-18.709|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 1012
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 1012
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 1e1ac6fca
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:42 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4759 ; free virtual = 14589
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 1e1ac6fca
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:42 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4759 ; free virtual = 14589
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 1e50d8e52
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:43 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4772 ; free virtual = 14602
+Phase 4 Initial Routing | Checksum: 1e50d8e52
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:43 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4772 ; free virtual = 14602
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 384
+ Number of Nodes with overlaps = 184
+ Number of Nodes with overlaps = 126
+ Number of Nodes with overlaps = 62
+ Number of Nodes with overlaps = 37
+ Number of Nodes with overlaps = 11
+ Number of Nodes with overlaps = 7
+ Number of Nodes with overlaps = 4
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.175 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 2e259928b
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4760 ; free virtual = 14590
+Phase 5 Rip-up And Reroute | Checksum: 2e259928b
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4760 ; free virtual = 14590
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4768 ; free virtual = 14598
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.268 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 6.1 Delay CleanUp | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4777 ; free virtual = 14607
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+Phase 6 Delay and Skew Optimization | Checksum: 34100343e
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.268 | TNS=0.000 | WHS=0.135 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+Phase 7 Post Hold Fix | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.081324 %
+ Global Horizontal Routing Utilization = 0.0987442 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4782 ; free virtual = 14612
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 2cadb3a06
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:46 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 230747a87
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 230747a87
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.268 | TNS=0.000 | WHS=0.135 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 230747a87
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+Total Elapsed time in route_design: 46.56 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 14e55bb2d
+
+Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 14e55bb2d
+
+Time (s): cpu = 00:00:59 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+95 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:01:00 ; elapsed = 00:00:47 . Memory (MB): peak = 3356.793 ; gain = 255.285 ; free physical = 4781 ; free virtual = 14611
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 4 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+115 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4736 ; free virtual = 14567
+Wrote PlaceDB: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4724 ; free virtual = 14557
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4741 ; free virtual = 14574
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4744 ; free virtual = 14577
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4744 ; free virtual = 14577
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4744 ; free virtual = 14577
+Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3412.820 ; gain = 0.000 ; free physical = 4743 ; free virtual = 14577
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+Command: write_bitstream -force audioProc.bit -bin_file
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./audioProc.bit...
+Writing bitstream ./audioProc.bin...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+126 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 3732.207 ; gain = 319.387 ; free physical = 4410 ; free virtual = 14260
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 5 14:14:25 2025...
diff --git a/proj/AudioProc.runs/impl_1/runme.sh b/proj/AudioProc.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4ea96a84a94d803bb34b516acf6bc7b38f34d280
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+
+
diff --git a/proj/AudioProc.runs/impl_1/vivado.jou b/proj/AudioProc.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..ef87361e88da84af8d82fe81c3f600c42209daa1
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Mar 5 14:12:22 2025
+# Process ID: 90623
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-641
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3100.043 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :17651 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado.pb b/proj/AudioProc.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b093cf985d5b55105196d5dbde898b5b4af5b5f1
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/vivado.pb differ
diff --git a/proj/AudioProc.runs/impl_1/write_bitstream.pb b/proj/AudioProc.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3bf22dc88ddc5bbcaf524f7852659d5de4ff36b9
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/write_bitstream.pb differ
diff --git a/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst b/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc b/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5e3177db710f2380d1ff90d9f251e84965eed8d2
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc
@@ -0,0 +1,51 @@
+set_property SRC_FILE_INFO {cfile:/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc rfile:../../../../src/constraints/NexysVideo_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports { led3 }];#[get_ports {LED[3]}]
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports { led4 }];#[get_ports {LED[4]}]
+set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports { led5 }];#[get_ports {LED[5]}]
+set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports { led6 }];#[get_ports {LED[6]}]
+set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports { led7 }];#[get_ports {LED[7]}]
+set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports BTNC]
+set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports BTND]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports BTNL]
+set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports BTNR]
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports BTNU]
+set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports rstn]
+set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports sw]
+set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports { sw3 }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports { sw4 }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports { sw5 }]; #IO_0_15 Sch=sw[5]
+set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { sw6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { sw7 }]; #IO_25_15 Sch=sw[7]
+set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ac_adc_sdata]
+set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ac_bclk]
+set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ac_dac_sdata]
+set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ac_lrclk]
+set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ac_mclk]
+set_property src_info {type:XDC file:1 line:202 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports scl]
+set_property src_info {type:XDC file:1 line:203 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports sda]
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3b94a0714cd9c4cad253f0d753af5037b03a90bb
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="c24masso" Host="fl-tp-br-641" Pid="89881" HostCore="4" HostMemory="16257800">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/.vivado.end.rst b/proj/AudioProc.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.js b/proj/AudioProc.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.sh b/proj/AudioProc.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/synth_1/__synthesis_is_complete__ b/proj/AudioProc.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/audioProc.dcp b/proj/AudioProc.runs/synth_1/audioProc.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..400882679fa8f72577d00073a51f364aff380386
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/audioProc.dcp differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc.tcl b/proj/AudioProc.runs/synth_1/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a01d8e3f07a5fc6205a04fc933e125c50c5dc9f1
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc.tcl
@@ -0,0 +1,128 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/audioProc.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a200tsbg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/wt [current_project]
+set_property parent.project_path /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_repo_paths /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo [current_project]
+update_ip_catalog
+set_property ip_output_repo /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_verilog -library xil_defaultlib {
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/debounce.v
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v
+}
+read_vhdl -library xil_defaultlib {
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd
+ /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/i2s_ctl.vhd
+}
+read_ip -quiet /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc
+set_property used_in_implementation false [get_files /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef audioProc.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/proj/AudioProc.runs/synth_1/audioProc.vds b/proj/AudioProc.runs/synth_1/audioProc.vds
new file mode 100644
index 0000000000000000000000000000000000000000..8fc5bb0c7572d0bec4806af70f31e55fc3db8fd5
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -0,0 +1,446 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Mar 5 14:11:09 2025
+# Process ID: 89958
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1
+# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/audioProc.vds
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-641
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3452.992 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :17667 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.520 ; gain = 204.840 ; free physical = 6606 ; free virtual = 16287
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 90171
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2393.703 ; gain = 420.555 ; free physical = 5467 ; free virtual = 15159
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:13]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/.Xil/Vivado-89958-fl-tp-br-641/realtime/clk_wiz_0_stub.vhdl:19]
+WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:85]
+WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:85]
+INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:24]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:51]
+INFO: [Synth 8-638] synthesizing module 'TWICtl' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:330]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:363]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:381]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:399]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:417]
+INFO: [Synth 8-256] done synthesizing module 'TWICtl' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:151]
+INFO: [Synth 8-6155] done synthesizing module 'audio_init' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:24]
+INFO: [Synth 8-6157] synthesizing module 'debounce' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/debounce.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'debounce' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/debounce.v:23]
+INFO: [Synth 8-638] synthesizing module 'i2s_ctl' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-256] done synthesizing module 'i2s_ctl' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'fir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:28]
+ Parameter dwidth bound to: 24 - type: integer
+ Parameter ntaps bound to: 16 - type: integer
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:28]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7023] instance 'leftFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7023] instance 'rightFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+INFO: [Synth 8-6155] done synthesizing module 'audioProc' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:13]
+WARNING: [Synth 8-6014] Unused sequential element timeOutCnt_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:236]
+WARNING: [Synth 8-6014] Unused sequential element errTypeR_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:313]
+WARNING: [Synth 8-6014] Unused sequential element regData1_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:135]
+WARNING: [Synth 8-6014] Unused sequential element initFbWe_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:150]
+WARNING: [Synth 8-3848] Net O_FilteredSampleValid in module/entity controlUnit does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:39]
+WARNING: [Synth 8-3848] Net dbg_output_0 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:18]
+WARNING: [Synth 8-3848] Net dbg_output_1 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:19]
+WARNING: [Synth 8-3848] Net dbg_output_2 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:20]
+WARNING: [Synth 8-3848] Net dbg_output_3 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:21]
+WARNING: [Synth 8-3848] Net dbg_output_4 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:22]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataL_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:225]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataR_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:226]
+WARNING: [Synth 8-7129] Port O_FilteredSampleValid in module controlUnit is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2478.641 ; gain = 505.492 ; free physical = 5393 ; free virtual = 15090
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.453 ; gain = 523.305 ; free physical = 5392 ; free virtual = 15088
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.453 ; gain = 523.305 ; free physical = 5392 ; free virtual = 15088
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2496.453 ; gain = 0.000 ; free physical = 5392 ; free virtual = 15088
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/audioProc_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/audioProc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2646.203 ; gain = 0.000 ; free physical = 5391 ; free virtual = 15090
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2646.203 ; gain = 0.000 ; free physical = 5388 ; free virtual = 15086
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5392 ; free virtual = 15091
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5392 ; free virtual = 15091
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
+Applied set_property CLOCK_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 7).
+Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5392 ; free virtual = 15091
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ stidle | 0001 | 0000
+ ststart | 0100 | 0001
+ stwrite | 0000 | 0011
+ stsack | 0011 | 0110
+ stread | 0010 | 0010
+ stmnackstart | 0110 | 1001
+ stmack | 0111 | 0111
+ stmnackstop | 0101 | 1000
+ ststop | 1100 | 0101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'gray' in module 'TWICtl'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00001 | 000
+ store | 00010 | 001
+ processing_loop | 00100 | 010
+ output | 01000 | 011
+ wait_end_sample | 10000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5357 ; free virtual = 15057
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 32 Bit Adders := 1
+ 2 Input 31 Bit Adders := 1
+ 2 Input 13 Bit Adders := 5
+ 2 Input 8 Bit Adders := 2
+ 2 Input 7 Bit Adders := 5
+ 2 Input 6 Bit Adders := 2
+ 2 Input 5 Bit Adders := 4
+ 2 Input 4 Bit Adders := 5
+ 2 Input 3 Bit Adders := 3
+ 2 Input 2 Bit Adders := 3
++---Registers :
+ 33 Bit Registers := 1
+ 32 Bit Registers := 3
+ 31 Bit Registers := 1
+ 24 Bit Registers := 2
+ 20 Bit Registers := 2
+ 13 Bit Registers := 5
+ 8 Bit Registers := 37
+ 7 Bit Registers := 3
+ 5 Bit Registers := 4
+ 4 Bit Registers := 4
+ 3 Bit Registers := 1
+ 2 Bit Registers := 2
+ 1 Bit Registers := 18
++---Muxes :
+ 2 Input 32 Bit Muxes := 3
+ 2 Input 24 Bit Muxes := 2
+ 2 Input 20 Bit Muxes := 2
+ 2 Input 8 Bit Muxes := 16
+ 2 Input 5 Bit Muxes := 9
+ 8 Input 5 Bit Muxes := 1
+ 5 Input 5 Bit Muxes := 2
+ 16 Input 5 Bit Muxes := 2
+ 9 Input 4 Bit Muxes := 1
+ 21 Input 4 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 9
+ 3 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 45
+ 4 Input 1 Bit Muxes := 21
+ 3 Input 1 Bit Muxes := 5
+ 9 Input 1 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 6
+ 36 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5325 ; free virtual = 15032
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5333 ; free virtual = 15040
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5346 ; free virtual = 15053
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5342 ; free virtual = 15051
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5340 ; free virtual = 15047
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5340 ; free virtual = 15047
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |clk_wiz | 1|
+|2 |CARRY4 | 40|
+|3 |LUT1 | 45|
+|4 |LUT2 | 131|
+|5 |LUT3 | 64|
+|6 |LUT4 | 67|
+|7 |LUT5 | 98|
+|8 |LUT6 | 250|
+|9 |MUXF7 | 33|
+|10 |MUXF8 | 16|
+|11 |FDCE | 312|
+|12 |FDPE | 2|
+|13 |FDRE | 255|
+|14 |FDSE | 20|
+|15 |IBUF | 8|
+|16 |IOBUF | 2|
+|17 |OBUF | 9|
++------+--------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 1 critical warnings and 38 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2646.203 ; gain = 523.305 ; free physical = 5345 ; free virtual = 15052
+Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2646.211 ; gain = 673.055 ; free physical = 5353 ; free virtual = 15059
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2646.211 ; gain = 0.000 ; free physical = 5648 ; free virtual = 15355
+INFO: [Netlist 29-17] Analyzing 91 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2646.211 ; gain = 0.000 ; free physical = 5648 ; free virtual = 15355
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+Synth Design complete | Checksum: 12085f41
+INFO: [Common 17-83] Releasing license: Synthesis
+49 Infos, 103 Warnings, 1 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2646.211 ; gain = 1055.879 ; free physical = 5648 ; free virtual = 15355
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2180.945; main = 1831.334; forked = 398.735
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3707.285; main = 2646.207; forked = 1061.078
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2646.211 ; gain = 0.000 ; free physical = 5671 ; free virtual = 15378
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 5 14:12:17 2025...
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..0fb24ee5a682f595bbbfc23a047d5be6b7c2f8a7
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..fee3069df0f5ef6603d98ace79d89cd94f9bacd8
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
@@ -0,0 +1,191 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Mar 5 14:12:16 2025
+| Host : fl-tp-br-641 running 64-bit Ubuntu 24.04.2 LTS
+| Command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 645 | 0 | 0 | 134600 | 0.48 |
+| LUT as Logic | 645 | 0 | 0 | 134600 | 0.48 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 589 | 0 | 0 | 269200 | 0.22 |
+| Register as Flip Flop | 589 | 0 | 0 | 269200 | 0.22 |
+| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
+| F7 Muxes | 33 | 0 | 0 | 67300 | 0.05 |
+| F8 Muxes | 16 | 0 | 0 | 33650 | 0.05 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 312 | Yes | - | Reset |
+| 20 | Yes | Set | - |
+| 255 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 19 | 0 | 0 | 285 | 6.67 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 312 | Flop & Latch |
+| FDRE | 255 | Flop & Latch |
+| LUT6 | 250 | LUT |
+| LUT2 | 131 | LUT |
+| LUT5 | 98 | LUT |
+| LUT4 | 67 | LUT |
+| LUT3 | 64 | LUT |
+| LUT1 | 45 | LUT |
+| CARRY4 | 40 | CarryLogic |
+| MUXF7 | 33 | MuxFx |
+| FDSE | 20 | Flop & Latch |
+| MUXF8 | 16 | MuxFx |
+| IBUF | 10 | IO |
+| OBUF | 9 | IO |
+| OBUFT | 2 | IO |
+| FDPE | 2 | Flop & Latch |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0fac04d47c597ece3a1d210368e3c3e685eeedac
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -0,0 +1,119 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1741180265">
+ <File Type="RDS-DCP" Name="audioProc.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="audioProc_utilization_synth.pb"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
+ <File Type="RDS-UTIL" Name="audioProc_utilization_synth.rpt"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="RDS-RDS" Name="audioProc.vds"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
+</GenRun>
diff --git a/proj/AudioProc.runs/synth_1/htr.txt b/proj/AudioProc.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6eaa206564a408917c3a3780eaa04c938f0a3fb9
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
diff --git a/proj/AudioProc.runs/synth_1/rundef.js b/proj/AudioProc.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..753f590723e7e3bf6e771dafe591ec341caa8a71
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/synth_1/runme.bat b/proj/AudioProc.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..fc09c361ae4baac700b4d3d025dc2ac5f60af984
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -0,0 +1,436 @@
+
+*** Running vivado
+ with args -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Mar 5 14:11:09 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.520 ; gain = 204.840 ; free physical = 6606 ; free virtual = 16287
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 90171
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2393.703 ; gain = 420.555 ; free physical = 5467 ; free virtual = 15159
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:13]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/.Xil/Vivado-89958-fl-tp-br-641/realtime/clk_wiz_0_stub.vhdl:19]
+WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:85]
+WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:85]
+INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:24]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:51]
+INFO: [Synth 8-638] synthesizing module 'TWICtl' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:330]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:363]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:381]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:399]
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:417]
+INFO: [Synth 8-256] done synthesizing module 'TWICtl' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:151]
+INFO: [Synth 8-6155] done synthesizing module 'audio_init' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:24]
+INFO: [Synth 8-6157] synthesizing module 'debounce' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/debounce.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'debounce' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/debounce.v:23]
+INFO: [Synth 8-638] synthesizing module 'i2s_ctl' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-256] done synthesizing module 'i2s_ctl' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'fir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:28]
+ Parameter dwidth bound to: 24 - type: integer
+ Parameter ntaps bound to: 16 - type: integer
+INFO: [Synth 8-226] default block is never used [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-638] synthesizing module 'operativeUnit' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'operativeUnit' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/operativeUnit.vhd:50]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:28]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'leftFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7023] instance 'leftFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'rightFir' [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7023] instance 'rightFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:204]
+INFO: [Synth 8-6155] done synthesizing module 'audioProc' (0#1) [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:13]
+WARNING: [Synth 8-6014] Unused sequential element timeOutCnt_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:236]
+WARNING: [Synth 8-6014] Unused sequential element errTypeR_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/TWICtl.vhd:313]
+WARNING: [Synth 8-6014] Unused sequential element regData1_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:135]
+WARNING: [Synth 8-6014] Unused sequential element initFbWe_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audio_init.v:150]
+WARNING: [Synth 8-3848] Net O_FilteredSampleValid in module/entity controlUnit does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/controlUnit.vhd:39]
+WARNING: [Synth 8-3848] Net dbg_output_0 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:18]
+WARNING: [Synth 8-3848] Net dbg_output_1 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:19]
+WARNING: [Synth 8-3848] Net dbg_output_2 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:20]
+WARNING: [Synth 8-3848] Net dbg_output_3 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:21]
+WARNING: [Synth 8-3848] Net dbg_output_4 in module/entity fir does not have driver. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/fir.vhd:22]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataL_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:225]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataR_reg was removed. [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/hdl/audioProc.v:226]
+WARNING: [Synth 8-7129] Port O_FilteredSampleValid in module controlUnit is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2478.641 ; gain = 505.492 ; free physical = 5393 ; free virtual = 15090
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.453 ; gain = 523.305 ; free physical = 5392 ; free virtual = 15088
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.453 ; gain = 523.305 ; free physical = 5392 ; free virtual = 15088
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2496.453 ; gain = 0.000 ; free physical = 5392 ; free virtual = 15088
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/constraints/NexysVideo_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/audioProc_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/audioProc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2646.203 ; gain = 0.000 ; free physical = 5391 ; free virtual = 15090
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2646.203 ; gain = 0.000 ; free physical = 5388 ; free virtual = 15086
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5392 ; free virtual = 15091
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5392 ; free virtual = 15091
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
+Applied set_property CLOCK_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 7).
+Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5392 ; free virtual = 15091
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ stidle | 0001 | 0000
+ ststart | 0100 | 0001
+ stwrite | 0000 | 0011
+ stsack | 0011 | 0110
+ stread | 0010 | 0010
+ stmnackstart | 0110 | 1001
+ stmack | 0111 | 0111
+ stmnackstop | 0101 | 1000
+ ststop | 1100 | 0101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'gray' in module 'TWICtl'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00001 | 000
+ store | 00010 | 001
+ processing_loop | 00100 | 010
+ output | 01000 | 011
+ wait_end_sample | 10000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5357 ; free virtual = 15057
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 32 Bit Adders := 1
+ 2 Input 31 Bit Adders := 1
+ 2 Input 13 Bit Adders := 5
+ 2 Input 8 Bit Adders := 2
+ 2 Input 7 Bit Adders := 5
+ 2 Input 6 Bit Adders := 2
+ 2 Input 5 Bit Adders := 4
+ 2 Input 4 Bit Adders := 5
+ 2 Input 3 Bit Adders := 3
+ 2 Input 2 Bit Adders := 3
++---Registers :
+ 33 Bit Registers := 1
+ 32 Bit Registers := 3
+ 31 Bit Registers := 1
+ 24 Bit Registers := 2
+ 20 Bit Registers := 2
+ 13 Bit Registers := 5
+ 8 Bit Registers := 37
+ 7 Bit Registers := 3
+ 5 Bit Registers := 4
+ 4 Bit Registers := 4
+ 3 Bit Registers := 1
+ 2 Bit Registers := 2
+ 1 Bit Registers := 18
++---Muxes :
+ 2 Input 32 Bit Muxes := 3
+ 2 Input 24 Bit Muxes := 2
+ 2 Input 20 Bit Muxes := 2
+ 2 Input 8 Bit Muxes := 16
+ 2 Input 5 Bit Muxes := 9
+ 8 Input 5 Bit Muxes := 1
+ 5 Input 5 Bit Muxes := 2
+ 16 Input 5 Bit Muxes := 2
+ 9 Input 4 Bit Muxes := 1
+ 21 Input 4 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 9
+ 3 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 45
+ 4 Input 1 Bit Muxes := 21
+ 3 Input 1 Bit Muxes := 5
+ 9 Input 1 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 6
+ 36 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5325 ; free virtual = 15032
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5333 ; free virtual = 15040
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5346 ; free virtual = 15053
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5342 ; free virtual = 15051
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5340 ; free virtual = 15047
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5340 ; free virtual = 15047
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |clk_wiz | 1|
+|2 |CARRY4 | 40|
+|3 |LUT1 | 45|
+|4 |LUT2 | 131|
+|5 |LUT3 | 64|
+|6 |LUT4 | 67|
+|7 |LUT5 | 98|
+|8 |LUT6 | 250|
+|9 |MUXF7 | 33|
+|10 |MUXF8 | 16|
+|11 |FDCE | 312|
+|12 |FDPE | 2|
+|13 |FDRE | 255|
+|14 |FDSE | 20|
+|15 |IBUF | 8|
+|16 |IOBUF | 2|
+|17 |OBUF | 9|
++------+--------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2646.203 ; gain = 673.055 ; free physical = 5345 ; free virtual = 15052
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 1 critical warnings and 38 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2646.203 ; gain = 523.305 ; free physical = 5345 ; free virtual = 15052
+Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2646.211 ; gain = 673.055 ; free physical = 5353 ; free virtual = 15059
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2646.211 ; gain = 0.000 ; free physical = 5648 ; free virtual = 15355
+INFO: [Netlist 29-17] Analyzing 91 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2646.211 ; gain = 0.000 ; free physical = 5648 ; free virtual = 15355
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+Synth Design complete | Checksum: 12085f41
+INFO: [Common 17-83] Releasing license: Synthesis
+49 Infos, 103 Warnings, 1 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2646.211 ; gain = 1055.879 ; free physical = 5648 ; free virtual = 15355
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2180.945; main = 1831.334; forked = 398.735
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3707.285; main = 2646.207; forked = 1061.078
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2646.211 ; gain = 0.000 ; free physical = 5671 ; free virtual = 15378
+INFO: [Common 17-1381] The checkpoint '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 5 14:12:17 2025...
diff --git a/proj/AudioProc.runs/synth_1/runme.sh b/proj/AudioProc.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..897194ef81a4d1116429d892263321c01aefbe5b
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..acd05be58f2a2dae79dfa5c2e9342ed816111f8a
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Mar 5 14:11:09 2025
+# Process ID: 89958
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1
+# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/audioProc.vds
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-641
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3452.992 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :17667 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b4a3682e464b09d133c8b417803e4a5694536e80
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/vivado.pb differ
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
index 82283987bce2c4a53a865a8baf09bb363c9c6e7c..af11d285a5e3df42f50a872f19e2ba3e93fa1a9e 100644
--- a/proj/AudioProc.xpr
+++ b/proj/AudioProc.xpr
@@ -182,6 +182,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
<File Path="$PPRDIR/tb_firUnit_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
@@ -244,11 +245,9 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
- <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
- </StratHandle>
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design">
<Option Id="FsmExtraction">1</Option>
<Option Id="KeepEquivalentRegisters">1</Option>
@@ -258,15 +257,14 @@
<Option Id="ShregMinSize">5</Option>
</Step>
</Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_wiz_0_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_0" Part="xc7a200tsbg484-1" ConstrsSet="clk_wiz_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clk_wiz_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -274,11 +272,9 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
- <Desc>Vivado Implementation Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -291,15 +287,14 @@
<Option Id="BinFile">1</Option>
</Step>
</Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
- <Desc>Default settings for Implementation.</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
diff --git a/vivado.jou b/vivado.jou
index 4057a4e112e3be9afb44ac0de2f6df0222d32daa..d0219aa63f9c4634fb54219fcfbe7afb10881d3b 100644
--- a/vivado.jou
+++ b/vivado.jou
@@ -3,23 +3,27 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Wed Feb 26 09:51:27 2025
-# Process ID: 9416
+# Start of session at: Wed Mar 5 14:07:44 2025
+# Process ID: 87819
# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
# Command line: vivado
# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.log
# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.jou
-# Running On :fl-tp-br-604
+# Running On :fl-tp-br-641
# Platform :Ubuntu
-# Operating System :Ubuntu 24.04.1 LTS
-# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4294.632 MHz
-# CPU Physical cores:6
-# CPU Logical cores :12
-# Host memory :16467 MB
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3456.621 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
# Swap memory :4294 MB
-# Total Virtual :20762 MB
-# Available Virtual :17504 MB
+# Total Virtual :20942 MB
+# Available Virtual :19630 MB
#-----------------------------------------------------------
start_gui
-source ./proj/create_project.tcl
+open_project /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.xpr
+update_compile_order -fileset sources_1
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+wait_on_run impl_1
+open_run impl_1
diff --git a/vivado.log b/vivado.log
index 51717703ce9b5140cf08917520a05d0005fae187..172ce418e80c0f47f178b78336d50697610b2572 100644
--- a/vivado.log
+++ b/vivado.log
@@ -3,95 +3,171 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Wed Feb 26 09:51:27 2025
-# Process ID: 9416
+# Start of session at: Wed Mar 5 14:07:44 2025
+# Process ID: 87819
# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
# Command line: vivado
# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.log
# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.jou
-# Running On :fl-tp-br-604
+# Running On :fl-tp-br-641
# Platform :Ubuntu
-# Operating System :Ubuntu 24.04.1 LTS
-# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency :4294.632 MHz
-# CPU Physical cores:6
-# CPU Logical cores :12
-# Host memory :16467 MB
+# Operating System :Ubuntu 24.04.2 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3456.621 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
# Swap memory :4294 MB
-# Total Virtual :20762 MB
-# Available Virtual :17504 MB
+# Total Virtual :20942 MB
+# Available Virtual :19630 MB
#-----------------------------------------------------------
start_gui
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
-WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
-source ./proj/create_project.tcl
-# if {[info exists ::create_path]} {
-# set dest_dir $::create_path
-# } else {
-# set dest_dir [pwd]
-# }
-# puts "INFO: Creating new project in $dest_dir"
-INFO: Creating new project in /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
-# set proj_name "AudioProc"
-# set origin_dir ".."
-# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
-# set src_dir $origin_dir/src
-# set repo_dir $origin_dir/repo
-# set part_num "xc7a200tsbg484-1"
-# create_project $proj_name $dest_dir
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa100_2ms:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa100_2ms/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa100_2ms:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa100_2ms/1.2/1.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa101_2ms:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa101_2ms/1.1/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa101_2ms:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa101_2ms/1.2/1.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admva600_dev:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admva600_dev/1.0/1.0/board.xml as part xcvc1902-vsva2197-1mp-i-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v1:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v1/1.2/1.2/board.xml as part xczu3eg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v2:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v2/1.1/1.1/board.xml as part xczu3eg-sbva484-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v2:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v2/1.2/1.2/board.xml as part xczu3eg-sbva484-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_7ev_cc:part0:1.5 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_7ev_cc/1.5/1.5/board.xml as part xczu7ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_eg_iocc_production:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_3eg_iocc/1.2/1.2/board.xml as part xczu3eg-sfva625-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_eg_pciecc_production:part0:1.3 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_3eg_pciecc/1.3/1.3/board.xml as part xczu3eg-sfva625-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:zuboard_1cg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/zub1cg/1.0/1.0/board.xml as part xczu1cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-25/E.0/1.0/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-25/1.1/1.1/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-50/B.0/1.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-50/1.1/1.1/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:cmod-s7-25:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/cmod-s7-25/B.0/1.0/board.xml as part xc7s25csga225-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys2/H/1.1/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-3eg/B.0/1.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-3eg/D.0/1.1/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_5ev:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-5ev/C.0/1.1/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4cg-4e002g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/2.4/board.xml as part xczu4cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4eg-4e002g-e008g-bid:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/2.C/board.xml as part xczu4eg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4ev-4e002g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4ev-4e002g-e008g-lia/1.0/2.8/board.xml as part xczu4ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c5ev-4e002g-e008g-bid:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/2.D/board.xml as part xczu5ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c5ev-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/2.5/board.xml as part xczu5ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7cg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/2.1/board.xml as part xczu7cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7cg-4e004g-e008g-liy:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/2.H/board.xml as part xczu7cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7ev-4e004g-e008g-lea:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lea/1.0/2.0/board.xml as part xczu7ev-fbvb900-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7ev-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/2.B/board.xml as part xczu7ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-11eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-11eg-4e004g-e008g-lia/1.0/1.2/board.xml as part xczu11eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-11eg-4e008g-e008g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/1.9/board.xml as part xczu11eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-17eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-17eg-4e004g-e008g-lia/1.0/1.1/board.xml as part xczu17eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bef:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/1.7/board.xml as part xczu19eg-ffvc1760-3-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-big:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/1.6/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bii:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/1.C/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bij:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/1.D/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-19eg-4e004g-e008g-lia/1.0/1.5/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lie:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/1.4/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lih:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/1.8/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e128g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/1.3/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e008g-bie:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/1.A/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e008g-bij:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/1.E/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e016g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/1.B/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-2cg1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-2cg1-4e002g-e008g-bee/1.0/2.2/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-3eg1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-3eg1-4e002g-e008g-bee/1.0/2.1/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-4ev1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-4ev1-4e002g-e008g-bee/1.0/2.0/board.xml as part xczu4ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-5ev1-4e002g-e008g-bed:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-5ev1-4e002g-e008g-bed/1.0/2.4/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-5ev1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-5ev1-4e002g-e008g-bee/1.0/2.3/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7cg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7CG/1.0/1.0/board.xml as part xczu7cg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7cg:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7CG/2.0/2.0/board.xml as part xczu7cg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7eg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EG/1.0/1.0/board.xml as part xczu7eg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7eg:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EG/2.0/2.0/board.xml as part xczu7eg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7ev:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EV/1.0/1.0/board.xml as part xczu7ev-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7ev:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EV/2.0/2.0/board.xml as part xczu7ev-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7305-s50:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7305-S50/1.0/1.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k160t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K160T/1.0/1.0/board.xml as part xc7k160tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k410t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K410T-3E/1.0/1.0/board.xml as part xc7k410tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k410t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K410T/1.0/1.0/board.xml as part xc7k410tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k70t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K70T/1.0/1.0/board.xml as part xc7k70tfbg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k160t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K160T-3E/1.0/1.0/board.xml as part xc7k160tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k160t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K160T/1.0/1.0/board.xml as part xc7k160tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k410t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K410T-3E/1.0/1.0/board.xml as part xc7k410tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k410t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K410T/1.0/1.0/board.xml as part xc7k410tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8305-au15p-1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8305-AU15P-1E/1.0/1.0/board.xml as part xcau15p-ffvb676-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8305-au15p-2e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8305-AU15P-2E/1.0/1.0/board.xml as part xcau15p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8310-au25p:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8310-AU25P/1.0/1.0/board.xml as part xcau25p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8320-au25p:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8320-AU25P/1.2/1.2/board.xml as part xcau25p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku060-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU060-3E/1.0/1.0/board.xml as part xcku060-ffva1517-3-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku060:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU060/1.0/1.0/board.xml as part xcku060-ffva1517-1-c specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku115:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU115/1.0/1.0/board.xml as part xcku115-flva1517-1-c specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8370-ku11p:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8370-KU11P/1.0/1.0/board.xml as part xcku11p-ffva1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:am0010_3eg_1i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/AM0010_3EG_1I/1.0/1.0/board.xml as part xczu3eg-sfvc784-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:am0010_4ev_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/AM0010_4EV_1E/1.0/1.0/board.xml as part xczu4ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_070_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_70_2C/1.0/1.0/board.xml as part xc7k70tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_070_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_70_2I/1.0/1.0/board.xml as part xc7k70tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2C/1.0/1.0/board.xml as part xc7k160tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2c:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2C/2.0/2.0/board.xml as part xc7k160tffg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2I/1.0/1.0/board.xml as part xc7k160tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_3e:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_3E/2.0/2.0/board.xml as part xc7k160tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_325_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_325_2C/1.0/1.0/board.xml as part xc7k325tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_325_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_325_2I/1.0/1.0/board.xml as part xc7k325tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_410_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_410_2C/1.0/1.0/board.xml as part xc7k410tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_410_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_410_2I/1.0/1.0/board.xml as part xc7k410tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0802_2cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0802_2CG_1E/1.0/1.0/board.xml as part xczu2cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0802_2cg_1e:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0802_2CG_1E/2.0/2.0/board.xml as part xczu2cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/1.0/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2cg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/2.0/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2eg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/1.0/board.xml as part xczu2eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2eg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/2.0/board.xml as part xczu2eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/1.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e:part0:5.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/5.0/5.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/2.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e_tebf0808:part0:6.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/6.0/6.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/1.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:3.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/3.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:5.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/5.0/5.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/2.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:4.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/4.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:6.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/6.0/6.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+INFO: [Common 17-14] Message 'Board 49-26' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+open_project /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.xpr
+WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'.
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.gen/sources_1'.
+Scanning sources...
+Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
-create_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 8079.234 ; gain = 197.969 ; free physical = 7226 ; free virtual = 15602
-# set proj_dir [get_property directory [current_project]]
-# set obj [get_projects $proj_name]
-# set_property "default_lib" "xil_defaultlib" $obj
-# set_property "part" "$part_num" $obj
-# set_property "simulator_language" "Mixed" $obj
-# set_property "target_language" "VHDL" $obj
-# if {[string equal [get_filesets -quiet sources_1] ""]} {
-# create_fileset -srcset sources_1
-# }
-# if {[string equal [get_filesets -quiet constrs_1] ""]} {
-# create_fileset -constrset constrs_1
-# }
-# set obj [get_filesets sources_1]
-# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
-# add_files -quiet $src_dir/hdl
-# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
-# add_files -fileset constrs_1 -quiet $src_dir/constraints
-# if {[string equal [get_runs -quiet synth_1] ""]} {
-# create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
-# } else {
-# set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
-# set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
-# }
-# set obj [get_runs synth_1]
-# set_property "part" "$part_num" $obj
-# set_property "steps.synth_design.args.fanout_limit" "400" $obj
-# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
-# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
-# set_property "steps.synth_design.args.resource_sharing" "off" $obj
-# set_property "steps.synth_design.args.no_lc" "1" $obj
-# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
-# current_run -synthesis [get_runs synth_1]
-# if {[string equal [get_runs -quiet impl_1] ""]} {
-# create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
-# } else {
-# set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
-# set_property flow "Vivado Implementation 2014" [get_runs impl_1]
-# }
-# set obj [get_runs impl_1]
-# set_property "part" "$part_num" $obj
-# set_property "steps.write_bitstream.args.bin_file" "1" $obj
-# current_run -implementation [get_runs impl_1]
-impl_1
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+update_compile_order -fileset sources_1
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+[Wed Mar 5 14:11:06 2025] Launched synth_1...
+Run output will be captured here: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/synth_1/runme.log
+[Wed Mar 5 14:11:06 2025] Launched impl_1...
+Run output will be captured here: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/proj/AudioProc.runs/impl_1/runme.log
+open_run impl_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 8392.973 ; gain = 0.000 ; free physical = 6687 ; free virtual = 16534
+INFO: [Netlist 29-17] Analyzing 92 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8459.723 ; gain = 0.000 ; free physical = 6599 ; free virtual = 16446
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+INFO: [Designutils 20-5722] Start Reading Physical Databases.
+Reading placement.
+Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15899
+Reading placer database...
+Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+Read PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+Reading routing.
+Read RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+Read Physdb Files: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+Restored from archive | CPU: 0.090000 secs | Memory: 1.395515 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.1 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9096.586 ; gain = 0.000 ; free physical = 6052 ; free virtual = 15900
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+open_run: Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 9252.500 ; gain = 1212.160 ; free physical = 5881 ; free virtual = 15766
exit
-INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 09:59:12 2025...
+INFO: [Common 17-206] Exiting Vivado at Wed Mar 5 14:22:25 2025...
diff --git a/vivado_9416.backup.jou b/vivado_9416.backup.jou
new file mode 100644
index 0000000000000000000000000000000000000000..4057a4e112e3be9afb44ac0de2f6df0222d32daa
--- /dev/null
+++ b/vivado_9416.backup.jou
@@ -0,0 +1,25 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 09:51:27 2025
+# Process ID: 9416
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
+# Command line: vivado
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.log
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4294.632 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :17504 MB
+#-----------------------------------------------------------
+start_gui
+source ./proj/create_project.tcl
diff --git a/vivado_9416.backup.log b/vivado_9416.backup.log
new file mode 100644
index 0000000000000000000000000000000000000000..51717703ce9b5140cf08917520a05d0005fae187
--- /dev/null
+++ b/vivado_9416.backup.log
@@ -0,0 +1,97 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 09:51:27 2025
+# Process ID: 9416
+# Current directory: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
+# Command line: vivado
+# Log file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.log
+# Journal file: /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso/vivado.jou
+# Running On :fl-tp-br-604
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4294.632 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :17504 MB
+#-----------------------------------------------------------
+start_gui
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+source ./proj/create_project.tcl
+# if {[info exists ::create_path]} {
+# set dest_dir $::create_path
+# } else {
+# set dest_dir [pwd]
+# }
+# puts "INFO: Creating new project in $dest_dir"
+INFO: Creating new project in /homes/c24masso/Bureau/tp-vhdl-mee/UE-medcon/tp-filtre-etudiant-c24masso
+# set proj_name "AudioProc"
+# set origin_dir ".."
+# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+# set src_dir $origin_dir/src
+# set repo_dir $origin_dir/repo
+# set part_num "xc7a200tsbg484-1"
+# create_project $proj_name $dest_dir
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+create_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 8079.234 ; gain = 197.969 ; free physical = 7226 ; free virtual = 15602
+# set proj_dir [get_property directory [current_project]]
+# set obj [get_projects $proj_name]
+# set_property "default_lib" "xil_defaultlib" $obj
+# set_property "part" "$part_num" $obj
+# set_property "simulator_language" "Mixed" $obj
+# set_property "target_language" "VHDL" $obj
+# if {[string equal [get_filesets -quiet sources_1] ""]} {
+# create_fileset -srcset sources_1
+# }
+# if {[string equal [get_filesets -quiet constrs_1] ""]} {
+# create_fileset -constrset constrs_1
+# }
+# set obj [get_filesets sources_1]
+# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
+# add_files -quiet $src_dir/hdl
+# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
+# add_files -fileset constrs_1 -quiet $src_dir/constraints
+# if {[string equal [get_runs -quiet synth_1] ""]} {
+# create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
+# } else {
+# set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
+# set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
+# }
+# set obj [get_runs synth_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.synth_design.args.fanout_limit" "400" $obj
+# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
+# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
+# set_property "steps.synth_design.args.resource_sharing" "off" $obj
+# set_property "steps.synth_design.args.no_lc" "1" $obj
+# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
+# current_run -synthesis [get_runs synth_1]
+# if {[string equal [get_runs -quiet impl_1] ""]} {
+# create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+# } else {
+# set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+# set_property flow "Vivado Implementation 2014" [get_runs impl_1]
+# }
+# set obj [get_runs impl_1]
+# set_property "part" "$part_num" $obj
+# set_property "steps.write_bitstream.args.bin_file" "1" $obj
+# current_run -implementation [get_runs impl_1]
+impl_1
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 09:59:12 2025...