Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
T
tp-ecg-etudiant-d24spera
Manage
Activity
Members
Labels
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Environments
Terraform modules
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
tp-vhdl-mee
MEDCON
gr-vhdl-d24spera
tp-ecg-etudiant-d24spera
Commits
11e322e6
Commit
11e322e6
authored
1 month ago
by
Davi SPERANDIO AGATTI
Browse files
Options
Downloads
Patches
Plain Diff
first commit
parent
f0e49b50
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
src/hdl/operativeUnit.vhd
+2
-0
2 additions, 0 deletions
src/hdl/operativeUnit.vhd
with
2 additions
and
0 deletions
src/hdl/operativeUnit.vhd
+
2
−
0
View file @
11e322e6
...
...
@@ -50,6 +50,8 @@ end entity operativeUnit;
architecture
arch_operativeUnit
of
operativeUnit
is
qsdqsd
type
registerFile
is
array
(
0
to
94
)
of
signed
(
10
downto
0
);
type
registerCoefFile
is
array
(
0
to
47
)
of
signed
(
11
downto
0
);
-- 1 bit signal 1 bit integer 10 bit floating point representation
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment