diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 9fd1a5704c26b0ec114bc055a9942da9170523de..c58284018ac3cd0b334f4c7d70c7912873984181 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -105,9 +105,6 @@ begin
         else
             SR_futurState <= PROCESSING_LOOP_FIR_2;
         end if;
-        
---      when OUTPUT =>
---            SR_futurState <= WAIT_END_SAMPLE;
 
       when WAIT_END_SAMPLE =>
         if I_inputSampleValid = '0' then
@@ -146,13 +143,11 @@ begin
   
   O_initSum             <= '1' when (SR_presentState = STORE) else
                             I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_1) else
---                            I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
                             I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else 
                             I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
   
   
   O_loadSum             <= not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_1) else
---                           not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
                            '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
                            not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
                            '1' when (SR_presentState = PROCESSING_LOOP_FIR_2) else 
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 4300ffff4e72e5081069a4dfc3bf90af6d6668f5..77cf371e6a1ee1128fbd6d08474595f6e759d01a 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -51,8 +51,20 @@ end entity operativeUnit;
 
 architecture arch_operativeUnit of operativeUnit is
   
-  type registerFile         is array(0 to 94) of signed(10 downto 0);
-  type registerCoefFile     is array(0 to 47) of signed(11 downto 0); -- 1 bit signal 1 bit integer 10 bit floating point representation
+  constant integerRepresSamples : integer  := 10;
+  constant floatRepresSamples   : integer  := 10;
+  constant nBitSamples          : integer  := integerRepresSamples + floatRepresSamples + 1; -- Adding the bit of the signal
+  
+
+  constant integerRepresCoef    : integer  := 1;
+  constant floatRepresCoef      : integer  := 10;
+  constant nBitCoef             : integer  := floatRepresCoef + integerRepresCoef + 1; --Adding the bit of the signal
+
+  constant floatRepresTotal     : integer  := floatRepresSamples + floatRepresCoef;
+  
+  
+  type registerFile         is array(0 to 94) of signed((nBitSamples - 1) downto 0);
+  type registerCoefFile     is array(0 to 47) of signed((nBitCoef - 1) downto 0); -- 1 bit signal 1 bit integer 10 bit floating point representation
   
 
   signal SR_shiftRegister_FIR_1     : registerFile;  -- shift register file used to store and shift input samples
@@ -138,24 +150,21 @@ architecture arch_operativeUnit of operativeUnit is
                             );
 
   signal S_maxAddress       : integer := 47;
-  signal S_lastAdress       : integer := 94;
+  signal S_lastAdress       : integer := 94;     -- 2^6 < 94 < 2^7
 
 
-  signal SC_sample          : signed(10 downto 0);
-  signal SC_SymmetricSample : signed(10 downto 0);
-  signal SC_opSymmetric     : signed(11 downto 0);
+  signal SC_sample          : signed((nBitSamples - 1) downto 0);  
+  signal SC_SymmetricSample : signed((nBitSamples - 1)  downto 0);
+  signal SC_opSymmetric     : signed(nBitSamples  downto 0);    -- (nBitSamples - 1) + 1
   
-  signal SC_multOperand1    : signed(11 downto 0);
-  signal SC_multOperand2    : signed(11 downto 0);
-  signal SC_MultResult      : signed(23 downto 0);  -- Result of the multiplication Xi*Hi
-  signal SC_addResult       : signed(30 downto 0);  -- result of the accumulation addition
-  signal SR_sum             : signed(30 downto 0);  -- Accumulation register
-  signal SR_Y               : signed(10 downto 0);  -- filtered sample storage register
+  signal SC_multOperand1    : signed(nBitSamples downto 0);    -- (nBitSamples - 1) + 1
+  signal SC_multOperand2    : signed((nBitCoef - 1) downto 0);  
+  signal SC_MultResult      : signed((nBitSamples + nBitCoef) downto 0);  -- Result of the multiplication Xi*Hi
+  signal SC_addResult       : signed((nBitSamples + nBitCoef + 7) downto 0);  -- result of the accumulation addition, adding 7 bits
+  signal SR_sum             : signed((nBitSamples + nBitCoef + 7) downto 0);  -- Accumulation register
+  signal SR_Y               : signed(integerRepresSamples downto 0);  -- filtered sample storage register
   signal SR_readAddrReg     : integer range 0 to 94;  -- register files read address
   signal SR_readAddrReg2    : integer range 0 to 94;  -- register files read address
---  signal SR_readAddrCoef    : integer range 0 to 47;  -- register files read address
-
-
 
 begin
 
@@ -163,10 +172,9 @@ begin
   begin  -- process shift
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_shiftRegister_FIR_1 <= (others => (others => '0'));
-    elsif rising_edge(I_clock) then     -- rising edge clock
+    elsif rising_edge(I_clock) then     -- rising edge clock     
         if(I_loadShift = '1') then
-            --SR_shiftRegister_FIR_1(SR_readAddrReg) <= signed(I_inputSample);
-            SR_shiftRegister_FIR_1(0) <= signed(I_inputSample);
+            SR_shiftRegister_FIR_1(0) <= signed(I_inputSample&"0000000000");  -- It need to adapt the amount of zeroes according to <floatRepresSamples> 
             SR_shiftRegister_FIR_1(1 to 94) <= SR_shiftRegister_FIR_1(0 to 93);
         end if;
     end if;
@@ -176,22 +184,12 @@ begin
   begin
     if I_reset = '1' then               -- asynchronous reset (active high)
       SR_readAddrReg <= 0;
---      SR_readAddrCoef <= 0;
     elsif rising_edge(I_clock) then     -- rising edge clock
         if(I_initAddress = '1') then
             SR_readAddrReg <= 0;
---            SR_readAddrCoef <= 0;
         elsif (I_incrAddress = '1' and SR_readAddrReg < S_maxAddress) then
             SR_readAddrReg <= SR_readAddrReg + 1;
---            if (I_SelFilter = "00" or I_SelFilter = "11") then
---                if SR_readAddrReg >= ((S_maxAddress + 1)/2) then
---                    SR_readAddrCoef <= SR_readAddrCoef - 1;
---                else
---                    SR_readAddrCoef <= SR_readAddrCoef + 1;
---                end if;
---            else
---                SR_readAddrCoef <= SR_readAddrCoef + 1;
---            end if;
+
         end if;
     end if;
   end process incr_address;
@@ -212,7 +210,7 @@ begin
             S_lastAdress    <= 1;
 
         when "11" =>
-            SR_opRegister   <= SR_shiftRegister_IIR_FF;
+            SR_opRegister   <= SR_shiftRegister_IIR_FB;
             SR_opCoef       <= SR_coefRegister_FIR_2;
             S_maxAddress    <= 5;
             S_lastAdress    <= 10;
@@ -282,29 +280,29 @@ end process select_sample_operator;
             case I_SelFilter is
                 
                 when "00" =>
-                    SR_shiftRegister_IIR_FF(1 to 2) <= SR_shiftRegister_IIR_FF(0 to 1);
-                    if (SR_sum(9) = '1') then     -- Treating the truncation
-                        SR_shiftRegister_IIR_FF(0) <= SR_sum(20 downto 10) + 1;
+                    SR_shiftRegister_IIR_FF(1 to 94) <= SR_shiftRegister_IIR_FF(0 to 93);
+                    if (SC_addResult(floatRepresCoef - 1) = '1') then     -- Treating the truncation
+                        SR_shiftRegister_IIR_FF(0) <= SC_addResult((nBitSamples + floatRepresCoef - 1) downto floatRepresCoef) + 1;
                     else
-                        SR_shiftRegister_IIR_FF(0) <= SR_sum(20 downto 10);
+                        SR_shiftRegister_IIR_FF(0) <= SC_addResult((nBitSamples + floatRepresCoef - 1) downto floatRepresCoef);
                     end if;
     
                 when "01" =>
                         null;
                         
                 when "10" =>
-                    SR_shiftRegister_IIR_FB(1 to 2) <= SR_shiftRegister_IIR_FB(0 to 1);
-                    if (SR_sum(9) = '1') then     -- Treating the truncation
-                        SR_shiftRegister_IIR_FB(0) <= SR_sum(20 downto 10) + 1;
+                    SR_shiftRegister_IIR_FB(1 to 94) <= SR_shiftRegister_IIR_FB(0 to 93);
+                    if (SC_addResult(floatRepresCoef - 1) = '1') then     -- Treating the truncation
+                        SR_shiftRegister_IIR_FB(0) <= SC_addResult((nBitSamples + floatRepresCoef - 1) downto floatRepresCoef) + 1;
                     else
-                        SR_shiftRegister_IIR_FB(0) <= SR_sum(20 downto 10);
+                        SR_shiftRegister_IIR_FB(0) <= SC_addResult((nBitSamples + floatRepresCoef - 1) downto floatRepresCoef);
                     end if;
     
                 when others =>
-                    if (SR_sum(9) = '1') then     -- Treating the truncation
-                        SR_Y <= SR_sum(20 downto 10) + 1;
+                    if (SC_addResult(floatRepresTotal - 1) = '1') then     -- Treating the truncation
+                        SR_Y <= SC_addResult((floatRepresTotal + integerRepresSamples) downto floatRepresTotal) + 1;
                     else
-                        SR_Y <= SR_sum(20 downto 10);
+                        SR_Y <= SC_addResult((floatRepresTotal + integerRepresSamples) downto floatRepresTotal);
                     end if;
             end case;
         end if;   
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index c6974a53183a85091461c3afe850e630f9eee9ac..7fe4decf88dd225d68c4c1c7e227a5ca50219735 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -52,12 +52,12 @@ begin
   SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
 
   -- Sample period = 20 clk period
-  SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
+  SC_inputSampleValid <=  not SC_inputSampleValid after 100 ns;
 
   -- Null signal followed by a Dirac and then an arbitrary sequence
   SC_inputSample <= "00000000000",
-                    "01111111111" after 51 ns,
-                    "00000000000" after 251 ns;
+                    "01111111111" after 50 ns,
+                    "00000000000" after 3500 ns;