From 7fd8d6efab82b30117f1b1b9e4cf20e453bb1f2a Mon Sep 17 00:00:00 2001
From: Davi SPERANDIO AGATTI <d24spera@fl-tp-br-632.imta.fr>
Date: Thu, 20 Mar 2025 18:05:29 +0100
Subject: [PATCH] advancing in optimisation
---
src/hdl/controlUnit.vhd | 9 +++-
src/hdl/firUnit.vhd | 5 +++
src/hdl/operativeUnit.vhd | 89 ++++++++++++++++++++++++++-------------
3 files changed, 73 insertions(+), 30 deletions(-)
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 38a4ac2..9fd1a57 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -32,6 +32,7 @@ entity controlUnit is
I_processingDone : in std_logic;
O_loadShift : out std_logic; -- filtered sample
O_SelFilter : out std_logic_vector(1 downto 0);
+ O_symmetric : out std_logic;
O_initAddress : out std_logic; -- Control signal to initialize register read address
O_incrAddress : out std_logic; -- Control signal to increment register read address
O_initSum : out std_logic; -- Control signal to initialize the MAC register
@@ -128,6 +129,11 @@ begin
"10" when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
"11" when (SR_presentState = PROCESSING_LOOP_FIR_2) else "00";
+ O_symmetric <= '1' when (SR_presentState = PROCESSING_LOOP_FIR_1) else
+ '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
+ '1' when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
+
+
O_initAddress <= '1' when (SR_presentState = STORE) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_1) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
@@ -146,7 +152,8 @@ begin
O_loadSum <= not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_1) else
- not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
+-- not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
+ '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
'1' when (SR_presentState = PROCESSING_LOOP_FIR_2) else
not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 0b0b1c9..35881b8 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -46,6 +46,7 @@ architecture archi_firUnit of firUnit is
I_processingDone : in std_logic;
O_loadShift : out std_logic;
O_SelFilter : out std_logic_vector(1 downto 0);
+ O_symmetric : out std_logic;
O_initAddress : out std_logic;
O_incrAddress : out std_logic;
O_initSum : out std_logic;
@@ -61,6 +62,7 @@ architecture archi_firUnit of firUnit is
I_inputSample : in std_logic_vector(10 downto 0);
I_loadShift : in std_logic;
I_SelFilter : in std_logic_vector(1 downto 0);
+ I_symmetric : in std_logic;
I_initAddress : in std_logic;
I_incrAddress : in std_logic;
I_initSum : in std_logic;
@@ -73,6 +75,7 @@ architecture archi_firUnit of firUnit is
signal SC_processingDone : std_logic;
signal SC_loadShift : std_logic;
signal SC_SelFilter : std_logic_vector(1 downto 0);
+ signal SC_symmetric : std_logic;
signal SC_initAddress : std_logic;
signal SC_incrAddress : std_logic;
signal SC_initSum : std_logic;
@@ -88,6 +91,7 @@ begin
I_inputSampleValid => I_inputSampleValid,
I_processingDone => SC_processingDone,
O_SelFilter => SC_SelFilter,
+ O_symmetric => SC_symmetric,
O_loadShift => SC_loadShift,
O_initAddress => SC_initAddress,
O_incrAddress => SC_incrAddress,
@@ -103,6 +107,7 @@ begin
I_inputSample => I_inputSample,
I_loadShift => SC_loadShift,
I_SelFilter => SC_SelFilter,
+ I_symmetric => SC_symmetric,
I_initAddress => SC_initAddress,
I_incrAddress => SC_incrAddress,
I_initSum => SC_initSum,
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index fded6d8..4300fff 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -37,6 +37,7 @@ entity operativeUnit is
I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
I_loadShift : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
I_SelFilter : in std_logic_vector(1 downto 0);
+ I_symmetric : in std_logic;
I_initAddress : in std_logic; -- Control signal to initialize register read address
I_incrAddress : in std_logic; -- Control signal to increment register read address
I_initSum : in std_logic; -- Control signal to initialize the MAC register
@@ -50,8 +51,6 @@ end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
- qsdqsd
-
type registerFile is array(0 to 94) of signed(10 downto 0);
type registerCoefFile is array(0 to 47) of signed(11 downto 0); -- 1 bit signal 1 bit integer 10 bit floating point representation
@@ -138,17 +137,23 @@ architecture arch_operativeUnit of operativeUnit is
others => to_signed( 0,12)
);
- signal S_maxAddress : integer := 94;
+ signal S_maxAddress : integer := 47;
+ signal S_lastAdress : integer := 94;
- signal SC_multOperand1 : signed(10 downto 0);
- signal SC_multOperand2 : signed(11 downto 0);
- signal SC_MultResult : signed(22 downto 0); -- Result of the multiplication Xi*Hi
- signal SC_addResult : signed(29 downto 0); -- result of the accumulation addition
- signal SR_sum : signed(29 downto 0); -- Accumulation register
- signal SR_Y : signed(10 downto 0); -- filtered sample storage register
- signal SR_readAddrReg : integer range 0 to 94; -- register files read address
- signal SR_readAddrCoef : integer range 0 to 47; -- register files read address
+ signal SC_sample : signed(10 downto 0);
+ signal SC_SymmetricSample : signed(10 downto 0);
+ signal SC_opSymmetric : signed(11 downto 0);
+
+ signal SC_multOperand1 : signed(11 downto 0);
+ signal SC_multOperand2 : signed(11 downto 0);
+ signal SC_MultResult : signed(23 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(30 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(30 downto 0); -- Accumulation register
+ signal SR_Y : signed(10 downto 0); -- filtered sample storage register
+ signal SR_readAddrReg : integer range 0 to 94; -- register files read address
+ signal SR_readAddrReg2 : integer range 0 to 94; -- register files read address
+-- signal SR_readAddrCoef : integer range 0 to 47; -- register files read address
@@ -171,22 +176,22 @@ begin
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddrReg <= 0;
- SR_readAddrCoef <= 0;
+-- SR_readAddrCoef <= 0;
elsif rising_edge(I_clock) then -- rising edge clock
if(I_initAddress = '1') then
SR_readAddrReg <= 0;
- SR_readAddrCoef <= 0;
+-- SR_readAddrCoef <= 0;
elsif (I_incrAddress = '1' and SR_readAddrReg < S_maxAddress) then
SR_readAddrReg <= SR_readAddrReg + 1;
- if (I_SelFilter = "00" or I_SelFilter = "11") then
- if SR_readAddrReg >= ((S_maxAddress + 1)/2) then
- SR_readAddrCoef <= SR_readAddrCoef - 1;
- else
- SR_readAddrCoef <= SR_readAddrCoef + 1;
- end if;
- else
- SR_readAddrCoef <= SR_readAddrCoef + 1;
- end if;
+-- if (I_SelFilter = "00" or I_SelFilter = "11") then
+-- if SR_readAddrReg >= ((S_maxAddress + 1)/2) then
+-- SR_readAddrCoef <= SR_readAddrCoef - 1;
+-- else
+-- SR_readAddrCoef <= SR_readAddrCoef + 1;
+-- end if;
+-- else
+-- SR_readAddrCoef <= SR_readAddrCoef + 1;
+-- end if;
end if;
end if;
end process incr_address;
@@ -195,34 +200,60 @@ select_filter : process(I_SelFilter, SR_shiftRegister_FIR_1, SR_shiftRegister_II
begin
case I_SelFilter is
when "01" =>
- SR_opRegister <= SR_shiftRegister_IIR_FF;
+ SR_opRegister <= SR_shiftRegister_IIR_FF;
SR_opCoef <= SR_coefRegister_IIR_FF;
- S_maxAddress <= 2;
+ S_maxAddress <= 1;
+ S_lastAdress <= 2;
when "10" =>
SR_opRegister <= SR_shiftRegister_IIR_FB;
SR_opCoef <= SR_coefRegister_IIR_FB;
S_maxAddress <= 1;
+ S_lastAdress <= 1;
when "11" =>
SR_opRegister <= SR_shiftRegister_IIR_FF;
SR_opCoef <= SR_coefRegister_FIR_2;
- S_maxAddress <= 10;
+ S_maxAddress <= 5;
+ S_lastAdress <= 10;
when others =>
SR_opRegister <= SR_shiftRegister_FIR_1;
SR_opCoef <= SR_coefRegister_FIR_1;
- S_maxAddress <= 94;
+ S_maxAddress <= 47;
+ S_lastAdress <= 94;
end case;
end process select_filter;
+ SC_sample <= SR_opRegister(SR_readAddrReg);
+ SR_readAddrReg2 <= S_lastAdress - SR_readAddrReg;
+ SC_SymmetricSample <= SR_opRegister(SR_readAddrReg2);
+
+
+select_sample_operator : process(I_symmetric, SC_SymmetricSample, SC_sample) is
+begin
+
+ if I_symmetric = '1' then
+ if (SR_readAddrReg = S_maxAddress) then
+ SC_opSymmetric <= resize(SC_sample, SC_opSymmetric'length);
+ else
+ SC_opSymmetric <= resize(SC_sample, SC_opSymmetric'length) + SC_SymmetricSample;
+ end if;
+ else
+ SC_opSymmetric <= resize(SC_sample, SC_opSymmetric'length);
+ end if;
+
+end process select_sample_operator;
+
+
+
O_processingDone <= '1' when (SR_readAddrReg = S_maxAddress) else '0';
- SC_multOperand1 <= SR_opRegister(SR_readAddrReg) ; -- 8 bits
- SC_multOperand2 <= SR_opCoef(SR_readAddrCoef) ; -- 8 bits
- SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 16 bits
+ SC_multOperand1 <= SC_opSymmetric ; -- 8 bits
+ SC_multOperand2 <= SR_opCoef(SR_readAddrReg) ; -- 8 bits
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2; -- 16 bits
SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
sum_acc : process (I_reset, I_clock) is
--
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