From 8de2873b20a4290338b5ee0c7e6817b0aa712c02 Mon Sep 17 00:00:00 2001
From: Davi SPERANDIO AGATTI <d24spera@fl-tp-br-632.imta.fr>
Date: Wed, 19 Mar 2025 14:01:53 +0100
Subject: [PATCH] ajustes 19 mars
---
src-ref/octaveScript.m | 29 ++++++++++-------------------
src-ref/testbench.m | 13 ++++++-------
src/hdl/controlUnit.vhd | 8 +++++---
src/hdl/firUnit.vhd | 8 ++++----
src/hdl/operativeUnit.vhd | 10 ++++++----
src/hdl/tb_firUnit.vhd | 8 ++++----
6 files changed, 35 insertions(+), 41 deletions(-)
diff --git a/src-ref/octaveScript.m b/src-ref/octaveScript.m
index 745948a..d0d714f 100644
--- a/src-ref/octaveScript.m
+++ b/src-ref/octaveScript.m
@@ -23,9 +23,9 @@ subplot(2,3,3);plot(y_minus_BL(1:1000));title('Baseline wander reduced -- zoomed
%elimination du bruit à 50Hz par un coupe-bande tout basique
-f50Hz=fir1(100, [45 55]/Fn, 'stop');
-y_minus_50Hz_simple = filter(f50Hz,[1],y_minus_BL);
-subplot(2,3,4);plot(y_minus_50Hz_simple(1:1000));title('FIR1 band-cut-- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
+%f50Hz=fir1(100, [45 55]/Fn, 'stop');
+%y_minus_50Hz_simple = filter(f50Hz,[1],y_minus_BL);
+%subplot(2,3,4);plot(y_minus_50Hz_simple(1:1000));title('FIR1 band-cut-- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
%elimination du bruit à 50Hz par un coupe-bande plus elabore
[b,a]=pei_tseng_notch ( 50 / Fn, 10/Fn );
@@ -38,22 +38,13 @@ Fstop = 60;
F = [0 Fpass Fstop Fn]/(Fn);
A = [1 1 0 0];
fLP = remez(10,F,A); % Voir pour Matlab: firpm
-yLP = filter(fLP,[1],y_minus_50Hz_simple);
-
-yLP_2 = filter(fLP,[1],y_minus_50Hz_pei_tseng);
-
-subplot(2,3,6);plot(yLP(1:1000));title('Low-pass filter to suppress high-freq noise -- zoomed');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
-figure(2)
-subplot(2,1,1);plot(T(:,2));title('Raw ECG signal');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
-subplot(2,1,2);
-hold on;
-plot(yLP);
-plot(yLP_2);
-legend("BandPass", "Notch");
-hold off;
-title('After 3 filters');xlabel('Samples (Fs=500Hz)');ylabel('Magnitude (digital signal)');
-print(2, "ECG_raw_3filters.pdf", "-dpdflatexstandalone");
-figure(3)
+
+yLP = filter(fLP,[1],y_minus_50Hz_pei_tseng);
+
+disp(yLP(1:50))
+
+%print(2, "ECG_raw_3filters.pdf", "-dpdflatexstandalone");
+%figure(3)
diff --git a/src-ref/testbench.m b/src-ref/testbench.m
index 77b1ed4..836bb3d 100644
--- a/src-ref/testbench.m
+++ b/src-ref/testbench.m
@@ -6,7 +6,6 @@
Fs = 500; % Frequence d'echantillonnage
Fn = Fs/2; % Frequence de Nyquist
-
% a primeira impressao precisariamos de 18 bits, mas como a entrada é discretizada em 11 bits
% precisaremos de 10/11 bits para codificar os coeficientes
@@ -16,7 +15,7 @@ pkg load signal;
%Pour les trois filtres suivants, on peut jouer sur les ordres
% donc le nombre de coefficients des filtres numeriques
-t = 0:0.02:1;
+t = 0:0.02:0.2;
x = zeros(length(t));
x(2) = 2^10;
@@ -29,9 +28,9 @@ x(2) = 2^10;
%PRIMEIRO FILTRO PRECISA SER PROFUNDO
fBaseLine=fir1(128, 5/Fn, 'high');
-fBaseLine = round(fBaseLine*2^10) %REQUANTIZACAO DOS COEFICIENTES
+fBaseLine = round(fBaseLine*2^10); %REQUANTIZACAO DOS COEFICIENTES
-fBaseLine = fBaseLine(18:112)
+fBaseLine = fBaseLine(18:112);
disp("Coeficientes 1 filtro");
for i =1:1:length(fBaseLine)
@@ -40,7 +39,7 @@ for i =1:1:length(fBaseLine)
end
-y_minus_BL= filter(fBaseLine,[1], x)/2^10
+y_minus_BL= filter(fBaseLine,[1], x)/2^10;
%elimination du bruit à 50Hz par un coupe-bande plus elabore
@@ -53,7 +52,7 @@ disp("Coeficientes 2 filtro");
round(b*2^10)
round(a*2^10)
-y_minus_50Hz_pei_tseng = filter(b,a,y_minus_BL);
+y_minus_50Hz_pei_tseng = round(filter(b*2^10, a*2^10, y_minus_BL))/2^10;
%lissage du bruit haute frequence par filtre de Parks-McClellan
@@ -71,7 +70,7 @@ for i =1:1:length(fLP)
round(fLP(i)*2^10)
end
-yLP = filter(fLP,[1],y_minus_50Hz_pei_tseng);
+yLP = round(filter(fLP*2^10,[1],y_minus_50Hz_pei_tseng))/2^10;
disp("Input Signal")
x
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 9090b9b..7ef817c 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -131,7 +131,7 @@ begin
O_initAddress <= '1' when (SR_presentState = STORE) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_1) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
- '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else '0';
+ I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else '0';
O_incrAddress <= not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_1) else
not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
@@ -141,13 +141,15 @@ begin
O_initSum <= '1' when (SR_presentState = STORE) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_1) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
- '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else '0';
+ '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
+ I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
O_loadSum <= not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_1) else
not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
- '1' when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
+ '1' when (SR_presentState = PROCESSING_LOOP_FIR_2) else
+ not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
O_loadY <= I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_1) else
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
index 158ab49..0b0b1c9 100644
--- a/src/hdl/firUnit.vhd
+++ b/src/hdl/firUnit.vhd
@@ -28,9 +28,9 @@ entity firUnit is
port (
I_clock : in std_logic; -- global clock
I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
+ O_filteredSample : out std_logic_vector(10 downto 0); -- filtered sample
O_filteredSampleValid : out std_logic
);
@@ -58,7 +58,7 @@ architecture archi_firUnit of firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSample : in std_logic_vector(10 downto 0);
I_loadShift : in std_logic;
I_SelFilter : in std_logic_vector(1 downto 0);
I_initAddress : in std_logic;
@@ -67,7 +67,7 @@ architecture archi_firUnit of firUnit is
I_loadSum : in std_logic;
I_loadY : in std_logic;
O_processingDone : out std_logic;
- O_Y : out std_logic_vector(7 downto 0));
+ O_Y : out std_logic_vector(10 downto 0));
end component operativeUnit;
signal SC_processingDone : std_logic;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 8f368bf..c41b2fb 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -51,7 +51,7 @@ end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
type registerFile is array(0 to 94) of signed(10 downto 0);
- type registerCoefFile is array(0 to 48) of signed(11 downto 0); -- 1 bit signal 1 bit integer 10 bit floating point representation
+ type registerCoefFile is array(0 to 47) of signed(11 downto 0); -- 1 bit signal 1 bit integer 10 bit floating point representation
signal SR_shiftRegister_FIR_1 : registerFile; -- shift register file used to store and shift input samples
@@ -169,13 +169,15 @@ begin
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddrReg <= 0;
+ SR_readAddrCoef <= 0;
elsif rising_edge(I_clock) then -- rising edge clock
if(I_initAddress = '1') then
SR_readAddrReg <= 0;
+ SR_readAddrCoef <= 0;
elsif (I_incrAddress = '1' and SR_readAddrReg < S_maxAddress) then
SR_readAddrReg <= SR_readAddrReg + 1;
- if I_SelFilter = "00" or I_SelFilter = "11" then
- if SR_readAddrReg > ((S_maxAddress + 1)/2) then
+ if (I_SelFilter = "00" or I_SelFilter = "11") then
+ if SR_readAddrReg >= ((S_maxAddress + 1)/2) then
SR_readAddrCoef <= SR_readAddrCoef - 1;
else
SR_readAddrCoef <= SR_readAddrCoef + 1;
@@ -200,7 +202,7 @@ begin
SR_opCoef <= SR_coefRegister_IIR_FB;
S_maxAddress <= 1;
- when "01" =>
+ when "11" =>
SR_opRegister <= SR_shiftRegister_IIR_FF;
SR_opCoef <= SR_coefRegister_FIR_2;
S_maxAddress <= 10;
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index 4364ca0..1ed86e3 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -33,17 +33,17 @@ architecture archi_tb_firUnit of tb_firUnit is
port (
I_clock : in std_logic;
I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSample : in std_logic_vector(10 downto 0);
I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0);
+ O_filteredSample : out std_logic_vector(10 downto 0);
O_filteredSampleValid : out std_logic);
end component firUnit;
signal SC_clock : std_logic := '0';
signal SC_reset : std_logic;
- signal SC_inputSample : std_logic_vector(7 downto 0);
+ signal SC_inputSample : std_logic_vector(10 downto 0);
signal SC_inputSampleValid : std_logic:='0';
- signal SC_filteredSample : std_logic_vector(7 downto 0);
+ signal SC_filteredSample : std_logic_vector(10 downto 0);
signal SC_filteredSampleValid : std_logic;
begin
--
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