From f0e49b50c7c812ad0f993b04bf3f6cca8b097b5b Mon Sep 17 00:00:00 2001
From: Davi SPERANDIO AGATTI <d24spera@fl-tp-br-632.imta.fr>
Date: Thu, 20 Mar 2025 16:35:52 +0100
Subject: [PATCH] i guess it works
---
src/hdl/controlUnit.vhd | 6 +++---
src/hdl/tb_firUnit.vhd | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 7ef817c..38a4ac2 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -140,9 +140,9 @@ begin
O_initSum <= '1' when (SR_presentState = STORE) else
I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_1) else
- I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
- '1' when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
- I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
+-- I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDFORWARD) else
+ I_processingDone when (SR_presentState = PROCESSING_LOOP_IIR_FEEDBACK) else
+ I_processingDone when (SR_presentState = PROCESSING_LOOP_FIR_2) else '0';
O_loadSum <= not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_FIR_1) else
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index 1ed86e3..c6974a5 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -56,8 +56,8 @@ begin
-- Null signal followed by a Dirac and then an arbitrary sequence
SC_inputSample <= "00000000000",
- "01111111111" after 401 ns,
- "00000000000" after 601 ns;
+ "01111111111" after 51 ns,
+ "00000000000" after 251 ns;
--
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