From 3b40b54fd92dd8fcc3d6faf33315130548dc515d Mon Sep 17 00:00:00 2001
From: Davi SPERANDIO AGATTI <d24spera@fl-tp-br-632.imta.fr>
Date: Tue, 25 Mar 2025 12:11:00 +0100
Subject: [PATCH] one last push
---
octave/script_ielec.m | 15 ++---
src/hdl/operativeUnit.vhd | 119 +++++++++++++++++---------------------
src/hdl/tb_firUnit.vhd | 2 +-
3 files changed, 63 insertions(+), 73 deletions(-)
diff --git a/octave/script_ielec.m b/octave/script_ielec.m
index 2e28be6..6d28ecf 100644
--- a/octave/script_ielec.m
+++ b/octave/script_ielec.m
@@ -1,5 +1,5 @@
% Parâmetros do filtro
-fc = 1000; % Frequência de corte (Hz) ###TROCAR PARA 1K
+fc = 800; % Frequência de corte (Hz) ###TROCAR PARA 1K
fs = 44100; % Frequência de amostragem (Hz)
n = 3; % Ordem do filtro
@@ -87,13 +87,14 @@ x_padded = [x_rounded(1:50), zeros(1,10)];
% Aplicar o filtro IIR com a função filter()
y = filter(b, a, x_rounded);
-disp('50 primeiros valores do sinal filtrado sem arredondar:');
-disp(y(1:50));
+%disp('50 primeiros valores do sinal filtrado sem arredondar:');
+%disp(y(1:50));
+p2=10;
-y = filter(round(b*2^7), round(a*2^7), x_rounded);
+y = filter(round(b*2^p2), round(a*2^p2), x_rounded);
-y_padded = filter(round(b*2^7), round(a*2^7), x_padded);
+y_padded = filter(round(b*2^p2), round(a*2^p2), x_padded);
y_rounded = round(y);
y_padded = round(y_padded);
@@ -120,11 +121,11 @@ disp(y_padded);
disp("Rounded B")
b
-round(b*2^7)
+round(b*2^p2)
disp("Rounded -A")
a
--round(a*2^7)
+-round(a*2^p2)
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index c96827b..168ef15 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -49,11 +49,22 @@ entity operativeUnit is
end entity operativeUnit;
architecture arch_operativeUnit of operativeUnit is
+
+
+ constant integerRepresSamples : integer := 7;
+ constant floatRepresSamples : integer := 10;
+ constant nBitSamples : integer := integerRepresSamples + floatRepresSamples + 1;
+
+
+ constant integerRepresCoef : integer := 2;
+ constant floatRepresCoef : integer := 10;
+ constant nBitCoef : integer := floatRepresCoef + integerRepresCoef + 1;
+
+ constant floatRepresTotal : integer := floatRepresSamples + floatRepresCoef;
- constant floatRepresentation : integer := 10;
- type registerFile is array(0 to 3) of signed(7 downto 0);
- type registerCoefFile is array(0 to 3) of signed((floatRepresentation - 1) downto 0); -- 1 bit of signal, 2 bit for the integer, 7 bits for floating point
+ type registerFile is array(0 to 3) of signed((nBitSamples - 1) downto 0);
+ type registerCoefFile is array(0 to 3) of signed((nBitCoef - 1) downto 0); -- 1 bit of signal, 2 bit for the integer, 7 bits for floating point
signal SR_shiftRegisterSamples : registerFile; -- shift register file used to store and shift input samples
signal SR_shiftOutputRegister : registerFile; -- shift register file used to store and shift past output values
@@ -62,73 +73,53 @@ architecture arch_operativeUnit of operativeUnit is
signal SR_opCoef : registerCoefFile;
-
-
--- Low-pass filter with Fc = 1kHz provided with octave command
--- [b, a] = butter(3, 5000 / (44100/2), 'low')
- constant SR_coefRegister_B_low : registerCoefFile :=
- (to_signed( 3, floatRepresentation), -- x[n]
- to_signed( 10, floatRepresentation), -- x[n-1]
- to_signed( 10, floatRepresentation), -- x[n-2]
- to_signed( 3, floatRepresentation) -- x[n-3]
- );
--- High-pass filter with Fc = 1kHz provided with octave command
--- [b, a] = butter(3, 8000 / (44100/2), 'high')
+-- High-pass filter with Fc = 800Hz provided with octave command
+-- [b, a] = butter(3, 800 / (44100/2), 'high')
constant SR_coefRegister_B_high : registerCoefFile :=
- (to_signed( 111,floatRepresentation), -- x[n]
- to_signed(-333,floatRepresentation), -- x[n-1]
- to_signed( 333,floatRepresentation), -- x[n-2]
- to_signed(-111,floatRepresentation) -- x[n-3]
- );
+ (to_signed( 914,nBitCoef), -- x[n]
+ to_signed(-2741,nBitCoef), -- x[n-1]
+ to_signed( 2741,nBitCoef), -- x[n-2]
+ to_signed(-914,nBitCoef) -- x[n-3]
+ );
+
+-- constant SR_coefRegister_B_high : registerCoefFile :=
+-- (to_signed( 114,nBitCoef), -- x[n]
+-- to_signed(-343,nBitCoef), -- x[n-1]
+-- to_signed( 343,nBitCoef), -- x[n-2]
+-- to_signed(-114,nBitCoef) -- x[n-3]
+-- );
+
+
-- Store the NEGAVITE values of the A coeficients
-- A coeficients are the same for both low pass and high pass filters in this case
constant SR_coefRegister_A : registerCoefFile :=
- (to_signed( 348, floatRepresentation), -- y[n-1]
- to_signed(-316, floatRepresentation), -- y[n-2]
- to_signed( 96, floatRepresentation), -- y[n-3]
- to_signed( 0, floatRepresentation) -- y[n-4] -> NOT USED for order 3 filter
+ (to_signed( 2839, nBitCoef), -- y[n-1]
+ to_signed(-2631, nBitCoef), -- y[n-2]
+ to_signed( 815, nBitCoef), -- y[n-3]
+ to_signed( 0, nBitCoef) -- y[n-4] -> NOT USED for order 3 filter
);
-
+
+-- constant SR_coefRegister_A : registerCoefFile :=
+-- (to_signed( 355, nBitCoef), -- y[n-1]
+-- to_signed(-329, nBitCoef), -- y[n-2]
+-- to_signed( 102, nBitCoef), -- y[n-3]
+-- to_signed( 0, nBitCoef) -- y[n-4] -> NOT USED for order 3 filter
+-- );
signal S_maxAddress : integer := 3;
--- signal S_processingDone : std_logic;
- signal SC_multOperand1 : signed( 7 downto 0);
- signal SC_multOperand2 : signed((floatRepresentation - 1) downto 0);
- signal SC_MultResult : signed(17 downto 0); -- Result of the multiplication Xi*Hi
- signal SC_addResult : signed(19 downto 0); -- result of the accumulation addition
- signal SR_sum : signed(19 downto 0); -- Accumulation register
- signal SR_Y : signed( 7 downto 0); -- filtered sample storage register
+ signal SC_multOperand1 : signed((nBitSamples - 1) downto 0);
+ signal SC_multOperand2 : signed((nBitCoef - 1) downto 0);
+ signal SC_MultResult : signed((nBitCoef + nBitSamples - 1) downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(33 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(33 downto 0); -- Accumulation register
+ signal SR_Y : signed((integerRepresSamples) downto 0); -- filtered sample storage register
signal SR_readAddress : integer range 0 to 3; -- register files read address
-begin
-
-
--- ROM register used file to store IIR coefficients
--- SR_coefRegister_B_high <= (to_signed( 62,floatRepresentation), -- x[n]
--- to_signed(-185,floatRepresentation), -- x[n-1]
--- to_signed( 185,floatRepresentation), -- x[n-2]
--- to_signed( -62,floatRepresentation) -- x[n-3]
--- );
-
-
--- ROM register used file to store IIR coefficients
--- SR_coefRegister_B_low <= (to_signed( 3, floatRepresentation), -- x[n]
--- to_signed( 10, floatRepresentation), -- x[n-1]
--- to_signed( 10, floatRepresentation), -- x[n-2]
--- to_signed( 3, floatRepresentation) -- x[n-3]
--- );
-
-
--- SR_coefRegister_A <= (to_signed(-205, floatRepresentation), -- y[n-1]
--- to_signed( 132, floatRepresentation), -- y[n-2]
--- to_signed( -30, floatRepresentation), -- y[n-3]
--- to_signed( 0, floatRepresentation) -- y[n-4] -> NOT USED for order 3 filter
--- );
-
+begin
shift_samples : process (I_reset, I_clock) is
begin -- process samples' shift
@@ -136,7 +127,7 @@ begin
SR_shiftRegisterSamples <= (others => (others => '0'));
elsif rising_edge(I_clock) then -- rising edge clock
if(I_loadShift = '1') then
- SR_shiftRegisterSamples(0) <= signed(I_inputSample);
+ SR_shiftRegisterSamples(0) <= signed(I_inputSample&"0000000000");
SR_shiftRegisterSamples(1 to 3) <= SR_shiftRegisterSamples(0 to 2);
end if;
end if;
@@ -168,7 +159,6 @@ begin
end if;
end process select_feed;
--- S_processingDone <= '1' when (SR_readAddress = S_maxAddress) else '0';
O_processingDone <= '1' when (SR_readAddress = S_maxAddress) else '0';
SC_multOperand1 <= SR_opRegister(SR_readAddress) ; -- 8 bits
@@ -199,15 +189,14 @@ begin
if (I_loadY = '1') then
SR_shiftOutputRegister(1 to 3) <= SR_shiftOutputRegister(0 to 2);
-
- if (SR_sum(6) = '1') then -- Treating the truncation
+ SR_shiftOutputRegister(0) <= SR_sum((floatRepresCoef + nBitSamples - 1) downto floatRepresCoef);
+
+ if (SR_sum((floatRepresTotal - 1)) = '1') then -- Treating the truncation
- SR_Y <= SR_sum(14 downto 7) + 1;
- SR_shiftOutputRegister(0) <= SR_sum(14 downto 7) + 1;
+ SR_Y <= SR_sum((floatRepresTotal + integerRepresSamples) downto floatRepresTotal) + 1;
else
- SR_Y <= SR_sum(14 downto 7);
- SR_shiftOutputRegister(0) <= SR_sum(14 downto 7);
+ SR_Y <= SR_sum((floatRepresTotal + integerRepresSamples) downto floatRepresTotal);
end if;
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
index d86088b..dbbfefa 100644
--- a/src/hdl/tb_firUnit.vhd
+++ b/src/hdl/tb_firUnit.vhd
@@ -54,7 +54,7 @@ begin
-- Sample period = 20 clk period
SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
- -- Null signal followed by a Dirac and then an arbitrary sequence
+ -- Null signal followed b0y a Dirac and then an arbitrary sequence
-- dirac sequence 0 127 0 36 100 82 219 11 128 127 186
-- SC_inputSample <= "00000000",
-- "01111111" after 401 ns,
--
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