diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 78f1812177ad8e33750313c5da68d69d5ac0c013..9ff9461d51e1d45e29df495bd388161f561e7685 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -3,10 +3,11 @@
-- Project :
-------------------------------------------------------------------------------
-- File : operativeUnit.vhd
--- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Author : Davi SPERANDIO AGATTI <davi.sperandio-agatti@imt-atlantique.net>
+-- Author : Marouen AIDOUDI <marouen.aidoudi@imt-atlantique.net>
-- Company :
--- Created : 2018-04-11
--- Last update: 2019-02-13
+-- Created : 2025-03-11
+-- Last update: 2025-03-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -16,7 +17,6 @@
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
--- 2018-04-11 1.0 jnbazin Created
-------------------------------------------------------------------------------
library ieee;
@@ -113,8 +113,6 @@ begin
I_processingDone when (SR_presentState = PROCESSING_LOOP_1) else '0';
O_incrAddress <= not(I_processingDone) when (SR_presentState = PROCESSING_LOOP_1) else
'1' when (SR_presentState = PROCESSING_LOOP_2) else '0';
--- O_initSum <= '1' when (SR_presentState = STORE) else
--- I_processingDone when (SR_presentState = PROCESSING_LOOP_1) else '0';
O_initSum <= '1' when (SR_presentState = STORE) else '0';
O_loadSum <= '1' when (SR_presentState = PROCESSING_LOOP_1) else
'1' when (SR_presentState = PROCESSING_LOOP_2) else '0';
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 168ef15a4aa81791993ed1d0fbba29404056c676..75ecd3dc02108ce9d13768c9cc941d5ceff50849 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -3,10 +3,11 @@
-- Project :
-------------------------------------------------------------------------------
-- File : operativeUnit.vhd
--- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Author : Davi SPERANDIO AGATTI <davi.sperandio-agatti@imt-atlantique.net>
+-- Author : Marouen AIDOUDI <marouen.aidoudi@imt-atlantique.net>
-- Company :
--- Created : 2018-04-11
--- Last update: 2019-02-13
+-- Created : 2025-03-11
+-- Last update: 2025-03-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -14,15 +15,11 @@
-- register for samples, registers for coefficients, a MAC and a register to
-- store the result
-------------------------------------------------------------------------------
--- Copyright (c) 2018
+-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
--- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve
--- the user experience ;)
--- 2018-04-11 1.0 jnbazin Created
--- 2018-04-18 1.0 marzel Modification of SR_Y assignment to a round
--- instead of a trunc
+
-------------------------------------------------------------------------------
library ieee;
@@ -75,37 +72,22 @@ architecture arch_operativeUnit of operativeUnit is
-- High-pass filter with Fc = 800Hz provided with octave command
-- [b, a] = butter(3, 800 / (44100/2), 'high')
+
constant SR_coefRegister_B_high : registerCoefFile :=
(to_signed( 914,nBitCoef), -- x[n]
to_signed(-2741,nBitCoef), -- x[n-1]
to_signed( 2741,nBitCoef), -- x[n-2]
to_signed(-914,nBitCoef) -- x[n-3]
);
-
--- constant SR_coefRegister_B_high : registerCoefFile :=
--- (to_signed( 114,nBitCoef), -- x[n]
--- to_signed(-343,nBitCoef), -- x[n-1]
--- to_signed( 343,nBitCoef), -- x[n-2]
--- to_signed(-114,nBitCoef) -- x[n-3]
--- );
-
-
-- Store the NEGAVITE values of the A coeficients
--- A coeficients are the same for both low pass and high pass filters in this case
+-- [b, a] = butter(3, 800 / (44100/2), 'high')
constant SR_coefRegister_A : registerCoefFile :=
(to_signed( 2839, nBitCoef), -- y[n-1]
to_signed(-2631, nBitCoef), -- y[n-2]
to_signed( 815, nBitCoef), -- y[n-3]
to_signed( 0, nBitCoef) -- y[n-4] -> NOT USED for order 3 filter
);
-
--- constant SR_coefRegister_A : registerCoefFile :=
--- (to_signed( 355, nBitCoef), -- y[n-1]
--- to_signed(-329, nBitCoef), -- y[n-2]
--- to_signed( 102, nBitCoef), -- y[n-3]
--- to_signed( 0, nBitCoef) -- y[n-4] -> NOT USED for order 3 filter
--- );
signal S_maxAddress : integer := 3;