From ad858547c0122f3218052916a0d59f1f94bbbf2d Mon Sep 17 00:00:00 2001
From: Grazia OBUZOR <g24obuzo@fl-tp-br-634.imta.fr>
Date: Tue, 11 Mar 2025 14:48:44 +0100
Subject: [PATCH] update operative unit (and control unit)
---
src/hdl/controlUnit.vhd | 79 ++++++++++-----------------------------
src/hdl/operativeUnit.vhd | 10 +++--
2 files changed, 27 insertions(+), 62 deletions(-)
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 451347c..1785bc6 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -63,85 +63,46 @@ begin
case SR_presentState is
when WAIT_SAMPLE =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '0';
-
- if(I_inputSampleValid = '1')then
+ if (I_inputSampleValid = '1') then
SR_futurState <= STORE;
- else
+ else
SR_futurState <= WAIT_SAMPLE;
- end if;
-
+ end if;
+
when STORE =>
- O_loadShift <= '1';
- O_initAddress <= '1';
- O_incrAddress <= '0';
- O_initSum <= '1';
- O_loadSum <= '0';
- O_loadY <= '0';
-
SR_futurState <= PROCESSING_LOOP;
-
+
when PROCESSING_LOOP =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '1';
- O_initSum <= '0';
- O_loadSum <= '1';
- O_loadY <= '0';
-
- if(I_processingDone = '1')then
+ if (I_processingDone = '1') then
SR_futurState <= OUTPUT;
- else
+ else
SR_futurState <= PROCESSING_LOOP;
- end if;
-
+ end if;
+
+
when OUTPUT =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '1';
-
SR_futurState <= WAIT_END_SAMPLE;
-
+
when WAIT_END_SAMPLE =>
- O_loadShift <= '0';
- O_initAddress <= '0';
- O_incrAddress <= '0';
- O_initSum <= '0';
- O_loadSum <= '0';
- O_loadY <= '0';
-
- if(I_inputSampleValid = '0')then
+ if (I_inputSampleValid = '0') then
SR_futurState <= WAIT_SAMPLE;
- else
+ else
SR_futurState <= WAIT_END_SAMPLE;
- end if;
+ end if;
when others => null;
end case;
end process;
--- O_loadShift <= '1' when SR_presentState = STORE else '0';
--- O_initAddress <= '1' when _BLANK_ ;
--- O_incrAddress <= '1' when _BLANK_ ;
--- O_initSum <= '1' when _BLANK_ ;
--- O_loadSum <= '1' when _BLANK_ ;
--- O_loadY <= '1' when _BLANK_ ;
--- O_FilteredSampleValid <= '1' when _BLANK_ ;
-
-
+ O_loadShift <= '1' when SR_presentState=STORE else '0';
+ O_initAddress <= '1' when SR_presentState=STORE else '0';
+ O_incrAddress <= '1' when SR_presentState=PROCESSING_LOOP else '0';
+ O_initSum <= '1' when SR_presentState=STORE else '0';
+ O_loadSum <= '1' when SR_presentState=PROCESSING_LOOP else '0';
+ O_loadY <= '1' when SR_presentState=OUTPUT else '0';
O_FilteredSampleValid <= '1' when SR_presentState=WAIT_END_SAMPLE else '0';
-
-
end architecture archi_operativeUnit;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index fad6850..fb46294 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -65,7 +65,7 @@ architecture arch_operativeUnit of operativeUnit is
begin
--- Low-pass filter provided with octave (or Matlab ;)) command
+-- Low-pass filter provided with octave (or Matlab command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
SR_coefRegister <= (to_signed(2, 8), -- ROM register used file to store FIR coefficients -- chiffres fractionnaires entre -1 et +1; premier chiffre est signée
to_signed(3, 8),
@@ -115,7 +115,7 @@ begin
end if;
end process incr_address;
- O_processingDone <= '1' when SR_readAddress = 15 else '0' ;
+ O_processingDone <= '1' when SR_readAddress = 14 else '0' ;
SC_multOperand1 <= SR_shiftRegister(SR_readAddress); -- 8 bits
SC_multOperand2 <= SR_coefRegister(SR_readAddress); -- 8 bits
@@ -141,7 +141,11 @@ begin
SR_Y <= (others => '0');
elsif rising_edge(I_clock) then
if (I_loadY= '1') then
+ if SC_addResult(6) = '1' then
+ SR_Y <= SC_addResult(14 downto 7) + 1;
+ else
SR_Y <= SC_addResult(14 downto 7);
+ end if;
end if;
end if;
@@ -149,4 +153,4 @@ begin
O_Y <= std_logic_vector(SR_Y);
-end architecture arch_operativeUnit;
+end architecture arch_operativeUnit;
\ No newline at end of file
--
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