From 6fc2ff4334c491b0499626deafcf354fa4f56966 Mon Sep 17 00:00:00 2001
From: Florian HUYNH <f22huynh@fl-tp-br-637.imta.fr>
Date: Wed, 26 Mar 2025 15:53:03 +0100
Subject: [PATCH] correction du control Unit
---
src/hdl/controlUnit.vhd | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 81c7d53..f5a0321 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -33,7 +33,7 @@ end entity controlUnit;
architecture archi_operativeUnit of controlUnit is
- type T_state is (WAIT_SAMPLE, STORE_X, PROCESSING_LOOP_Y, STORE_Y, PROCESSING_LOOP_Z1, WAIT, PROCESSING_LOOP_Z2, STORE_Z, PROCESSING_LOOP_R, OUTPUT, WAIT_END_SAMPLE); -- state list
+ type T_state is (WAIT_SAMPLE, STORE_X, PROCESSING_LOOP_Y, STORE_Y, PROCESSING_LOOP_Z1, TRANSITION, PROCESSING_LOOP_Z2, STORE_Z, PROCESSING_LOOP_R, OUTPUT, WAIT_END_SAMPLE); -- state list
signal SR_presentState : T_state;
signal SR_futurState : T_state;
@@ -42,9 +42,9 @@ begin
process (I_clock, I_reset) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
- SR_presentState <= WAIT_SAMPLE
+ SR_presentState <= WAIT_SAMPLE;
elsif rising_edge(I_clock) then -- rising clock edge
- SR_presentState <= SR_futurState
+ SR_presentState <= SR_futurState;
end if;
end process;
@@ -57,7 +57,7 @@ begin
SR_futurState <= STORE_X;
else
SR_futurState <= WAIT_SAMPLE;
-
+ end if;
when STORE_X =>
SR_futurState <= PROCESSING_LOOP_Y;
@@ -66,17 +66,17 @@ begin
SR_futurState <= STORE_Y;
else
SR_futurState <= PROCESSING_LOOP_Y;
-
+ end if;
when STORE_Y =>
SR_futurState <= PROCESSING_LOOP_Z1;
when PROCESSING_LOOP_Z1 =>
if I_processingDone = '1' then
- SR_futurState <= WAIT;
+ SR_futurState <= TRANSITION;
else
SR_futurState <= PROCESSING_LOOP_Z1;
-
- when WAIT =>
+ end if;
+ when TRANSITION =>
SR_futurState <= PROCESSING_LOOP_Z2;
when PROCESSING_LOOP_Z2 =>
@@ -84,7 +84,7 @@ begin
SR_futurState <= STORE_Z;
else
SR_futurState <= PROCESSING_LOOP_Z2;
-
+ end if;
when STORE_Z =>
SR_futurState <= PROCESSING_LOOP_R;
@@ -93,7 +93,7 @@ begin
SR_futurState <= OUTPUT;
else
SR_futurState <= PROCESSING_LOOP_R;
-
+ end if;
when OUTPUT =>
SR_futurState <= WAIT_END_SAMPLE;
@@ -102,7 +102,7 @@ begin
SR_futurState <= WAIT_SAMPLE;
else
SR_futurState <= WAIT_END_SAMPLE;
-
+ end if;
when others => null;
end case;
end process;
@@ -110,11 +110,11 @@ begin
O_loadShift_X <= '1' when SR_presentState = STORE_X else '0';
O_loadShift_Y <= '1' when SR_presentState = STORE_Y else '0';
O_loadShift_Z <= '1' when SR_presentState = STORE_Z else '0';
- O_initAddress <= '1' when SR_presentState = STORE_X or SR_presentState = STORE_Y or SR_presentState = WAIT or SR_presentState = STORE_Z else '0';
+ O_initAddress <= '1' when SR_presentState = STORE_X or SR_presentState = STORE_Y or SR_presentState = TRANSITION or SR_presentState = STORE_Z else '0';
O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP_Y or SR_presentState = PROCESSING_LOOP_Z1 or SR_presentState = PROCESSING_LOOP_Z2 or SR_presentState = PROCESSING_LOOP_R else '0';
O_X <= '1' when SR_presentState = STORE_X else '0';
O_Y <= '1' when SR_presentState = STORE_Y else '0';
- O_Z1 <= '1' when SR_presentState = WAIT else '0';
+ O_Z1 <= '1' when SR_presentState = TRANSITION else '0';
O_Z2 <= '1' when SR_presentState = STORE_Z else '0';
O_initSum <= '1' when SR_presentState = STORE_X or SR_presentState = STORE_Y or SR_presentState = STORE_Z else '0';
O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP_Y or SR_presentState = PROCESSING_LOOP_Z1 or SR_presentState = PROCESSING_LOOP_Z2 or SR_presentState = PROCESSING_LOOP_R else '0';
@@ -122,4 +122,4 @@ begin
O_FilteredSampleValid <= '1' when SR_presentState = WAIT_END_SAMPLE else '0';
-end architecture archi_operativeUnit;
\ No newline at end of file
+end architecture archi_operativeUnit;
--
GitLab