diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index a277fdfa7a77717a847ae5d206ec9db2d2ae2e1c..8cee07e2170120faae836e5ec93f105f5fc220d7 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -32,7 +32,9 @@ use ieee.numeric_std.all;
entity operativeUnit is
port (
- initAddress : in std_logic;
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_initAddress : in std_logic;
I_incrAddress : in std_logic;
I_x : in std_logic;
I_y : in std_logic;
@@ -47,8 +49,8 @@ entity operativeUnit is
I_loadY : in std_logic;
I_loadRun : in std_logic;
- O_processingDone: in std_logic;
- O_Y : in std_logic_vector(10 downto 0)
+ O_processingDone: out std_logic;
+ O_Y : out std_logic_vector(10 downto 0)
);
end entity operativeUnit;
@@ -59,47 +61,35 @@ architecture arch_operativeUnit of operativeUnit is
type registerFile_a is array(0 to 1) of signed(10 downto 0);
type registerFile_g is array(0 to 10) of signed(10 downto 0);
- signal SR_read_add_x : unsigned(128 downto 0);
- signal SR_read_add_y : unsigned(2 downto 0);
- signal SR_read_add_z1 : unsigned(1 downto 0);
- signal SR_read_add_z2 : unsigned(10 downto 0);
-
- signal SR_Sample_Sel : unsigned(2 downto 0);
- signal SR_Coeff_Sel : unsigned(3 downto 0);
-
- signal SC_sample_x : signed(10 downto 0);
- signal SC_sample_y : signed(10 downto 0);
- signal SC_sample_z : signed(10 downto 0);
-
- signal SC_coeff_h : signed(10 downto 0);
- signal SC_coeff_b : signed(10 downto 0);
- signal SC_coeff_a : signed(10 downto 0);
- signal SC_coeff_g : signed(10 downto 0);
+ signal SR_read_add_x : integer range 0 to 128;
+ signal SR_read_add_y : integer range 0 to 2;
+ signal SR_read_add_z1 : integer range 0 to 1;
+ signal SR_read_add_z2 : integer range 0 to 10;
signal SC_multOperand1 : signed(10 downto 0);
signal SC_multOperand2 : signed(10 downto 0);
- signal SC_add : unsigned(28 downto 0);
+ signal SC_add : signed(28 downto 0);
- signal SC_multResult : unsigned(21 downto 0);
- signal SC_addResult : unsigned(28 downto 0);
+ signal SC_multResult : signed(21 downto 0);
+ signal SC_addResult : signed(28 downto 0);
signal SC_output : signed(10 downto 0);
- signal SC_coeff_h : registerFile_h;
- signal SC_coeff_b : registerFile_b;
- signal SC_coeff_a : registerFile_a;
- signal SC_coeff_g : registerFile_g;
+ signal SC_coeffReg_h : registerFile_h;
+ signal SC_coeffReg_b : registerFile_b;
+ signal SC_coeffReg_a : registerFile_a;
+ signal SC_coeffReg_g : registerFile_g;
- signal SC_sample_x : registerFile_h;
- signal SC_sample_y : registerFile_b;
- signal SC_sample_z : registerFile_g;
+ signal SC_sampleReg_x : registerFile_h;
+ signal SC_sampleReg_y : registerFile_b;
+ signal SC_sampleReg_z : registerFile_g;
begin
-- Low-pass filter provided with octave (or Matlab ;)) command
--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
- SC_coeff_h <= (to_signed(0,11),
+ SC_coeffReg_h <= (to_signed(0,11),
to_signed(0,11),
to_signed(0,11),
to_signed(0,11),
@@ -230,15 +220,15 @@ begin
to_signed(0,11)
);
- SC_coeff_b <= (to_signed(480, 11), -- ROM register used file to store FIR coefficients
+ SC_coeffReg_b <= (to_signed(480, 11), -- ROM register used file to store FIR coefficients
to_signed(-777, 11),
to_signed(480, 11)
);
- SC_coeff_a <= (to_signed(-777, 11), -- ROM register used file to store FIR coefficients
+ SC_coeffReg_a <= (to_signed(-777, 11), -- ROM register used file to store FIR coefficients
to_signed(449, 11)
);
- SC_coeff_g <= (to_signed(-119,11),
+ SC_coeffReg_g <= (to_signed(-119,11),
to_signed(122,11),
to_signed(149,11),
to_signed(191,11),
@@ -254,19 +244,19 @@ begin
shift : process (I_clock, I_reset) is
begin -- process shift
if I_reset = '1' then
- SC_sample_x <= (others => '0');
- SC_sample_y <= (others => '0');
- SC_sample_z <= (others => '0');
+ SC_sampleReg_x <= (others => (others => '0'));
+ SC_sampleReg_y <= (others => (others => '0'));
+ SC_sampleReg_z <= (others => (others => '0'));
elsif rising_edge(I_clock) then
if I_loadShift_x = '1' then
- SC_sample_x <= SC_sample_x(1 to 128);
- SC_sample_x(0) <= signed(I_inputSample);
+ SC_sampleReg_x(1 to 128) <= SC_sampleReg_x(0 to 127);
+ SC_sampleReg_x(0) <= signed(I_inputSample);
elsif I_loadShift_y = '1' then
- SC_sample_y <= SR_read_add_y(1 to 2);
- SC_sample_y(0) <= signed(SC_addResult(10 to 20)); -- a checker
+ SC_sampleReg_y(1 to 2) <= SC_sampleReg_y(0 to 1);
+ SC_sampleReg_y(0) <= signed(SC_addResult(20 downto 10)); -- a checker
elsif I_loadShift_z = '1' then
- SC_sample_z <= SR_read_add_z2(1 to 10);
- SC_sample_z(0) <= signed(SC_addResult(9 to 19)); -- a checker
+ SC_sampleReg_z(1 to 10) <= SC_sampleReg_z(0 to 9);
+ SC_sampleReg_z(0) <= signed(SC_addResult(19 downto 9)); -- a checker
end if;
end if;
end process shift;
@@ -274,10 +264,10 @@ begin
incr_address : process (I_clock, I_reset) is
begin
if I_reset = '1' then
- SR_read_add_x <= (others => '0');
- SR_read_add_y <= (others => '0');
- SR_read_add_z1 <= (others => '0');
- SR_read_add_z2 <= (others => '0');
+ SR_read_add_x <= 0;
+ SR_read_add_y <= 0;
+ SR_read_add_z1 <= 0;
+ SR_read_add_z2 <= 0;
elsif rising_edge(I_clock) then
if I_initAddress = '1' then
SR_read_add_x <= 0;
@@ -301,22 +291,24 @@ begin
end if;
end process incr_address;
- O_processingDone <= '1' when SR_read_add_x > 128 or
- SR_read_add_y > 3 or
- SR_read_add_z1 > 2 or
- SR_read_add_z2 > 11
+ O_processingDone <= '1' when SR_read_add_x >= 128 or
+ SR_read_add_y >= 3 or
+ SR_read_add_z1 >= 2 or
+ SR_read_add_z2 >= 11
else '0';
- SC_multOperand1 <= SR_Sample_Sel(SC_sample_x) when I_x = '1' else
- SR_Sample_Sel(SC_sample_y) when I_y = '1' else
- SR_Sample_Sel(SC_sample_z) when I_z1 = '1' else
- SR_Sample_Sel(SC_sample_z) when I_z2 = '1' else
+ SC_multOperand1 <= SC_sampleReg_x(SR_read_add_x) when I_x = '1' else
+ SC_sampleReg_y(SR_read_add_y) when I_y = '1' else
+ SC_sampleReg_z(SR_read_add_z1) when I_z1 = '1' else
+ SC_sampleReg_z(SR_read_add_z2) when I_z2 = '1' else
(others => '0');
- SC_multOperand2 <= SR_Coeff_Select(SC_coeff_h) when I_x = '1' else
- SR_Coeff_Select(SC_coeff_b) when I_y = '1' else
- SR_Coeff_Select(SC_coeff_a) when I_z1 = '1' else
- SR_Coeff_Select(SC_coeff_g) when I_z2 = '1' else
+
+ SC_multOperand2 <= SC_coeffReg_h(SR_read_add_x) when I_x = '1' else
+ SC_coeffReg_b(SR_read_add_y) when I_y = '1' else
+ SC_coeffReg_a(SR_read_add_z1) when I_z1 = '1' else
+ SC_coeffReg_g(SR_read_add_z2) when I_z2 = '1' else
(others => '0');
+
SC_multResult <= SC_multOperand1*SC_multOperand2;
SC_addResult <= SC_multResult + SC_add;