diff --git a/src/hdl/TWICtl.vhd b/src/hdl/TWICtl.vhd
deleted file mode 100644
index e0dad088dc435c2270e1b22384bd168dece168a1..0000000000000000000000000000000000000000
--- a/src/hdl/TWICtl.vhd
+++ /dev/null
@@ -1,571 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: Digilent Ro
--- Engineer: Elod Gyorgy
---
--- Create Date: 14:55:31 04/07/2011
--- Design Name:
--- Module Name: TWIUtils - Package
--- Project Name: TWI Master Controller Reference Design
--- Target Devices:
--- Tool versions:
--- Description: This package provides enumeration types for TWI (Two-Wire
--- Interface) bus status and error conditions.
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-package TWIUtils is
- type busState_type is (busUnknown, busBusy, busFree);
- type error_type is (errArb, errNAck);
-end TWIUtils;
-
-package body TWIUtils is
-end TWIUtils;
-
-----------------------------------------------------------------------------------
--- Company: Digilent Ro
--- Engineer: Elod Gyorgy
---
--- Create Date: 14:55:31 04/07/2011
--- Design Name:
--- Module Name: TWICtl - Behavioral
--- Project Name: TWI Master Controller Reference Design
--- Target Devices:
--- Tool versions:
--- Description: TWICtl is a reusabled Master Controller implementation of the
--- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
--- FAST mode should also be theoretically possible, although it has not been
--- tested. It adheres to arbitration rules, thus supporting multi-master TWI
--- buses. Slave-wait is also supported.
---
---
--- Dependencies: digilent.TWIUtils package - TWICtl.vhd
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.math_real.all;
-
-library digilent;
---use digilent.TWIUtils.ALL;
-
-entity TWICtl is
-----------------------------------------------------------------------------------
--- Title : Mode of operation
--- Description: The controller can be instructed to initiate/continue/stop a
--- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
--- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
--- signals are synchronous to CLK and input signals must also be synchronous to
--- CLK. Signals are active-high.
--- Fast-track instructions (single byte transfer):
--- -put the TWI address on A_I
--- -if data is written put it on D_I
--- -assert STB_I
--- -when DONE_O pulse arrives, read data is present on D_O, if any
--- -repeat, or deassert STB_I
--- Detailed data transfer flow:
--- -when DONE_O is low, the controller is ready to accept commands
--- -data transfer can be initiated by putting a TWI slave address on the A_I
--- bus and providing a strobe (STB_I)
--- -the direction of data transfer (read/write) is determined by the LSB of the
--- address (0-write, 1-read)
--- -in case of a 'write' the data byte should also be present on the D_I bus
--- prior to the arrival of the strobe (STB_I)
--- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
--- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
--- together with DONE_I high indicates success
--- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
--- strobe can be sent; this is useful, when multiple bytes are sent/received
--- in a single transfer packet; for ex. for write transfers, a new byte can
--- be put on the D_I and STB_I provided;
--- -if no new strobe is provided, the transfer will end
--- -if a new strobe is provided, but the address changed, the current transfer
--- will end and a new will begin
--- -starting a new transfer can be forced with the MSG_I pin; if asserted with
--- a strobe, the data byte will be written/read in a new packet; the advantage
--- of this is relevant only in multi-master buses: rather than waiting for the
--- current transfer to end and the bus to be released, a new transfer can be
--- initiated without giving up the control over the bus
-----------------------------------------------------------------------------------
- generic (CLOCKFREQ : natural := 50); -- input CLK frequency in MHz
- port (
- MSG_I : in STD_LOGIC; --new message
- STB_I : in STD_LOGIC; --strobe
- A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
- D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
- D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
- DONE_O : out STD_LOGIC; --done status signal
- ERR_O : out STD_LOGIC; --error status
- CLK : in std_logic;
- SRST : in std_logic;
-----------------------------------------------------------------------------------
--- TWI bus signals
-----------------------------------------------------------------------------------
- SDA : inout std_logic; --TWI SDA
- SCL : inout std_logic --TWI SCL
- );
-end TWICtl;
-
-architecture Behavioral of TWICtl is
- attribute fsm_encoding: string;
-
- constant FSCL : natural := 400_000; --in Hz SCL clock frequency
- constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
- constant TSCL_CYCLES : natural :=
- natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
- constant TIMEOUT_CYCLES : natural :=
- natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
-
- type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
- stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
- type busState_type is (busUnknown, busFree, busBusy);
- type error_type is (errNAck, errArb);
- signal state, nstate : state_type;
- attribute fsm_encoding of state: signal is "gray";
-
- signal dSda, ddSda, dScl, ddScl : std_logic;
- signal fStart, fStop : std_logic;
- signal busState : busState_type := busUnknown;
- signal errTypeR, errType : error_type;
- signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
- signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
- signal slaveWait, arbLost : std_logic;
- signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
- signal rSda, rScl : std_logic := '1';
- signal subState : std_logic_vector(1 downto 0) := "00";
- signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
- signal bitCount : natural range 0 to 7 := 7;
- signal int_Rst : std_logic := '0';
-begin
-
-----------------------------------------------------------------------------------
---Bus State detection
-----------------------------------------------------------------------------------
-SYNC_FFS: process(CLK)
- begin
- if Rising_Edge(CLK) then
- dSda <= SDA;
- ddSda <= dSda;
- dScl <= SCL;
- end if;
- end process;
-
- fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
- fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
-
-TWISTATE: process(CLK)
- begin
- if Rising_Edge(CLK) then
- if (int_Rst = '1') then
- busState <= busUnknown;
- elsif (fStart = '1') then --If START condition detected, bus is busy
- busState <= busBusy;
- elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
- busState <= busFree;
- end if;
- end if;
- end process;
-
-TBUF_CNT: process(CLK)
- begin
- if Rising_Edge(CLK) then
- if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
- busFreeCnt <= TSCL_CYCLES;
- elsif (dSCL = '1' and dSDA = '1') then
- busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
- end if;
- end if;
- end process;
-
-----------------------------------------------------------------------------------
---Slave devices can insert wait states by keeping SCL low
-----------------------------------------------------------------------------------
- slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
- '0';
-----------------------------------------------------------------------------------
---If the SDA line does not correspond to the transmitted data while the SCL line
---is at the HIGH level the master lost an arbitration to another master.
-----------------------------------------------------------------------------------
- arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
- '0';
-
-----------------------------------------------------------------------------------
--- Internal reset signal
-----------------------------------------------------------------------------------
- RST_PROC: process (CLK)
- begin
- if Rising_Edge(CLK) then
- if (state = stIdle and SRST = '0') then
- int_Rst <= '0';
- elsif (SRST = '1') then
- int_Rst <= '1';
- end if;
- end if;
- end process;
-
-----------------------------------------------------------------------------------
--- SCL period counter
-----------------------------------------------------------------------------------
-SCL_CNT: process (CLK)
- begin
- if Rising_Edge(CLK) then
- if (sclCnt = 0 or state = stIdle) then
- sclCnt <= TSCL_CYCLES/4;
- elsif (slaveWait = '0') then -- clock synchronization with other masters
- sclCnt <= sclCnt - 1;
- end if;
- end if;
- end process;
-
-----------------------------------------------------------------------------------
--- SCL period counter
-----------------------------------------------------------------------------------
-TIMEOUT_CNT: process (CLK)
- begin
- if Rising_Edge(CLK) then
- if (timeOutCnt = 0 or slaveWait = '0') then
- timeOutCnt <= TIMEOUT_CYCLES;
- elsif (slaveWait = '1') then -- count timeout on wait period inserted by slave
- timeOutCnt <= timeOutCnt - 1;
- end if;
- end if;
- end process;
-
-----------------------------------------------------------------------------------
--- Title: Data byte shift register
--- Description: Stores the byte to be written or the byte read depending on the
--- transfer direction.
-----------------------------------------------------------------------------------
-DATABYTE_SHREG: process (CLK)
- begin
- if Rising_Edge(CLK) then
- if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
- dataByte <= loadByte; --latch address/data
- bitCount <= 7;
- --set flag so that we now what is the byte we are sending
- if (latchData = '1') then
- addrNData <= '0';
- else
- addrNData <= '1';
- end if;
- elsif (shiftBit = '1' and sclCnt = 0) then
- dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
- bitCount <= bitCount - 1;
- end if;
- end if;
- end process;
-
- loadByte <= A_I when latchAddr = '1' else
- D_I;
- dataBitOut <= dataByte(dataByte'high);
-
- D_O <= dataByte;
-
-----------------------------------------------------------------------------------
--- Title: Current address register
--- Description: Stores the TWI slave address
-----------------------------------------------------------------------------------
-CURRADDR_REG: process (CLK)
- begin
- if Rising_Edge(CLK) then
- if (latchAddr = '1') then
- currAddr <= A_I; --latch address/data
- end if;
- end if;
- end process;
-
- rwBit <= currAddr(0);
-----------------------------------------------------------------------------------
--- Title: Substate counter
--- Description: Divides each state into 4, to respect the setup and hold times of
--- the TWI bus.
-----------------------------------------------------------------------------------
-SUBSTATE_CNT: process (CLK)
- begin
- if Rising_Edge(CLK) then
- if (state = stIdle) then
- subState <= "00";
- elsif (sclCnt = 0) then
- subState <= subState + 1;
- end if;
- end if;
- end process;
-
-SYNC_PROC: process (CLK)
- begin
- if Rising_Edge(CLK) then
- state <= nstate;
-
- rSda <= iSda;
- rScl <= iScl;
- DONE_O <= iDone;
- ERR_O <= iErr;
- errTypeR <= errType;
- end if;
- end process;
-
-OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
- sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
- begin
- iSda <= rSda; --no change by default
- iScl <= rScl;
- iDone <= '0';
- iErr <= '0';
- errType <= errTypeR; --keep error type
- shiftBit <= '0';
- latchAddr <= '0';
- latchData <= '0';
-
- if (state = stStart) then
- case (subState) is
- when "00" =>
- iSda <= '1';
- --keep SCL
- when "01" =>
- iSda <= '1';
- iScl <= '1';
- when "10" =>
- iSda <= '0';
- iScl <= '1';
- when "11" =>
- iSda <= '0';
- iScl <= '0';
- when others =>
- end case;
- end if;
-
- if (state = stStop or state = stStopError) then
- case (subState) is
- when "00" =>
- iSda <= '0';
- --keep SCL
- when "01" =>
- iSda <= '0';
- iScl <= '1';
- when "10" =>
- iSda <= '1';
- iScl <= '1';
- when others =>
- end case;
- end if;
-
- if (state = stRead or state = stSAck) then
- case (subState) is
- when "00" =>
- iSda <= '1'; --this will be 'Z' on SDA
- --keep SCL
- when "01" =>
- --keep SDA
- iScl <= '1';
- when "10" =>
- --keep SDA
- iScl <= '1';
- when "11" =>
- --keep SDA
- iScl <= '0';
- when others =>
- end case;
- end if;
-
- if (state = stWrite) then
- case (subState) is
- when "00" =>
- iSda <= dataBitOut;
- --keep SCL
- when "01" =>
- --keep SDA
- iScl <= '1';
- when "10" =>
- --keep SDA
- iScl <= '1';
- when "11" =>
- --keep SDA
- iScl <= '0';
- when others =>
- end case;
- end if;
-
- if (state = stMAck) then
- case (subState) is
- when "00" =>
- iSda <= '0'; -- acknowledge by writing 0
- --keep SCL
- when "01" =>
- --keep SDA
- iScl <= '1';
- when "10" =>
- --keep SDA
- iScl <= '1';
- when "11" =>
- --keep SDA
- iScl <= '0';
- when others =>
- end case;
- end if;
-
- if (state = stMNAckStop or state = stMNAckStart) then
- case (subState) is
- when "00" =>
- iSda <= '1'; -- not acknowledge by writing 1
- --keep SCL
- when "01" =>
- --keep SDA
- iScl <= '1';
- when "10" =>
- --keep SDA
- iScl <= '1';
- when "11" =>
- --keep SDA
- iScl <= '0';
- when others =>
- end case;
- end if;
-
- if (state = stSAck and sclCnt = 0 and subState = "01") then
- if (dSda = '1') then
- iDone <= '1';
- iErr <= '1'; --not acknowledged
- errType <= errNAck;
- elsif (addrNData = '0') then
- --we are done only when the data is sent too after the address
- iDone <= '1';
- end if;
- end if;
-
- if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
- iDone <= '1'; --read done
- end if;
-
- if (state = stWrite and arbLost = '1') then
- iDone <= '1'; --write done
- iErr <= '1'; --we lost the arbitration
- errType <= errArb;
- end if;
-
- if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
- ((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
- shiftBit <= '1';
- end if;
-
- if (state = stStart) then
- latchAddr <= '1';
- end if;
-
- if (state = stSAck and subState = "11") then --get the data byte for the next write
- latchData <= '1';
- end if;
-
- end process;
-
-NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I,
-SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
- begin
-
- nstate <= state; --default is to stay in current state
-
- case (state) is
- when stIdle =>
- if (STB_I = '1' and busState = busFree and SRST = '0') then
- nstate <= stStart;
- end if;
-
- when stStart =>
- if (subState = "11" and sclCnt = 0) then
- nstate <= stWrite;
- end if;
-
- when stWrite =>
- if (arbLost = '1') then
- nstate <= stIdle;
- elsif (subState = "11" and sclCnt = 0 and bitCount = 0) then
- nstate <= stSAck;
- end if;
-
- when stSAck =>
- if (subState = "11" and sclCnt = 0) then
- if (int_Rst = '1' or dataByte(0) = '1') then
- nstate <= stStop;
- else
- if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
- if (rwBit = '1') then
- nstate <= stRead;
- else
- nstate <= stWrite;
- end if;
- elsif (STB_I = '1') then
- if (MSG_I = '1' or currAddr /= A_I) then
- nstate <= stStart;
- else
- if (rwBit = '1') then
- nstate <= stRead;
- else
- nstate <= stWrite;
- end if;
- end if;
- else
- nstate <= stStop;
- end if;
- end if;
- end if;
-
- when stStop =>
- if (subState = "10" and sclCnt = 0) then
- nstate <= stIdle;
- end if;
-
- when stRead =>
- if (subState = "11" and sclCnt = 0 and bitCount = 7) then --bitCount will underflow
- if (int_Rst = '0' and STB_I = '1') then
- if (MSG_I = '1' or currAddr /= A_I) then
- nstate <= stMNAckStart;
- else
- nstate <= stMAck;
- end if;
- else
- nstate <= stMNAckStop;
- end if;
- end if;
-
- when stMAck =>
- if (subState = "11" and sclCnt = 0) then
- nstate <= stRead;
- end if;
-
- when stMNAckStart =>
- if (arbLost = '1') then
- nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
- elsif (subState = "11" and sclCnt = 0) then
- nstate <= stStart;
- end if;
-
- when stMNAckStop =>
- if (arbLost = '1') then
- nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
- elsif (subState = "11" and sclCnt = 0) then
- nstate <= stStop;
- end if;
-
- when others =>
- nstate <= stIdle;
- end case;
- end process;
-
-----------------------------------------------------------------------------------
--- Open-drain outputs for bi-directional SDA and SCL
-----------------------------------------------------------------------------------
- SDA <= 'Z' when rSDA = '1' else
- '0';
- SCL <= 'Z' when rSCL = '1' else
- '0';
-
-end Behavioral;
\ No newline at end of file
diff --git a/src/hdl/audioProc.v b/src/hdl/audioProc.v
deleted file mode 100644
index cae83dfc1161c885ee157b699a414b3778f03f22..0000000000000000000000000000000000000000
--- a/src/hdl/audioProc.v
+++ /dev/null
@@ -1,231 +0,0 @@
-// -*- Mode: Verilog -*-
-// Filename : audioProc.v
-// Description : Audio processing project for IMTA A1S2 Labs in digital electronics, based on looper project by Digilent Inc.
-// Author : Matthieu Arzel
-// Created On : Fri Feb 8 11:16:35 2019
-// Last Modified By: Matthieu Arzel
-// Last Modified On: Fri Feb 8 11:16:35 2019
-// Update Count : 0
-// Status : Unknown, Use with caution!
-
-`timescale 1ns / 1ps
-
-module audioProc(
-
-
- input BTNL,
- input BTNR,
- input BTND,
- input BTNC,
- input BTNU,
- // input JA1,
- // input JA2,
- // input JA3,
- // input JA4,
-
- input CLK100MHZ,
- input rstn,
- input sw,
- //input [3:0]sw,
- input sw3,
- input sw4,
- input sw5,
- input sw6,
- input sw7,
- output led3,
- output led4,
- output led5,
- output led6,
- output led7,
-
- inout scl,
- inout sda,
-
- output ac_mclk,
- input ac_adc_sdata,
- output ac_dac_sdata,
- output ac_bclk,
- output ac_lrclk
-
- );
-
- wire rst;
- assign rst = ~rstn;
- wire clk50;
- parameter tenhz = 10000000;
-
-
-
- wire [4:0] buttons_i;
- assign buttons_i = {BTNU, BTNR, BTNC, BTND, BTNL};
-
- reg [21:0] max_block=0;
-
- wire set_max;
- wire reset_max;
-
-
- wire [4:0] buttons_db;//Debounced buttons
-
- wire data_flag;
- reg [23:0] sound_dataL;
- reg [23:0] sound_dataR;
- wire data_ready;
-
- wire mix_data;
- wire [21:0] block48KHz;
-
- wire clk_out_100MHZ;
- wire clk_out_200MHZ;
-
-
- //////////////////////////////////////////////////////////////////////////////////////////////////////////
- //// clk_wiz instantiation and wiring
- //////////////////////////////////////////////////////////////////////////////////////////////////////////
- clk_wiz_0 clk_1
- (
- // Clock in ports
- .clk_in1(CLK100MHZ),
- // Clock out ports
- .clk_out1(clk_out_100MHZ),
- .clk_out2(clk_out_200MHZ),
- .clk_out3(ac_mclk),
- .clk_out4(clk50),
- // Status and control signals
- .locked()
- );
-
- //////////////////////////////////////////////////////////////////////////////////////////////////////////
- //// Audio Initialization via TWI
- //////////////////////////////////////////////////////////////////////////////////////////////////////////
-
- audio_init initialize_audio
- (
- .clk(clk50),
- .rst(rst),
- .sda(sda),
- .scl(scl)
- );
-
-
- wire [23:0] mixL;
- wire [23:0] mixR;
-
-
- debounce dbuttons(
- .clock(clk_out_100MHZ),
- .reset(rst),
- .button(buttons_i),
- .out(buttons_db)
- );
-
-
-
-
-
-
- ////////////////////////////////////////////////////////////////////////////////////////////////////////
- // Audio input and output
- ////////////////////////////////////////////////////////////////////////////////////////////////////////
-
- wire [23:0] in_audioL;
- wire [23:0] in_audioR;
- wire [23:0] out_audioL;
- wire [23:0] out_audioR;
-
- i2s_ctl audio_inout(
- .CLK_I(clk_out_100MHZ), //Sys clk
- .RST_I(rst), //Sys rst
- .EN_TX_I(1), // Transmit Enable (push sound data into chip)
- .EN_RX_I(1), //Receive enable (pull sound data out of chip)
- .FS_I(4'b0101), //Sampling rate selector
- .MM_I(0), //Audio controller Master mode select
- .D_L_I(mixL), //Left channel data input from mix (mixed audio output)
- .D_R_I(mixR), //Right channel data input from mix
- .D_L_O(in_audioL), // Left channel data (input from mic input)
- .D_R_O(in_audioR), // Right channel data (input from mic input)
- .BCLK_O(ac_bclk), // serial CLK
- .LRCLK_O(ac_lrclk), // channel CLK
- .SDATA_O(ac_dac_sdata), // Output serial data
- .SDATA_I(ac_adc_sdata) // Input serial data
- );
-
- reg lrclkD1=0;
- reg lrclkD2=0;
-
- always@(posedge(clk_out_100MHZ))begin
- lrclkD1<=ac_lrclk;
- lrclkD2<=lrclkD1;
- end
-
- reg pulse48kHz;
- wire lrclkrise;
- assign lrclkrise = lrclkD1 & ~lrclkD2;
- reg[3:0] lrclkcnt=0;
-
- always@(posedge(clk_out_100MHZ))begin
- if (lrclkcnt==15)begin
- pulse48kHz<=1;
- lrclkcnt<=0;
- end
- else
- pulse48kHz<=0;
- if (lrclkrise)lrclkcnt<=lrclkcnt+1;
- end
- //////////////////////////////
- //FIR filter
- // Marz
- /////////////////////////////
- wire [23:0] inputLeftSample, inputRightSample,outputLeftSample,outputRightSample;
- wire [4:0] configSw;
-
- assign inputLeftSample = in_audioL;
- assign inputRightSample = in_audioR;
- assign configSw[0]=sw3;
- assign configSw[1]=sw4;
- assign configSw[2]=sw5;
- assign configSw[3]=sw6;
- assign configSw[4]=sw7;
- assign led3=sw3;
- assign led4=sw4;
- assign led5=sw5;
- assign led6=sw6;
- assign led7=sw7;
-
- fir #(24,16) leftFir
- (
- inputLeftSample,
- outputLeftSample,
- configSw,//config_sw, // : in std_logic_vector(3 downto 0); --inutilise dans le TP majeure
- clk_out_100MHZ, // : in std_logic;
- rst,// : in std_logic;
- pulse48kHz// : in std_logic; -- signal de validation de din a la frequence des echantillons audio
- );
- fir #(24,16) rightFir
- (
- inputRightSample,
- outputRightSample,
- configSw,//config_sw, // : in std_logic_vector(3 downto 0); --inutilise dans le TP majeure
- clk_out_100MHZ, // : in std_logic;
- rst,// : in std_logic;
- pulse48kHz// : in std_logic; -- signal de validation de din a la frequence des echantillons audio
- );
-
- assign mixL = buttons_db[2] ? in_audioL : outputLeftSample;
- assign mixR = buttons_db[2] ? in_audioR : outputRightSample;
-
-
- ////////////////////////////////////////////////////////////////////////////////////////////////////////
- //// Data in latch
- ////////////////////////////////////////////////////////////////////////////////////////////////////////
-
- //Latch audio data input when data_flag goes high
- always@(posedge(clk_out_100MHZ))begin
- if (data_flag==1)begin
- sound_dataL<=in_audioL;
- sound_dataR<=in_audioR;
- end
- end
-
-
-endmodule
diff --git a/src/hdl/audio_init.v b/src/hdl/audio_init.v
deleted file mode 100644
index 0f331842cd81d9470f1e7ecb0bc15cc6dab92ecd..0000000000000000000000000000000000000000
--- a/src/hdl/audio_init.v
+++ /dev/null
@@ -1,246 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 07/08/2015 06:07:53 PM
-// Design Name:
-// Module Name: audio_init
-// Project Name:
-// Target Devices:
-// Tool Versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-
-
-module audio_init(
- input clk,
- input rst,
- inout sda,
- inout scl
- );
- parameter stRegAddr1 = 4'b0000;
- parameter stRegAddr2 = 4'b0001;
- parameter stData1 = 4'b0010;
- parameter stData2 = 4'b0011;
- parameter stError = 4'b0100;
- parameter stDone = 4'b0101;
- parameter stIdle = 4'b0110;
- parameter stDelay = 4'b0111;
- parameter stPLLsecond = 4'b1111;
-
- parameter INIT_VECTORS = 35;
- parameter IRD = 1'b1;//init read
- parameter IWR = 1'b0;//init write
- parameter delay = 1000*24;
-
- reg [3:0] state=stIdle;//State machine
- reg [32:0] initWord;
- reg initFbWe;
- reg initEn;
- reg [6:0]initA=0;
- always @(posedge(clk))begin
- case (initA)
- 0: initWord <= {IWR,31'h40150100};
- 1: initWord <= {IWR,31'h40160000};
- 2: initWord <= {IWR,31'h40170000};
- 3: initWord <= {IWR,31'h40F80000};
- 4: initWord <= {IWR,31'h40191300};
- 5: initWord <= {IWR,31'h402A0300};
- 6: initWord <= {IWR,31'h40290300};
- 7: initWord <= {IWR,31'h40F20100};
- 8: initWord <= {IWR,31'h40F97F00};
- 9: initWord <= {IWR,31'h40FA0300};
-
- 10: initWord <= {IWR,31'h40200300};
- 11: initWord <= {IWR,31'h40220100};
- 12: initWord <= {IWR,31'h40210900};
- 13: initWord <= {IWR,31'h4025E600};
- 14: initWord <= {IWR,31'h4026E600};
- 15: initWord <= {IWR,31'h40270300};
- 16: initWord <= {IWR,31'h40100100};
- 17: initWord <= {IWR,31'h40280000};
- 18: initWord <= {IWR,31'h4023E600};
- 19: initWord <= {IWR,31'h4024E600};
-
- 20: initWord <= {IWR,31'h400A0100};
- 21: initWord <= {IWR,31'h400B0500};
- 22: initWord <= {IWR,31'h400C0100};
- 23: initWord <= {IWR,31'h400D0500};
- 24: initWord <= {IWR,31'h400E0300};
- 25: initWord <= {IWR,31'h400F0300};
- 26: initWord <= {IWR,31'h401C2100};
- 27: initWord <= {IWR,31'h401D0000};
- 28: initWord <= {IWR,31'h401E4100};
- 29: initWord <= {IWR,31'h401F0000};
- 30: initWord <= {IWR,31'h40F30100};
- 31: initWord <= {IWR,31'h40F40000};
- 32: initWord <= {IWR,31'h40000F00};
- 33: initWord <= {IWR,31'h4002007D};//This sends the address of the PLL reg and the first config bits
- 34: initWord <= {IWR,31'h000C2101}; //These are the config bytes for the PLL reg
- endcase
- end
- reg msg;//New message signal
- reg stb;//Strobe signal
- reg [7:0] data_i;//Data into TWI controller
- wire [7:0] data_o;//Data out of TWI controller
- wire done;
- wire error;
- wire errortype;
- wire [7:0] twiAddr;//Address of device on TWI
- reg [7:0] regData1;
-
- reg delayEn=0;
- integer delaycnt;
-
-
- assign twiAddr[7:1] = 7'b0111011;
-
- assign twiAddr[0] = 0;
-
- TWICtl twi_controller(
- .MSG_I(msg),
- .STB_I(stb),
- .A_I(twiAddr),
- .D_I(data_i),
- .D_O(data_o),
- .DONE_O(done),
- .ERR_O(error),
- .CLK(clk),
- .SRST(rst),
- .SDA(sda),
- .SCL(scl)
- );
-
-
-
-always @(posedge(clk))begin
- if (delayEn==1)
- delaycnt<=delaycnt-1;
- else
- delaycnt<=delay;
-end
-
-
-always @(posedge(clk))begin
- if (state == stData1 && done == 1 && error != 1)
- regData1 <= data_o;
-end
-
-
-always @(posedge(clk))begin
- if (rst==1)begin
- state<= stIdle;
- delayEn <= 0;
- initA <=0;
- end
- else begin
- data_i <= "--------";
- stb <= 0;
- msg <= 0;
-
- initFbWe <= 0;
- case (state)
- stRegAddr1: begin// Sends x40
- if (done == 1)begin
- if (error == 1)
- state <= stError;
- else
- state <= stRegAddr2;
- end
- data_i <= initWord[31:24];
- stb <= 1;
- msg <= 1;
- end
- stRegAddr2: begin //Sends register address x40(XX)
- if (done == 1)begin
- if (error == 1)
- state <= stError;
- else
- state <= stData1;
- end
- data_i <= initWord[23:16];
- stb <= 1;
- end
- stData1: begin
- if (done == 1) begin
- if (error == 1)
- state <= stError;
- else begin
- if (initWord[7:0]!=0)//If there is another byte, send it
- state <= stData2;
- else begin//no more bytes to send
- initEn <= 1;
-
- if (initA == INIT_VECTORS-1)//Done with all instructions
- state <= stDone;
- else //Only 3 bytes to send
- state <= stDelay;
- end
- end
- end
- if (initWord[32] == 1) msg <= 1;
- data_i <= initWord[15:8];
- stb <= 1;
- end
- stData2: begin
- if (done == 1)begin
- if (error == 1)
- state <= stError;
- else begin
- initEn<=1;
- if (initWord[32] == 1) initFbWe <= 1;
- if (initWord[23:16]== 8'h02)begin//If its the PLL register
- initA<=initA+1;//Move initWord to the remaining PLL config bits
- state <= stPLLsecond;//And send them
- end
- else if (initA == INIT_VECTORS-1)
- state <= stDone;
- else
- state <= stDelay;
- end
- end
- data_i <= initWord[7:0];
- stb <= 1;
- end
- stPLLsecond:begin
- if (done == 1)begin
- if (error == 1)
- state <= stError;
- else
- state <= stRegAddr2;
- end
- data_i <= initWord[31:24];
- stb <= 1;
- end
- stError: begin
- state <= stRegAddr1;
- end
- stDone: begin
- end
- stIdle:begin
- state <= stRegAddr1;
- end
- stDelay:begin
- delayEn <= 1;
- if (delaycnt==0)begin
- delayEn<=0;
- if (initEn)begin
- initA<=initA+1;
- initEn <= 0;
- end
- state<=stRegAddr1;
- end
- end
- endcase
- end
-end
-endmodule
diff --git a/src/hdl/debounce.v b/src/hdl/debounce.v
deleted file mode 100644
index 033a4fb552ee7347d5862c49eb3068ddc1a4c23d..0000000000000000000000000000000000000000
--- a/src/hdl/debounce.v
+++ /dev/null
@@ -1,108 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 05/13/2015 09:14:14 PM
-// Design Name:
-// Module Name: debounce
-// Project Name:
-// Target Devices:
-// Tool Versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-
-module debounce(
- input clock,//100MHz clock
- input reset,
- input [4:0] button,//Buttons to debounce
- output reg [4:0]out
-);
-
-reg [12:0] cnt0=0, cnt1=0, cnt2=0, cnt3=0, cnt4;
-reg [4:0] IV = 0;
-
-//parameter dbTime = 19;
-parameter dbTime = 4000;
-
-always @ (posedge(clock))begin
- if(reset==1)begin
- cnt0<=0;
- cnt1<=0;
- cnt2<=0;
- cnt3<=0;
- cnt4<=0;
- out<=0;
- end
- else begin
- if(button[0]==IV[0]) begin
- if (cnt0==dbTime) begin
- out[0]<=IV[0];
- end
- else begin
- cnt0<=cnt0+1;
- end
- end
- else begin
- cnt0<=0;
- IV[0]<=button[0];
- end
- if(button[1]==IV[1]) begin
- if (cnt1==dbTime) begin
- out[1]<=IV[1];
- end
- else begin
- cnt1<=cnt1+1;
- end
- end
- else begin
- cnt1<=0;
- IV[1]<=button[1];
- end
- if(button[2]==IV[2]) begin
- if (cnt2==dbTime) begin
- out[2]<=IV[2];
- end
- else begin
- cnt2<=cnt2+1;
- end
- end
- else begin
- cnt2<=0;
- IV[2]<=button[2];
- end
- if(button[3]==IV[3]) begin
- if (cnt3==dbTime) begin
- out[3]<=IV[3];
- end
- else begin
- cnt3<=cnt3+1;
- end
- end
- else begin
- cnt3<=0;
- IV[3]<=button[3];
- end
- if(button[4]==IV[4]) begin
- if (cnt4==dbTime) begin
- out[4]<=IV[4];
- end
- else begin
- cnt4<=cnt4+1;
- end
- end
- else begin
- cnt4<=0;
- IV[4]<=button[4];
- end
- end
-end
-endmodule
\ No newline at end of file
diff --git a/src/hdl/fir.vhd b/src/hdl/fir.vhd
deleted file mode 100644
index 785d6e4cc41d94861610fdfffcc75a8fd166d83c..0000000000000000000000000000000000000000
--- a/src/hdl/fir.vhd
+++ /dev/null
@@ -1,93 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity fir is
-
- generic (
- dwidth : natural := 18;
- ntaps : natural := 15);
-
- port (
- din : in std_logic_vector(dwidth-1 downto 0);
- dout : out std_logic_vector(dwidth-1 downto 0);
- config_sw : in std_logic_vector(4 downto 0); --inutilise dans le TP majeure
- clk : in std_logic;
- rst : in std_logic;
- ce : in std_logic; -- signal de validation de din a la frequence des echantillons audio
- dbg_output_0 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
- dbg_output_1 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
- dbg_output_2 : out std_logic; --inutilise dans le TP majeure
- dbg_output_3 : out std_logic; --inutilise dans le TP majeure
- dbg_output_4 : out std_logic --inutilise dans le TP majeure
--- dout_valid : out std_logic
- );
-
-end fir;
-
-architecture myarch of fir is
-
- component firUnit is
- port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
- I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0);
- O_filteredSampleValid : out std_logic);
- end component firUnit;
-
-
- signal D_in, D_out : std_logic_vector(7 downto 0);
-
-begin -- myarch
-
--- Quantization on 8 bits or less
-
--- When config_sw(3)='1', rounding is made by finding the nearest value else rounding is made by truncating.
- prc : process (config_sw(3 downto 0), din) is
- begin -- process prc
- case to_integer(unsigned(config_sw(3 downto 0))) is
- when 0 => D_in <= din(dwidth-1 downto dwidth -8);
- when 1 => D_in <= din(dwidth-1 downto dwidth -7)&'0';
- when 2 => D_in <= din(dwidth-1 downto dwidth -6)&"00";
- when 3 => D_in <= din(dwidth-1 downto dwidth -5)&"000";
- when 4 => D_in <= din(dwidth-1 downto dwidth -4)&"0000";
- when 5 => D_in <= din(dwidth-1 downto dwidth -3)&"00000";
- when 6 => D_in <= din(dwidth-1 downto dwidth -2)&"000000";
- when 7 => D_in <= din(dwidth-1)&"0000000";
- when 8 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -8);else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -8))+1); end if;
- when 9 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -7)&'0'; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -7))+1)&'0'; end if;
- when 10 => if din(dwidth-7) = '0' then D_in <= din(dwidth-1 downto dwidth -6)&"00"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -6))+1)&"00"; end if;
- when 11 => if din(dwidth-6) = '0' then D_in <= din(dwidth-1 downto dwidth -5)&"000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -5))+1)&"000"; end if;
- when 12 => if din(dwidth-5) = '0' then D_in <= din(dwidth-1 downto dwidth -4)&"0000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -4))+1)&"0000"; end if;
- when 13 => if din(dwidth-4) = '0' then D_in <= din(dwidth-1 downto dwidth -3)&"00000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -3))+1)&"00000"; end if;
- when 14 => if din(dwidth-3) = '0' then D_in <= din(dwidth-1 downto dwidth -2)&"000000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -2))+1)&"000000"; end if;
- when 15 => D_in <= din(dwidth-1)&"0000000";
- when others => D_in <= (others => '0');
- end case;
- end process prc;
-
---FIR over 8 bits
-
- firUnit_1 : entity work.firUnit
- port map (
- I_clock => clk,
- I_reset => rst,
- I_inputSample => D_in,
- I_inputSampleValid => ce,
- O_filteredSample => D_out,
- O_filteredSampleValid => open);
-
-
--- End of FIR
-
-
- dout(dwidth-1 downto dwidth -8) <= D_out when config_sw(4) = '1' else D_in;
- dout(dwidth-9 downto 0) <= (others => '0');
-
-
-
-
-
-end myarch;
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
deleted file mode 100644
index 2c317f0ec840bcf248f38de4cb7f766b7afb95df..0000000000000000000000000000000000000000
--- a/src/hdl/firUnit.vhd
+++ /dev/null
@@ -1,109 +0,0 @@
--------------------------------------------------------------------------------
--- Title : firUnit
--- Project :
--------------------------------------------------------------------------------
--- File : operativeUnit.vhd
--- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
--- Company :
--- Created : 2018-04-11
--- Last update: 2018-04-11
--- Platform :
--- Standard : VHDL'93/02
--------------------------------------------------------------------------------
--- Description: 8 bit FIR
--------------------------------------------------------------------------------
--- Copyright (c) 2018
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2018-04-11 1.0 jnbazin Created
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity firUnit is
-
- port (
- I_clock : in std_logic; -- global clock
- I_reset : in std_logic; -- asynchronous global reset
- I_inputSample : in std_logic_vector(7 downto 0); -- 8 bit input sample
- I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0); -- filtered sample
- O_filteredSampleValid : out std_logic
- );
-
-end entity firUnit;
-
-architecture archi_firUnit of firUnit is
-
- component controlUnit is
- port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSampleValid : in std_logic;
- I_processingDone : in std_logic;
- O_loadShift : out std_logic;
- O_initAddress : out std_logic;
- O_incrAddress : out std_logic;
- O_initSum : out std_logic;
- O_loadSum : out std_logic;
- O_loadY : out std_logic;
- O_FilteredSampleValid : out std_logic);
- end component controlUnit;
-
- component operativeUnit is
- port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
- I_loadShift : in std_logic;
- I_initAddress : in std_logic;
- I_incrAddress : in std_logic;
- I_initSum : in std_logic;
- I_loadSum : in std_logic;
- I_loadY : in std_logic;
- O_processingDone : out std_logic;
- O_Y : out std_logic_vector(7 downto 0));
- end component operativeUnit;
-
- signal SC_processingDone : std_logic;
- signal SC_loadShift : std_logic;
- signal SC_initAddress : std_logic;
- signal SC_incrAddress : std_logic;
- signal SC_initSum : std_logic;
- signal SC_loadSum : std_logic;
- signal SC_loadY : std_logic;
-
-begin
-
- controlUnit_1 : entity work.controlUnit
- port map (
- I_clock => I_clock,
- I_reset => I_reset,
- I_inputSampleValid => I_inputSampleValid,
- I_processingDone => SC_processingDone,
- O_loadShift => SC_loadShift,
- O_initAddress => SC_initAddress,
- O_incrAddress => SC_incrAddress,
- O_initSum => SC_initSum,
- O_loadSum => SC_loadSum,
- O_loadY => SC_loadY,
- O_FilteredSampleValid => O_FilteredSampleValid);
-
- operativeUnit_1 : entity work.operativeUnit
- port map (
- I_clock => I_clock,
- I_reset => I_reset,
- I_inputSample => I_inputSample,
- I_loadShift => SC_loadShift,
- I_initAddress => SC_initAddress,
- I_incrAddress => SC_incrAddress,
- I_initSum => SC_initSum,
- I_loadSum => SC_loadSum,
- I_loadY => SC_loadY,
- O_processingDone => SC_processingDone,
- O_Y => O_filteredSample);
-
-end architecture archi_firUnit;
diff --git a/src/hdl/i2s_ctl.vhd b/src/hdl/i2s_ctl.vhd
deleted file mode 100644
index 1b608ad94f8e2751241dfec581c148f45cfad09e..0000000000000000000000000000000000000000
--- a/src/hdl/i2s_ctl.vhd
+++ /dev/null
@@ -1,296 +0,0 @@
--------------------------------------------------------------------------------
---
--- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
---
--------------------------------------------------------------------------------
--- FILE NAME : i2s_ctl.vhd
--- MODULE NAME : I2S Control
--- AUTHOR : Mihaita Nagy
--- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
--------------------------------------------------------------------------------
--- REVISION HISTORY
--- VERSION DATE AUTHOR DESCRIPTION
--- 1.0 2012-25-01 Mihaita Nagy Created
--- 2.0 2012-02-04 Mihaita Nagy Remade the i2s_transmitter.vhd and
--- i2s_receiver.vhd into one new module.
--- 3.0 2014-12-02 HegbeliC Implemented edge detection for the
--- master mode and the division rate
--- for the different sampling rates
--------------------------------------------------------------------------------
--- KEYWORDS : I2S
--------------------------------------------------------------------------------
--- DESCRIPTION : This module implements the I2S transmitter and receiver
--- interface, with a 32-bit Stereo data transmission. Parameter
--- C_DATA_WIDTH sets the width of the data to be transmitted,
--- with a maximum value of 32 bits. If a smaller width size is
--- used (i.e. 24) than the remaining bits that needs to be
--- transmitted to complete the 32-bit length, are automaticaly
--- set to 0.
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-------------------------------------------------------------------------
--- Module Declaration
-------------------------------------------------------------------------
-entity i2s_ctl is
- generic (
- -- Width of one Slot (24/20/18/16-bit wide)
- C_DATA_WIDTH: integer := 24
- );
- port (
- CLK_I : in std_logic; -- System clock (100 MHz)
- RST_I : in std_logic; -- System reset
- EN_TX_I : in std_logic; -- Transmit enable
- EN_RX_I : in std_logic; -- Receive enable
- FS_I : in std_logic_vector(3 downto 0); -- Sampling rate slector
- MM_I : in std_logic; -- Audio controler Master Mode delcetor
- D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
- D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
--- OE_L_O : out std_logic; -- Left channel data output enable pulse
--- OE_R_O : out std_logic; -- Right channel data output enable pulse
--- WE_L_O : out std_logic; -- Left channel data write enable pulse
--- WE_R_O : out std_logic; -- Right channel data write enable pulse
- D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
- D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
- BCLK_O : out std_logic; -- serial CLK
- LRCLK_O : out std_logic; -- channel CLK
- SDATA_O : out std_logic; -- Output serial data
- SDATA_I : in std_logic -- Input serial data
- );
-end i2s_ctl;
-
-architecture Behavioral of i2s_ctl is
-
-------------------------------------------------------------------------
--- Signal Declarations
-------------------------------------------------------------------------
--- Counter for the clock divider
-signal Cnt_Bclk : integer range 0 to 31;
-
--- Counter for the L/R clock divider
-signal Cnt_Lrclk : integer range 0 to 31;
-
--- Rising and Falling edge impulses of the serial clock
-signal BCLK_Fall, BCLK_Rise : std_logic;
-signal BCLK_Fall_int, BCLK_Rise_int : std_logic;
---signal BCLK_Fall_shot, BCLK_Rise_shot : std_logic;
-
--- Synchronisation signals for Rising and Falling edge
-signal Q1R, Q2R, Q3R : std_logic;
-signal Q1F, Q2F, Q3F : std_logic;
-
--- Internal synchronous BCLK signal
-signal BCLK_int : std_logic;
-
--- Internal synchronous LRCLK signal
-signal LRCLK_int : std_logic;
-signal LRCLK : std_logic;
-
---
-signal Data_Out_int : std_logic_vector(31 downto 0);
-
---
-signal Data_In_int : std_logic_vector(31 downto 0);
-
---
-signal D_L_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
-
---
-signal D_R_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
-
---Internal synchronous OE signals
-signal OE_R_int, OE_L_int : std_logic;
-
---Internal synchronous WE signals
-signal WE_R_int, WE_L_int : std_logic;
-
--- Division rate for the BCLK and LRCLK
-signal DIV_RATE : natural := 4;
-
-------------------------------------------------------------------------
--- Module Implementation
-------------------------------------------------------------------------
-
-begin
-
-------------------------------------------------------------------------
--- Sampling frequency and data width decoder (DIV_RATE, C_DATA_WIDTH)
-------------------------------------------------------------------------
-
- BIT_FS: process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- case (FS_I) is
- when x"0" => DIV_RATE <= 24;
- when x"1" => DIV_RATE <= 16;
- when x"2" => DIV_RATE <= 12;
- when x"3" => DIV_RATE <= 8;
- when x"4" => DIV_RATE <= 6;
- when x"5" => DIV_RATE <= 4;
- when x"6" => DIV_RATE <= 2;
- when others => DIV_RATE <= 4;
- end case;
- end if;
- end process;
-
-------------------------------------------------------------------------
--- Serial clock generator (BCLK_O, BCLK_Fall, BCLK_Rise)
-------------------------------------------------------------------------
- SER_CLK: process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- Cnt_Bclk <= 0;
- BCLK_int <= '0';
- elsif Cnt_Bclk = ((DIV_RATE/2)-1) then
- Cnt_Bclk <= 0;
- BCLK_int <= not BCLK_int;
- else
- Cnt_Bclk <= Cnt_Bclk + 1;
- end if;
- end if;
- end process SER_CLK;
-
- -- Rising and Falling edges when in Slave mode
- BCLK_Fall_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '1' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
- BCLK_Rise_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '0' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
-
-
-
- -- Falling edge selection with respect to Master Mode bit
- BCLK_Fall <= BCLK_Fall_int;
-
- -- Risesing edge selection with respect to Master Mode bit
- BCLK_Rise <= BCLK_Rise_int;
-
- -- Serial clock output
- BCLK_O <= BCLK_int when EN_RX_I = '1' or EN_TX_I = '1' else '1';
-
-------------------------------------------------------------------------
--- Left/Right clock generator (LRCLK_O, LRCLK_Pls)
-------------------------------------------------------------------------
- LRCLK_GEN: process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- Cnt_Lrclk <= 0;
- LRCLK <= '0'; -- Left channel active by default
- elsif BCLK_Fall = '1' then
- if Cnt_Lrclk = 31 then -- half of frame (64 bits)
- Cnt_Lrclk <= 0;
- LRCLK <= not LRCLK;
- else
- Cnt_Lrclk <= Cnt_Lrclk + 1;
- end if;
- end if;
- end if;
- end process LRCLK_GEN;
-
- -- L/R clock output
- LRCLK_O <= LRCLK when EN_TX_I = '1' or EN_RX_I = '1' else '0';
- LRCLK_int <= LRCLK;
-
-
-------------------------------------------------------------------------
--- Load in paralled data, shift out serial data (SDATA_O)
-------------------------------------------------------------------------
- SER_DATA_O: process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- Data_Out_int(31) <= '0';
- Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; -- Left channel data by default
- Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
- elsif Cnt_Lrclk = 0 and BCLK_Rise = '1' then -- load par. data
- if LRCLK_int = '1' then
- Data_Out_int(31) <= '0';
- Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_R_I;
- Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
- else
- Data_Out_int(31) <= '0';
- Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I;
- Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
- end if;
- elsif BCLK_Fall = '1' then -- shift out ser. data
- Data_Out_int <= Data_Out_int(30 downto 0) & '0';
- end if;
- end if;
- end process SER_DATA_O;
-
- -- Serial data output
- SDATA_O <= Data_Out_int(31) when EN_TX_I = '1' else '0';
-
-------------------------------------------------------------------------
--- Shift in serial data, load out parallel data (SDATA_I)
-------------------------------------------------------------------------
- SER_DATA_I: process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- Data_In_int <= (others => '0');
- D_L_O_int <= (others => '0');
- D_R_O_int <= (others => '0');
- elsif Cnt_Lrclk = 0 and BCLK_Fall = '1' then -- load par. data
- if LRCLK_int = '1' then
- D_L_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
- Data_In_int <= (others => '0');
- else
- D_R_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
- Data_In_int <= (others => '0');
- end if;
- elsif BCLK_Rise = '1' then -- shift in ser. data
- Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
- end if;
- end if;
- end process SER_DATA_I;
-
- D_L_O <= D_L_O_int;
- D_R_O <= D_R_O_int;
-
---------------------------------------------------------------------------
----- Output Enable signals (for FIFO)
---------------------------------------------------------------------------
--- OE_GEN: process(CLK_I)
--- begin
--- if rising_edge(CLK_I) then
--- if Cnt_Lrclk = 31 and BCLK_Fall = '1' then
--- if LRCLK_int = '1' then -- Right channel
--- OE_R_int <= '1';
--- else -- Left channel
--- OE_L_int <= '1';
--- end if;
--- else
--- OE_R_int <= '0';
--- OE_L_int <= '0';
--- end if;
--- end if;
--- end process OE_GEN;
-
--- OE_R_O <= OE_R_int when EN_TX_I = '1' else '0';
--- OE_L_O <= OE_L_int when EN_TX_I = '1' else '0';
-
---------------------------------------------------------------------------
----- Write Enable signals (for FIFO)
---------------------------------------------------------------------------
--- WE_GEN: process(CLK_I)
--- begin
--- if rising_edge(CLK_I) then
--- if Cnt_Lrclk = 1 and BCLK_Rise = '1' then
--- if LRCLK_int = '1' then -- Right channel
--- WE_R_int <= '1';
--- else -- Left channel
--- WE_L_int <= '1';
--- end if;
--- else
--- WE_R_int <= '0';
--- WE_L_int <= '0';
--- end if;
--- end if;
--- end process WE_GEN;
-
--- WE_R_O <= WE_R_int when EN_RX_I = '1' else '0';
--- WE_L_O <= WE_L_int when EN_RX_I = '1' else '0';
-
-end Behavioral;
-
diff --git a/src/hdl/processingUnitIP.v b/src/hdl/processingUnitIP.v
deleted file mode 100644
index 8ca1850662db62f5cc46beeed26fa9fef75e7d4c..0000000000000000000000000000000000000000
--- a/src/hdl/processingUnitIP.v
+++ /dev/null
@@ -1,3270 +0,0 @@
-// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
-// Date : Mon Feb 25 17:59:18 2019
-// Host : marzel-XPS-13-9350 running 64-bit Ubuntu 18.04.2 LTS
-// Command : write_verilog
-// /home/marzel/Documents/enseignements/IMTA_ELEC_A1S2_TAF/UV_ELEC_A1S2/TP_loto_ProcSon/ProcSon/NexysVideo/src/hdl/processingUnitIP.v
-// Design : operativeUnit
-// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
-// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
-// design files.
-// Device : xc7a200tsbg484-1
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* STRUCTURAL_NETLIST = "yes" *)
-module operativeUnit
- (I_clock,
- I_reset,
- I_inputSample,
- I_loadShift,
- I_initAddress,
- I_incrAddress,
- I_initSum,
- I_loadSum,
- I_loadY,
- O_processingDone,
- O_Y);
- input I_clock;
- input I_reset;
- input [7:0]I_inputSample;
- input I_loadShift;
- input I_initAddress;
- input I_incrAddress;
- input I_initSum;
- input I_loadSum;
- input I_loadY;
- output O_processingDone;
- output [7:0]O_Y;
-
- wire \<const0> ;
- wire \<const1> ;
- wire I_clock;
- wire I_clock_IBUF;
- wire I_clock_IBUF_BUFG;
- wire I_incrAddress;
- wire I_incrAddress_IBUF;
- wire I_initAddress;
- wire I_initAddress_IBUF;
- wire I_initSum;
- wire I_initSum_IBUF;
- wire [7:0]I_inputSample;
- wire [7:0]I_inputSample_IBUF;
- wire I_loadShift;
- wire I_loadShift_IBUF;
- wire I_loadSum;
- wire I_loadSum_IBUF;
- wire I_loadY;
- wire I_loadY_IBUF;
- wire I_reset;
- wire I_reset_IBUF;
- wire [14:7]L;
- wire [7:0]O_Y;
- wire [7:0]O_Y_OBUF;
- wire O_processingDone;
- wire O_processingDone_OBUF;
- wire [14:0]SC_MultResult;
- wire [4:0]SC_multOperand2;
- wire \SR_Y[4]_i_11_n_0 ;
- wire \SR_Y[4]_i_12_n_0 ;
- wire \SR_Y[4]_i_13_n_0 ;
- wire \SR_Y[4]_i_14_n_0 ;
- wire \SR_Y[4]_i_15_n_0 ;
- wire \SR_Y[4]_i_16_n_0 ;
- wire \SR_Y[4]_i_17_n_0 ;
- wire \SR_Y[4]_i_18_n_0 ;
- wire \SR_Y[4]_i_19_n_0 ;
- wire \SR_Y[4]_i_20_n_0 ;
- wire \SR_Y[4]_i_21_n_0 ;
- wire \SR_Y[4]_i_22_n_0 ;
- wire \SR_Y[4]_i_23_n_0 ;
- wire \SR_Y[4]_i_24_n_0 ;
- wire \SR_Y[4]_i_25_n_0 ;
- wire \SR_Y[4]_i_26_n_0 ;
- wire \SR_Y[4]_i_28_n_0 ;
- wire \SR_Y[4]_i_29_n_0 ;
- wire \SR_Y[4]_i_30_n_0 ;
- wire \SR_Y[4]_i_32_n_0 ;
- wire \SR_Y[4]_i_33_n_0 ;
- wire \SR_Y[4]_i_34_n_0 ;
- wire \SR_Y[4]_i_35_n_0 ;
- wire \SR_Y[4]_i_36_n_0 ;
- wire \SR_Y[4]_i_37_n_0 ;
- wire \SR_Y[4]_i_38_n_0 ;
- wire \SR_Y[4]_i_39_n_0 ;
- wire \SR_Y[4]_i_40_n_0 ;
- wire \SR_Y[4]_i_41_n_0 ;
- wire \SR_Y[4]_i_42_n_0 ;
- wire \SR_Y[4]_i_43_n_0 ;
- wire \SR_Y[4]_i_44_n_0 ;
- wire \SR_Y[4]_i_45_n_0 ;
- wire \SR_Y[4]_i_46_n_0 ;
- wire \SR_Y[4]_i_47_n_0 ;
- wire \SR_Y[4]_i_48_n_0 ;
- wire \SR_Y[4]_i_49_n_0 ;
- wire \SR_Y[4]_i_50_n_0 ;
- wire \SR_Y[4]_i_51_n_0 ;
- wire \SR_Y[4]_i_5_n_0 ;
- wire \SR_Y[4]_i_6_n_0 ;
- wire \SR_Y[4]_i_7_n_0 ;
- wire \SR_Y[4]_i_8_n_0 ;
- wire \SR_Y[7]_i_11_n_0 ;
- wire \SR_Y[7]_i_12_n_0 ;
- wire \SR_Y[7]_i_13_n_0 ;
- wire \SR_Y[7]_i_15_n_0 ;
- wire \SR_Y[7]_i_16_n_0 ;
- wire \SR_Y[7]_i_17_n_0 ;
- wire \SR_Y[7]_i_18_n_0 ;
- wire \SR_Y[7]_i_19_n_0 ;
- wire \SR_Y[7]_i_20_n_0 ;
- wire \SR_Y[7]_i_21_n_0 ;
- wire \SR_Y[7]_i_22_n_0 ;
- wire \SR_Y[7]_i_25_n_0 ;
- wire \SR_Y[7]_i_26_n_0 ;
- wire \SR_Y[7]_i_27_n_0 ;
- wire \SR_Y[7]_i_28_n_0 ;
- wire \SR_Y[7]_i_3_n_0 ;
- wire \SR_Y[7]_i_42_n_0 ;
- wire \SR_Y[7]_i_43_n_0 ;
- wire \SR_Y[7]_i_44_n_0 ;
- wire \SR_Y[7]_i_45_n_0 ;
- wire \SR_Y[7]_i_46_n_0 ;
- wire \SR_Y[7]_i_47_n_0 ;
- wire \SR_Y[7]_i_48_n_0 ;
- wire \SR_Y[7]_i_49_n_0 ;
- wire \SR_Y[7]_i_50_n_0 ;
- wire \SR_Y[7]_i_51_n_0 ;
- wire \SR_Y[7]_i_52_n_0 ;
- wire \SR_Y[7]_i_53_n_0 ;
- wire \SR_Y[7]_i_54_n_0 ;
- wire \SR_Y[7]_i_55_n_0 ;
- wire \SR_Y[7]_i_56_n_0 ;
- wire \SR_Y[7]_i_57_n_0 ;
- wire \SR_Y[7]_i_5_n_0 ;
- wire \SR_Y[7]_i_6_n_0 ;
- wire \SR_Y[7]_i_7_n_0 ;
- wire \SR_Y[7]_i_9_n_0 ;
- wire \SR_Y_reg[4]_i_10_n_0 ;
- wire \SR_Y_reg[4]_i_10_n_1 ;
- wire \SR_Y_reg[4]_i_10_n_2 ;
- wire \SR_Y_reg[4]_i_10_n_3 ;
- wire \SR_Y_reg[4]_i_27_n_0 ;
- wire \SR_Y_reg[4]_i_27_n_1 ;
- wire \SR_Y_reg[4]_i_27_n_2 ;
- wire \SR_Y_reg[4]_i_27_n_3 ;
- wire \SR_Y_reg[4]_i_27_n_4 ;
- wire \SR_Y_reg[4]_i_27_n_5 ;
- wire \SR_Y_reg[4]_i_27_n_6 ;
- wire \SR_Y_reg[4]_i_27_n_7 ;
- wire \SR_Y_reg[4]_i_2_n_0 ;
- wire \SR_Y_reg[4]_i_2_n_1 ;
- wire \SR_Y_reg[4]_i_2_n_2 ;
- wire \SR_Y_reg[4]_i_2_n_3 ;
- wire \SR_Y_reg[4]_i_3_n_0 ;
- wire \SR_Y_reg[4]_i_3_n_1 ;
- wire \SR_Y_reg[4]_i_3_n_2 ;
- wire \SR_Y_reg[4]_i_3_n_3 ;
- wire \SR_Y_reg[4]_i_3_n_5 ;
- wire \SR_Y_reg[4]_i_4_n_0 ;
- wire \SR_Y_reg[4]_i_4_n_1 ;
- wire \SR_Y_reg[4]_i_4_n_2 ;
- wire \SR_Y_reg[4]_i_4_n_3 ;
- wire \SR_Y_reg[4]_i_9_n_0 ;
- wire \SR_Y_reg[4]_i_9_n_1 ;
- wire \SR_Y_reg[4]_i_9_n_2 ;
- wire \SR_Y_reg[4]_i_9_n_3 ;
- wire \SR_Y_reg[7]_i_10_n_0 ;
- wire \SR_Y_reg[7]_i_10_n_1 ;
- wire \SR_Y_reg[7]_i_10_n_2 ;
- wire \SR_Y_reg[7]_i_10_n_3 ;
- wire \SR_Y_reg[7]_i_10_n_4 ;
- wire \SR_Y_reg[7]_i_10_n_5 ;
- wire \SR_Y_reg[7]_i_10_n_6 ;
- wire \SR_Y_reg[7]_i_10_n_7 ;
- wire \SR_Y_reg[7]_i_14_n_1 ;
- wire \SR_Y_reg[7]_i_14_n_3 ;
- wire \SR_Y_reg[7]_i_14_n_6 ;
- wire \SR_Y_reg[7]_i_14_n_7 ;
- wire \SR_Y_reg[7]_i_2_n_2 ;
- wire \SR_Y_reg[7]_i_2_n_3 ;
- wire \SR_Y_reg[7]_i_33_n_0 ;
- wire \SR_Y_reg[7]_i_34_n_0 ;
- wire \SR_Y_reg[7]_i_35_n_0 ;
- wire \SR_Y_reg[7]_i_36_n_0 ;
- wire \SR_Y_reg[7]_i_38_n_0 ;
- wire \SR_Y_reg[7]_i_39_n_0 ;
- wire \SR_Y_reg[7]_i_40_n_0 ;
- wire \SR_Y_reg[7]_i_41_n_0 ;
- wire \SR_Y_reg[7]_i_4_n_1 ;
- wire \SR_Y_reg[7]_i_4_n_2 ;
- wire \SR_Y_reg[7]_i_4_n_3 ;
- wire \SR_Y_reg[7]_i_8_n_2 ;
- wire \SR_Y_reg[7]_i_8_n_3 ;
- wire \SR_Y_reg[7]_i_8_n_5 ;
- wire \SR_Y_reg[7]_i_8_n_6 ;
- wire \SR_Y_reg[7]_i_8_n_7 ;
- wire \SR_readAddress[0]_i_1_n_0 ;
- wire \SR_readAddress[1]_i_1_n_0 ;
- wire \SR_readAddress[2]_i_1_n_0 ;
- wire \SR_readAddress[3]_i_1_n_0 ;
- wire \SR_readAddress[3]_i_2_n_0 ;
- wire [3:0]SR_readAddress_reg__0;
- wire [7:0]\SR_shiftRegister[0] ;
- wire [7:0]\SR_shiftRegister_reg[0]__0 ;
- wire [7:0]\SR_shiftRegister_reg[10]__0 ;
- wire [7:0]\SR_shiftRegister_reg[11]__0 ;
- wire [7:0]\SR_shiftRegister_reg[12]__0 ;
- wire [7:0]\SR_shiftRegister_reg[13]__0 ;
- wire [7:0]\SR_shiftRegister_reg[14]__0 ;
- wire [7:0]\SR_shiftRegister_reg[15]__0 ;
- wire [7:0]\SR_shiftRegister_reg[1]__0 ;
- wire [7:0]\SR_shiftRegister_reg[2]__0 ;
- wire [7:0]\SR_shiftRegister_reg[3]__0 ;
- wire [7:0]\SR_shiftRegister_reg[4]__0 ;
- wire [7:0]\SR_shiftRegister_reg[5]__0 ;
- wire [7:0]\SR_shiftRegister_reg[6]__0 ;
- wire [7:0]\SR_shiftRegister_reg[7]__0 ;
- wire [7:0]\SR_shiftRegister_reg[8]__0 ;
- wire [7:0]\SR_shiftRegister_reg[9]__0 ;
- wire \SR_sum[0]_i_10_n_0 ;
- wire \SR_sum[0]_i_13_n_0 ;
- wire \SR_sum[0]_i_14_n_0 ;
- wire \SR_sum[0]_i_15_n_0 ;
- wire \SR_sum[0]_i_16_n_0 ;
- wire \SR_sum[0]_i_17_n_0 ;
- wire \SR_sum[0]_i_18_n_0 ;
- wire \SR_sum[0]_i_19_n_0 ;
- wire \SR_sum[0]_i_1_n_0 ;
- wire \SR_sum[0]_i_20_n_0 ;
- wire \SR_sum[0]_i_21_n_0 ;
- wire \SR_sum[0]_i_22_n_0 ;
- wire \SR_sum[0]_i_23_n_0 ;
- wire \SR_sum[0]_i_24_n_0 ;
- wire \SR_sum[0]_i_25_n_0 ;
- wire \SR_sum[0]_i_26_n_0 ;
- wire \SR_sum[0]_i_27_n_0 ;
- wire \SR_sum[0]_i_31_n_0 ;
- wire \SR_sum[0]_i_32_n_0 ;
- wire \SR_sum[0]_i_33_n_0 ;
- wire \SR_sum[0]_i_3_n_0 ;
- wire \SR_sum[0]_i_45_n_0 ;
- wire \SR_sum[0]_i_46_n_0 ;
- wire \SR_sum[0]_i_47_n_0 ;
- wire \SR_sum[0]_i_48_n_0 ;
- wire \SR_sum[0]_i_49_n_0 ;
- wire \SR_sum[0]_i_4_n_0 ;
- wire \SR_sum[0]_i_50_n_0 ;
- wire \SR_sum[0]_i_51_n_0 ;
- wire \SR_sum[0]_i_52_n_0 ;
- wire \SR_sum[0]_i_53_n_0 ;
- wire \SR_sum[0]_i_54_n_0 ;
- wire \SR_sum[0]_i_55_n_0 ;
- wire \SR_sum[0]_i_56_n_0 ;
- wire \SR_sum[0]_i_57_n_0 ;
- wire \SR_sum[0]_i_58_n_0 ;
- wire \SR_sum[0]_i_59_n_0 ;
- wire \SR_sum[0]_i_5_n_0 ;
- wire \SR_sum[0]_i_60_n_0 ;
- wire \SR_sum[0]_i_6_n_0 ;
- wire \SR_sum[0]_i_7_n_0 ;
- wire \SR_sum[0]_i_8_n_0 ;
- wire \SR_sum[0]_i_9_n_0 ;
- wire \SR_sum[12]_i_2_n_0 ;
- wire \SR_sum[12]_i_3_n_0 ;
- wire \SR_sum[12]_i_4_n_0 ;
- wire \SR_sum[12]_i_5_n_0 ;
- wire \SR_sum[12]_i_6_n_0 ;
- wire \SR_sum[4]_i_2_n_0 ;
- wire \SR_sum[4]_i_3_n_0 ;
- wire \SR_sum[4]_i_4_n_0 ;
- wire \SR_sum[4]_i_5_n_0 ;
- wire \SR_sum[4]_i_6_n_0 ;
- wire \SR_sum[4]_i_7_n_0 ;
- wire \SR_sum[4]_i_8_n_0 ;
- wire \SR_sum[4]_i_9_n_0 ;
- wire \SR_sum[8]_i_2_n_0 ;
- wire \SR_sum[8]_i_3_n_0 ;
- wire \SR_sum[8]_i_4_n_0 ;
- wire \SR_sum[8]_i_5_n_0 ;
- wire \SR_sum[8]_i_6_n_0 ;
- wire \SR_sum[8]_i_7_n_0 ;
- wire \SR_sum[8]_i_8_n_0 ;
- wire \SR_sum[8]_i_9_n_0 ;
- wire [14:0]SR_sum_reg;
- wire \SR_sum_reg[0]_i_11_n_0 ;
- wire \SR_sum_reg[0]_i_11_n_1 ;
- wire \SR_sum_reg[0]_i_11_n_2 ;
- wire \SR_sum_reg[0]_i_11_n_3 ;
- wire \SR_sum_reg[0]_i_11_n_4 ;
- wire \SR_sum_reg[0]_i_11_n_5 ;
- wire \SR_sum_reg[0]_i_11_n_6 ;
- wire \SR_sum_reg[0]_i_11_n_7 ;
- wire \SR_sum_reg[0]_i_12_n_0 ;
- wire \SR_sum_reg[0]_i_12_n_1 ;
- wire \SR_sum_reg[0]_i_12_n_2 ;
- wire \SR_sum_reg[0]_i_12_n_3 ;
- wire \SR_sum_reg[0]_i_12_n_4 ;
- wire \SR_sum_reg[0]_i_2_n_0 ;
- wire \SR_sum_reg[0]_i_2_n_1 ;
- wire \SR_sum_reg[0]_i_2_n_2 ;
- wire \SR_sum_reg[0]_i_2_n_3 ;
- wire \SR_sum_reg[0]_i_2_n_4 ;
- wire \SR_sum_reg[0]_i_2_n_5 ;
- wire \SR_sum_reg[0]_i_2_n_6 ;
- wire \SR_sum_reg[0]_i_2_n_7 ;
- wire \SR_sum_reg[0]_i_37_n_0 ;
- wire \SR_sum_reg[0]_i_38_n_0 ;
- wire \SR_sum_reg[0]_i_39_n_0 ;
- wire \SR_sum_reg[0]_i_40_n_0 ;
- wire \SR_sum_reg[0]_i_41_n_0 ;
- wire \SR_sum_reg[0]_i_42_n_0 ;
- wire \SR_sum_reg[0]_i_43_n_0 ;
- wire \SR_sum_reg[0]_i_44_n_0 ;
- wire \SR_sum_reg[12]_i_1_n_2 ;
- wire \SR_sum_reg[12]_i_1_n_3 ;
- wire \SR_sum_reg[12]_i_1_n_5 ;
- wire \SR_sum_reg[12]_i_1_n_6 ;
- wire \SR_sum_reg[12]_i_1_n_7 ;
- wire \SR_sum_reg[4]_i_1_n_0 ;
- wire \SR_sum_reg[4]_i_1_n_1 ;
- wire \SR_sum_reg[4]_i_1_n_2 ;
- wire \SR_sum_reg[4]_i_1_n_3 ;
- wire \SR_sum_reg[4]_i_1_n_4 ;
- wire \SR_sum_reg[4]_i_1_n_5 ;
- wire \SR_sum_reg[4]_i_1_n_6 ;
- wire \SR_sum_reg[4]_i_1_n_7 ;
- wire \SR_sum_reg[8]_i_1_n_0 ;
- wire \SR_sum_reg[8]_i_1_n_1 ;
- wire \SR_sum_reg[8]_i_1_n_2 ;
- wire \SR_sum_reg[8]_i_1_n_3 ;
- wire \SR_sum_reg[8]_i_1_n_4 ;
- wire \SR_sum_reg[8]_i_1_n_5 ;
- wire \SR_sum_reg[8]_i_1_n_6 ;
- wire \SR_sum_reg[8]_i_1_n_7 ;
- wire [7:0]p_0_in;
- wire [3:0]\NLW_SR_Y_reg[4]_i_10_O_UNCONNECTED ;
- wire [3:0]\NLW_SR_Y_reg[4]_i_3_O_UNCONNECTED ;
- wire [3:0]\NLW_SR_Y_reg[7]_i_14_CO_UNCONNECTED ;
-
- GND GND
- (.G(\<const0> ));
- BUFG I_clock_IBUF_BUFG_inst
- (.I(I_clock_IBUF),
- .O(I_clock_IBUF_BUFG));
- IBUF I_clock_IBUF_inst
- (.I(I_clock),
- .O(I_clock_IBUF));
- IBUF I_incrAddress_IBUF_inst
- (.I(I_incrAddress),
- .O(I_incrAddress_IBUF));
- IBUF I_initAddress_IBUF_inst
- (.I(I_initAddress),
- .O(I_initAddress_IBUF));
- IBUF I_initSum_IBUF_inst
- (.I(I_initSum),
- .O(I_initSum_IBUF));
- IBUF \I_inputSample_IBUF[0]_inst
- (.I(I_inputSample[0]),
- .O(I_inputSample_IBUF[0]));
- IBUF \I_inputSample_IBUF[1]_inst
- (.I(I_inputSample[1]),
- .O(I_inputSample_IBUF[1]));
- IBUF \I_inputSample_IBUF[2]_inst
- (.I(I_inputSample[2]),
- .O(I_inputSample_IBUF[2]));
- IBUF \I_inputSample_IBUF[3]_inst
- (.I(I_inputSample[3]),
- .O(I_inputSample_IBUF[3]));
- IBUF \I_inputSample_IBUF[4]_inst
- (.I(I_inputSample[4]),
- .O(I_inputSample_IBUF[4]));
- IBUF \I_inputSample_IBUF[5]_inst
- (.I(I_inputSample[5]),
- .O(I_inputSample_IBUF[5]));
- IBUF \I_inputSample_IBUF[6]_inst
- (.I(I_inputSample[6]),
- .O(I_inputSample_IBUF[6]));
- IBUF \I_inputSample_IBUF[7]_inst
- (.I(I_inputSample[7]),
- .O(I_inputSample_IBUF[7]));
- IBUF I_loadShift_IBUF_inst
- (.I(I_loadShift),
- .O(I_loadShift_IBUF));
- IBUF I_loadSum_IBUF_inst
- (.I(I_loadSum),
- .O(I_loadSum_IBUF));
- IBUF I_loadY_IBUF_inst
- (.I(I_loadY),
- .O(I_loadY_IBUF));
- IBUF I_reset_IBUF_inst
- (.I(I_reset),
- .O(I_reset_IBUF));
- OBUF \O_Y_OBUF[0]_inst
- (.I(O_Y_OBUF[0]),
- .O(O_Y[0]));
- OBUF \O_Y_OBUF[1]_inst
- (.I(O_Y_OBUF[1]),
- .O(O_Y[1]));
- OBUF \O_Y_OBUF[2]_inst
- (.I(O_Y_OBUF[2]),
- .O(O_Y[2]));
- OBUF \O_Y_OBUF[3]_inst
- (.I(O_Y_OBUF[3]),
- .O(O_Y[3]));
- OBUF \O_Y_OBUF[4]_inst
- (.I(O_Y_OBUF[4]),
- .O(O_Y[4]));
- OBUF \O_Y_OBUF[5]_inst
- (.I(O_Y_OBUF[5]),
- .O(O_Y[5]));
- OBUF \O_Y_OBUF[6]_inst
- (.I(O_Y_OBUF[6]),
- .O(O_Y[6]));
- OBUF \O_Y_OBUF[7]_inst
- (.I(O_Y_OBUF[7]),
- .O(O_Y[7]));
- OBUF O_processingDone_OBUF_inst
- (.I(O_processingDone_OBUF),
- .O(O_processingDone));
- LUT3 #(
- .INIT(8'h80))
- O_processingDone_OBUF_inst_i_1
- (.I0(SR_readAddress_reg__0[1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[2]),
- .O(O_processingDone_OBUF));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[0]_i_1
- (.I0(\SR_Y_reg[4]_i_3_n_5 ),
- .I1(L[7]),
- .O(p_0_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT3 #(
- .INIT(8'h78))
- \SR_Y[1]_i_1
- (.I0(\SR_Y_reg[4]_i_3_n_5 ),
- .I1(L[7]),
- .I2(L[8]),
- .O(p_0_in[1]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h7F80))
- \SR_Y[2]_i_1
- (.I0(L[7]),
- .I1(\SR_Y_reg[4]_i_3_n_5 ),
- .I2(L[8]),
- .I3(L[9]),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT5 #(
- .INIT(32'h7FFF8000))
- \SR_Y[3]_i_1
- (.I0(L[8]),
- .I1(\SR_Y_reg[4]_i_3_n_5 ),
- .I2(L[7]),
- .I3(L[9]),
- .I4(L[10]),
- .O(p_0_in[3]));
- LUT6 #(
- .INIT(64'h7FFFFFFF80000000))
- \SR_Y[4]_i_1
- (.I0(L[9]),
- .I1(L[7]),
- .I2(\SR_Y_reg[4]_i_3_n_5 ),
- .I3(L[8]),
- .I4(L[10]),
- .I5(L[11]),
- .O(p_0_in[4]));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_11
- (.I0(SC_MultResult[7]),
- .I1(SR_sum_reg[7]),
- .O(\SR_Y[4]_i_11_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_12
- (.I0(SC_MultResult[6]),
- .I1(SR_sum_reg[6]),
- .O(\SR_Y[4]_i_12_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_13
- (.I0(SC_MultResult[5]),
- .I1(SR_sum_reg[5]),
- .O(\SR_Y[4]_i_13_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_14
- (.I0(SC_MultResult[4]),
- .I1(SR_sum_reg[4]),
- .O(\SR_Y[4]_i_14_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \SR_Y[4]_i_15
- (.I0(\SR_Y_reg[7]_i_10_n_5 ),
- .I1(\SR_Y_reg[7]_i_14_n_6 ),
- .O(\SR_Y[4]_i_15_n_0 ));
- LUT2 #(
- .INIT(4'h8))
- \SR_Y[4]_i_16
- (.I0(\SR_Y_reg[7]_i_10_n_6 ),
- .I1(\SR_Y_reg[7]_i_14_n_7 ),
- .O(\SR_Y[4]_i_16_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \SR_Y[4]_i_17
- (.I0(\SR_Y_reg[4]_i_27_n_4 ),
- .I1(\SR_Y_reg[7]_i_10_n_7 ),
- .O(\SR_Y[4]_i_17_n_0 ));
- LUT2 #(
- .INIT(4'h9))
- \SR_Y[4]_i_18
- (.I0(\SR_Y_reg[7]_i_10_n_7 ),
- .I1(\SR_Y_reg[4]_i_27_n_4 ),
- .O(\SR_Y[4]_i_18_n_0 ));
- LUT4 #(
- .INIT(16'h8778))
- \SR_Y[4]_i_19
- (.I0(\SR_Y_reg[7]_i_14_n_6 ),
- .I1(\SR_Y_reg[7]_i_10_n_5 ),
- .I2(\SR_Y_reg[7]_i_10_n_4 ),
- .I3(\SR_Y_reg[7]_i_14_n_1 ),
- .O(\SR_Y[4]_i_19_n_0 ));
- LUT4 #(
- .INIT(16'h8778))
- \SR_Y[4]_i_20
- (.I0(\SR_Y_reg[7]_i_14_n_7 ),
- .I1(\SR_Y_reg[7]_i_10_n_6 ),
- .I2(\SR_Y_reg[7]_i_10_n_5 ),
- .I3(\SR_Y_reg[7]_i_14_n_6 ),
- .O(\SR_Y[4]_i_20_n_0 ));
- LUT4 #(
- .INIT(16'hE11E))
- \SR_Y[4]_i_21
- (.I0(\SR_Y_reg[7]_i_10_n_7 ),
- .I1(\SR_Y_reg[4]_i_27_n_4 ),
- .I2(\SR_Y_reg[7]_i_10_n_6 ),
- .I3(\SR_Y_reg[7]_i_14_n_7 ),
- .O(\SR_Y[4]_i_21_n_0 ));
- LUT4 #(
- .INIT(16'h6999))
- \SR_Y[4]_i_22
- (.I0(\SR_Y_reg[7]_i_10_n_7 ),
- .I1(\SR_Y_reg[4]_i_27_n_4 ),
- .I2(\SR_Y_reg[4]_i_27_n_5 ),
- .I3(\SR_sum_reg[0]_i_11_n_4 ),
- .O(\SR_Y[4]_i_22_n_0 ));
- LUT3 #(
- .INIT(8'h96))
- \SR_Y[4]_i_23
- (.I0(\SR_sum_reg[0]_i_11_n_7 ),
- .I1(\SR_sum_reg[0]_i_12_n_4 ),
- .I2(SR_sum_reg[3]),
- .O(\SR_Y[4]_i_23_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_24
- (.I0(SC_MultResult[2]),
- .I1(SR_sum_reg[2]),
- .O(\SR_Y[4]_i_24_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_25
- (.I0(SC_MultResult[1]),
- .I1(SR_sum_reg[1]),
- .O(\SR_Y[4]_i_25_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_26
- (.I0(SC_MultResult[0]),
- .I1(SR_sum_reg[0]),
- .O(\SR_Y[4]_i_26_n_0 ));
- LUT3 #(
- .INIT(8'h96))
- \SR_Y[4]_i_28
- (.I0(\SR_sum_reg[0]_i_11_n_5 ),
- .I1(\SR_sum_reg[0]_i_11_n_4 ),
- .I2(\SR_Y_reg[4]_i_27_n_5 ),
- .O(\SR_Y[4]_i_28_n_0 ));
- LUT2 #(
- .INIT(4'h9))
- \SR_Y[4]_i_29
- (.I0(\SR_sum_reg[0]_i_11_n_5 ),
- .I1(\SR_Y_reg[4]_i_27_n_6 ),
- .O(\SR_Y[4]_i_29_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_30
- (.I0(\SR_Y_reg[4]_i_27_n_7 ),
- .I1(\SR_sum_reg[0]_i_11_n_6 ),
- .O(\SR_Y[4]_i_30_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_31
- (.I0(\SR_sum_reg[0]_i_12_n_4 ),
- .I1(\SR_sum_reg[0]_i_11_n_7 ),
- .O(SC_MultResult[3]));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_32
- (.I0(\SR_Y[4]_i_40_n_0 ),
- .I1(\SR_Y[4]_i_41_n_0 ),
- .I2(\SR_Y[4]_i_42_n_0 ),
- .O(\SR_Y[4]_i_32_n_0 ));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_33
- (.I0(\SR_Y[4]_i_43_n_0 ),
- .I1(\SR_Y[4]_i_44_n_0 ),
- .I2(\SR_Y[4]_i_45_n_0 ),
- .O(\SR_Y[4]_i_33_n_0 ));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_34
- (.I0(\SR_Y[4]_i_46_n_0 ),
- .I1(\SR_Y[4]_i_47_n_0 ),
- .I2(\SR_Y[4]_i_48_n_0 ),
- .O(\SR_Y[4]_i_34_n_0 ));
- LUT3 #(
- .INIT(8'h17))
- \SR_Y[4]_i_35
- (.I0(\SR_sum[0]_i_32_n_0 ),
- .I1(\SR_sum[0]_i_31_n_0 ),
- .I2(\SR_sum[0]_i_33_n_0 ),
- .O(\SR_Y[4]_i_35_n_0 ));
- LUT4 #(
- .INIT(16'h6996))
- \SR_Y[4]_i_36
- (.I0(\SR_Y[4]_i_32_n_0 ),
- .I1(\SR_Y[4]_i_49_n_0 ),
- .I2(\SR_Y[4]_i_50_n_0 ),
- .I3(\SR_Y[4]_i_51_n_0 ),
- .O(\SR_Y[4]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'h17E8E817E81717E8))
- \SR_Y[4]_i_37
- (.I0(\SR_Y[4]_i_45_n_0 ),
- .I1(\SR_Y[4]_i_44_n_0 ),
- .I2(\SR_Y[4]_i_43_n_0 ),
- .I3(\SR_Y[4]_i_41_n_0 ),
- .I4(\SR_Y[4]_i_40_n_0 ),
- .I5(\SR_Y[4]_i_42_n_0 ),
- .O(\SR_Y[4]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'h17E8E817E81717E8))
- \SR_Y[4]_i_38
- (.I0(\SR_Y[4]_i_48_n_0 ),
- .I1(\SR_Y[4]_i_47_n_0 ),
- .I2(\SR_Y[4]_i_46_n_0 ),
- .I3(\SR_Y[4]_i_44_n_0 ),
- .I4(\SR_Y[4]_i_43_n_0 ),
- .I5(\SR_Y[4]_i_45_n_0 ),
- .O(\SR_Y[4]_i_38_n_0 ));
- LUT6 #(
- .INIT(64'h17E8E817E81717E8))
- \SR_Y[4]_i_39
- (.I0(\SR_sum[0]_i_33_n_0 ),
- .I1(\SR_sum[0]_i_31_n_0 ),
- .I2(\SR_sum[0]_i_32_n_0 ),
- .I3(\SR_Y[4]_i_47_n_0 ),
- .I4(\SR_Y[4]_i_46_n_0 ),
- .I5(\SR_Y[4]_i_48_n_0 ),
- .O(\SR_Y[4]_i_39_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_40
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_40_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_41
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_41_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_42
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_42_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_43
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_43_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_44
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_44_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_45
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_45_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_46
- (.I0(\SR_shiftRegister[0] [2]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_46_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_47
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_47_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_48
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_48_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_Y[4]_i_49
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[4]_i_49_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_5
- (.I0(SC_MultResult[11]),
- .I1(SR_sum_reg[11]),
- .O(\SR_Y[4]_i_5_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_Y[4]_i_50
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_50_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_Y[4]_i_51
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_Y[4]_i_51_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_6
- (.I0(SC_MultResult[10]),
- .I1(SR_sum_reg[10]),
- .O(\SR_Y[4]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_7
- (.I0(SC_MultResult[9]),
- .I1(SR_sum_reg[9]),
- .O(\SR_Y[4]_i_7_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[4]_i_8
- (.I0(SC_MultResult[8]),
- .I1(SR_sum_reg[8]),
- .O(\SR_Y[4]_i_8_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[5]_i_1
- (.I0(\SR_Y[7]_i_3_n_0 ),
- .I1(L[12]),
- .O(p_0_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT3 #(
- .INIT(8'h78))
- \SR_Y[6]_i_1
- (.I0(\SR_Y[7]_i_3_n_0 ),
- .I1(L[12]),
- .I2(L[13]),
- .O(p_0_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h7F80))
- \SR_Y[7]_i_1
- (.I0(L[12]),
- .I1(\SR_Y[7]_i_3_n_0 ),
- .I2(L[13]),
- .I3(L[14]),
- .O(p_0_in[7]));
- LUT6 #(
- .INIT(64'hFFF55FFFDDF55F77))
- \SR_Y[7]_i_11
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [6]),
- .O(\SR_Y[7]_i_11_n_0 ));
- LUT5 #(
- .INIT(32'hFDDD777F))
- \SR_Y[7]_i_12
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_Y[7]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hDDC00377FFFFFFFF))
- \SR_Y[7]_i_13
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [7]),
- .O(\SR_Y[7]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_15
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [5]),
- .O(\SR_Y[7]_i_15_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_16
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [4]),
- .O(\SR_Y[7]_i_16_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_17
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [3]),
- .O(\SR_Y[7]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'h333AACCC220AA088))
- \SR_Y[7]_i_18
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_Y[7]_i_18_n_0 ));
- LUT5 #(
- .INIT(32'hD32C6060))
- \SR_Y[7]_i_19
- (.I0(\SR_shiftRegister[0] [5]),
- .I1(\SR_shiftRegister[0] [6]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [7]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h2CD39F9F))
- \SR_Y[7]_i_20
- (.I0(\SR_shiftRegister[0] [4]),
- .I1(\SR_shiftRegister[0] [5]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [6]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_20_n_0 ));
- LUT5 #(
- .INIT(32'h2CD39F9F))
- \SR_Y[7]_i_21
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(\SR_shiftRegister[0] [4]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [5]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_21_n_0 ));
- LUT5 #(
- .INIT(32'h2CD39F9F))
- \SR_Y[7]_i_22
- (.I0(\SR_shiftRegister[0] [2]),
- .I1(\SR_shiftRegister[0] [3]),
- .I2(SC_multOperand2[4]),
- .I3(\SR_shiftRegister[0] [4]),
- .I4(SC_multOperand2[3]),
- .O(\SR_Y[7]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'h134001C400000000))
- \SR_Y[7]_i_25
- (.I0(\SR_shiftRegister[0] [7]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [6]),
- .O(\SR_Y[7]_i_25_n_0 ));
- LUT3 #(
- .INIT(8'h71))
- \SR_Y[7]_i_26
- (.I0(\SR_Y[4]_i_50_n_0 ),
- .I1(\SR_Y[4]_i_49_n_0 ),
- .I2(\SR_Y[4]_i_51_n_0 ),
- .O(\SR_Y[7]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hCE3FFCB3DD7FFD77))
- \SR_Y[7]_i_27
- (.I0(\SR_shiftRegister[0] [6]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [7]),
- .O(\SR_Y[7]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'h8171FC0C1EEE3CCC))
- \SR_Y[7]_i_28
- (.I0(SC_multOperand2[0]),
- .I1(\SR_Y[4]_i_50_n_0 ),
- .I2(\SR_shiftRegister[0] [6]),
- .I3(SC_multOperand2[2]),
- .I4(\SR_shiftRegister[0] [7]),
- .I5(SC_multOperand2[1]),
- .O(\SR_Y[7]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \SR_Y[7]_i_3
- (.I0(L[11]),
- .I1(L[9]),
- .I2(L[7]),
- .I3(\SR_Y_reg[4]_i_3_n_5 ),
- .I4(L[8]),
- .I5(L[10]),
- .O(\SR_Y[7]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h542A))
- \SR_Y[7]_i_31
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .O(SC_multOperand2[4]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT4 #(
- .INIT(16'h724E))
- \SR_Y[7]_i_32
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .O(SC_multOperand2[3]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT4 #(
- .INIT(16'h6006))
- \SR_Y[7]_i_37
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[1]),
- .O(SC_multOperand2[0]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_42
- (.I0(\SR_shiftRegister_reg[3]__0 [7]),
- .I1(\SR_shiftRegister_reg[2]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [7]),
- .O(\SR_Y[7]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_43
- (.I0(\SR_shiftRegister_reg[7]__0 [7]),
- .I1(\SR_shiftRegister_reg[6]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [7]),
- .O(\SR_Y[7]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_44
- (.I0(\SR_shiftRegister_reg[11]__0 [7]),
- .I1(\SR_shiftRegister_reg[10]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [7]),
- .O(\SR_Y[7]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_45
- (.I0(\SR_shiftRegister_reg[15]__0 [7]),
- .I1(\SR_shiftRegister_reg[14]__0 [7]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [7]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [7]),
- .O(\SR_Y[7]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_46
- (.I0(\SR_shiftRegister_reg[3]__0 [6]),
- .I1(\SR_shiftRegister_reg[2]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [6]),
- .O(\SR_Y[7]_i_46_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_47
- (.I0(\SR_shiftRegister_reg[7]__0 [6]),
- .I1(\SR_shiftRegister_reg[6]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [6]),
- .O(\SR_Y[7]_i_47_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_48
- (.I0(\SR_shiftRegister_reg[11]__0 [6]),
- .I1(\SR_shiftRegister_reg[10]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [6]),
- .O(\SR_Y[7]_i_48_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_49
- (.I0(\SR_shiftRegister_reg[15]__0 [6]),
- .I1(\SR_shiftRegister_reg[14]__0 [6]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [6]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [6]),
- .O(\SR_Y[7]_i_49_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[7]_i_5
- (.I0(SR_sum_reg[14]),
- .I1(SC_MultResult[14]),
- .O(\SR_Y[7]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_50
- (.I0(\SR_shiftRegister_reg[3]__0 [5]),
- .I1(\SR_shiftRegister_reg[2]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [5]),
- .O(\SR_Y[7]_i_50_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_51
- (.I0(\SR_shiftRegister_reg[7]__0 [5]),
- .I1(\SR_shiftRegister_reg[6]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [5]),
- .O(\SR_Y[7]_i_51_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_52
- (.I0(\SR_shiftRegister_reg[11]__0 [5]),
- .I1(\SR_shiftRegister_reg[10]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [5]),
- .O(\SR_Y[7]_i_52_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_53
- (.I0(\SR_shiftRegister_reg[15]__0 [5]),
- .I1(\SR_shiftRegister_reg[14]__0 [5]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [5]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [5]),
- .O(\SR_Y[7]_i_53_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_54
- (.I0(\SR_shiftRegister_reg[3]__0 [4]),
- .I1(\SR_shiftRegister_reg[2]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [4]),
- .O(\SR_Y[7]_i_54_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_55
- (.I0(\SR_shiftRegister_reg[7]__0 [4]),
- .I1(\SR_shiftRegister_reg[6]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [4]),
- .O(\SR_Y[7]_i_55_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_56
- (.I0(\SR_shiftRegister_reg[11]__0 [4]),
- .I1(\SR_shiftRegister_reg[10]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [4]),
- .O(\SR_Y[7]_i_56_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_Y[7]_i_57
- (.I0(\SR_shiftRegister_reg[15]__0 [4]),
- .I1(\SR_shiftRegister_reg[14]__0 [4]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [4]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [4]),
- .O(\SR_Y[7]_i_57_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[7]_i_6
- (.I0(SC_MultResult[13]),
- .I1(SR_sum_reg[13]),
- .O(\SR_Y[7]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h6))
- \SR_Y[7]_i_7
- (.I0(SC_MultResult[12]),
- .I1(SR_sum_reg[12]),
- .O(\SR_Y[7]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h78))
- \SR_Y[7]_i_9
- (.I0(\SR_Y_reg[7]_i_14_n_1 ),
- .I1(\SR_Y_reg[7]_i_10_n_4 ),
- .I2(\SR_Y_reg[7]_i_8_n_7 ),
- .O(\SR_Y[7]_i_9_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[0]),
- .Q(O_Y_OBUF[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[1]),
- .Q(O_Y_OBUF[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[2]),
- .Q(O_Y_OBUF[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[3]),
- .Q(O_Y_OBUF[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[4]),
- .Q(O_Y_OBUF[4]));
- CARRY4 \SR_Y_reg[4]_i_10
- (.CI(\<const0> ),
- .CO({\SR_Y_reg[4]_i_10_n_0 ,\SR_Y_reg[4]_i_10_n_1 ,\SR_Y_reg[4]_i_10_n_2 ,\SR_Y_reg[4]_i_10_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum_reg[0]_i_11_n_5 ,\SR_Y_reg[4]_i_27_n_6 ,\SR_Y_reg[4]_i_27_n_7 ,\SR_sum_reg[0]_i_12_n_4 }),
- .O({SC_MultResult[6:4],\NLW_SR_Y_reg[4]_i_10_O_UNCONNECTED [0]}),
- .S({\SR_Y[4]_i_28_n_0 ,\SR_Y[4]_i_29_n_0 ,\SR_Y[4]_i_30_n_0 ,SC_MultResult[3]}));
- CARRY4 \SR_Y_reg[4]_i_2
- (.CI(\SR_Y_reg[4]_i_3_n_0 ),
- .CO({\SR_Y_reg[4]_i_2_n_0 ,\SR_Y_reg[4]_i_2_n_1 ,\SR_Y_reg[4]_i_2_n_2 ,\SR_Y_reg[4]_i_2_n_3 }),
- .CYINIT(\<const0> ),
- .DI(SC_MultResult[11:8]),
- .O(L[11:8]),
- .S({\SR_Y[4]_i_5_n_0 ,\SR_Y[4]_i_6_n_0 ,\SR_Y[4]_i_7_n_0 ,\SR_Y[4]_i_8_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_27
- (.CI(\SR_sum_reg[0]_i_12_n_0 ),
- .CO({\SR_Y_reg[4]_i_27_n_0 ,\SR_Y_reg[4]_i_27_n_1 ,\SR_Y_reg[4]_i_27_n_2 ,\SR_Y_reg[4]_i_27_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_Y[4]_i_32_n_0 ,\SR_Y[4]_i_33_n_0 ,\SR_Y[4]_i_34_n_0 ,\SR_Y[4]_i_35_n_0 }),
- .O({\SR_Y_reg[4]_i_27_n_4 ,\SR_Y_reg[4]_i_27_n_5 ,\SR_Y_reg[4]_i_27_n_6 ,\SR_Y_reg[4]_i_27_n_7 }),
- .S({\SR_Y[4]_i_36_n_0 ,\SR_Y[4]_i_37_n_0 ,\SR_Y[4]_i_38_n_0 ,\SR_Y[4]_i_39_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_3
- (.CI(\SR_Y_reg[4]_i_9_n_0 ),
- .CO({\SR_Y_reg[4]_i_3_n_0 ,\SR_Y_reg[4]_i_3_n_1 ,\SR_Y_reg[4]_i_3_n_2 ,\SR_Y_reg[4]_i_3_n_3 }),
- .CYINIT(\<const0> ),
- .DI(SC_MultResult[7:4]),
- .O({L[7],\SR_Y_reg[4]_i_3_n_5 ,\NLW_SR_Y_reg[4]_i_3_O_UNCONNECTED [1:0]}),
- .S({\SR_Y[4]_i_11_n_0 ,\SR_Y[4]_i_12_n_0 ,\SR_Y[4]_i_13_n_0 ,\SR_Y[4]_i_14_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_4
- (.CI(\SR_Y_reg[4]_i_10_n_0 ),
- .CO({\SR_Y_reg[4]_i_4_n_0 ,\SR_Y_reg[4]_i_4_n_1 ,\SR_Y_reg[4]_i_4_n_2 ,\SR_Y_reg[4]_i_4_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_Y[4]_i_15_n_0 ,\SR_Y[4]_i_16_n_0 ,\SR_Y[4]_i_17_n_0 ,\SR_Y[4]_i_18_n_0 }),
- .O(SC_MultResult[10:7]),
- .S({\SR_Y[4]_i_19_n_0 ,\SR_Y[4]_i_20_n_0 ,\SR_Y[4]_i_21_n_0 ,\SR_Y[4]_i_22_n_0 }));
- CARRY4 \SR_Y_reg[4]_i_9
- (.CI(\<const0> ),
- .CO({\SR_Y_reg[4]_i_9_n_0 ,\SR_Y_reg[4]_i_9_n_1 ,\SR_Y_reg[4]_i_9_n_2 ,\SR_Y_reg[4]_i_9_n_3 }),
- .CYINIT(\<const0> ),
- .DI({SR_sum_reg[3],SC_MultResult[2:0]}),
- .S({\SR_Y[4]_i_23_n_0 ,\SR_Y[4]_i_24_n_0 ,\SR_Y[4]_i_25_n_0 ,\SR_Y[4]_i_26_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[5]),
- .Q(O_Y_OBUF[5]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[6]),
- .Q(O_Y_OBUF[6]));
- FDCE #(
- .INIT(1'b0))
- \SR_Y_reg[7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadY_IBUF),
- .CLR(I_reset_IBUF),
- .D(p_0_in[7]),
- .Q(O_Y_OBUF[7]));
- CARRY4 \SR_Y_reg[7]_i_10
- (.CI(\SR_sum_reg[0]_i_11_n_0 ),
- .CO({\SR_Y_reg[7]_i_10_n_0 ,\SR_Y_reg[7]_i_10_n_1 ,\SR_Y_reg[7]_i_10_n_2 ,\SR_Y_reg[7]_i_10_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_Y[7]_i_15_n_0 ,\SR_Y[7]_i_16_n_0 ,\SR_Y[7]_i_17_n_0 ,\SR_Y[7]_i_18_n_0 }),
- .O({\SR_Y_reg[7]_i_10_n_4 ,\SR_Y_reg[7]_i_10_n_5 ,\SR_Y_reg[7]_i_10_n_6 ,\SR_Y_reg[7]_i_10_n_7 }),
- .S({\SR_Y[7]_i_19_n_0 ,\SR_Y[7]_i_20_n_0 ,\SR_Y[7]_i_21_n_0 ,\SR_Y[7]_i_22_n_0 }));
- CARRY4 \SR_Y_reg[7]_i_14
- (.CI(\SR_Y_reg[4]_i_27_n_0 ),
- .CO({\SR_Y_reg[7]_i_14_n_1 ,\NLW_SR_Y_reg[7]_i_14_CO_UNCONNECTED [1],\SR_Y_reg[7]_i_14_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\SR_Y[7]_i_25_n_0 ,\SR_Y[7]_i_26_n_0 }),
- .O({\SR_Y_reg[7]_i_14_n_6 ,\SR_Y_reg[7]_i_14_n_7 }),
- .S({\<const0> ,\<const1> ,\SR_Y[7]_i_27_n_0 ,\SR_Y[7]_i_28_n_0 }));
- CARRY4 \SR_Y_reg[7]_i_2
- (.CI(\SR_Y_reg[4]_i_2_n_0 ),
- .CO({\SR_Y_reg[7]_i_2_n_2 ,\SR_Y_reg[7]_i_2_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,SC_MultResult[13:12]}),
- .O(L[14:12]),
- .S({\<const0> ,\SR_Y[7]_i_5_n_0 ,\SR_Y[7]_i_6_n_0 ,\SR_Y[7]_i_7_n_0 }));
- MUXF8 \SR_Y_reg[7]_i_23
- (.I0(\SR_Y_reg[7]_i_33_n_0 ),
- .I1(\SR_Y_reg[7]_i_34_n_0 ),
- .O(\SR_shiftRegister[0] [7]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_Y_reg[7]_i_24
- (.I0(\SR_Y_reg[7]_i_35_n_0 ),
- .I1(\SR_Y_reg[7]_i_36_n_0 ),
- .O(\SR_shiftRegister[0] [6]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_Y_reg[7]_i_29
- (.I0(\SR_Y_reg[7]_i_38_n_0 ),
- .I1(\SR_Y_reg[7]_i_39_n_0 ),
- .O(\SR_shiftRegister[0] [5]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_Y_reg[7]_i_30
- (.I0(\SR_Y_reg[7]_i_40_n_0 ),
- .I1(\SR_Y_reg[7]_i_41_n_0 ),
- .O(\SR_shiftRegister[0] [4]),
- .S(SR_readAddress_reg__0[3]));
- MUXF7 \SR_Y_reg[7]_i_33
- (.I0(\SR_Y[7]_i_42_n_0 ),
- .I1(\SR_Y[7]_i_43_n_0 ),
- .O(\SR_Y_reg[7]_i_33_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_34
- (.I0(\SR_Y[7]_i_44_n_0 ),
- .I1(\SR_Y[7]_i_45_n_0 ),
- .O(\SR_Y_reg[7]_i_34_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_35
- (.I0(\SR_Y[7]_i_46_n_0 ),
- .I1(\SR_Y[7]_i_47_n_0 ),
- .O(\SR_Y_reg[7]_i_35_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_36
- (.I0(\SR_Y[7]_i_48_n_0 ),
- .I1(\SR_Y[7]_i_49_n_0 ),
- .O(\SR_Y_reg[7]_i_36_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_38
- (.I0(\SR_Y[7]_i_50_n_0 ),
- .I1(\SR_Y[7]_i_51_n_0 ),
- .O(\SR_Y_reg[7]_i_38_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_39
- (.I0(\SR_Y[7]_i_52_n_0 ),
- .I1(\SR_Y[7]_i_53_n_0 ),
- .O(\SR_Y_reg[7]_i_39_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- CARRY4 \SR_Y_reg[7]_i_4
- (.CI(\SR_Y_reg[4]_i_4_n_0 ),
- .CO({\SR_Y_reg[7]_i_4_n_1 ,\SR_Y_reg[7]_i_4_n_2 ,\SR_Y_reg[7]_i_4_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\SR_Y_reg[7]_i_8_n_5 ,\<const0> ,\SR_Y_reg[7]_i_8_n_7 }),
- .O(SC_MultResult[14:11]),
- .S({\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_6 ,\SR_Y[7]_i_9_n_0 }));
- MUXF7 \SR_Y_reg[7]_i_40
- (.I0(\SR_Y[7]_i_54_n_0 ),
- .I1(\SR_Y[7]_i_55_n_0 ),
- .O(\SR_Y_reg[7]_i_40_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_Y_reg[7]_i_41
- (.I0(\SR_Y[7]_i_56_n_0 ),
- .I1(\SR_Y[7]_i_57_n_0 ),
- .O(\SR_Y_reg[7]_i_41_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- CARRY4 \SR_Y_reg[7]_i_8
- (.CI(\SR_Y_reg[7]_i_10_n_0 ),
- .CO({\SR_Y_reg[7]_i_8_n_2 ,\SR_Y_reg[7]_i_8_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\<const0> ,\SR_Y[7]_i_11_n_0 }),
- .O({\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_6 ,\SR_Y_reg[7]_i_8_n_7 }),
- .S({\<const0> ,\<const1> ,\SR_Y[7]_i_12_n_0 ,\SR_Y[7]_i_13_n_0 }));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT2 #(
- .INIT(4'h1))
- \SR_readAddress[0]_i_1
- (.I0(SR_readAddress_reg__0[0]),
- .I1(I_initAddress_IBUF),
- .O(\SR_readAddress[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT3 #(
- .INIT(8'h06))
- \SR_readAddress[1]_i_1
- (.I0(SR_readAddress_reg__0[1]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(I_initAddress_IBUF),
- .O(\SR_readAddress[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'h006A))
- \SR_readAddress[2]_i_1
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(I_initAddress_IBUF),
- .O(\SR_readAddress[2]_i_1_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \SR_readAddress[3]_i_1
- (.I0(I_incrAddress_IBUF),
- .I1(I_initAddress_IBUF),
- .O(\SR_readAddress[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT5 #(
- .INIT(32'h00006AAA))
- \SR_readAddress[3]_i_2
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(I_initAddress_IBUF),
- .O(\SR_readAddress[3]_i_2_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[0]_i_1_n_0 ),
- .Q(SR_readAddress_reg__0[0]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[1]_i_1_n_0 ),
- .Q(SR_readAddress_reg__0[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[2]_i_1_n_0 ),
- .Q(SR_readAddress_reg__0[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_readAddress_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_readAddress[3]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_readAddress[3]_i_2_n_0 ),
- .Q(SR_readAddress_reg__0[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[0]),
- .Q(\SR_shiftRegister_reg[0]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[1]),
- .Q(\SR_shiftRegister_reg[0]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[2]),
- .Q(\SR_shiftRegister_reg[0]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[3]),
- .Q(\SR_shiftRegister_reg[0]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[4]),
- .Q(\SR_shiftRegister_reg[0]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[5]),
- .Q(\SR_shiftRegister_reg[0]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[6]),
- .Q(\SR_shiftRegister_reg[0]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[0][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(I_inputSample_IBUF[7]),
- .Q(\SR_shiftRegister_reg[0]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [0]),
- .Q(\SR_shiftRegister_reg[10]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [1]),
- .Q(\SR_shiftRegister_reg[10]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [2]),
- .Q(\SR_shiftRegister_reg[10]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [3]),
- .Q(\SR_shiftRegister_reg[10]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [4]),
- .Q(\SR_shiftRegister_reg[10]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [5]),
- .Q(\SR_shiftRegister_reg[10]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [6]),
- .Q(\SR_shiftRegister_reg[10]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[10][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[9]__0 [7]),
- .Q(\SR_shiftRegister_reg[10]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [0]),
- .Q(\SR_shiftRegister_reg[11]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [1]),
- .Q(\SR_shiftRegister_reg[11]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [2]),
- .Q(\SR_shiftRegister_reg[11]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [3]),
- .Q(\SR_shiftRegister_reg[11]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [4]),
- .Q(\SR_shiftRegister_reg[11]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [5]),
- .Q(\SR_shiftRegister_reg[11]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [6]),
- .Q(\SR_shiftRegister_reg[11]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[11][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[10]__0 [7]),
- .Q(\SR_shiftRegister_reg[11]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [0]),
- .Q(\SR_shiftRegister_reg[12]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [1]),
- .Q(\SR_shiftRegister_reg[12]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [2]),
- .Q(\SR_shiftRegister_reg[12]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [3]),
- .Q(\SR_shiftRegister_reg[12]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [4]),
- .Q(\SR_shiftRegister_reg[12]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [5]),
- .Q(\SR_shiftRegister_reg[12]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [6]),
- .Q(\SR_shiftRegister_reg[12]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[12][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[11]__0 [7]),
- .Q(\SR_shiftRegister_reg[12]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [0]),
- .Q(\SR_shiftRegister_reg[13]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [1]),
- .Q(\SR_shiftRegister_reg[13]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [2]),
- .Q(\SR_shiftRegister_reg[13]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [3]),
- .Q(\SR_shiftRegister_reg[13]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [4]),
- .Q(\SR_shiftRegister_reg[13]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [5]),
- .Q(\SR_shiftRegister_reg[13]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [6]),
- .Q(\SR_shiftRegister_reg[13]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[13][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[12]__0 [7]),
- .Q(\SR_shiftRegister_reg[13]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [0]),
- .Q(\SR_shiftRegister_reg[14]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [1]),
- .Q(\SR_shiftRegister_reg[14]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [2]),
- .Q(\SR_shiftRegister_reg[14]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [3]),
- .Q(\SR_shiftRegister_reg[14]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [4]),
- .Q(\SR_shiftRegister_reg[14]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [5]),
- .Q(\SR_shiftRegister_reg[14]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [6]),
- .Q(\SR_shiftRegister_reg[14]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[14][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[13]__0 [7]),
- .Q(\SR_shiftRegister_reg[14]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [0]),
- .Q(\SR_shiftRegister_reg[15]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [1]),
- .Q(\SR_shiftRegister_reg[15]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [2]),
- .Q(\SR_shiftRegister_reg[15]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [3]),
- .Q(\SR_shiftRegister_reg[15]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [4]),
- .Q(\SR_shiftRegister_reg[15]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [5]),
- .Q(\SR_shiftRegister_reg[15]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [6]),
- .Q(\SR_shiftRegister_reg[15]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[15][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[14]__0 [7]),
- .Q(\SR_shiftRegister_reg[15]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [0]),
- .Q(\SR_shiftRegister_reg[1]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [1]),
- .Q(\SR_shiftRegister_reg[1]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [2]),
- .Q(\SR_shiftRegister_reg[1]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [3]),
- .Q(\SR_shiftRegister_reg[1]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [4]),
- .Q(\SR_shiftRegister_reg[1]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [5]),
- .Q(\SR_shiftRegister_reg[1]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [6]),
- .Q(\SR_shiftRegister_reg[1]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[1][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[0]__0 [7]),
- .Q(\SR_shiftRegister_reg[1]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [0]),
- .Q(\SR_shiftRegister_reg[2]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [1]),
- .Q(\SR_shiftRegister_reg[2]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [2]),
- .Q(\SR_shiftRegister_reg[2]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [3]),
- .Q(\SR_shiftRegister_reg[2]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [4]),
- .Q(\SR_shiftRegister_reg[2]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [5]),
- .Q(\SR_shiftRegister_reg[2]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [6]),
- .Q(\SR_shiftRegister_reg[2]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[2][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[1]__0 [7]),
- .Q(\SR_shiftRegister_reg[2]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [0]),
- .Q(\SR_shiftRegister_reg[3]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [1]),
- .Q(\SR_shiftRegister_reg[3]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [2]),
- .Q(\SR_shiftRegister_reg[3]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [3]),
- .Q(\SR_shiftRegister_reg[3]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [4]),
- .Q(\SR_shiftRegister_reg[3]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [5]),
- .Q(\SR_shiftRegister_reg[3]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [6]),
- .Q(\SR_shiftRegister_reg[3]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[3][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[2]__0 [7]),
- .Q(\SR_shiftRegister_reg[3]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [0]),
- .Q(\SR_shiftRegister_reg[4]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [1]),
- .Q(\SR_shiftRegister_reg[4]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [2]),
- .Q(\SR_shiftRegister_reg[4]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [3]),
- .Q(\SR_shiftRegister_reg[4]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [4]),
- .Q(\SR_shiftRegister_reg[4]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [5]),
- .Q(\SR_shiftRegister_reg[4]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [6]),
- .Q(\SR_shiftRegister_reg[4]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[4][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[3]__0 [7]),
- .Q(\SR_shiftRegister_reg[4]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [0]),
- .Q(\SR_shiftRegister_reg[5]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [1]),
- .Q(\SR_shiftRegister_reg[5]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [2]),
- .Q(\SR_shiftRegister_reg[5]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [3]),
- .Q(\SR_shiftRegister_reg[5]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [4]),
- .Q(\SR_shiftRegister_reg[5]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [5]),
- .Q(\SR_shiftRegister_reg[5]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [6]),
- .Q(\SR_shiftRegister_reg[5]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[5][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[4]__0 [7]),
- .Q(\SR_shiftRegister_reg[5]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [0]),
- .Q(\SR_shiftRegister_reg[6]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [1]),
- .Q(\SR_shiftRegister_reg[6]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [2]),
- .Q(\SR_shiftRegister_reg[6]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [3]),
- .Q(\SR_shiftRegister_reg[6]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [4]),
- .Q(\SR_shiftRegister_reg[6]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [5]),
- .Q(\SR_shiftRegister_reg[6]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [6]),
- .Q(\SR_shiftRegister_reg[6]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[6][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[5]__0 [7]),
- .Q(\SR_shiftRegister_reg[6]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [0]),
- .Q(\SR_shiftRegister_reg[7]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [1]),
- .Q(\SR_shiftRegister_reg[7]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [2]),
- .Q(\SR_shiftRegister_reg[7]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [3]),
- .Q(\SR_shiftRegister_reg[7]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [4]),
- .Q(\SR_shiftRegister_reg[7]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [5]),
- .Q(\SR_shiftRegister_reg[7]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [6]),
- .Q(\SR_shiftRegister_reg[7]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[7][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[6]__0 [7]),
- .Q(\SR_shiftRegister_reg[7]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [0]),
- .Q(\SR_shiftRegister_reg[8]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [1]),
- .Q(\SR_shiftRegister_reg[8]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [2]),
- .Q(\SR_shiftRegister_reg[8]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [3]),
- .Q(\SR_shiftRegister_reg[8]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [4]),
- .Q(\SR_shiftRegister_reg[8]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [5]),
- .Q(\SR_shiftRegister_reg[8]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [6]),
- .Q(\SR_shiftRegister_reg[8]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[8][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[7]__0 [7]),
- .Q(\SR_shiftRegister_reg[8]__0 [7]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][0]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [0]),
- .Q(\SR_shiftRegister_reg[9]__0 [0]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][1]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [1]),
- .Q(\SR_shiftRegister_reg[9]__0 [1]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][2]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [2]),
- .Q(\SR_shiftRegister_reg[9]__0 [2]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][3]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [3]),
- .Q(\SR_shiftRegister_reg[9]__0 [3]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][4]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [4]),
- .Q(\SR_shiftRegister_reg[9]__0 [4]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][5]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [5]),
- .Q(\SR_shiftRegister_reg[9]__0 [5]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][6]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [6]),
- .Q(\SR_shiftRegister_reg[9]__0 [6]));
- FDCE #(
- .INIT(1'b0))
- \SR_shiftRegister_reg[9][7]
- (.C(I_clock_IBUF_BUFG),
- .CE(I_loadShift_IBUF),
- .CLR(I_reset_IBUF),
- .D(\SR_shiftRegister_reg[8]__0 [7]),
- .Q(\SR_shiftRegister_reg[9]__0 [7]));
- LUT2 #(
- .INIT(4'hE))
- \SR_sum[0]_i_1
- (.I0(I_loadSum_IBUF),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[0]_i_10
- (.I0(SC_MultResult[0]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[0]),
- .O(\SR_sum[0]_i_10_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \SR_sum[0]_i_13
- (.I0(\SR_sum[0]_i_27_n_0 ),
- .O(\SR_sum[0]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hFDDD777F))
- \SR_sum[0]_i_14
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_sum[0]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h724E0000))
- \SR_sum[0]_i_15
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(\SR_shiftRegister[0] [1]),
- .O(\SR_sum[0]_i_15_n_0 ));
- LUT6 #(
- .INIT(64'h02228880FDDD777F))
- \SR_sum[0]_i_16
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_sum[0]_i_27_n_0 ),
- .O(\SR_sum[0]_i_16_n_0 ));
- LUT6 #(
- .INIT(64'hCED287B3FDDD777F))
- \SR_sum[0]_i_17
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_sum[0]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'h113AAC44220AA088))
- \SR_sum[0]_i_18
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [0]),
- .O(\SR_sum[0]_i_18_n_0 ));
- LUT5 #(
- .INIT(32'h028AA280))
- \SR_sum[0]_i_19
- (.I0(\SR_shiftRegister[0] [0]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_sum[0]_i_19_n_0 ));
- LUT3 #(
- .INIT(8'h69))
- \SR_sum[0]_i_20
- (.I0(\SR_sum[0]_i_31_n_0 ),
- .I1(\SR_sum[0]_i_32_n_0 ),
- .I2(\SR_sum[0]_i_33_n_0 ),
- .O(\SR_sum[0]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'h9B4AA1E6A88AA22A))
- \SR_sum[0]_i_21
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[3]),
- .I5(\SR_shiftRegister[0] [0]),
- .O(\SR_sum[0]_i_21_n_0 ));
- LUT5 #(
- .INIT(32'h60060000))
- \SR_sum[0]_i_22
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(\SR_shiftRegister[0] [1]),
- .O(\SR_sum[0]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'h6696969666666666))
- \SR_sum[0]_i_23
- (.I0(\SR_sum[0]_i_31_n_0 ),
- .I1(\SR_sum[0]_i_33_n_0 ),
- .I2(\SR_shiftRegister[0] [1]),
- .I3(SC_multOperand2[1]),
- .I4(\SR_shiftRegister[0] [0]),
- .I5(SC_multOperand2[2]),
- .O(\SR_sum[0]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'h96AAAA96AAAAAAAA))
- \SR_sum[0]_i_24
- (.I0(\SR_sum[0]_i_21_n_0 ),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[3]),
- .I4(SR_readAddress_reg__0[1]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_sum[0]_i_24_n_0 ));
- LUT6 #(
- .INIT(64'hF7C143DF08028020))
- \SR_sum[0]_i_25
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[2]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister[0] [0]),
- .O(\SR_sum[0]_i_25_n_0 ));
- LUT5 #(
- .INIT(32'h00828200))
- \SR_sum[0]_i_26
- (.I0(\SR_shiftRegister[0] [0]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_sum[0]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'h113AAC44220AA088))
- \SR_sum[0]_i_27
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[0]),
- .I3(SR_readAddress_reg__0[1]),
- .I4(SR_readAddress_reg__0[2]),
- .I5(\SR_shiftRegister[0] [2]),
- .O(\SR_sum[0]_i_27_n_0 ));
- LUT3 #(
- .INIT(8'h06))
- \SR_sum[0]_i_3
- (.I0(\SR_sum_reg[0]_i_11_n_7 ),
- .I1(\SR_sum_reg[0]_i_12_n_4 ),
- .I2(I_initSum_IBUF),
- .O(\SR_sum[0]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT5 #(
- .INIT(32'h557D7D55))
- \SR_sum[0]_i_31
- (.I0(\SR_shiftRegister[0] [2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[2]),
- .I4(SR_readAddress_reg__0[3]),
- .O(\SR_sum[0]_i_31_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT5 #(
- .INIT(32'hF5FD7F5F))
- \SR_sum[0]_i_32
- (.I0(\SR_shiftRegister[0] [1]),
- .I1(SR_readAddress_reg__0[3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_sum[0]_i_32_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT5 #(
- .INIT(32'hFF7D7DFF))
- \SR_sum[0]_i_33
- (.I0(\SR_shiftRegister[0] [3]),
- .I1(SR_readAddress_reg__0[1]),
- .I2(SR_readAddress_reg__0[3]),
- .I3(SR_readAddress_reg__0[0]),
- .I4(SR_readAddress_reg__0[2]),
- .O(\SR_sum[0]_i_33_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT4 #(
- .INIT(16'hF99F))
- \SR_sum[0]_i_34
- (.I0(SR_readAddress_reg__0[3]),
- .I1(SR_readAddress_reg__0[2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[0]),
- .O(SC_multOperand2[1]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h581A))
- \SR_sum[0]_i_35
- (.I0(SR_readAddress_reg__0[2]),
- .I1(SR_readAddress_reg__0[0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(SR_readAddress_reg__0[3]),
- .O(SC_multOperand2[2]));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_4
- (.I0(SC_MultResult[2]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_45
- (.I0(\SR_shiftRegister_reg[3]__0 [1]),
- .I1(\SR_shiftRegister_reg[2]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [1]),
- .O(\SR_sum[0]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_46
- (.I0(\SR_shiftRegister_reg[7]__0 [1]),
- .I1(\SR_shiftRegister_reg[6]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [1]),
- .O(\SR_sum[0]_i_46_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_47
- (.I0(\SR_shiftRegister_reg[11]__0 [1]),
- .I1(\SR_shiftRegister_reg[10]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [1]),
- .O(\SR_sum[0]_i_47_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_48
- (.I0(\SR_shiftRegister_reg[15]__0 [1]),
- .I1(\SR_shiftRegister_reg[14]__0 [1]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [1]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [1]),
- .O(\SR_sum[0]_i_48_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_49
- (.I0(\SR_shiftRegister_reg[3]__0 [2]),
- .I1(\SR_shiftRegister_reg[2]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [2]),
- .O(\SR_sum[0]_i_49_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_5
- (.I0(SC_MultResult[1]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_50
- (.I0(\SR_shiftRegister_reg[7]__0 [2]),
- .I1(\SR_shiftRegister_reg[6]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [2]),
- .O(\SR_sum[0]_i_50_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_51
- (.I0(\SR_shiftRegister_reg[11]__0 [2]),
- .I1(\SR_shiftRegister_reg[10]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [2]),
- .O(\SR_sum[0]_i_51_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_52
- (.I0(\SR_shiftRegister_reg[15]__0 [2]),
- .I1(\SR_shiftRegister_reg[14]__0 [2]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [2]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [2]),
- .O(\SR_sum[0]_i_52_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_53
- (.I0(\SR_shiftRegister_reg[3]__0 [0]),
- .I1(\SR_shiftRegister_reg[2]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [0]),
- .O(\SR_sum[0]_i_53_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_54
- (.I0(\SR_shiftRegister_reg[7]__0 [0]),
- .I1(\SR_shiftRegister_reg[6]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [0]),
- .O(\SR_sum[0]_i_54_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_55
- (.I0(\SR_shiftRegister_reg[11]__0 [0]),
- .I1(\SR_shiftRegister_reg[10]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [0]),
- .O(\SR_sum[0]_i_55_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_56
- (.I0(\SR_shiftRegister_reg[15]__0 [0]),
- .I1(\SR_shiftRegister_reg[14]__0 [0]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [0]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [0]),
- .O(\SR_sum[0]_i_56_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_57
- (.I0(\SR_shiftRegister_reg[3]__0 [3]),
- .I1(\SR_shiftRegister_reg[2]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[1]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[0]__0 [3]),
- .O(\SR_sum[0]_i_57_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_58
- (.I0(\SR_shiftRegister_reg[7]__0 [3]),
- .I1(\SR_shiftRegister_reg[6]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[5]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[4]__0 [3]),
- .O(\SR_sum[0]_i_58_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_59
- (.I0(\SR_shiftRegister_reg[11]__0 [3]),
- .I1(\SR_shiftRegister_reg[10]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[9]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[8]__0 [3]),
- .O(\SR_sum[0]_i_59_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[0]_i_6
- (.I0(SC_MultResult[0]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[0]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \SR_sum[0]_i_60
- (.I0(\SR_shiftRegister_reg[15]__0 [3]),
- .I1(\SR_shiftRegister_reg[14]__0 [3]),
- .I2(SR_readAddress_reg__0[1]),
- .I3(\SR_shiftRegister_reg[13]__0 [3]),
- .I4(SR_readAddress_reg__0[0]),
- .I5(\SR_shiftRegister_reg[12]__0 [3]),
- .O(\SR_sum[0]_i_60_n_0 ));
- LUT4 #(
- .INIT(16'h0906))
- \SR_sum[0]_i_7
- (.I0(\SR_sum_reg[0]_i_12_n_4 ),
- .I1(\SR_sum_reg[0]_i_11_n_7 ),
- .I2(I_initSum_IBUF),
- .I3(SR_sum_reg[3]),
- .O(\SR_sum[0]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[0]_i_8
- (.I0(SC_MultResult[2]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[2]),
- .O(\SR_sum[0]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[0]_i_9
- (.I0(SC_MultResult[1]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[1]),
- .O(\SR_sum[0]_i_9_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[12]_i_2
- (.I0(SC_MultResult[13]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[12]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[12]_i_3
- (.I0(SC_MultResult[12]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[12]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[12]_i_4
- (.I0(SC_MultResult[14]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[14]),
- .O(\SR_sum[12]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[12]_i_5
- (.I0(SC_MultResult[13]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[13]),
- .O(\SR_sum[12]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[12]_i_6
- (.I0(SC_MultResult[12]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[12]),
- .O(\SR_sum[12]_i_6_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_2
- (.I0(SC_MultResult[7]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_3
- (.I0(SC_MultResult[6]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_4
- (.I0(SC_MultResult[5]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[4]_i_5
- (.I0(SC_MultResult[4]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[4]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_6
- (.I0(SC_MultResult[7]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[7]),
- .O(\SR_sum[4]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_7
- (.I0(SC_MultResult[6]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[6]),
- .O(\SR_sum[4]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_8
- (.I0(SC_MultResult[5]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[5]),
- .O(\SR_sum[4]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[4]_i_9
- (.I0(SC_MultResult[4]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[4]),
- .O(\SR_sum[4]_i_9_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_2
- (.I0(SC_MultResult[11]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_3
- (.I0(SC_MultResult[10]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_3_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_4
- (.I0(SC_MultResult[9]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_4_n_0 ));
- LUT2 #(
- .INIT(4'h2))
- \SR_sum[8]_i_5
- (.I0(SC_MultResult[8]),
- .I1(I_initSum_IBUF),
- .O(\SR_sum[8]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_6
- (.I0(SC_MultResult[11]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[11]),
- .O(\SR_sum[8]_i_6_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_7
- (.I0(SC_MultResult[10]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[10]),
- .O(\SR_sum[8]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_8
- (.I0(SC_MultResult[9]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[9]),
- .O(\SR_sum[8]_i_8_n_0 ));
- LUT3 #(
- .INIT(8'h12))
- \SR_sum[8]_i_9
- (.I0(SC_MultResult[8]),
- .I1(I_initSum_IBUF),
- .I2(SR_sum_reg[8]),
- .O(\SR_sum[8]_i_9_n_0 ));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[0]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_7 ),
- .Q(SR_sum_reg[0]));
- CARRY4 \SR_sum_reg[0]_i_11
- (.CI(\<const0> ),
- .CO({\SR_sum_reg[0]_i_11_n_0 ,\SR_sum_reg[0]_i_11_n_1 ,\SR_sum_reg[0]_i_11_n_2 ,\SR_sum_reg[0]_i_11_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[0]_i_13_n_0 ,\SR_sum[0]_i_14_n_0 ,\SR_sum[0]_i_15_n_0 ,\<const0> }),
- .O({\SR_sum_reg[0]_i_11_n_4 ,\SR_sum_reg[0]_i_11_n_5 ,\SR_sum_reg[0]_i_11_n_6 ,\SR_sum_reg[0]_i_11_n_7 }),
- .S({\SR_sum[0]_i_16_n_0 ,\SR_sum[0]_i_17_n_0 ,\SR_sum[0]_i_18_n_0 ,\SR_sum[0]_i_19_n_0 }));
- CARRY4 \SR_sum_reg[0]_i_12
- (.CI(\<const0> ),
- .CO({\SR_sum_reg[0]_i_12_n_0 ,\SR_sum_reg[0]_i_12_n_1 ,\SR_sum_reg[0]_i_12_n_2 ,\SR_sum_reg[0]_i_12_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[0]_i_20_n_0 ,\SR_sum[0]_i_21_n_0 ,\SR_sum[0]_i_22_n_0 ,\<const0> }),
- .O({\SR_sum_reg[0]_i_12_n_4 ,SC_MultResult[2:0]}),
- .S({\SR_sum[0]_i_23_n_0 ,\SR_sum[0]_i_24_n_0 ,\SR_sum[0]_i_25_n_0 ,\SR_sum[0]_i_26_n_0 }));
- CARRY4 \SR_sum_reg[0]_i_2
- (.CI(\<const0> ),
- .CO({\SR_sum_reg[0]_i_2_n_0 ,\SR_sum_reg[0]_i_2_n_1 ,\SR_sum_reg[0]_i_2_n_2 ,\SR_sum_reg[0]_i_2_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[0]_i_3_n_0 ,\SR_sum[0]_i_4_n_0 ,\SR_sum[0]_i_5_n_0 ,\SR_sum[0]_i_6_n_0 }),
- .O({\SR_sum_reg[0]_i_2_n_4 ,\SR_sum_reg[0]_i_2_n_5 ,\SR_sum_reg[0]_i_2_n_6 ,\SR_sum_reg[0]_i_2_n_7 }),
- .S({\SR_sum[0]_i_7_n_0 ,\SR_sum[0]_i_8_n_0 ,\SR_sum[0]_i_9_n_0 ,\SR_sum[0]_i_10_n_0 }));
- MUXF8 \SR_sum_reg[0]_i_28
- (.I0(\SR_sum_reg[0]_i_37_n_0 ),
- .I1(\SR_sum_reg[0]_i_38_n_0 ),
- .O(\SR_shiftRegister[0] [1]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_sum_reg[0]_i_29
- (.I0(\SR_sum_reg[0]_i_39_n_0 ),
- .I1(\SR_sum_reg[0]_i_40_n_0 ),
- .O(\SR_shiftRegister[0] [2]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_sum_reg[0]_i_30
- (.I0(\SR_sum_reg[0]_i_41_n_0 ),
- .I1(\SR_sum_reg[0]_i_42_n_0 ),
- .O(\SR_shiftRegister[0] [0]),
- .S(SR_readAddress_reg__0[3]));
- MUXF8 \SR_sum_reg[0]_i_36
- (.I0(\SR_sum_reg[0]_i_43_n_0 ),
- .I1(\SR_sum_reg[0]_i_44_n_0 ),
- .O(\SR_shiftRegister[0] [3]),
- .S(SR_readAddress_reg__0[3]));
- MUXF7 \SR_sum_reg[0]_i_37
- (.I0(\SR_sum[0]_i_45_n_0 ),
- .I1(\SR_sum[0]_i_46_n_0 ),
- .O(\SR_sum_reg[0]_i_37_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_38
- (.I0(\SR_sum[0]_i_47_n_0 ),
- .I1(\SR_sum[0]_i_48_n_0 ),
- .O(\SR_sum_reg[0]_i_38_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_39
- (.I0(\SR_sum[0]_i_49_n_0 ),
- .I1(\SR_sum[0]_i_50_n_0 ),
- .O(\SR_sum_reg[0]_i_39_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_40
- (.I0(\SR_sum[0]_i_51_n_0 ),
- .I1(\SR_sum[0]_i_52_n_0 ),
- .O(\SR_sum_reg[0]_i_40_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_41
- (.I0(\SR_sum[0]_i_53_n_0 ),
- .I1(\SR_sum[0]_i_54_n_0 ),
- .O(\SR_sum_reg[0]_i_41_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_42
- (.I0(\SR_sum[0]_i_55_n_0 ),
- .I1(\SR_sum[0]_i_56_n_0 ),
- .O(\SR_sum_reg[0]_i_42_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_43
- (.I0(\SR_sum[0]_i_57_n_0 ),
- .I1(\SR_sum[0]_i_58_n_0 ),
- .O(\SR_sum_reg[0]_i_43_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- MUXF7 \SR_sum_reg[0]_i_44
- (.I0(\SR_sum[0]_i_59_n_0 ),
- .I1(\SR_sum[0]_i_60_n_0 ),
- .O(\SR_sum_reg[0]_i_44_n_0 ),
- .S(SR_readAddress_reg__0[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[10]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_5 ),
- .Q(SR_sum_reg[10]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[11]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_4 ),
- .Q(SR_sum_reg[11]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[12]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[12]_i_1_n_7 ),
- .Q(SR_sum_reg[12]));
- CARRY4 \SR_sum_reg[12]_i_1
- (.CI(\SR_sum_reg[8]_i_1_n_0 ),
- .CO({\SR_sum_reg[12]_i_1_n_2 ,\SR_sum_reg[12]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\<const0> ,\<const0> ,\SR_sum[12]_i_2_n_0 ,\SR_sum[12]_i_3_n_0 }),
- .O({\SR_sum_reg[12]_i_1_n_5 ,\SR_sum_reg[12]_i_1_n_6 ,\SR_sum_reg[12]_i_1_n_7 }),
- .S({\<const0> ,\SR_sum[12]_i_4_n_0 ,\SR_sum[12]_i_5_n_0 ,\SR_sum[12]_i_6_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[13]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[12]_i_1_n_6 ),
- .Q(SR_sum_reg[13]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[14]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[12]_i_1_n_5 ),
- .Q(SR_sum_reg[14]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[1]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_6 ),
- .Q(SR_sum_reg[1]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[2]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_5 ),
- .Q(SR_sum_reg[2]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[3]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[0]_i_2_n_4 ),
- .Q(SR_sum_reg[3]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[4]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_7 ),
- .Q(SR_sum_reg[4]));
- CARRY4 \SR_sum_reg[4]_i_1
- (.CI(\SR_sum_reg[0]_i_2_n_0 ),
- .CO({\SR_sum_reg[4]_i_1_n_0 ,\SR_sum_reg[4]_i_1_n_1 ,\SR_sum_reg[4]_i_1_n_2 ,\SR_sum_reg[4]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[4]_i_2_n_0 ,\SR_sum[4]_i_3_n_0 ,\SR_sum[4]_i_4_n_0 ,\SR_sum[4]_i_5_n_0 }),
- .O({\SR_sum_reg[4]_i_1_n_4 ,\SR_sum_reg[4]_i_1_n_5 ,\SR_sum_reg[4]_i_1_n_6 ,\SR_sum_reg[4]_i_1_n_7 }),
- .S({\SR_sum[4]_i_6_n_0 ,\SR_sum[4]_i_7_n_0 ,\SR_sum[4]_i_8_n_0 ,\SR_sum[4]_i_9_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[5]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_6 ),
- .Q(SR_sum_reg[5]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[6]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_5 ),
- .Q(SR_sum_reg[6]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[7]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[4]_i_1_n_4 ),
- .Q(SR_sum_reg[7]));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[8]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_7 ),
- .Q(SR_sum_reg[8]));
- CARRY4 \SR_sum_reg[8]_i_1
- (.CI(\SR_sum_reg[4]_i_1_n_0 ),
- .CO({\SR_sum_reg[8]_i_1_n_0 ,\SR_sum_reg[8]_i_1_n_1 ,\SR_sum_reg[8]_i_1_n_2 ,\SR_sum_reg[8]_i_1_n_3 }),
- .CYINIT(\<const0> ),
- .DI({\SR_sum[8]_i_2_n_0 ,\SR_sum[8]_i_3_n_0 ,\SR_sum[8]_i_4_n_0 ,\SR_sum[8]_i_5_n_0 }),
- .O({\SR_sum_reg[8]_i_1_n_4 ,\SR_sum_reg[8]_i_1_n_5 ,\SR_sum_reg[8]_i_1_n_6 ,\SR_sum_reg[8]_i_1_n_7 }),
- .S({\SR_sum[8]_i_6_n_0 ,\SR_sum[8]_i_7_n_0 ,\SR_sum[8]_i_8_n_0 ,\SR_sum[8]_i_9_n_0 }));
- FDCE #(
- .INIT(1'b0))
- \SR_sum_reg[9]
- (.C(I_clock_IBUF_BUFG),
- .CE(\SR_sum[0]_i_1_n_0 ),
- .CLR(I_reset_IBUF),
- .D(\SR_sum_reg[8]_i_1_n_6 ),
- .Q(SR_sum_reg[9]));
- VCC VCC
- (.P(\<const1> ));
-endmodule
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
deleted file mode 100644
index e19d713585d5121f39e78cd67ed5edb8a48f4ed0..0000000000000000000000000000000000000000
--- a/src/hdl/tb_firUnit.vhd
+++ /dev/null
@@ -1,87 +0,0 @@
--------------------------------------------------------------------------------
--- Title : FirUnit
--- Project :
--------------------------------------------------------------------------------
--- File : operativeUnit.vhd
--- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
--- Company :
--- Created : 2018-04-11
--- Last update: 2019-02-26
--- Platform :
--- Standard : VHDL'93/02
--------------------------------------------------------------------------------
--- Description: 8 bit FIR
--------------------------------------------------------------------------------
--- Copyright (c) 2018
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2018-04-11 1.0 jnbazin Created
--- 2018-04-18 1.1 marzel Modified to add more test inputs
--- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity tb_firUnit is
-end entity tb_firUnit;
-
-architecture archi_tb_firUnit of tb_firUnit is
- component firUnit is
- port (
- I_clock : in std_logic;
- I_reset : in std_logic;
- I_inputSample : in std_logic_vector(7 downto 0);
- I_inputSampleValid : in std_logic;
- O_filteredSample : out std_logic_vector(7 downto 0);
- O_filteredSampleValid : out std_logic);
- end component firUnit;
-
- signal SC_clock : std_logic := '0';
- signal SC_reset : std_logic;
- signal SC_inputSample : std_logic_vector(7 downto 0);
- signal SC_inputSampleValid : std_logic:='0';
- signal SC_filteredSample : std_logic_vector(7 downto 0);
- signal SC_filteredSampleValid : std_logic;
-
-begin
-
- SC_clock <= not SC_clock after 5 ns;
- SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
-
- -- Sample period = 20 clk period
- SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
-
- -- Null signal followed by a Dirac and then an arbitrary sequence
- SC_inputSample <= "00000000",
- "01111111" after 401 ns,
- "00000000" after 601 ns,
- "00100100" after 4201 ns,
- "01100100" after 4401 ns,
- "10100010" after 4601 ns,
- "11011011" after 4801 ns,
- "00001011" after 5001 ns,
- "10000000" after 5201 ns,
- "01111111" after 5401 ns,
- "10111010" after 5601 ns;
-
-
--- the filter output on 8 bits is a sequence of signed numbers (with the assumption
--- of rounding the output, so the accuracy can be slightly different depending
--- on your final stage):
- -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
- -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
-
-
- firUnit_1 : entity work.firUnit
- port map (
- I_clock => SC_clock,
- I_reset => SC_reset,
- I_inputSample => SC_inputSample,
- I_inputSampleValid => SC_inputSampleValid,
- O_filteredSample => SC_filteredSample,
- O_filteredSampleValid => SC_filteredSampleValid);
-
-end architecture archi_tb_firUnit;