diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index cd056f619d4a6c4caddd9df5b41f43ed435892f3..7bd82f0ee613b4e68c4e19cb12928980d85bc1c1 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -8,18 +8,19 @@
## Questions
### Question filtre 1 : Combien de processus sont utilisés et de quelles natures sont-ils ? Comment les différenciez-vous ?
-
+Deux process sont utilisés. Le premier est un process synchrone qui gère le passage d'état présent à état futur avec un reset asynchrone. Le second est un process asynchrone qui permet de gérer la FSM.
### Question filtre 2 : La simulation vous permet-elle de valider votre description VHDL ? Justifiez.
-
+La simulation permet de valider le fait que notre FSM fonctionne correctement.
### Question filtre 3 : Validez-vous la conception de l’unité de contrôle ?
-
+Oui, l'unité de contrôle que nous avons compléter donne les résultats attendus.
### Question filtre 4 : Combien de processus sont utilisés et de quelles natures sont-ils ?
-
+On utilise 4 process synchrones.
### Question filtre 5 : La simulation vous permet-elle de valider votre description VHDL ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ? Justifiez
-
+En ayant implémenter l'arrondi, la simulation montre une bonne implémentation.
### Question filtre 6 : Validez-vous la conception de l’unité opérative ? Sinon, quel élément pose problème ? Comment pouvez-vous le corriger ?
+On obtient un signal filtré plus ou moins echantillonnés dépendants des paramètres atrribués.
\ No newline at end of file
diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index bd839a9b01be6c20eb7b6840fcbab9fd73e2336d..e5b2b06967c1b8c09a9fed10ec0855a41594e89d 100644
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@@ -1,52 +1,52 @@
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