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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/27/2025 06:16:48 PM
+-- Design Name: 
+-- Module Name: ControlUnit - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ControlUnit is
+port (
+    I_clock               : in  std_logic;  
+    I_reset               : in  std_logic;  
+    I_inputSampleValid    : in  std_logic;  
+    I_processingDone_1    : in  std_logic;
+    I_processingDone_2    : in  std_logic;
+    I_processingDone_3    : in  std_logic;
+    I_processingDone_4    : in  std_logic;
+    I_processingDone_5    : in  std_logic;
+    O_inLoop              : out unsigned(7 downto 0);
+    O_loadShift_1         : out std_logic;  
+    O_loadShift_2         : out std_logic;  
+    O_loadShift_3         : out std_logic;  
+    O_initAddress         : out std_logic;  
+    O_incrAddress         : out std_logic;  
+    O_initSum             : out std_logic;  
+    O_loadSum             : out std_logic;  
+    O_loadY               : out std_logic;  
+    O_FilteredSampleValid : out std_logic  
+  );
+end ControlUnit;
+
+architecture Behavioral of ControlUnit is
+
+type T_state is (
+    WAIT_SAMPLE,
+    STORE_1,
+    STORE_2,
+    STORE_3,
+    PROCESSING_LOOP_1,
+    PROCESSING_LOOP_2,
+    PROCESSING_LOOP_3,
+    PROCESSING_LOOP_4,
+    PROCESSING_LOOP_5,
+    OUTPUT,
+    WAIT_END_SAMPLE
+  );  
+  signal SR_presentState : T_state;
+  signal SR_futurState   : T_state;
+
+begin
+  -- Processus de synchronisation
+  process (I_clock, I_reset) is
+  begin
+    if I_reset = '1' then              
+      SR_presentState <= WAIT_SAMPLE;
+    elsif rising_edge(I_clock) then    
+      SR_presentState <= SR_futurState;
+    end if;
+  end process;
+
+  -- Processus combinatoire pour la machine à états
+  process (SR_presentState, I_inputSampleValid, I_processingDone_1,
+           I_processingDone_2, I_processingDone_3, I_processingDone_4,
+           I_processingDone_5) is
+  begin
+    -- Valeurs par défaut des sorties
+    O_inLoop <= (others => '0');
+    O_initAddress <= '0';
+    O_incrAddress <= '0';
+    O_initSum <= '0';
+    O_loadSum <= '0';
+   
+    case SR_presentState is
+      when WAIT_SAMPLE =>
+        if I_inputSampleValid = '1' then
+          SR_futurState <= STORE_1;
+        else
+          SR_futurState <= WAIT_SAMPLE;
+        end if;
+     
+      when STORE_1 =>
+        O_initAddress <= '1';
+        O_initSum <= '1';
+        SR_futurState <= PROCESSING_LOOP_1;
+       
+      when PROCESSING_LOOP_1 =>
+        O_inLoop <= to_unsigned(1, 8);
+        O_incrAddress <= '1';
+        O_loadSum <= '1';
+        if I_processingDone_1 = '1' then
+          SR_futurState <= STORE_2;
+        else
+          SR_futurState <= PROCESSING_LOOP_1;
+        end if;
+     
+      when STORE_2 =>
+        O_initAddress <= '1';
+        O_initSum <= '1';
+        SR_futurState <= PROCESSING_LOOP_2;
+       
+      when PROCESSING_LOOP_2 =>
+        O_inLoop <= to_unsigned(2, 8);
+        O_incrAddress <= '1';
+        O_loadSum <= '1';
+        if I_processingDone_2 = '1' then
+          SR_futurState <= PROCESSING_LOOP_3;
+        else
+          SR_futurState <= PROCESSING_LOOP_2;
+        end if;
+       
+      when PROCESSING_LOOP_3 =>
+        O_inLoop <= to_unsigned(3, 8);
+        O_incrAddress <= '1';
+        O_loadSum <= '1';
+        if I_processingDone_3 = '1' then
+          SR_futurState <= STORE_3;
+        else
+          SR_futurState <= PROCESSING_LOOP_3;
+        end if;
+       
+      when STORE_3 =>
+        O_initAddress <= '1';
+        O_initSum <= '1';
+        SR_futurState <= PROCESSING_LOOP_4;
+     
+      when PROCESSING_LOOP_4 =>
+        O_inLoop <= to_unsigned(4, 8);
+        O_incrAddress <= '1';
+        O_loadSum <= '1';
+        if I_processingDone_4 = '1' then
+          SR_futurState <= PROCESSING_LOOP_5;
+        else
+          SR_futurState <= PROCESSING_LOOP_4;
+        end if;
+       
+      when PROCESSING_LOOP_5 =>
+        O_inLoop <= to_unsigned(5, 8);
+        O_incrAddress <= '1';
+        O_loadSum <= '1';
+        if I_processingDone_5 = '1' then
+          SR_futurState <= OUTPUT;
+        else
+          SR_futurState <= PROCESSING_LOOP_5;
+        end if;
+ 
+      when OUTPUT =>
+        SR_futurState <= WAIT_END_SAMPLE;
+     
+      when WAIT_END_SAMPLE =>
+        if I_inputSampleValid = '0' then
+          SR_futurState <= WAIT_SAMPLE;
+        else
+          SR_futurState <= WAIT_END_SAMPLE;
+        end if;
+       
+      when others =>
+        SR_futurState <= WAIT_SAMPLE;
+    end case;
+  end process;
+
+  -- Affectation des autres signaux de sortie
+  O_loadShift_1 <= '1' when SR_presentState = STORE_1 else '0';
+  O_loadShift_2 <= '1' when SR_presentState = STORE_2 else '0';
+  O_loadShift_3 <= '1' when SR_presentState = STORE_3 else '0';
+  O_loadY <= '1' when SR_presentState = OUTPUT else '0';
+  O_FilteredSampleValid <= '1' when SR_presentState = WAIT_END_SAMPLE else '0';
+
+
+
+end Behavioral;