diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index bd839a9b01be6c20eb7b6840fcbab9fd73e2336d..ab7715bb0f8584de688d941d3e18ba8ff013a514 100644
--- a/docs/img/FSM.drawio
+++ b/docs/img/FSM.drawio
@@ -1,150 +1,300 @@
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diff --git a/docs/img/OperativeUnit.png b/docs/img/OperativeUnit.png
index 64a947ab89b5c179f8cda30834baa893918774d1..1f41efc15da85a8aed34cf72af15abdc8cc5233e 100644
Binary files a/docs/img/OperativeUnit.png and b/docs/img/OperativeUnit.png differ
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1c4356ddb44318d2cfa4a1a9b7166d3226772cef
--- /dev/null
+++ b/src/hdl/controlUnit.vhd
@@ -0,0 +1,149 @@
+-------------------------------------------------------------------------------
+-- Title : controlUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Control unit of a sequential FIR filter.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity controlUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_processingDone : in std_logic;
+ O_loadShiftX : out std_logic;
+ O_loadShiftY : out std_logic;
+ O_loadShiftZ : out std_logic; -- filtered sample
+ O_initAddress : out std_logic; -- Control signal to initialize register read address
+ O_incrAddress : out std_logic; -- Control signal to increment register read address
+ O_initSum : out std_logic; -- Control signal to initialize the MAC register
+ O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadOutput : out std_logic;
+ O_FilteredSampleValid : out std_logic;
+ O_sel_proc : out std_logic_vector (1 downto 0 )-- Data valid signal for filtered sample
+ );
+
+end entity controlUnit;
+architecture archi_operativeUnit of controlUnit is
+
+
+ type T_state is (WAIT_SAMPLE, STORE_X, PROCESSING_LOOP_Y, STORE_Y, PROCESSING_LOOP_Z_f, PROCESSING_LOOP_Z_b, STORE_Z, PROCESSING_LOOP_R, OUTPUT, WAIT_END_SAMPLE); -- state list
+ signal SR_presentState : T_state;
+ signal SR_futurState : T_state;
+
+begin
+
+-- initialisation de l'état
+ process (I_reset,I_clock) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_presentState <= WAIT_SAMPLE ;
+ elsif rising_edge(I_clock) then -- rising clock edge
+ SR_presentState <= SR_futurState ;
+ end if;
+ end process;
+
+
+-- transition
+ process (SR_presentState,I_inputSampleValid,I_processingDone) is
+ begin
+ case SR_presentState is
+ when WAIT_SAMPLE =>
+ if I_inputSampleValid = '1' then
+ SR_futurState <= STORE_X ;
+ else
+ SR_futurState <= WAIT_SAMPLE ;
+ end if;
+
+ when STORE_X =>
+ SR_futurState <= PROCESSING_LOOP_Y ;
+
+ when PROCESSING_LOOP_Y =>
+ if I_processingDone = '1' then
+ SR_futurState <= STORE_Y ;
+ else
+ SR_futurState <= PROCESSING_LOOP_Y ;
+ end if;
+
+ when STORE_Y =>
+ SR_futurState <= PROCESSING_LOOP_Z_f ;
+
+ when PROCESSING_LOOP_Z_f =>
+ if I_processingDone = '1' then
+ SR_futurState <= PROCESSING_LOOP_Z_b ;
+ else
+ SR_futurState <= PROCESSING_LOOP_Z_f ;
+ end if;
+
+ when PROCESSING_LOOP_Z_b =>
+ if I_processingDone = '1' then
+ SR_futurState <= STORE_Z ;
+ else
+ SR_futurState <= PROCESSING_LOOP_Z_b ;
+ end if;
+
+ when STORE_Z =>
+ SR_futurState <= PROCESSING_LOOP_R ;
+
+ when PROCESSING_LOOP_R =>
+ if I_processingDone = '1' then
+ SR_futurState <= OUTPUT ;
+ else
+ SR_futurState <= PROCESSING_LOOP_R ;
+ end if;
+
+ when OUTPUT =>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+ when WAIT_END_SAMPLE =>
+ if I_inputSampleValid = '0' then
+ SR_futurState <= WAIT_SAMPLE;
+ else
+ SR_futurState <= WAIT_END_SAMPLE ;
+ end if;
+
+ when others =>
+ SR_futurState <= WAIT_SAMPLE;
+ end case;
+ end process;
+
+
+
+
+ O_loadShiftX <= '1' when SR_presentState = STORE_X else '0' ;
+ O_loadShiftY <= '1' when SR_presentState = STORE_Y else '0' ;
+ O_loadShiftZ <= '1' when SR_presentState = STORE_Z else '0' ;
+ O_initAddress <= '1' when SR_presentState = STORE_X or SR_presentState = STORE_Y or SR_presentState = STORE_Z or (SR_presentState = PROCESSING_LOOP_Z_f and I_processingDone='1') else '0' ;
+ O_incrAddress <= '1' when (SR_presentState = PROCESSING_LOOP_Y or SR_presentState = PROCESSING_LOOP_Z_f or SR_presentState = PROCESSING_LOOP_Z_b or SR_presentState = PROCESSING_LOOP_R) else '0';
+ O_initSum <= '1' when SR_presentState = STORE_X or SR_presentState = STORE_Y or SR_presentState = STORE_Z else '0';
+ O_loadSum <= '1' when (SR_presentState = PROCESSING_LOOP_Y or SR_presentState = PROCESSING_LOOP_Z_f or SR_presentState = PROCESSING_LOOP_Z_b or SR_presentState = PROCESSING_LOOP_R) else '0' ;
+ O_loadOutput <= '1' when SR_presentState = OUTPUT or SR_presentState = STORE_Y or SR_presentState = STORE_Z else '0' ;
+ O_FilteredSampleValid <= '1' when SR_presentState = OUTPUT else '0' ;
+ O_sel_proc <= "01" when SR_presentState = STORE_Y or SR_presentState = PROCESSING_LOOP_Z_f else
+ "10" when SR_presentState = PROCESSING_LOOP_Z_b else
+ "11" when SR_presentState = STORE_Z or SR_presentState = PROCESSING_LOOP_R else
+ "00";
+
+
+
+
+end architecture archi_operativeUnit;
diff --git a/src/hdl/firUnit.vhd b/src/hdl/firUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7dd517feecd2eb92397e0c7f3d440f5432bfe421
--- /dev/null
+++ b/src/hdl/firUnit.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+-- Title : firUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2018-04-11
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity firUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 11 bit input sample
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(10 downto 0); -- filtered sample
+ O_filteredSampleValid : out std_logic
+ );
+
+end entity firUnit;
+
+architecture archi_firUnit of firUnit is
+
+ component controlUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSampleValid : in std_logic;
+ I_processingDone : in std_logic;
+ O_loadShiftX : out std_logic;
+ O_loadShiftY : out std_logic;
+ O_loadShiftZ : out std_logic;
+ O_initAddress : out std_logic;
+ O_incrAddress : out std_logic;
+ O_initSum : out std_logic;
+ O_loadSum : out std_logic;
+ O_loadOutput : out std_logic;
+ O_FilteredSampleValid : out std_logic;
+ O_sel_proc : out std_logic_vector (1 downto 0));
+ end component controlUnit;
+
+ component operativeUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSample : in std_logic_vector(10 downto 0);
+ I_loadShiftX : in std_logic;
+ I_loadShiftY : in std_logic;
+ I_loadShiftZ : in std_logic;
+ I_initAddress : in std_logic;
+ I_incrAddress : in std_logic;
+ I_initSum : in std_logic;
+ I_loadSum : in std_logic;
+ I_loadOutput : in std_logic;
+ I_sel_proc : in std_logic_vector (1 downto 0 );
+ O_processingDone : out std_logic;
+ O_R : out std_logic_vector(10 downto 0));
+ end component operativeUnit;
+
+ signal SC_processingDone : std_logic;
+ signal SC_loadShiftX : std_logic;
+ signal SC_loadShiftY : std_logic;
+ signal SC_loadShiftZ : std_logic;
+ signal SC_initAddress : std_logic;
+ signal SC_incrAddress : std_logic;
+ signal SC_initSum : std_logic;
+ signal SC_loadSum : std_logic;
+ signal SC_loadOutput : std_logic;
+ signal SC_sel_proc : std_logic_vector (1 downto 0);
+
+begin
+
+ controlUnit_1 : entity work.controlUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSampleValid => I_inputSampleValid,
+ I_processingDone => SC_processingDone,
+ O_loadShiftX => SC_loadShiftX,
+ O_loadShiftY => SC_loadShiftY,
+ O_loadShiftZ => SC_loadShiftZ,
+ O_initAddress => SC_initAddress,
+ O_incrAddress => SC_incrAddress,
+ O_initSum => SC_initSum,
+ O_loadSum => SC_loadSum,
+ O_loadOutput => SC_loadOutput,
+ O_FilteredSampleValid => O_FilteredSampleValid,
+ O_sel_proc => SC_sel_proc);
+
+ operativeUnit_1 : entity work.operativeUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSample => I_inputSample,
+ I_loadShiftX => SC_loadShiftX,
+ I_loadShiftY => SC_loadShiftY,
+ I_loadShiftZ => SC_loadShiftZ,
+ I_initAddress => SC_initAddress,
+ I_incrAddress => SC_incrAddress,
+ I_initSum => SC_initSum,
+ I_loadSum => SC_loadSum,
+ I_loadOutput => SC_loadOutput,
+ I_sel_proc => SC_sel_proc,
+ O_processingDone => SC_processingDone,
+ O_R => O_filteredSample);
+
+end architecture archi_firUnit;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..aa634b1d98d8546379fc46d4a3a00d8432e47980
--- /dev/null
+++ b/src/hdl/operativeUnit.vhd
@@ -0,0 +1,299 @@
+-------------------------------------------------------------------------------
+-- Title : operativeUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Operative unit of a sequential FIR filter. Including shift
+-- register for samples, registers for coefficients, a MAC and a register to
+-- store the result
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve
+-- the user experience ;)
+-- 2018-04-11 1.0 jnbazin Created
+-- 2018-04-18 1.0 marzel Modification of SR_Y assignment to a round
+-- instead of a trunc
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity operativeUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_loadShiftX : in std_logic;
+ I_loadShiftY : in std_logic;
+ I_loadShiftZ : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_initAddress : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress : in std_logic; -- Control signal to increment register read address
+ I_initSum : in std_logic; -- Control signal to initialize the MAC register
+ I_loadSum : in std_logic; -- Control signal to load the MAC register;
+ I_loadOutput : in std_logic;
+ I_sel_proc : in std_logic_vector (1 downto 0 );
+ O_processingDone : out std_logic; -- Indicate that processing is done
+ O_R : out std_logic_vector(10 downto 0) -- filtered sample
+ );
+
+end entity operativeUnit;
+
+architecture arch_operativeUnit of operativeUnit is
+ type registerFileH is array(0 to 94) of signed(11 downto 0);
+ type registerFileB is array(0 to 2) of signed(11 downto 0);
+ type registerFileA is array(0 to 1) of signed(11 downto 0);
+ type registerFileG is array(0 to 10) of signed(11 downto 0);
+
+ type registerFileX is array(0 to 94) of signed(10 downto 0);
+ type registerFileY is array(0 to 2) of signed(10 downto 0);
+ type registerFileZ is array(0 to 10) of signed(10 downto 0);
+
+ signal SR_shiftRegisterX : registerFileX;
+ signal SR_shiftRegisterY : registerFileY;
+ signal SR_shiftRegisterZ : registerFileZ;
+
+ signal SR_coefRegisterH : registerFileH;
+ signal SR_coefRegisterB : registerFileB;
+ signal SR_coefRegisterA : registerFileA;
+ signal SR_coefRegisterG : registerFileG;
+
+ -- shift register file used to store and shift input samples
+
+
+ signal SC_multOperand1 : signed(10 downto 0);
+ signal SC_multOperand2 : signed(11 downto 0);
+ signal SC_MultResult : signed(22 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(29 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(29 downto 0); -- Accumulation register
+ signal SR_R : signed(10 downto 0); -- filtered sample storage register
+ signal SR_readAddress : std_logic_vector(6 downto 0); -- register files read address
+
+
+
+begin
+
+-- Low-pass filter provided with octave (or Matlab ;)) command
+--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
+
+-- for i=18:112 printf("to_signed(%d,11),\n", round(fBaseLine(i)*2^10)) endfor
+
+SR_coefRegisterH <= (to_signed(-1,12),
+to_signed(-1,12),
+to_signed(-1,12),
+to_signed(-1,12),
+to_signed(-1,12),
+to_signed(-1,12),
+to_signed(-2,12),
+to_signed(-2,12),
+to_signed(-2,12),
+to_signed(-3,12),
+to_signed(-3,12),
+to_signed(-3,12),
+to_signed(-4,12),
+to_signed(-4,12),
+to_signed(-5,12),
+to_signed(-5,12),
+to_signed(-6,12),
+to_signed(-6,12),
+to_signed(-7,12),
+to_signed(-7,12),
+to_signed(-8,12),
+to_signed(-8,12),
+to_signed(-9,12),
+to_signed(-10,12),
+to_signed(-10,12),
+to_signed(-11,12),
+to_signed(-11,12),
+to_signed(-12,12),
+to_signed(-13,12),
+to_signed(-13,12),
+to_signed(-14,12),
+to_signed(-14,12),
+to_signed(-15,12),
+to_signed(-15,12),
+to_signed(-16,12),
+to_signed(-16,12),
+to_signed(-17,12),
+to_signed(-17,12),
+to_signed(-18,12),
+to_signed(-18,12),
+to_signed(-18,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(1004,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-19,12),
+to_signed(-18,12),
+to_signed(-18,12),
+to_signed(-18,12),
+to_signed(-17,12),
+to_signed(-17,12),
+to_signed(-16,12),
+to_signed(-16,12),
+to_signed(-15,12),
+to_signed(-15,12),
+to_signed(-14,12),
+to_signed(-14,12),
+to_signed(-13,12),
+to_signed(-13,12),
+to_signed(-12,12),
+to_signed(-11,12),
+to_signed(-11,12),
+to_signed(-10,12),
+to_signed(-10,12),
+to_signed(-9, 12),
+to_signed(-8, 12),
+to_signed(-8, 12),
+to_signed(-7, 12),
+to_signed(-7, 12),
+to_signed(-6, 12),
+to_signed(-6, 12),
+to_signed(-5, 12),
+to_signed(-5, 12),
+to_signed(-4, 12),
+to_signed(-4, 12),
+to_signed(-3, 12),
+to_signed(-3, 12),
+to_signed(-3, 12),
+to_signed(-2, 12),
+to_signed(-2, 12),
+to_signed(-2, 12),
+to_signed(-1, 12),
+to_signed(-1, 12),
+to_signed(-1, 12),
+to_signed(-1, 12),
+to_signed(-1, 12),
+to_signed(-1, 12));
+
+SR_coefRegisterA <= (to_signed(-1554,12), to_signed(897,12));
+SR_coefRegisterB <= (to_signed(961,12), to_signed(-1554,12), to_signed(961,12));
+
+SR_coefRegisterG <= (to_signed(-119,12),
+to_signed(122,12),
+to_signed(149,12),
+to_signed(191,12),
+to_signed(226,12),
+to_signed(239,12),
+to_signed(226,12),
+to_signed(191,12),
+to_signed(149,12),
+to_signed(122,12),
+to_signed(-119,12));
+
+
+ shiftX : process (I_clock,I_reset) is
+ begin -- process shift
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_shiftRegisterX <= (others => (others => '0'));
+ elsif rising_edge (I_clock) then
+ if I_loadShiftX ='1' then
+ SR_shiftRegisterX(0 to 93) <= SR_shiftRegisterX(1 to 94);
+ SR_shiftRegisterX(94) <= signed(I_inputSample);
+ end if;
+ end if;
+ end process shiftX;
+
+ shiftY : process (I_clock,I_reset) is
+ begin -- process shift
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_shiftRegisterY <= (others => (others => '0'));
+ elsif rising_edge (I_clock) then
+ if I_loadShiftY ='1' then
+ SR_shiftRegisterY(0 to 1) <= SR_shiftRegisterY(1 to 2);
+ SR_shiftRegisterY(2) <= SR_R;
+ end if;
+ end if;
+ end process shiftY;
+
+ shiftZ : process (I_clock,I_reset) is
+ begin -- process shift
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_shiftRegisterZ <= (others => (others => '0'));
+ elsif rising_edge (I_clock) then
+ if I_loadShiftZ ='1' then
+ SR_shiftRegisterZ(0 to 9) <= SR_shiftRegisterZ(1 to 10);
+ SR_shiftRegisterZ(10) <= SR_R;
+ end if;
+ end if;
+ end process shiftZ;
+
+ incr_address : process (I_reset,I_clock) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_readAddress <= (others => '0');
+ elsif rising_edge (I_clock) then
+ if I_incrAddress ='1' then
+ SR_readAddress <= std_logic_vector(unsigned(SR_readAddress) +1);
+ elsif I_initAddress ='1' then
+ SR_readAddress <= (others => '0');
+ end if;
+ end if;
+ end process incr_address;
+
+ O_processingDone <= '1' when (SR_readAddress = std_logic_vector(to_unsigned(93,7)) and I_sel_proc= "00")
+ OR (SR_readAddress = std_logic_vector(to_unsigned(1,7)) and I_sel_proc= "01")
+ OR (SR_readAddress = std_logic_vector(to_unsigned(0,7)) and I_sel_proc= "10")
+ OR (SR_readAddress = std_logic_vector(to_unsigned(9,7)) and I_sel_proc= "11") else '0';
+
+
+ SC_multOperand1 <= SR_shiftRegisterX(to_integer(unsigned(SR_readAddress))) when I_sel_proc= "00" else
+ SR_shiftRegisterY(to_integer(unsigned(SR_readAddress))) when I_sel_proc= "01" else
+ SR_shiftRegisterZ(to_integer(unsigned(SR_readAddress))); -- 11 bits
+ SC_multOperand2 <= SR_coefRegisterH(to_integer(unsigned(SR_readAddress))) when I_sel_proc= "00" else
+ SR_coefRegisterB(to_integer(unsigned(SR_readAddress))) when I_sel_proc= "01" else
+ - SR_coefRegisterA(to_integer(unsigned(SR_readAddress))) when I_sel_proc= "10" else
+ SR_coefRegisterG(to_integer(unsigned(SR_readAddress))); -- 11 bits
+ SC_MultResult <= SC_multOperand1*SC_multOperand2 ; -- 23 bits
+ SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+
+ sum_acc : process (I_reset,I_clock) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_sum <= (others => '0');
+ elsif rising_edge (I_clock) then
+ if I_loadSum ='1' then
+ SR_sum <= SC_addResult;
+ elsif I_initSum ='1' then
+ SR_sum <= (others => '0');
+ end if;
+ end if;
+ end process sum_acc;
+
+
+ store_result : process (I_clock) is
+ begin
+ if rising_edge (I_clock) then
+ if I_loadOutput ='1' then
+ if SR_sum(9)= '1' then
+ SR_R <= SR_sum(20 downto 10)+"00000001";
+ else
+ SR_R <= SR_sum(20 downto 10);
+ end if;
+ end if;
+ end if;
+
+ end process store_result;
+
+ O_R <= std_logic_vector(SR_R);
+
+end architecture arch_operativeUnit;