From 07f5f5c6b3834ac2214fa5dd2af41192d859cf3e Mon Sep 17 00:00:00 2001
From: Juliette DUMAS <j22duma2@fl-tp-br-632.imta.fr>
Date: Wed, 12 Feb 2025 12:21:29 +0100
Subject: [PATCH] TP loto
---
docs/compte-rendu.md | 2 +
src/automate.vhd | 80 +++++++++++++++++++++++++++++++---------
src/compteur_modulo4.vhd | 6 +--
src/compteur_modulo6.vhd | 12 ++++--
src/mux6_1.vhd | 8 +++-
5 files changed, 83 insertions(+), 25 deletions(-)
diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index bcc655d..af8f9e7 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -4,9 +4,11 @@
## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+Tous les signaux d'entrées dont les changements impactent le signal de sortie. Ici, I_0, I_1, I_2, I_3, I_4, I_5, I_sel.
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+Si le test n'est pas exhaustif, des LATCHs apparaîtront dans les ressources utilisées. Si les valeurs prises par le test correspondent bien à toute les valeurs prises réellement alors cela ne devrait pas poser problème en utilisation réelle mais attention aux erreurs d'inattention.
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
diff --git a/src/automate.vhd b/src/automate.vhd
index 1ccb931..fbb28e8 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,27 +36,73 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
- __BLANK_TO_FILL__
+ SR_STATE <= st_wait_success ;
elsif rising_edge(I_clk)then
- case SR_STATE is
- case SR_STATE is
-
- when st_wait_success =>
- O_l_green <= '1';
- O_l_red <= '0';
- O_counting <= '0';
- O_store <= '0';
- if I_button = '1' then
- SR_STATE <= st_counting;
+ if I_button = '1' and (SR_STATE = st_wait_success or SR_STATE = st_wait_failed) then
+ SR_STATE <= st_counting;
+ end if;
+ if SR_STATE = st_counting and I_button ='0' then
+ SR_STATE <= st_compar;
+ end if;
+ if SR_STATE=st_compar and i_invalide ='0' then
+ SR_STATE <= st_store;
+ elsif SR_STATE=st_compar then
+ SR_STATE <= st_wait_failed;
+ end if;
+ if SR_STATE = st_store and I_end='0' then
+ SR_STATE <= st_wait_success;
+ elsif SR_STATE = st_store and I_end='1' then
+ SR_STATE <= st_end_red;
+ end if;
+ if SR_STATE = st_end_red and I_clk_display='1' then
+ SR_STATE <= st_end_green;
+ end if;
+ if SR_STATE = st_end_green and I_clk_display='0' then
+ SR_STATE <= st_end_red;
end if;
-
- when __BLANK_TO_FILL__
-
- __BLANK_TO_FILL__
-
- end case;
end if;
end process;
+process (SR_STATE)
+begin
+ case SR_STATE is
+ when st_wait_success =>
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ when st_wait_failed =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ when st_counting =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '1';
+ O_store <= '0';
+ when st_compar =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ when st_store =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '1';
+ when st_end_green =>
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ when st_end_red =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ end case;
+end process;
+
end a_automate;
diff --git a/src/compteur_modulo4.vhd b/src/compteur_modulo4.vhd
index f2b951f..c7d26dc 100644
--- a/src/compteur_modulo4.vhd
+++ b/src/compteur_modulo4.vhd
@@ -20,12 +20,12 @@ architecture modulo4_a of compteur_modulo4 is
begin
- mod4 : process (clk, rst)
+ mod4 : process (I_clk, I_rst)
begin
- if rst = '1' then
+ if I_rst = '1' then
SR_Counter <= "00";
- elsif rising_edge(clk) then
+ elsif rising_edge(I_clk) then
if SR_Counter = "11" then
SR_Counter <= "00";
else
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 7962a90..469f28c 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -20,12 +20,18 @@ architecture modulo6_a of compteur_modulo6 is
begin
- process (_BLANK_)
+ process (I_clk,I_rst)
begin
if I_rst = '1' then
- _BLANK_
+ SR_Counter <= "000" ;
elsif rising_edge(I_clk) then
- _BLANK_
+ if I_block ='1' then
+ SR_Counter <= SR_Counter;
+ elsif SR_Counter = "101" then
+ SR_Counter <= "000";
+ else
+ SR_Counter <= SR_Counter +1;
+ end if;
end if;
end process;
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
index a689bef..17b7e0e 100644
--- a/src/mux6_1.vhd
+++ b/src/mux6_1.vhd
@@ -20,8 +20,12 @@ end mux6_1;
architecture a_mux6_1 of mux6_1 is
begin
-__BLANK_TO_FILL__
-
+O_mux6 <= I_0 when (I_sel = "000") else
+ I_1 when (I_sel = "001") else
+ I_2 when (I_sel = "010") else
+ I_3 when (I_sel = "011") else
+ I_4 when (I_sel = "100") else
+ I_5;
end a_mux6_1;
--
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