From d7292a81a1e179cb9853e3718b0ae6b8e44a2cfe Mon Sep 17 00:00:00 2001 From: MENEGON XAVIER Joao Vitor <joao-vitor.menegon-xavier@imt-atlantique.net> Date: Fri, 28 Mar 2025 13:35:05 +0000 Subject: [PATCH] Update file controlUnit.vhd --- sources/controlUnit.vhd | 159 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 sources/controlUnit.vhd diff --git a/sources/controlUnit.vhd b/sources/controlUnit.vhd new file mode 100644 index 0000000..26fe9cb --- /dev/null +++ b/sources/controlUnit.vhd @@ -0,0 +1,159 @@ +------------------------------------------------------------------------------- +-- Title : controlUnit +-- Project : +------------------------------------------------------------------------------- +-- File : operativeUnit.vhd +-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr> +-- Company : +-- Created : 2018-04-11 +-- Last update: 2019-02-13 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Copyright (c) 2018 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2018-04-11 1.0 jnbazin Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity controlUnit is + + port ( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_processingDoneFIR1 : in std_logic; + I_processingDoneFIR2 : in std_logic; + I_processingDoneIIR : in std_logic; + I_loadShiftFIR1 : in std_logic; + I_loadShiftIIR : in std_logic; + I_loadShiftFIR2 : in std_logic; + I_selectSample : in std_logic; + I_selectCoeff : in std_logic; + I_initAddress : in std_logic; + I_incrAddress : in std_logic; + I_initSum : in std_logic; + I_loadSum : in std_logic; + I_loadOut : in std_logic; + O_loadShift : out std_logic; -- filtered sample + O_initAddress : out std_logic; -- Control signal to initialize register read address + O_incrAddress : out std_logic; -- Control signal to increment register read address + O_initSum : out std_logic; -- Control signal to initialize the MAC register + O_loadSum : out std_logic; -- Control signal to load the MAC register; + O_loadY : out std_logic; -- Control signal to load Y register + O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample + ); + +end entity controlUnit; +architecture archi_operativeUnit of controlUnit is + + + type T_state is (WAIT_SAMPLE, STORE_FIR1, PROCESSING_LOOP_FIR1, STORE_IIR1, PROCESSING_LOOP_IIR1, INIT_ADDRESS, PROCESSING_LOOP_IIR2, STORE_FIR2, PROCESSING_LOOP_FIR2, OUTPUT, WAIT_END_SAMPLE); -- state list + signal SR_presentState : T_state; + signal SR_futurState : T_state; + +begin + + process (I_reset, I_clock) is + begin + if I_reset = '1' then -- asynchronous reset (active high) + SR_presentState <= WAIT_SAMPLE; + elsif rising_edge(I_clock) then -- rising clock edge + SR_presentState <= SR_futurState; + end if; + end process; + + process (SR_presentState, I_inputSampleValid, I_processingDoneFIR1, I_processingDoneFIR2, I_processingDoneIIR) is + begin + case SR_presentState is + + when WAIT_SAMPLE => + if (I_inputSampleValid = '1') then + SR_futurState <= STORE_FIR1; + else + SR_futurState <= WAIT_SAMPLE; + end if; + + when STORE_FIR1 => + SR_futurState <= PROCESSING_LOOP_FIR1; + + when PROCESSING_LOOP_FIR1 => + if (I_processingDoneFIR1 = '1') then + SR_futurState <= STORE_IIR1; + else + SR_futurState <= PROCESSING_LOOP_FIR1; + end if; + + when STORE_IIR1 => + SR_futurState <= PROCESSING_LOOP_IIR1; + + when PROCESSING_LOOP_IIR1 => + if (I_processingDoneIIR = '1') then + SR_futurState <= INIT_ADDRESS; + else + SR_futurState <= PROCESSING_LOOP_IIR1; + end if; + + when INIT_ADDRESS => + SR_futurState <= PROCESSING_LOOP_IIR2; + + when PROCESSING_LOOP_IIR2 => + if (I_processingDoneIIR = '1') then + SR_futurState <= STORE_FIR2; + else + SR_futurState <= PROCESSING_LOOP_IIR2; + end if; + + when STORE_FIR2 => + SR_futurState <= PROCESSING_LOOP_FIR2; + + when PROCESSING_LOOP_FIR2 => + if (I_processingDoneFIR2 = '1') then + SR_futurState <= OUTPUT; + else + SR_futurState <= PROCESSING_LOOP_FIR2; + end if; + + when OUTPUT => + SR_futurState <= WAIT_END_SAMPLE; + + when WAIT_END_SAMPLE => + if (I_inputSampleValid = '0') then + SR_futurState <= WAIT_SAMPLE; + else + SR_futurState <= WAIT_END_SAMPLE; + end if; + + when others => + SR_futurState <= WAIT_SAMPLE; + + end case; + end process; + + --WAIT_SAMPLE, STORE_FIR1, PROCESSING_LOOP_FIR1, , , INIT_ADDRESS, , , , OUTPUT, WAIT_END_SAMPLE + + I_loadShiftFIR1 <= '1' when SR_presentState=STORE_FIR1 else '0'; + I_loadShiftIIR <= '1' when SR_presentState=STORE_IIR1 else '0'; + I_loadShiftFIR2 <= '1' when SR_presentState=STORE_FIR2 else '0'; + + I_selectSample <= "01" when SR_presentState=STORE_IIR1 else + "10" when SR_presentState=PROCESSING_LOOP_IIR2 else "00"; + + I_selectCoeff <= "01" when (SR_presentState=STORE_IIR1) or (SR_presentState=PROCESSING_LOOP_IIR1) else + "10" when SR_presentState=PROCESSING_LOOP_IIR2 else + "11" when (SR_presentState=STORE_FIR2) (SR_presentState=PROCESSING_LOOP_FIR2) else "00"; + + I_initAddress <= '1' when (SR_presentState=STORE_FIR1) or (SR_presentState=STORE_IIR1) or (SR_presentState=INIT_ADDRESS) or (SR_presentState=STORE_FIR2) else '0'; + I_incrAddress <= '1' when (SR_presentState=PROCESSING_LOOP_FIR1) or (SR_presentState=PROCESSING_LOOP_IIR1) or (SR_presentState=PROCESSING_LOOP_FIR2) else '0'; + I_initSum <= '1' when (SR_presentState=STORE_FIR1) or (SR_presentState=STORE_IIR1) or (SR_presentState=STORE_FIR2) else '0'; + I_loadSum <= '1' when (SR_presentState=PROCESSING_LOOP_FIR1) or (SR_presentState=PROCESSING_LOOP_IIR1) or (SR_presentState=PROCESSING_LOOP_IIR2) or (SR_presentState=PROCESSING_LOOP_FIR2) else '0'; + I_loadOut <= '1' when SR_presentState=OUTPUT else '0'; + + + +end architecture archi_operativeUnit; \ No newline at end of file -- GitLab