From 6a1dabca60b53d5c3e056c6c301492aa22ccd9f5 Mon Sep 17 00:00:00 2001 From: Michelly LUIS LACERDA <m24luisl@fl-tp-br-635.imta.fr> Date: Wed, 26 Mar 2025 17:03:25 +0100 Subject: [PATCH] control et operative unit incomplet --- project_1/project_1.cache/wt/project.wpc | 3 + project_1/project_1.hw/project_1.lpr | 7 + .../project_1.srcs/sources_1/new/FSM_ecg.v | 146 ++++++++++++ .../sources_1/new/controlUnit.v | 145 ++++++++++++ .../sources_1/new/controlUnit.vhd | 162 +++++++++++++ .../sources_1/new/operativeUnit.vhd | 145 ++++++++++++ project_1/project_1.xpr | 223 ++++++++++++++++++ 7 files changed, 831 insertions(+) create mode 100644 project_1/project_1.cache/wt/project.wpc create mode 100644 project_1/project_1.hw/project_1.lpr create mode 100644 project_1/project_1.srcs/sources_1/new/FSM_ecg.v create mode 100644 project_1/project_1.srcs/sources_1/new/controlUnit.v create mode 100644 project_1/project_1.srcs/sources_1/new/controlUnit.vhd create mode 100644 project_1/project_1.srcs/sources_1/new/operativeUnit.vhd create mode 100644 project_1/project_1.xpr diff --git a/project_1/project_1.cache/wt/project.wpc b/project_1/project_1.cache/wt/project.wpc new file mode 100644 index 0000000..9b34209 --- /dev/null +++ b/project_1/project_1.cache/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/project_1/project_1.hw/project_1.lpr b/project_1/project_1.hw/project_1.lpr new file mode 100644 index 0000000..afc0a86 --- /dev/null +++ b/project_1/project_1.hw/project_1.lpr @@ -0,0 +1,7 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<labtools version="1" minor="0"/> diff --git a/project_1/project_1.srcs/sources_1/new/FSM_ecg.v b/project_1/project_1.srcs/sources_1/new/FSM_ecg.v new file mode 100644 index 0000000..521e59a --- /dev/null +++ b/project_1/project_1.srcs/sources_1/new/FSM_ecg.v @@ -0,0 +1,146 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/26/2025 03:19:30 PM +// Design Name: +// Module Name: FSM_ecg +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity FSM_ecg is + + port ( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_processingDone_FIR1 : in std_logic; + I_processingDone_X_IIR : in std_logic; + I_processingDone_Y_IIR : in std_logic; + I_processingDone_FIR2 : in std_logic; + O_loadShift_FIR1 : out std_logic; -- filtered sample + O_loadShift_IIR : out std_logic; -- filtered sample + O_loadShift_FIR2 : out std_logic; -- filtered sample + O_initAddress : out std_logic; -- Control signal to initialize register read address + O_incrAddress : out std_logic; -- Control signal to increment register read address + O_initSum : out std_logic; -- Control signal to initialize the MAC register + O_loadSum : out std_logic; -- Control signal to load the MAC register; + O_loadOutput : out std_logic; -- Control signal to load Y register + O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample + ); + +end entity controlUnit; +architecture archi_operativeUnit of controlUnit is + + + type T_state is (WAIT_SAMPLE, STORE_FIR1, PROCESSING_LOOP_FIR1, STORE_IIR, PROCESSING_LOOP_X_IIR, INIT_Y, + PROCESSING_LOOP_Y_IIR, STORE_FIR2, PROCESSING_LOOP_FIR2, OUTPUT, WAIT_END_SAMPLE); -- state list + signal SR_presentState : T_state; + signal SR_futurState : T_state; + +begin + + process (I_clock,I_reset) is + begin + if I_reset = '1' then -- asynchronous reset (active high) + SR_presentState <= WAIT_SAMPLE; + elsif rising_edge(I_clock) then -- rising clock edge + SR_presentState <= SR_futurState; + end if; + end process; + + process (SR_presentState,I_inputSampleValid,I_processingDone_FIR1,I_processingDone_X_IIR,I_processingDone_Y_IIR,I_processingDone_FIR2) is + begin + case SR_presentState is + + when WAIT_SAMPLE => + if I_inputSampleValid = '1' then + SR_futurState <= STORE_FIR1; + else + SR_futurState <= WAIT_SAMPLE; + end if; + + when STORE_FIR1 => + SR_futurState <= PROCESSING_LOOP_FIR1; + + when PROCESSING_LOOP_FIR1 => + if I_processingDone_FIR1 = '1' then + SR_futurState <= STORE_IIR; + else + SR_futurState <= PROCESSING_LOOP_FIR1; + end if; + + when STORE_IIR => + SR_futurState <= PROCESSING_LOOP_X_IIR; + + when PROCESSING_LOOP_X_IIR => + if I_processingDone_X_IIR = '1' then + SR_futurState <= INIT_Y; + else + SR_futurState <= PROCESSING_LOOP_X_IIR; + end if; + + when INIT_Y => + SR_futurState <= PROCESSING_LOOP_Y_IIR; + + when PROCESSING_LOOP_Y_IIR => + if I_processingDone_Y_IIR = '1' then + SR_futurState <= STORE_FIR2; + else + SR_futurState <= PROCESSING_LOOP_Y_IIR; + end if; + + when STORE_FIR2 => + SR_futurState <= PROCESSING_LOOP_FIR2; + + when PROCESSING_LOOP_FIR2 => + if I_processingDone_FIR2 = '1' then + SR_futurState <= OUTPUT; + else + SR_futurState <= PROCESSING_LOOP_FIR2; + end if; + + when OUTPUT => + SR_futurState <= WAIT_END_SAMPLE; + + when WAIT_END_SAMPLE => + if I_inputSampleValid = '0' then + SR_futurState <= WAIT_SAMPLE; + else + SR_futurState <= WAIT_END_SAMPLE; + end if; + + when others => + SR_futurState <= WAIT_SAMPLE; + end case; + end process; + + + + O_loadShift_FIR1 <= '1' when SR_presentState = STORE_FIR1 else '0' ; + O_loadShift_IIR <= '1' when SR_presentState = STORE else '0' ; + O_loadShift_FIR2 <= '1' when SR_presentState = STORE else '0' ; + O_initAddress <= '1' when SR_presentState = STORE_FIR1 OR STORE_IIR OR STORE_FIR2 else '0' ; + O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR PROCESSING_LOOP_X_IIR OR PROCESSING_LOOP_Y_IIR OR PROCESSING_LOOP_FIR2 else '0' ; + O_initSum <= '1' when SR_presentState = STORE_FIR1 OR STORE_IIR OR STORE_FIR2 else '0' ; + O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR PROCESSING_LOOP_X_IIR OR PROCESSING_LOOP_Y_IIR OR PROCESSING_LOOP_FIR2 else '0' ; + O_loadOutput <= '1' when SR_presentState = OUTPUT else '0' ; + -- O_FilteredSampleValid <= '1' when _BLANK_ ; ???? + +end architecture archi_operativeUnit; + diff --git a/project_1/project_1.srcs/sources_1/new/controlUnit.v b/project_1/project_1.srcs/sources_1/new/controlUnit.v new file mode 100644 index 0000000..de01018 --- /dev/null +++ b/project_1/project_1.srcs/sources_1/new/controlUnit.v @@ -0,0 +1,145 @@ + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/26/2025 04:13:28 PM +// Design Name: +// Module Name: controlUnit +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity FSM_ecg is + + port ( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_processingDone_FIR1 : in std_logic; + I_processingDone_X_IIR : in std_logic; + I_processingDone_Y_IIR : in std_logic; + I_processingDone_FIR2 : in std_logic; + O_loadShift_FIR1 : out std_logic; -- filtered sample + O_loadShift_IIR : out std_logic; -- filtered sample + O_loadShift_FIR2 : out std_logic; -- filtered sample + O_initAddress : out std_logic; -- Control signal to initialize register read address + O_incrAddress : out std_logic; -- Control signal to increment register read address + O_initSum : out std_logic; -- Control signal to initialize the MAC register + O_loadSum : out std_logic; -- Control signal to load the MAC register; + O_loadOutput : out std_logic; -- Control signal to load Y register + O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample + ); + +end entity controlUnit; +architecture archi_operativeUnit of controlUnit is + + + type T_state is (WAIT_SAMPLE, STORE_FIR1, PROCESSING_LOOP_FIR1, STORE_IIR, PROCESSING_LOOP_X_IIR, INIT_Y, + PROCESSING_LOOP_Y_IIR, STORE_FIR2, PROCESSING_LOOP_FIR2, OUTPUT, WAIT_END_SAMPLE); -- state list + signal SR_presentState : T_state; + signal SR_futurState : T_state; + +begin + + process (I_clock,I_reset) is + begin + if I_reset = '1' then -- asynchronous reset (active high) + SR_presentState <= WAIT_SAMPLE; + elsif rising_edge(I_clock) then -- rising clock edge + SR_presentState <= SR_futurState; + end if; + end process; + + process (SR_presentState,I_inputSampleValid,I_processingDone_FIR1,I_processingDone_X_IIR,I_processingDone_Y_IIR,I_processingDone_FIR2) is + begin + case SR_presentState is + + when WAIT_SAMPLE => + if I_inputSampleValid = '1' then + SR_futurState <= STORE_FIR1; + else + SR_futurState <= WAIT_SAMPLE; + end if; + + when STORE_FIR1 => + SR_futurState <= PROCESSING_LOOP_FIR1; + + when PROCESSING_LOOP_FIR1 => + if I_processingDone_FIR1 = '1' then + SR_futurState <= STORE_IIR; + else + SR_futurState <= PROCESSING_LOOP_FIR1; + end if; + + when STORE_IIR => + SR_futurState <= PROCESSING_LOOP_X_IIR; + + when PROCESSING_LOOP_X_IIR => + if I_processingDone_X_IIR = '1' then + SR_futurState <= INIT_Y; + else + SR_futurState <= PROCESSING_LOOP_X_IIR; + end if; + + when INIT_Y => + SR_futurState <= PROCESSING_LOOP_Y_IIR; + + when PROCESSING_LOOP_Y_IIR => + if I_processingDone_Y_IIR = '1' then + SR_futurState <= STORE_FIR2; + else + SR_futurState <= PROCESSING_LOOP_Y_IIR; + end if; + + when STORE_FIR2 => + SR_futurState <= PROCESSING_LOOP_FIR2; + + when PROCESSING_LOOP_FIR2 => + if I_processingDone_FIR2 = '1' then + SR_futurState <= OUTPUT; + else + SR_futurState <= PROCESSING_LOOP_FIR2; + end if; + + when OUTPUT => + SR_futurState <= WAIT_END_SAMPLE; + + when WAIT_END_SAMPLE => + if I_inputSampleValid = '0' then + SR_futurState <= WAIT_SAMPLE; + else + SR_futurState <= WAIT_END_SAMPLE; + end if; + + when others => + SR_futurState <= WAIT_SAMPLE; + end case; + end process; + + + + O_loadShift_FIR1 <= '1' when SR_presentState = STORE_FIR1 else '0' ; + O_loadShift_IIR <= '1' when SR_presentState = STORE else '0' ; + O_loadShift_FIR2 <= '1' when SR_presentState = STORE else '0' ; + O_initAddress <= '1' when SR_presentState = STORE_FIR1 OR STORE_IIR OR STORE_FIR2 else '0' ; + O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR PROCESSING_LOOP_X_IIR OR PROCESSING_LOOP_Y_IIR OR PROCESSING_LOOP_FIR2 else '0' ; + O_initSum <= '1' when SR_presentState = STORE_FIR1 OR STORE_IIR OR STORE_FIR2 else '0' ; + O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR PROCESSING_LOOP_X_IIR OR PROCESSING_LOOP_Y_IIR OR PROCESSING_LOOP_FIR2 else '0' ; + O_loadOutput <= '1' when SR_presentState = OUTPUT else '0' ; + -- O_FilteredSampleValid <= '1' when _BLANK_ ; ???? + +end architecture archi_operativeUnit; diff --git a/project_1/project_1.srcs/sources_1/new/controlUnit.vhd b/project_1/project_1.srcs/sources_1/new/controlUnit.vhd new file mode 100644 index 0000000..469a31f --- /dev/null +++ b/project_1/project_1.srcs/sources_1/new/controlUnit.vhd @@ -0,0 +1,162 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03/26/2025 04:14:55 PM +-- Design Name: +-- Module Name: controlUnit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity controlUnit is +-- Port ( ); + +port ( + I_clock : in std_logic; -- global clock + I_reset : in std_logic; -- asynchronous global reset + I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register + I_processingDone_FIR1 : in std_logic; + I_processingDone_X_IIR : in std_logic; + I_processingDone_Y_IIR : in std_logic; + I_processingDone_FIR2 : in std_logic; + O_loadShift_FIR1 : out std_logic; -- filtered sample + O_loadShift_IIR : out std_logic; -- filtered sample + O_loadShift_FIR2 : out std_logic; -- filtered sample + O_initAddress : out std_logic; -- Control signal to initialize register read address + O_incrAddress : out std_logic; -- Control signal to increment register read address + O_initSum : out std_logic; -- Control signal to initialize the MAC register + O_loadSum : out std_logic; -- Control signal to load the MAC register; + O_loadOutput : out std_logic; -- Control signal to load Y register + O_sel : out std_logic_vector(1 downto 0); + O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample + ); +end controlUnit; + +architecture Behavioral of controlUnit is + + +type T_state is (WAIT_SAMPLE, STORE_FIR1, PROCESSING_LOOP_FIR1, STORE_IIR, PROCESSING_LOOP_X_IIR, INIT_Y, + PROCESSING_LOOP_Y_IIR, STORE_FIR2, PROCESSING_LOOP_FIR2, OUTPUT, WAIT_END_SAMPLE); -- state list + signal SR_presentState : T_state; + signal SR_futurState : T_state; + +begin + + process (I_clock,I_reset) is + begin + if I_reset = '1' then -- asynchronous reset (active high) + SR_presentState <= WAIT_SAMPLE; + elsif rising_edge(I_clock) then -- rising clock edge + SR_presentState <= SR_futurState; + end if; + end process; + + process (SR_presentState,I_inputSampleValid,I_processingDone_FIR1,I_processingDone_X_IIR,I_processingDone_Y_IIR,I_processingDone_FIR2) is + begin + case SR_presentState is + + when WAIT_SAMPLE => + if I_inputSampleValid = '1' then + SR_futurState <= STORE_FIR1; + else + SR_futurState <= WAIT_SAMPLE; + end if; + + when STORE_FIR1 => + O_sel <= "00"; + SR_futurState <= PROCESSING_LOOP_FIR1; + + when PROCESSING_LOOP_FIR1 => + if I_processingDone_FIR1 = '1' then + SR_futurState <= STORE_IIR; + else + SR_futurState <= PROCESSING_LOOP_FIR1; + end if; + + when STORE_IIR => + O_sel <= "01"; + SR_futurState <= PROCESSING_LOOP_X_IIR; + + when PROCESSING_LOOP_X_IIR => + if I_processingDone_X_IIR = '1' then + SR_futurState <= INIT_Y; + else + SR_futurState <= PROCESSING_LOOP_X_IIR; + end if; + + when INIT_Y => + O_sel <= "10"; + SR_futurState <= PROCESSING_LOOP_Y_IIR; + + when PROCESSING_LOOP_Y_IIR => + if I_processingDone_Y_IIR = '1' then + SR_futurState <= STORE_FIR2; + else + SR_futurState <= PROCESSING_LOOP_Y_IIR; + end if; + + when STORE_FIR2 => + O_sel <= "11"; + SR_futurState <= PROCESSING_LOOP_FIR2; + + when PROCESSING_LOOP_FIR2 => + if I_processingDone_FIR2 = '1' then + SR_futurState <= OUTPUT; + else + SR_futurState <= PROCESSING_LOOP_FIR2; + end if; + + when OUTPUT => + SR_futurState <= WAIT_END_SAMPLE; + + when WAIT_END_SAMPLE => + if I_inputSampleValid = '0' then + SR_futurState <= WAIT_SAMPLE; + else + SR_futurState <= WAIT_END_SAMPLE; + end if; + + when others => + SR_futurState <= WAIT_SAMPLE; + end case; + end process; + + + + O_loadShift_FIR1 <= '1' when SR_presentState = STORE_FIR1 else '0' ; + O_loadShift_IIR <= '1' when SR_presentState = STORE_IIR else '0' ; + O_loadShift_FIR2 <= '1' when SR_presentState = STORE_FIR2 else '0' ; + O_initAddress <= '1' when SR_presentState = STORE_FIR1 OR SR_presentState = STORE_IIR OR SR_presentState = STORE_FIR2 else '0' ; + O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR SR_presentState = PROCESSING_LOOP_X_IIR OR SR_presentState = PROCESSING_LOOP_Y_IIR OR SR_presentState = PROCESSING_LOOP_FIR2 else '0' ; + O_initSum <= '1' when SR_presentState = STORE_FIR1 OR SR_presentState = STORE_IIR OR SR_presentState = STORE_FIR2 else '0' ; + O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP_FIR1 OR SR_presentState = PROCESSING_LOOP_X_IIR OR SR_presentState = PROCESSING_LOOP_Y_IIR OR SR_presentState = PROCESSING_LOOP_FIR2 else '0' ; + O_loadOutput <= '1' when SR_presentState = OUTPUT else '0' ; + -- O_FilteredSampleValid <= '1' when _BLANK_ ; ???? + +end architecture Behavioral; + + diff --git a/project_1/project_1.srcs/sources_1/new/operativeUnit.vhd b/project_1/project_1.srcs/sources_1/new/operativeUnit.vhd new file mode 100644 index 0000000..b6d21dd --- /dev/null +++ b/project_1/project_1.srcs/sources_1/new/operativeUnit.vhd @@ -0,0 +1,145 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03/26/2025 04:22:28 PM +-- Design Name: +-- Module Name: operativeUnit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity operativeUnit is +-- Port ( ); +end operativeUnit; + +architecture Behavioral of operativeUnit is + type registerFile is array(0 to 94) of signed(10 downto 0); + signal SR_coefRegister_FIR1 : registerFile; + +begin + +SR_coefRegister_FIR1 <= (to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-2, 11), + to_signed(-2, 11), + to_signed(-2, 11), + to_signed(-3, 11), + to_signed(-3, 11), + to_signed(-3, 11), + to_signed(-4, 11), + to_signed(-4, 11), + to_signed(-5, 11), + to_signed(-5, 11), + to_signed(-6, 11), + to_signed(-6, 11), + to_signed(-7, 11), + to_signed(-7, 11), + to_signed(-8, 11), + to_signed(-8, 11), + to_signed(-9, 11), + to_signed(-10, 11), + to_signed(-10, 11), + to_signed(-11, 11), + to_signed(-11, 11), + to_signed(-12, 11), + to_signed(-13, 11), + to_signed(-13, 11), + to_signed(-14, 11), + to_signed(-14, 11), + to_signed(-15, 11), + to_signed(-15, 11), + to_signed(-16, 11), + to_signed(-16, 11), + to_signed(-17, 11), + to_signed(-17, 11), + to_signed(-18, 11), + to_signed(-18, 11), + to_signed(-18, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(1004, 121, + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-19, 11), + to_signed(-18, 11), + to_signed(-18, 11), + to_signed(-18, 11), + to_signed(-17, 11), + to_signed(-17, 11), + to_signed(-16, 11), + to_signed(-16, 11), + to_signed(-15, 11), + to_signed(-15, 11), + to_signed(-14, 11), + to_signed(-14, 11), + to_signed(-13, 11), + to_signed(-13, 11), + to_signed(-12, 11), + to_signed(-11, 11), + to_signed(-11, 11), + to_signed(-10, 11), + to_signed(-10, 11), + to_signed(-9, 11), + to_signed(-8, 11), + to_signed(-8, 11), + to_signed(-7, 11), + to_signed(-7, 11), + to_signed(-6, 11), + to_signed(-6, 11), + to_signed(-5, 11), + to_signed(-5, 11), + to_signed(-4, 11), + to_signed(-4, 11), + to_signed(-3, 11), + to_signed(-3, 11), + to_signed(-3, 11), + to_signed(-2, 11), + to_signed(-2, 11), + to_signed(-2, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11), + to_signed(-1, 11) + ); + + + + +end Behavioral; diff --git a/project_1/project_1.xpr b/project_1/project_1.xpr new file mode 100644 index 0000000..893001d --- /dev/null +++ b/project_1/project_1.xpr @@ -0,0 +1,223 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<Project Product="Vivado" Version="7" Minor="67" Path="/homes/m24luisl/project_1/project_1.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="ee81de0c9dfe421bad27c54a6f4a5d9e"/> + <Option Name="Part" Val="xc7a12ticsg325-1L"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2024.1"/> + <Option Name="SimulatorVersionModelSim" Val="2023.2"/> + <Option Name="SimulatorVersionQuesta" Val="2023.2"/> + <Option Name="SimulatorVersionXcelium" Val="23.03.002"/> + <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/> + <Option Name="SimulatorVersionRiviera" Val="2023.04"/> + <Option Name="SimulatorVersionActiveHdl" Val="14.1"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="BoardPart" Val=""/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="ClassicSocBoot" Val="FALSE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="32"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/controlUnit.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/operativeUnit.vhd"> + <FileInfo> + <Attr Name="AutoDisabled" Val="1"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="controlUnit"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="controlUnit"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Xcelium"> + <Option Name="Description" Val="Xcelium Parallel Simulator"/> + </Simulator> + <Simulator Name="VCS"> + <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="22"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a12ticsg325-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board/> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> -- GitLab