diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index bd839a9b01be6c20eb7b6840fcbab9fd73e2336d..99d7eb328651c1c52020d0df7e39679ef199adbb 100644
--- a/docs/img/FSM.drawio
+++ b/docs/img/FSM.drawio
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index 9bb0e4be6bf247cea4d08b3cc71698bff753d164..92b94638ef85556e0e5c7b27b3bacb30938901cf 100644
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diff --git a/docs/img/OperativeUnit.png b/docs/img/OperativeUnit.png
index 64a947ab89b5c179f8cda30834baa893918774d1..12b344251c2d86da2dd0fdc330bdd96af0867535 100644
Binary files a/docs/img/OperativeUnit.png and b/docs/img/OperativeUnit.png differ
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4b08342baf8b23039bac65422d7b94614007bfd1
--- /dev/null
+++ b/src/hdl/controlUnit.vhd
@@ -0,0 +1,147 @@
+-------------------------------------------------------------------------------
+-- Title : controlUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Control unit of a sequential FIR filter.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity controlUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_processingDone : in std_logic;
+ O_loadShift1 : out std_logic; -- filtered sample
+ O_loadShift2 : out std_logic; -- filtered sample
+ O_loadShift3 : out std_logic; -- filtered sample
+ O_initAddress : out std_logic; -- Control signal to initialize register read address
+ O_incrAddress : out std_logic; -- Control signal to increment register read address
+ O_initSum : out std_logic; -- Control signal to initialize the MAC register
+ O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadY : out std_logic; -- Control signal to load Y register
+ O_coefSelect : out std_logic_vector(1 downto 0);
+ O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
+ );
+
+end entity controlUnit;
+architecture archi_operativeUnit of controlUnit is
+
+
+ type T_state is (WAIT_SAMPLE, STORE, PROCESSING_LOOP_1, PROCESSING_LOOP_2_1, PROCESSING_LOOP_2_2, PROCESSING_LOOP_3, OUTPUT_1, OUTPUT_2, OUTPUT_3, ADDRESS_RESET, WAIT_END_SAMPLE); -- state list
+ signal SR_presentState : T_state;
+ signal SR_futurState : T_state;
+
+begin
+
+ process (I_clock,I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_presentState <= WAIT_SAMPLE;
+ elsif rising_edge(I_clock) then -- rising clock edge
+ SR_presentState <= SR_futurState;
+ end if;
+ end process;
+
+ process (SR_presentState, I_inputSampleValid, I_processingDone) is
+ begin
+ case SR_presentState is
+
+ when WAIT_SAMPLE =>
+ if I_inputSampleValid = '1' then
+ SR_futurState <= STORE;
+ else
+ SR_futurState <= WAIT_SAMPLE;
+ end if;
+
+ when STORE =>
+ SR_futurState <= PROCESSING_LOOP_1;
+
+ when PROCESSING_LOOP_1 =>
+ O_coefSelect <= "00";
+ if I_processingDone = '1' then
+ SR_futurState <= OUTPUT_1;
+ else
+ SR_futurState <= PROCESSING_LOOP_1;
+ end if;
+
+ when OUTPUT_1 =>
+ SR_futurState <= PROCESSING_LOOP_2_1;
+
+ when PROCESSING_LOOP_2_1 =>
+ O_coefSelect <= "01";
+ if I_processingDone = '1' then
+ SR_futurState <= ADDRESS_RESET;
+ else
+ SR_futurState <= PROCESSING_LOOP_2_1;
+ end if;
+
+ when ADDRESS_RESET =>
+ SR_futurState <= PROCESSING_LOOP_2_2;
+
+ when PROCESSING_LOOP_2_2 =>
+ O_coefSelect <= "10";
+ if I_processingDone = '1' then
+ SR_futurState <= OUTPUT_2;
+ else
+ SR_futurState <= PROCESSING_LOOP_2_2;
+ end if;
+
+ when OUTPUT_2 =>
+ SR_futurState <= PROCESSING_LOOP_3;
+
+ when PROCESSING_LOOP_3 =>
+ O_coefSelect <= "11";
+ if I_processingDone = '1' then
+ SR_futurState <= OUTPUT_3;
+ else
+ SR_futurState <= PROCESSING_LOOP_3;
+ end if;
+
+ when OUTPUT_3 =>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+ when WAIT_END_SAMPLE =>
+ if I_inputSampleValid = '0' then
+ SR_futurState <= WAIT_SAMPLE;
+ else
+ SR_futurState <= WAIT_END_SAMPLE;
+ end if;
+
+ when others => null;
+ end case;
+ end process;
+
+ O_loadShift1 <= '1' when SR_presentState = Store else '0';
+ O_loadShift2 <= '1' when SR_presentState = OUTPUT_1 else '0';
+ O_loadShift3 <= '1' when SR_presentState = OUTPUT_2 else '0';
+ O_initAddress <= '1' when SR_presentState = Store or SR_presentState = OUTPUT_1 or SR_presentState = OUTPUT_2 or SR_presentState = ADDRESS_RESET else '0';
+ O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP_1 or SR_presentState = PROCESSING_LOOP_2_1 or SR_presentState = PROCESSING_LOOP_2_2 or SR_presentState = PROCESSING_LOOP_3 else '0';
+ O_initSum <= '1' when SR_presentState = Store or SR_presentState = OUTPUT_1 or SR_presentState = OUTPUT_2 else '0';
+ O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP_1 or SR_presentState = PROCESSING_LOOP_2_1 or SR_presentState = PROCESSING_LOOP_2_2 or SR_presentState = PROCESSING_LOOP_3 else '0';
+ O_loadY <= '1' when SR_presentState = OUTPUT_3 else '0';
+ O_FilteredSampleValid <= '1' when SR_presentState = WAIT_END_SAMPLE else '0';
+
+
+
+
+
+end architecture archi_operativeUnit;
diff --git a/src/hdl/filterUnit.vhd b/src/hdl/filterUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ac96ccdf5023741b75ca669803ab6cef946078b4
--- /dev/null
+++ b/src/hdl/filterUnit.vhd
@@ -0,0 +1,125 @@
+-------------------------------------------------------------------------------
+-- Title : firUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2018-04-11
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity filterUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(10 downto 0); -- filtered sample
+ O_filteredSampleValid : out std_logic
+ );
+
+end entity filterUnit;
+
+architecture archi_filterUnit of filterUnit is
+
+ component controlUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSampleValid : in std_logic;
+ I_processingDone : in std_logic;
+ O_loadShift1 : out std_logic;
+ O_loadShift2 : out std_logic;
+ O_loadShift3 : out std_logic;
+ O_initAddress : out std_logic;
+ O_incrAddress : out std_logic;
+ O_initSum : out std_logic;
+ O_loadSum : out std_logic;
+ O_loadY : out std_logic;
+ O_coefSelect : out std_logic_vector(1 downto 0);
+ O_FilteredSampleValid : out std_logic);
+ end component controlUnit;
+
+ component operativeUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSample : in std_logic_vector(10 downto 0);
+ I_loadShift1 : in std_logic;
+ I_loadShift2 : in std_logic;
+ I_loadShift3 : in std_logic;
+ I_initAddress : in std_logic;
+ I_incrAddress : in std_logic;
+ I_initSum : in std_logic;
+ I_loadSum : in std_logic;
+ I_loadY : in std_logic;
+ I_coefSelect : out std_logic_vector(1 downto 0);
+ O_processingDone : out std_logic;
+ O_Y : out std_logic_vector(10 downto 0));
+ end component operativeUnit;
+
+ signal SC_processingDone : std_logic;
+ signal SC_loadShift1 : std_logic;
+ signal SC_loadShift2 : std_logic;
+ signal SC_loadShift3 : std_logic;
+ signal SC_initAddress : std_logic;
+ signal SC_incrAddress : std_logic;
+ signal SC_initSum : std_logic;
+ signal SC_loadSum : std_logic;
+ signal SC_loadY : std_logic;
+ signal SC_coefSelect : std_logic_vector(1 downto 0);
+
+
+begin
+
+ controlUnit_1 : entity work.controlUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSampleValid => I_inputSampleValid,
+ I_processingDone => SC_processingDone,
+ O_loadShift1 => SC_loadShift1,
+ O_loadShift2 => SC_loadShift2,
+ O_loadShift3 => SC_loadShift3,
+ O_initAddress => SC_initAddress,
+ O_incrAddress => SC_incrAddress,
+ O_initSum => SC_initSum,
+ O_loadSum => SC_loadSum,
+ O_loadY => SC_loadY,
+ O_coefSelect => SC_coefSelect,
+ O_FilteredSampleValid => O_FilteredSampleValid);
+
+ operativeUnit_1 : entity work.operativeUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSample => I_inputSample,
+ I_loadShift1 => SC_loadShift1,
+ I_loadShift2 => SC_loadShift2,
+ I_loadShift3 => SC_loadShift3,
+ I_initAddress => SC_initAddress,
+ I_incrAddress => SC_incrAddress,
+ I_initSum => SC_initSum,
+ I_loadSum => SC_loadSum,
+ I_loadY => SC_loadY,
+ I_coefSelect => SC_coefSelect,
+ O_processingDone => SC_processingDone,
+ O_Y => O_filteredSample);
+
+end architecture archi_filterUnit;
diff --git a/src/hdl/mac.vhd b/src/hdl/mac.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a38ab016b58d1bf18142b34c778108614911d756
--- /dev/null
+++ b/src/hdl/mac.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mac is
+ Port ( clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ sum_rst : in std_logic;
+ enable : in std_logic;
+ smpl : in signed(10 downto 0); -- 11-bit input a
+ coef : in signed(10 downto 0); -- 11-bit input b
+ acc_out : inout signed(28 downto 0) -- 29-bit acc output
+ );
+end entity mac;
+
+architecture Behavioral of mac is
+ signal acc : signed(28 downto 0) := (others => '0'); -- 29-bit acc
+begin
+
+ -- Process that handles multiplication and accumulation
+ process(clk, rst)
+ begin
+ if rst = '1' then
+ acc <= (others => '0'); -- Reset acc to 0
+ elsif rising_edge(clk) then
+ if (sum_rst = '1') then
+ acc <= (others => '0');
+ elsif (enable = '1') then
+ acc <= acc_out; -- Add prod to acc
+ end if;
+ end if;
+ end process;
+
+ -- Output the acc
+ acc_out <= acc + smpl * coef;
+
+end Behavioral;
\ No newline at end of file
diff --git a/src/hdl/mux4.vhd b/src/hdl/mux4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed8ff12b23da2934a5d673ad085b9e4620c7e397
--- /dev/null
+++ b/src/hdl/mux4.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mux4to1 is
+ generic (
+ DATA_WIDTH : integer := 11 -- Default width of the input data (can be changed)
+ );
+ Port (
+ sel : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit select input to choose between 4 entries
+ a : in signed(DATA_WIDTH-1 downto 0); -- 1st input (configurable width)
+ b : in signed(DATA_WIDTH-1 downto 0); -- 2nd input (configurable width)
+ c : in signed(DATA_WIDTH-1 downto 0); -- 3rd input (configurable width)
+ d : in signed(DATA_WIDTH-1 downto 0); -- 4th input (configurable width)
+ mux_out : out signed(DATA_WIDTH-1 downto 0) -- Output with configurable width
+ );
+end entity mux4to1;
+
+architecture Behavioral of mux4to1 is
+begin
+ process(sel, a, b, c, d)
+ begin
+ case sel is
+ when "00" => mux_out <= a; -- Select input 'a'
+ when "01" => mux_out <= b; -- Select input 'b'
+ when "10" => mux_out <= c; -- Select input 'c'
+ when "11" => mux_out <= d; -- Select input 'd'
+ when others => mux_out <= (others => '0'); -- Default case
+ end case;
+ end process;
+end Behavioral;
\ No newline at end of file
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ff5665cab44be00c980217aae0d8ac714cabb0cf
--- /dev/null
+++ b/src/hdl/operativeUnit.vhd
@@ -0,0 +1,380 @@
+-------------------------------------------------------------------------------
+-- Title : operativeUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Operative unit of a sequential FIR filter. Including shift
+-- register for samples, registers for coefficients, a MAC and a register to
+-- store the result
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve
+-- the user experience ;)
+-- 2018-04-11 1.0 jnbazin Created
+-- 2018-04-18 1.0 marzel Modification of SR_Y assignment to a round
+-- instead of a trunc
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity operativeUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_loadShift1 : in std_logic; -- filtered sample
+ I_loadShift2 : in std_logic; -- filtered sample
+ I_loadShift3 : in std_logic; -- filtered sample
+ I_initAddress : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress : in std_logic; -- Control signal to increment register read address
+ I_initSum : in std_logic; -- Control signal to initialize the MAC register
+ I_loadSum : in std_logic; -- Control signal to load the MAC register;
+ I_loadY : in std_logic; -- Control signal to load Y register
+ I_coefSelect : in std_logic_vector(1 downto 0);
+ O_processingDone : out std_logic; -- Indicate that processing is done
+ O_Y : out std_logic_vector(10 downto 0) -- filtered sample
+ );
+
+end entity operativeUnit;
+
+architecture arch_operativeUnit of operativeUnit is
+ signal SC_smpl : signed(10 downto 0);
+ signal SC_coef : signed(10 downto 0);
+ signal SC_result : signed(28 downto 0); -- result of the accumulation addition
+ signal SR_Y : signed(10 downto 0); -- filtered sample storage register
+ signal SR_readAddress : integer range 0 to 94; -- register files read address
+
+ signal SR_readAddress2_1 : integer range 0 to 2; -- register files read address
+ signal SR_readAddress2_2 : integer range 0 to 1; -- register files read address
+ signal SR_readAddress3 : integer range 0 to 10; -- register files read address
+
+
+ type registerFile1 is array(0 to 94) of signed(10 downto 0);
+ signal sampleReg1 : registerFile1;
+ type registerFile2 is array(0 to 2) of signed(10 downto 0);
+ signal sampleReg2 : registerFile2;
+ type registerFile3 is array(0 to 10) of signed(10 downto 0);
+ signal sampleReg3 : registerFile3;
+ signal maxSum : integer;
+
+ signal SR_coefRegister1 : registerFile1;
+ signal SR_coefRegister2_1 : registerFile2;
+ type registerFile2_2 is array(0 to 1) of signed(10 downto 0);
+ signal SR_coefRegister2_2 : registerFile2_2;
+ signal SR_coefRegister3 : registerFile3;
+
+ component mac is
+ Port ( clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ sum_rst : in std_logic;
+ enable: in std_logic;
+ smpl : in signed(10 downto 0); -- 11-bit input a
+ coef : in signed(10 downto 0); -- 11-bit input b
+ acc_out : inout signed(28 downto 0) -- 29-bit acc output
+ );
+ end component mac;
+
+ component mux4to1 is
+ generic (
+ DATA_WIDTH : integer := 11 -- Default width of the input data (can be changed)
+ );
+ Port (
+ sel : in STD_LOGIC_VECTOR(1 downto 0); -- 2-bit select input to choose between 4 entries
+ a : in signed(DATA_WIDTH-1 downto 0); -- 1st input (configurable width)
+ b : in signed(DATA_WIDTH-1 downto 0); -- 2nd input (configurable width)
+ c : in signed(DATA_WIDTH-1 downto 0); -- 3rd input (configurable width)
+ d : in signed(DATA_WIDTH-1 downto 0); -- 4th input (configurable width)
+ mux_out : out signed(DATA_WIDTH-1 downto 0) -- Output with configurable width
+ );
+end component mux4to1;
+
+begin
+
+ mac1 : mac
+ port map (
+ clk => I_clock,
+ rst => I_reset,
+ sum_rst => I_initSum,
+ enable => I_loadSum,
+ smpl => SC_smpl,
+ coef => SC_coef,
+ acc_out => SC_result
+ );
+
+-- mux_coef : mux4to1
+-- port map(
+-- sel => I_coefSelect,
+-- a => SR_coefRegister1(SR_readAddress),
+-- b => SR_coefRegister2_1(SR_readAddress),
+-- c => SR_coefRegister2_2(SR_readAddress),
+-- d => SR_coefRegister3(SR_readAddress),
+-- mux_out => SC_coef
+-- );
+
+
+ SR_readAddress2_1 <= SR_readAddress when(I_coefSelect = "01") else 0;
+ SR_readAddress2_2 <= SR_readAddress when(I_coefSelect = "10") else 0;
+ SR_readAddress3 <= SR_readAddress when(I_coefSelect = "11") else 0;
+
+ SC_coef <= SR_coefRegister1(SR_readAddress) when(I_coefSelect = "00")else
+ SR_coefRegister2_1(SR_readAddress2_1) when(I_coefSelect = "01")else
+ SR_coefRegister2_2(SR_readAddress2_2) when(I_coefSelect = "10")else
+ SR_coefRegister3(SR_readAddress3);
+
+-- mux_smpl : mux4to1
+-- port map(
+-- sel => I_coefSelect,
+-- a => sampleReg1(SR_readAddress),
+-- b => sampleReg2(SR_readAddress2_1),
+-- c => sampleReg3(SR_readAddress2_2),
+-- d => sampleReg3(SR_readAddress3),
+-- mux_out => SC_smpl
+-- );
+
+ SC_smpl <= sampleReg1(SR_readAddress) when(I_coefSelect = "00")else
+ sampleReg2(SR_readAddress2_1) when(I_coefSelect = "01")else
+ sampleReg3(SR_readAddress3);
+
+ shift : process (I_clock, I_reset) is
+ begin -- process shift
+ if I_reset = '1' then -- asynchronous reset (active high)
+ sampleReg1 <= (others => (others => '0'));
+ sampleReg2 <= (others => (others => '0'));
+ sampleReg3 <= (others => (others => '0'));
+ elsif rising_edge(I_clock) then
+ if I_loadShift1 = '1' then
+
+ for i in 0 to 93 loop
+
+ sampleReg1(i+1) <= sampleReg1(i);
+
+ end loop;
+
+ sampleReg1(0) <= Signed(I_inputSample);
+
+ elsif I_loadShift2 = '1' then
+
+ for i in 0 to 1 loop
+
+ sampleReg2(i+1) <= sampleReg2(i);
+
+ end loop;
+
+ sampleReg2(0) <= signed(SC_result(20 downto 10));
+
+ elsif I_loadShift3 = '1' then
+
+ for i in 0 to 9 loop
+
+ sampleReg3(i+1) <= sampleReg3(i);
+
+ end loop;
+
+ sampleReg3(0) <= signed(SC_result(19 downto 9));
+
+ end if;
+
+ end if;
+ end process shift;
+
+ incr_address : process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_readAddress <= 0;
+
+ elsif rising_edge(I_clock) then
+ if I_initAddress = '1' then
+ SR_readAddress <= 0;
+ elsif I_incrAddress = '1' then
+ SR_readAddress <= SR_readAddress+1;
+ end if;
+
+ end if;
+ end process incr_address;
+
+ maxSumSel : process (I_coefSelect) is
+ begin
+ case I_coefSelect is
+ when "00" =>
+ maxSum <= 93;
+ when "01" =>
+ maxSum <= 1;
+ when "10" =>
+ maxSum <= 0;
+ when "11" =>
+ maxSum <= 9;
+ when others =>
+ maxSum <= 0;
+ end case;
+ end process maxSumSel;
+
+ O_processingDone <= '1' when SR_readAddress = maxSum else '0' ;
+
+ -- SC_multOperand1 <= SR_shiftRegister(SR_readAddress) ; -- 8 bits
+ -- SC_multOperand2 <= SR_coefRegister(SR_readAddress) ; -- 8 bits
+ -- SC_MultResult <= SC_multOperand1 * SC_multOperand2 ; -- 16 bits
+ -- SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+
+ -- sum_acc : process (I_clock, I_reset) is
+ -- begin
+ -- if I_reset = '1' then -- asynchronous reset (active high)
+ -- SR_sum <= (others => '0');
+ -- elsif rising_edge(I_clock) then
+ -- if I_initSum = '1' then
+ -- SR_sum <= (others => '0');
+ -- elsif I_loadSum = '1' then
+ -- SR_sum <= SC_addResult;
+ -- end if;
+
+ -- end if;
+ -- end process sum_acc;
+
+ store_result : process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_Y <= (others => '0');
+ elsif rising_edge(I_clock) then
+ if I_loadY = '1' then
+ SR_Y <= SC_result(20 downto 10); --TODO: changer la sortie
+ end if;
+
+ end if;
+ end process store_result;
+
+ O_Y <= std_logic_vector(SR_Y);
+
+
+-- Low-pass filter provided with octave (or Matlab ;)) command
+--fir1(15, .001)/sqrt(sum(fir1(15, .001).^2))*2^6
+SR_coefRegister1 <= (to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-2, 11),
+to_signed(-2, 11),
+to_signed(-2, 11),
+to_signed(-3, 11),
+to_signed(-3, 11),
+to_signed(-3, 11),
+to_signed(-4, 11),
+to_signed(-4, 11),
+to_signed(-5, 11),
+to_signed(-5, 11),
+to_signed(-6, 11),
+to_signed(-6, 11),
+to_signed(-7, 11),
+to_signed(-7, 11),
+to_signed(-8, 11),
+to_signed(-8, 11),
+to_signed(-9, 11),
+to_signed(-10, 11),
+to_signed(-10, 11),
+to_signed(-11, 11),
+to_signed(-11, 11),
+to_signed(-12, 11),
+to_signed(-13, 11),
+to_signed(-13, 11),
+to_signed(-14, 11),
+to_signed(-14, 11),
+to_signed(-15, 11),
+to_signed(-15, 11),
+to_signed(-16, 11),
+to_signed(-16, 11),
+to_signed(-17, 11),
+to_signed(-17, 11),
+to_signed(-18, 11),
+to_signed(-18, 11),
+to_signed(-18, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(1004, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-19, 11),
+to_signed(-18, 11),
+to_signed(-18, 11),
+to_signed(-18, 11),
+to_signed(-17, 11),
+to_signed(-17, 11),
+to_signed(-16, 11),
+to_signed(-16, 11),
+to_signed(-15, 11),
+to_signed(-15, 11),
+to_signed(-14, 11),
+to_signed(-14, 11),
+to_signed(-13, 11),
+to_signed(-13, 11),
+to_signed(-12, 11),
+to_signed(-11, 11),
+to_signed(-11, 11),
+to_signed(-10, 11),
+to_signed(-10, 11),
+to_signed(-9, 11),
+to_signed(-8, 11),
+to_signed(-8, 11),
+to_signed(-7, 11),
+to_signed(-7, 11),
+to_signed(-6, 11),
+to_signed(-6, 11),
+to_signed(-5, 11),
+to_signed(-5, 11),
+to_signed(-4, 11),
+to_signed(-4, 11),
+to_signed(-3, 11),
+to_signed(-3, 11),
+to_signed(-3, 11),
+to_signed(-2, 11),
+to_signed(-2, 11),
+to_signed(-2, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11),
+to_signed(-1, 11));
+
+
+SR_coefRegister2_1 <= (to_signed(480, 11),
+to_signed(-777, 11),
+to_signed(480, 11));
+
+SR_coefRegister2_2 <= (to_signed(777, 11),
+to_signed(-449, 11));
+
+SR_coefRegister3 <= (to_signed(-119, 11),
+to_signed(122, 11),
+to_signed(149, 11),
+to_signed(191, 11),
+to_signed(226, 11),
+to_signed(239, 11),
+to_signed(226, 11),
+to_signed(191, 11),
+to_signed(149, 11),
+to_signed(122, 11),
+to_signed(-119, 11));
+
+
+
+end architecture arch_operativeUnit;
diff --git a/src/hdl/tb_firUnit.vhd b/src/hdl/tb_firUnit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..614b3dc83c7a8262707f2ef24df123b73ad26804
--- /dev/null
+++ b/src/hdl/tb_firUnit.vhd
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------------
+-- Title : FirUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-26
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-- 2018-04-18 1.1 marzel Modified to add more test inputs
+-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_filterUnit is
+end entity tb_filterUnit;
+
+architecture archi_tb_filterUnit of tb_filterUnit is
+ component filterUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSample : in std_logic_vector(10 downto 0);
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(10 downto 0);
+ O_filteredSampleValid : out std_logic);
+ end component filterUnit;
+
+ signal SC_clock : std_logic := '0';
+ signal SC_reset : std_logic;
+ signal SC_inputSample : std_logic_vector(10 downto 0);
+ signal SC_inputSampleValid : std_logic:='0';
+ signal SC_filteredSample : std_logic_vector(10 downto 0);
+ signal SC_filteredSampleValid : std_logic;
+
+begin
+
+ SC_clock <= not SC_clock after 5 ns;
+ SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
+
+ -- Sample period = 20 clk period
+ SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
+
+ -- Null signal followed by a Dirac and then an arbitrary sequence
+ SC_inputSample <= "00000000000",
+ "01111111111" after 401 ns,
+ "00000000000" after 5601 ns;
+
+
+-- the filter output on 8 bits is a sequence of signed numbers (with the assumption
+-- of rounding the output, so the accuracy can be slightly different depending
+-- on your final stage):
+ -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
+ -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
+
+
+ filterUnit_1 : entity work.filterUnit
+ port map (
+ I_clock => SC_clock,
+ I_reset => SC_reset,
+ I_inputSample => SC_inputSample,
+ I_inputSampleValid => SC_inputSampleValid,
+ O_filteredSample => SC_filteredSample,
+ O_filteredSampleValid => SC_filteredSampleValid);
+
+end architecture archi_tb_filterUnit;