diff --git a/docs/img/FSM.png b/docs/img/FSM.png
index 7f6db881fff5cdfb9351c0348dfec49ff082516d..513280e4c67d82a7ba29d052a485c5c4e5ef8562 100644
Binary files a/docs/img/FSM.png and b/docs/img/FSM.png differ
diff --git a/proj/AudioProc.cache/sim/ssm.db b/proj/AudioProc.cache/sim/ssm.db
new file mode 100644
index 0000000000000000000000000000000000000000..264726a569a9135e9b4d30e6211cf6e4fa468a0c
--- /dev/null
+++ b/proj/AudioProc.cache/sim/ssm.db
@@ -0,0 +1,11 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Feb 26 10:41:15 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,
diff --git a/proj/AudioProc.cache/wt/project.wpc b/proj/AudioProc.cache/wt/project.wpc
new file mode 100644
index 0000000000000000000000000000000000000000..9b342093142bd1b298b4af63bdebdead3a3ef56e
--- /dev/null
+++ b/proj/AudioProc.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/proj/AudioProc.cache/wt/synthesis.wdf b/proj/AudioProc.cache/wt/synthesis.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..40a65cdba943a815d0ec754b58a684410a768f41
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:617564696f50726f63:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f77:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64617461666c6f775f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c75745f63617363616465:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:343030:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:35:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:6f6e655f686f74:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:5b7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:6f6666:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d676c6f62616c5f726574696d696e67:64656661756c743a3a6175746f:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323573:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323736322e3333324d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313036302e3930364d42:00:00
+eof:4244571573
diff --git a/proj/AudioProc.cache/wt/synthesis_details.wdf b/proj/AudioProc.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/proj/AudioProc.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/proj/AudioProc.cache/wt/webtalk_pa.xml b/proj/AudioProc.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..60f2ae5f48208aed3fb8eaf75f505bb13b177f52
--- /dev/null
+++ b/proj/AudioProc.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Feb 26 11:36:43 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="66bbb89ed9f743bdb855d08ed6591932" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Flow_PerfOptimized_High" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/proj/AudioProc.cache/wt/xsim.wdf b/proj/AudioProc.cache/wt/xsim.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..51d5206f7011f2f0764fb661278617e58456141a
--- /dev/null
+++ b/proj/AudioProc.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:2427094519
diff --git a/proj/AudioProc.hw/AudioProc.lpr b/proj/AudioProc.hw/AudioProc.lpr
new file mode 100644
index 0000000000000000000000000000000000000000..aa18adc095c6432a86aa8a7a331502559213b706
--- /dev/null
+++ b/proj/AudioProc.hw/AudioProc.lpr
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0">
+ <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/proj/AudioProc.hw/hw_1/hw.xml b/proj/AudioProc.hw/hw_1/hw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2cc8b5c9dbf896cee7f203c4cfa2a0fccaedffa0
--- /dev/null
+++ b/proj/AudioProc.hw/hw_1/hw.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<hwsession version="1" minor="2">
+ <device name="xc7a200t_0" gui_info=""/>
+ <ObjectList object_type="hw_device" gui_info="">
+ <Object name="xc7a200t_0" gui_info="">
+ <Properties Property="FULL_PROBES.FILE" value=""/>
+ <Properties Property="PROBES.FILE" value=""/>
+ <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/audioProc.bit"/>
+ <Properties Property="SLR.COUNT" value="1"/>
+ </Object>
+ </ObjectList>
+ <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/proj/AudioProc.ip_user_files/README.txt b/proj/AudioProc.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100755
index 0000000000000000000000000000000000000000..c6b126bb4b8be62560df51240c9200f63d5efb97
--- /dev/null
+++ b/proj/AudioProc.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,103 @@
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+
+ -- Clock in ports
+ clk_in1 => clk_in1,
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/proj/AudioProc.runs/.jobs/vrs_config_1.xml b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..72462a3117826a75abfd89828c65aa4e4275cc2b
--- /dev/null
+++ b/proj/AudioProc.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/proj/AudioProc.runs/impl_1/.Vivado_Implementation.queue.rst b/proj/AudioProc.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.init_design.begin.rst b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..93da8b6abea827cdf4ea03380ac678227e5ac624
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l23debac" Host="" Pid="34927">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.init_design.end.rst b/proj/AudioProc.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.begin.rst b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..93da8b6abea827cdf4ea03380ac678227e5ac624
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l23debac" Host="" Pid="34927">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.opt_design.end.rst b/proj/AudioProc.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.place_design.begin.rst b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..93da8b6abea827cdf4ea03380ac678227e5ac624
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l23debac" Host="" Pid="34927">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.place_design.end.rst b/proj/AudioProc.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.route_design.begin.rst b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..93da8b6abea827cdf4ea03380ac678227e5ac624
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l23debac" Host="" Pid="34927">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.route_design.end.rst b/proj/AudioProc.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.vivado.begin.rst b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e793b70aa831cc0f47b4056048257ee2644755b3
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="l23debac" Host="fl-tp-br-608" Pid="34853" HostCore="12" HostMemory="16081428">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.vivado.end.rst b/proj/AudioProc.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..93da8b6abea827cdf4ea03380ac678227e5ac624
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="l23debac" Host="" Pid="34927">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/impl_1/.write_bitstream.end.rst b/proj/AudioProc.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/impl_1/ISEWrap.js b/proj/AudioProc.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/impl_1/ISEWrap.sh b/proj/AudioProc.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bin b/proj/AudioProc.runs/impl_1/audioProc.bin
new file mode 100644
index 0000000000000000000000000000000000000000..1230d2727f343837844862957e4317dcb2357204
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc.bin differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.bit b/proj/AudioProc.runs/impl_1/audioProc.bit
new file mode 100644
index 0000000000000000000000000000000000000000..290e0a88f893b745b9422a43c884d7376dc99235
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc.bit differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc.tcl b/proj/AudioProc.runs/impl_1/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6327bd7e203a48f5e3d4bfa0146ca00484c64ca5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc.tcl
@@ -0,0 +1,284 @@
+namespace eval ::optrace {
+ variable script "/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param chipscope.maxJobs 3
+ set_param runs.launchOptions { -jobs 6 }
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7a200tsbg484-1
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.cache/wt [current_project]
+ set_property parent.project_path /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.xpr [current_project]
+ set_property ip_repo_paths /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/repo [current_project]
+ update_ip_catalog
+ set_property ip_output_repo /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/audioProc.dcp
+ read_ip -quiet /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+OPTRACE "read constraints: implementation" START { }
+ read_xdc /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ link_design -top audioProc -part xc7a200tsbg484-1
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx" }
+ set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_io -file audioProc_io_placed.rpt" "report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb" "report_control_sets -verbose -file audioProc_control_sets_placed.rpt" }
+ set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx" "report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx" "report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx" "report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb" "report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt" "report_clock_utilization -file audioProc_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx" }
+ set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force audioProc_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+ write_checkpoint -force audioProc_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ catch { write_mem_info -force -no_partial_mmi audioProc.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force audioProc.bit -bin_file
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force audioProc}
+ catch {file copy -force audioProc.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/proj/AudioProc.runs/impl_1/audioProc.vdi b/proj/AudioProc.runs/impl_1/audioProc.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..abd1d72ba414e039030be2e74b4a9500a89dc91a
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc.vdi
@@ -0,0 +1,807 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 11:38:26 2025
+# Process ID: 34927
+# Current directory: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-608
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :1499.709 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :16357 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:19 ; elapsed = 00:01:03 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 6642 ; free virtual = 15003
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+update_ip_catalog: Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:09 . Memory (MB): peak = 1686.523 ; gain = 5.938 ; free physical = 6628 ; free virtual = 14988
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2097.469 ; gain = 0.000 ; free physical = 6212 ; free virtual = 14573
+INFO: [Netlist 29-17] Analyzing 99 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2870.988 ; gain = 624.930 ; free physical = 5626 ; free virtual = 13996
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2870.988 ; gain = 0.000 ; free physical = 5626 ; free virtual = 13996
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 2870.988 ; gain = 1176.527 ; free physical = 5626 ; free virtual = 13996
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2935.020 ; gain = 64.031 ; free physical = 5601 ; free virtual = 13972
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2935.020 ; gain = 0.000 ; free physical = 5601 ; free virtual = 13972
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 1 Initialization | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 2 Timer Update And Timing Data Collection | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 153e10ba0
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Retarget | Checksum: 153e10ba0
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 153e10ba0
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Constant propagation | Checksum: 153e10ba0
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 1af9906b9
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Sweep | Checksum: 1af9906b9
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells
+Phase 6 BUFG optimization | Checksum: 16d99f34e
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+BUFG optimization | Checksum: 16d99f34e
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 16d99f34e
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Shift Register Optimization | Checksum: 16d99f34e
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 1d945ff79
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Post Processing Netlist | Checksum: 1d945ff79
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 9 Finalization | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 2 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 2 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Ending Netlist Obfuscation Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+INFO: [Common 17-83] Releasing license: Implementation
+35 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+report_drc: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 88.043 ; free physical = 5289 ; free virtual = 13661
+generate_parallel_reports: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 88.043 ; free physical = 5289 ; free virtual = 13661
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5289 ; free virtual = 13662
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5289 ; free virtual = 13662
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5284 ; free virtual = 13657
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13655
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13655
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13655
+Write Physdb Complete: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5281 ; free virtual = 13655
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13656
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1bab39224
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13656
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13656
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 173dcc833
+
+Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5255 ; free virtual = 13632
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e2170656
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5249 ; free virtual = 13628
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e2170656
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5249 ; free virtual = 13628
+Phase 1 Placer Initialization | Checksum: 1e2170656
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5249 ; free virtual = 13628
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1d7e80512
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5259 ; free virtual = 13638
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 202ebee6b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5273 ; free virtual = 13652
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 202ebee6b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5273 ; free virtual = 13652
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 18ccd01ad
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5271 ; free virtual = 13651
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 18 LUTNM shape to break, 85 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 12, two critical 6, total 18, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 54 nets or LUTs. Breaked 18 LUTs, combined 36 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
+INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13648
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 18 | 36 | 54 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 18 | 36 | 54 | 0 | 9 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 15eef931f
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13649
+Phase 2.4 Global Placement Core | Checksum: 129c76092
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13648
+Phase 2 Global Placement | Checksum: 129c76092
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13648
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 16420d5ef
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5266 ; free virtual = 13648
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 21934284e
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5266 ; free virtual = 13648
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1eade4b9d
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5266 ; free virtual = 13648
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 16ab41fd8
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5265 ; free virtual = 13647
+
+Phase 3.5 Fast Optimization
+Phase 3.5 Fast Optimization | Checksum: 1b1008a71
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5262 ; free virtual = 13644
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1d31c1c21
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5256 ; free virtual = 13638
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1c522d8e8
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5256 ; free virtual = 13638
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 1f3ec45b6
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5256 ; free virtual = 13638
+
+Phase 3.9 Fast Optimization
+Phase 3.9 Fast Optimization | Checksum: 209647115
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5250 ; free virtual = 13632
+Phase 3 Detail Placement | Checksum: 209647115
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5250 ; free virtual = 13632
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 2f05449ba
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.026 | TNS=-2.986 |
+Phase 1 Physical Synthesis Initialization | Checksum: 22717f216
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5248 ; free virtual = 13630
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 26ff54906
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5248 ; free virtual = 13630
+Phase 4.1.1.1 BUFG Insertion | Checksum: 2f05449ba
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5248 ; free virtual = 13630
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.229. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13629
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Phase 4.1 Post Commit Optimization | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Phase 4.3 Placer Reporting | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14e62cb1f
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Ending Placer Task | Checksum: 10e1e419b
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+78 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5226 ; free virtual = 13609
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5215 ; free virtual = 13598
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5215 ; free virtual = 13597
+Wrote PlaceDB: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5214 ; free virtual = 13598
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5213 ; free virtual = 13597
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5213 ; free virtual = 13597
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5213 ; free virtual = 13597
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5211 ; free virtual = 13596
+Write Physdb Complete: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5211 ; free virtual = 13596
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 381a9127 ConstDB: 0 ShapeSum: 3de8c510 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 6bbe2e5b | NumContArr: 178c64c5 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2089c885a
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3501.484 ; gain = 184.758 ; free physical = 4970 ; free virtual = 13356
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2089c885a
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3501.484 ; gain = 184.758 ; free physical = 4970 ; free virtual = 13356
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2089c885a
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3501.484 ; gain = 184.758 ; free physical = 4970 ; free virtual = 13356
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 26c584cde
+
+Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 3569.242 ; gain = 252.516 ; free physical = 4900 ; free virtual = 13286
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.084 | TNS=-0.157 | WHS=-0.121 | THS=-17.691|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.000263185 %
+ Global Horizontal Routing Utilization = 0.000727032 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 976
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 966
+ Number of Partially Routed Nets = 10
+ Number of Node Overlaps = 7
+
+Phase 2 Router Initialization | Checksum: 336dd4049
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 336dd4049
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 248795aa0
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 4 Initial Routing | Checksum: 248795aa0
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 356
+ Number of Nodes with overlaps = 184
+ Number of Nodes with overlaps = 88
+ Number of Nodes with overlaps = 43
+ Number of Nodes with overlaps = 31
+ Number of Nodes with overlaps = 16
+ Number of Nodes with overlaps = 7
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.323 | TNS=-1.133 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 1a850c44d
+
+Time (s): cpu = 00:00:45 ; elapsed = 00:00:36 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4895 ; free virtual = 13282
+
+Phase 5.2 Global Iteration 1
+ Number of Nodes with overlaps = 137
+ Number of Nodes with overlaps = 71
+ Number of Nodes with overlaps = 47
+ Number of Nodes with overlaps = 34
+ Number of Nodes with overlaps = 25
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.031 | TNS=-0.051 | WHS=N/A | THS=N/A |
+
+Phase 5.2 Global Iteration 1 | Checksum: 2adbc2af9
+
+Time (s): cpu = 00:00:48 ; elapsed = 00:00:37 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 5.3 Global Iteration 2
+ Number of Nodes with overlaps = 136
+ Number of Nodes with overlaps = 79
+ Number of Nodes with overlaps = 43
+ Number of Nodes with overlaps = 37
+ Number of Nodes with overlaps = 25
+ Number of Nodes with overlaps = 16
+ Number of Nodes with overlaps = 25
+ Number of Nodes with overlaps = 19
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 4
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.001 | TNS=-0.001 | WHS=N/A | THS=N/A |
+
+Phase 5.3 Global Iteration 2 | Checksum: 22f6ec8ac
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 5 Rip-up And Reroute | Checksum: 22f6ec8ac
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.078 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 6.1 Delay CleanUp | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 6 Delay and Skew Optimization | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.078 | TNS=0.000 | WHS=0.131 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 7 Post Hold Fix | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0763438 %
+ Global Horizontal Routing Utilization = 0.0985459 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 24cf8f2b5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 24cf8f2b5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.078 | TNS=0.000 | WHS=0.131 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 24cf8f2b5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Total Elapsed time in route_design: 39.73 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 116e977f9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 116e977f9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+99 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:41 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+119 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4873 ; free virtual = 13262
+Wrote PlaceDB: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Write Physdb Complete: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4871 ; free virtual = 13262
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+Command: write_bitstream -force audioProc.bit -bin_file
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./audioProc.bit...
+Writing bitstream ./audioProc.bin...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+130 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3915.500 ; gain = 250.824 ; free physical = 4561 ; free virtual = 12964
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 11:42:01 2025...
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..20fae480ab47870ee84edfce46d1fd6343f39e97
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:45 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..ec85d625b596a5ab50c6ffe3ad71af392d67487b
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_bus_skew_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..25e9672ab175d6d782debee67ce48e976d6edda5
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_clock_utilization_routed.rpt
@@ -0,0 +1,252 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:45 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Device Cell Placement Summary for Global Clock g1
+8. Device Cell Placement Summary for Global Clock g2
+9. Device Cell Placement Summary for Global Clock g3
+10. Clock Region Cell Placement per Global Clock: Region X1Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 4 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 120 | 0 | 0 | 0 |
+| BUFIO | 0 | 40 | 0 | 0 | 0 |
+| BUFMR | 0 | 20 | 0 | 0 | 0 |
+| BUFR | 0 | 40 | 0 | 0 | 0 |
+| MMCM | 1 | 10 | 0 | 0 | 0 |
+| PLL | 0 | 10 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 459 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/clkout1_buf/O | clk_1/inst/clk_out1 |
+| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 1 | 120 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/clkout4_buf/O | clk_1/inst/clk_out4 |
+| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/clkf_buf/O | clk_1/inst/clkfbout_buf_clk_wiz_0 |
+| g3 | src3 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 0 | 1 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/clkout3_buf/O | clk_1/inst/clk_out3 |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+--------------------+--------------------------+-----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clk_out1_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT0 | clk_1/inst/clk_out1_clk_wiz_0 |
+| src1 | g1 | MMCME2_ADV/CLKOUT3 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 20.000 | clk_out4_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT3 | clk_1/inst/clk_out4_clk_wiz_0 |
+| src2 | g2 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKFBOUT | clk_1/inst/clkfbout_clk_wiz_0 |
+| src3 | g3 | MMCME2_ADV/CLKOUT2 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 83.333 | clk_out3_clk_wiz_0 | clk_1/inst/mmcm_adv_inst/CLKOUT2 | clk_1/inst/clk_out3_clk_wiz_0 |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------------+-----------------------------------+-------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
+| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y2 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 579 | 4000 | 202 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
+| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y4 | 0 | 0 |
+| Y3 | 0 | 0 |
+| Y2 | 0 | 0 |
+| Y1 | 0 | 0 |
+| Y0 | 0 | 0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+| g0 | BUFG/O | n/a | clk_out1_clk_wiz_0 | 10.000 | {0.000 5.000} | 459 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 459 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+7. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| g1 | BUFG/O | n/a | clk_out4_clk_wiz_0 | 20.000 | {0.000 10.000} | 120 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 120 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+8. Device Cell Placement Summary for Global Clock g2
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+| g2 | BUFG/O | n/a | clkfbout_clk_wiz_0 | 10.000 | {0.000 5.000} | 0 | 0 | 1 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
++-----------+-----------------+-------------------+--------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+9. Device Cell Placement Summary for Global Clock g3
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+| g3 | BUFG/O | n/a | clk_out3_clk_wiz_0 | 83.333 | {0.000 41.667} | 0 | 1 | 0 | 0 | clk_1/inst/clk_out3 |
++-----------+-----------------+-------------------+--------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+10. Clock Region Cell Placement per Global Clock: Region X1Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+| g0 | n/a | BUFG/O | None | 459 | 0 | 459 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out1 |
+| g1 | n/a | BUFG/O | None | 120 | 0 | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out4 |
+| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_1/inst/clkfbout_buf_clk_wiz_0 |
+| g3 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_1/inst/clk_out3 |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y3 [get_cells clk_1/inst/clkf_buf]
+set_property LOC BUFGCTRL_X0Y2 [get_cells clk_1/inst/clkout4_buf]
+set_property LOC BUFGCTRL_X0Y0 [get_cells clk_1/inst/clkout3_buf]
+set_property LOC BUFGCTRL_X0Y1 [get_cells clk_1/inst/clkout1_buf]
+
+# Location of IO Primitives which is load of clock spine
+set_property LOC IOB_X1Y118 [get_cells ac_mclk_OBUF_inst]
+
+# Location of clock ports
+set_property LOC IOB_X1Y124 [get_ports CLK100MHZ]
+
+# Clock net "clk_1/inst/clk_out4" driven by instance "clk_1/inst/clkout4_buf" located at site "BUFGCTRL_X0Y2"
+#startgroup
+create_pblock {CLKAG_clk_1/inst/clk_out4}
+add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out4"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out4}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
+
+# Clock net "clk_1/inst/clk_out1" driven by instance "clk_1/inst/clkout1_buf" located at site "BUFGCTRL_X0Y1"
+#startgroup
+create_pblock {CLKAG_clk_1/inst/clk_out1}
+add_cells_to_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_1/inst/clk_out1"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_1/inst/clk_out1}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
diff --git a/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d20bb6d0b619d4cebc4a795e02ba82b724970bf9
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_control_sets_placed.rpt
@@ -0,0 +1,111 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:00 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+| Design : audioProc
+| Device : xc7a200t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 33 |
+| Minimum number of control sets | 33 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 83 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 33 |
+| >= 0 to < 4 | 1 |
+| >= 4 to < 6 | 11 |
+| >= 6 to < 8 | 5 |
+| >= 8 to < 10 | 3 |
+| >= 10 to < 12 | 1 |
+| >= 12 to < 14 | 1 |
+| >= 14 to < 16 | 2 |
+| >= 16 | 9 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 34 | 20 |
+| No | No | Yes | 10 | 5 |
+| No | Yes | No | 44 | 14 |
+| Yes | No | No | 63 | 24 |
+| Yes | No | Yes | 310 | 98 |
+| Yes | Yes | No | 128 | 35 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++-------------------------------------------------+--------------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++-------------------------------------------------+--------------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| clk_1/inst/clk_out1 | dbuttons/IV[2]_i_1_n_0 | | 1 | 1 | 1.00 |
+| clk_1/inst/clk_out4 | rstn_IBUF | initialize_audio/data_i[5]_i_1_n_0 | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/E[0] | audio_inout/SR[0] | 1 | 4 | 4.00 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/FSM_gray_state[3]_i_1_n_0 | | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | initialize_audio/initWord[23]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0 | audio_inout/SR[0] | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out1 | lrclkcnt[3]_i_2_n_0 | lrclkcnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/operativeUnit_1/SR_readAddress[3]_i_1_n_0 | audio_inout/SR[0] | 2 | 4 | 2.00 |
+| leftFir/firUnit_1/controlUnit_1/SR_futurState | | | 2 | 5 | 2.50 |
+| clk_1/inst/clk_out1 | audio_inout/BCLK_Fall_int | audio_inout/SR[0] | 2 | 5 | 2.50 |
+| rightFir/firUnit_1/controlUnit_1/SR_futurState | | | 3 | 5 | 1.67 |
+| clk_1/inst/clk_out1 | | audio_inout/Cnt_Bclk[4]_i_1_n_0 | 2 | 5 | 2.50 |
+| clk_1/inst/clk_out4 | rstn_IBUF | | 2 | 6 | 3.00 |
+| clk_1/inst/clk_out1 | | | 5 | 6 | 1.20 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/state_reg[3][0] | audio_inout/SR[0] | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | | initialize_audio/twi_controller/busFreeCnt0 | 3 | 7 | 2.33 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/sclCnt[6]_i_2_n_0 | initialize_audio/twi_controller/sclCnt0 | 2 | 7 | 3.50 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[2] | audio_inout/SR[0] | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out4 | initialize_audio/twi_controller/dataByte[7]_i_1_n_0 | | 3 | 8 | 2.67 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[2] | audio_inout/SR[0] | 2 | 8 | 4.00 |
+| clk_1/inst/clk_out1 | | audio_inout/SR[0] | 5 | 10 | 2.00 |
+| clk_1/inst/clk_out1 | dbuttons/cnt2 | dbuttons/cnt2[12]_i_1_n_0 | 4 | 13 | 3.25 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/operativeUnit_1/SR_sum[0]_i_1_n_0 | audio_inout/SR[0] | 4 | 15 | 3.75 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/operativeUnit_1/SR_sum[0]_i_1_n_0 | audio_inout/SR[0] | 4 | 15 | 3.75 |
+| clk_1/inst/clk_out4 | | | 10 | 18 | 1.80 |
+| clk_1/inst/clk_out4 | initialize_audio/initWord[30]_i_1_n_0 | | 7 | 19 | 2.71 |
+| clk_1/inst/clk_out1 | audio_inout/D_L_O_int | audio_inout/SR[0] | 6 | 24 | 4.00 |
+| clk_1/inst/clk_out1 | audio_inout/D_R_O_int[23]_i_1_n_0 | audio_inout/SR[0] | 6 | 24 | 4.00 |
+| clk_1/inst/clk_out1 | audio_inout/Data_Out_int[31]_i_1_n_0 | | 9 | 25 | 2.78 |
+| clk_1/inst/clk_out4 | | initialize_audio/delaycnt0 | 9 | 32 | 3.56 |
+| clk_1/inst/clk_out1 | audio_inout/p_4_in | audio_inout/Data_In_int[31]_i_1_n_0 | 6 | 32 | 5.33 |
+| clk_1/inst/clk_out1 | leftFir/firUnit_1/controlUnit_1/Q[0] | audio_inout/SR[0] | 42 | 128 | 3.05 |
+| clk_1/inst/clk_out1 | rightFir/firUnit_1/controlUnit_1/Q[0] | audio_inout/SR[0] | 39 | 128 | 3.28 |
++-------------------------------------------------+--------------------------------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..060102c099034e5d5a9fd2809fc71f940f85f71c
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:40:45 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..f0c1cb2d00d7347420959479be2b38f9c51da16f
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..cb5bb3226dc0fb7cffeddb74a85bce825dc47e0a
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d9447e1030478425976d47d04be4e4e4b419f2ea
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt
@@ -0,0 +1,60 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:43 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 3
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+| PDRC-153 | Warning | Gated clock check | 2 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+PDRC-153#1 Warning
+Gated clock check
+Net leftFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Related violations: <none>
+
+PDRC-153#2 Warning
+Gated clock check
+Net rightFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..2275bd01f956ae02992f6e053e3d4776663310a2
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..1d66cf490d2a48c31822a169cdcaee619500fba0
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_io_placed.rpt
@@ -0,0 +1,526 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:00 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_io -file audioProc_io_placed.rpt
+| Design : audioProc
+| Device : xc7a200t
+| Speed File : -1
+| Package : sbg484
+| Package Version : FINAL 2012-06-12
+| Package Pin Delay Version : VERS. 2.0 2012-06-12
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 25 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA21 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B22 | BTNC | High Range | IO_L20N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| C2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| C22 | BTNL | High Range | IO_L20P_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D14 | BTNR | High Range | IO_L6P_T0_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D22 | BTND | High Range | IO_L22N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E22 | sw | High Range | IO_L22P_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
+| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F15 | BTNU | High Range | IO_0_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
+| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | rstn | High Range | IO_L12N_T1_MRCC_35 | INPUT | LVCMOS15 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| G22 | sw3 | High Range | IO_L24N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| H17 | sw4 | High Range | IO_L6P_T0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | sw5 | High Range | IO_0_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | sw6 | High Range | IO_L19P_T3_A22_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M17 | sw7 | High Range | IO_25_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.50 | | | | | | | | |
+| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| P19 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | CLK100MHZ | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | ac_adc_sdata | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| T5 | ac_bclk | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T20 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U5 | ac_lrclk | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U6 | ac_mclk | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U16 | led3 | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U21 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V5 | sda | High Range | IO_L16N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V15 | led4 | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W5 | scl | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W6 | ac_dac_sdata | High Range | IO_L15P_T2_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W15 | led6 | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W16 | led5 | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y13 | led7 | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
++------------+--------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..d77b02cd75c030eef1e2a80571c7bffdeeab233c
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7c5bc26422665a030b44562f717e5f885447fb03
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt
@@ -0,0 +1,147 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:44 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 22
++-----------+----------+--------------------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+----------+--------------------------------+------------+
+| TIMING-18 | Warning | Missing input or output delay | 11 |
+| TIMING-20 | Warning | Non-clocked latch | 10 |
+| LATCH-1 | Advisory | Existing latches in the design | 1 |
++-----------+----------+--------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-18#1 Warning
+Missing input or output delay
+An input delay is missing on BTNC relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay
+An input delay is missing on ac_adc_sdata relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay
+An input delay is missing on rstn relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay
+An input delay is missing on sw3 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay
+An input delay is missing on sw4 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay
+An input delay is missing on sw5 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay
+An input delay is missing on sw6 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#8 Warning
+Missing input or output delay
+An input delay is missing on sw7 relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#9 Warning
+Missing input or output delay
+An output delay is missing on ac_bclk relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#10 Warning
+Missing input or output delay
+An output delay is missing on ac_dac_sdata relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-18#11 Warning
+Missing input or output delay
+An output delay is missing on ac_lrclk relative to the rising and/or falling clock edge(s) of CLK100MHZ.
+Related violations: <none>
+
+TIMING-20#1 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#2 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#3 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#4 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#5 Warning
+Non-clocked latch
+The latch leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4] cannot be properly analyzed as its control pin leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#6 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[0]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#7 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[1]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#8 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[2]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#9 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[3]/G is not reached by a timing clock
+Related violations: <none>
+
+TIMING-20#10 Warning
+Non-clocked latch
+The latch rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4] cannot be properly analyzed as its control pin rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_futurState_reg[4]/G is not reached by a timing clock
+Related violations: <none>
+
+LATCH-1#1 Advisory
+Existing latches in the design
+There are 10 latches found in the design. Inferred latches are often the result of HDL coding mistakes, such as incomplete if or case statements.
+Related violations: <none>
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..a2c844341b51d312747b8962bdab0f7f008ada60
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_opt.dcp b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..0ef63736c693c7328c3276912d8e3feddf7040c2
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_opt.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_placed.dcp b/proj/AudioProc.runs/impl_1/audioProc_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..bc572420254144c242c1104e9e24b7b261b2025c
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diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5866eee072fa728a5749c08bec6dd42774339551
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpt
@@ -0,0 +1,160 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:45 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 0.249 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 0.098 |
+| Device Static (W) | 0.151 |
+| Effective TJA (C/W) | 3.3 |
+| Max Ambient (C) | 84.2 |
+| Junction Temperature (C) | 25.8 |
+| Confidence Level | Low |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks | 0.003 | 7 | --- | --- |
+| Slice Logic | 0.001 | 1363 | --- | --- |
+| LUT as Logic | 0.001 | 571 | 133800 | 0.43 |
+| CARRY4 | <0.001 | 46 | 33450 | 0.14 |
+| Register | <0.001 | 589 | 267600 | 0.22 |
+| F7/F8 Muxes | <0.001 | 50 | 133800 | 0.04 |
+| Others | 0.000 | 23 | --- | --- |
+| Signals | 0.001 | 978 | --- | --- |
+| MMCM | 0.085 | 1 | 10 | 10.00 |
+| I/O | 0.006 | 20 | 285 | 7.02 |
+| Static Power | 0.151 | | | |
+| Total | 0.249 | | | |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.037 | 0.007 | 0.031 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.078 | 0.047 | 0.031 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.006 | 0.001 | 0.005 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | High | User specified more than 95% of clocks | |
+| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Low | | |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 3.3 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++--------------------+-------------------------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++--------------------+-------------------------------+-----------------+
+| CLK100MHZ | CLK100MHZ | 10.0 |
+| clk_out1_clk_wiz_0 | clk_1/inst/clk_out1_clk_wiz_0 | 10.0 |
+| clk_out3_clk_wiz_0 | clk_1/inst/clk_out3_clk_wiz_0 | 83.3 |
+| clk_out4_clk_wiz_0 | clk_1/inst/clk_out4_clk_wiz_0 | 20.0 |
+| clkfbout_clk_wiz_0 | clk_1/inst/clkfbout_clk_wiz_0 | 10.0 |
++--------------------+-------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-----------------------+-----------+
+| Name | Power (W) |
++-----------------------+-----------+
+| audioProc | 0.098 |
+| clk_1 | 0.086 |
+| inst | 0.086 |
+| leftFir | 0.002 |
+| firUnit_1 | 0.002 |
+| operativeUnit_1 | 0.001 |
+| rightFir | 0.002 |
+| firUnit_1 | 0.002 |
+| operativeUnit_1 | 0.002 |
++-----------------------+-----------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..a325ffa8600bb1e6675121b5d60a9dacc78e86b8
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_power_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..380142a2f580d9c265913473af50d70cec9f0c1e
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_power_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.pb b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..344332c500ef28d4cd1b2618e44931a009ff3cff
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_route_status.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..03beb6803b42b4de0f7c559dbbfc08091b259684
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 1526 :
+ # of nets not needing routing.......... : 537 :
+ # of internally routed nets........ : 537 :
+ # of routable nets..................... : 989 :
+ # of fully routed nets............. : 989 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_routed.dcp b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..72f75e59ee24737a7243a31a025155e0e3180250
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_routed.dcp differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ef1b05b2729231b0a86e78c36bb884b87e4973a6
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c22a6b8a8e7abee280aef22c1c228b62ab4d6858
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpt
@@ -0,0 +1,3130 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:44 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+| Design : audioProc
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+ Inter-SLR Compensation : Conservative
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule Severity Description Violations
+--------- -------- ------------------------------ ----------
+TIMING-18 Warning Missing input or output delay 11
+TIMING-20 Warning Non-clocked latch 10
+LATCH-1 Advisory Existing latches in the design 1
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (50)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (10)
+5. checking no_input_delay (10)
+6. checking no_output_delay (5)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (50)
+-------------------------
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[1]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[2]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[3]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: leftFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[0]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[1]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[2]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[3]/Q (HIGH)
+
+ There are 5 register/latch pins with no clock driven by root clock pin: rightFir/firUnit_1/controlUnit_1/FSM_onehot_SR_presentState_reg[4]/Q (HIGH)
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (10)
+-------------------------------------------------
+ There are 10 pins that are not constrained for maximum delay. (HIGH)
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (10)
+-------------------------------
+ There are 10 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (5)
+-------------------------------
+ There are 5 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 0.084 0.000 0 1164 0.132 0.000 0 1164 3.000 0.000 0 589
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+CLK100MHZ {0.000 5.000} 10.000 100.000
+ clk_out1_clk_wiz_0 {0.000 5.000} 10.000 100.000
+ clk_out3_clk_wiz_0 {0.000 41.667} 83.333 12.000
+ clk_out4_clk_wiz_0 {0.000 10.000} 20.000 50.000
+ clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+CLK100MHZ 3.000 0.000 0 1
+ clk_out1_clk_wiz_0 0.084 0.000 0 939 0.132 0.000 0 939 4.500 0.000 0 461
+ clk_out3_clk_wiz_0 81.178 0.000 0 2
+ clk_out4_clk_wiz_0 14.404 0.000 0 225 0.151 0.000 0 225 9.500 0.000 0 122
+ clkfbout_clk_wiz_0 7.845 0.000 0 3
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: CLK100MHZ
+ To Clock: CLK100MHZ
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: CLK100MHZ
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { CLK100MHZ }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKIN1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0
+ To Clock: clk_out1_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.132ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.084ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.793ns (logic 4.359ns (44.511%) route 5.434ns (55.489%))
+ Logic Levels: 12 (CARRY4=3 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=3 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.118ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.823 -0.996 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y115 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y115 FDCE (Prop_fdce_C_Q) 0.419 -0.577 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.245 0.668 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X158Y120 LUT6 (Prop_lut6_I2_O) 0.297 0.965 f rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57/O
+ net (fo=1, routed) 0.000 0.965 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57_n_0
+ SLICE_X158Y120 MUXF7 (Prop_muxf7_I1_O) 0.214 1.179 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41/O
+ net (fo=1, routed) 0.000 1.179 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41_n_0
+ SLICE_X158Y120 MUXF8 (Prop_muxf8_I1_O) 0.088 1.267 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_30/O
+ net (fo=8, routed) 0.512 1.779 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[4]
+ SLICE_X161Y120 LUT5 (Prop_lut5_I0_O) 0.319 2.098 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48/O
+ net (fo=3, routed) 0.985 3.083 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48_n_0
+ SLICE_X157Y118 LUT6 (Prop_lut6_I0_O) 0.124 3.207 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38/O
+ net (fo=1, routed) 0.000 3.207 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38_n_0
+ SLICE_X157Y118 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 3.847 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/O[3]
+ net (fo=4, routed) 0.813 4.660 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_4
+ SLICE_X156Y119 LUT4 (Prop_lut4_I1_O) 0.306 4.966 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 4.966 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X156Y119 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.546 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.531 6.077 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X155Y119 LUT2 (Prop_lut2_I0_O) 0.302 6.379 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.379 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X155Y119 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 7.019 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[3]
+ net (fo=2, routed) 0.820 7.839 rightFir/firUnit_1/operativeUnit_1/L[11]
+ SLICE_X153Y119 LUT6 (Prop_lut6_I0_O) 0.306 8.145 r rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3/O
+ net (fo=3, routed) 0.528 8.673 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3_n_0
+ SLICE_X152Y119 LUT3 (Prop_lut3_I0_O) 0.124 8.797 r rightFir/firUnit_1/operativeUnit_1/SR_Y[6]_i_1/O
+ net (fo=1, routed) 0.000 8.797 rightFir/firUnit_1/operativeUnit_1/p_0_in[6]
+ SLICE_X152Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X152Y119 FDCE (Setup_fdce_C_D) 0.079 8.882 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]
+ -------------------------------------------------------------------
+ required time 8.882
+ arrival time -8.797
+ -------------------------------------------------------------------
+ slack 0.084
+
+Slack (MET) : 0.094ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.822ns (logic 4.388ns (44.675%) route 5.434ns (55.325%))
+ Logic Levels: 12 (CARRY4=3 LUT2=1 LUT4=2 LUT5=1 LUT6=3 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.118ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.823 -0.996 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y115 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y115 FDCE (Prop_fdce_C_Q) 0.419 -0.577 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.245 0.668 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X158Y120 LUT6 (Prop_lut6_I2_O) 0.297 0.965 f rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57/O
+ net (fo=1, routed) 0.000 0.965 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57_n_0
+ SLICE_X158Y120 MUXF7 (Prop_muxf7_I1_O) 0.214 1.179 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41/O
+ net (fo=1, routed) 0.000 1.179 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41_n_0
+ SLICE_X158Y120 MUXF8 (Prop_muxf8_I1_O) 0.088 1.267 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_30/O
+ net (fo=8, routed) 0.512 1.779 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[4]
+ SLICE_X161Y120 LUT5 (Prop_lut5_I0_O) 0.319 2.098 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48/O
+ net (fo=3, routed) 0.985 3.083 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48_n_0
+ SLICE_X157Y118 LUT6 (Prop_lut6_I0_O) 0.124 3.207 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38/O
+ net (fo=1, routed) 0.000 3.207 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38_n_0
+ SLICE_X157Y118 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 3.847 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/O[3]
+ net (fo=4, routed) 0.813 4.660 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_4
+ SLICE_X156Y119 LUT4 (Prop_lut4_I1_O) 0.306 4.966 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 4.966 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X156Y119 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.546 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.531 6.077 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X155Y119 LUT2 (Prop_lut2_I0_O) 0.302 6.379 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.379 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X155Y119 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 7.019 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[3]
+ net (fo=2, routed) 0.820 7.839 rightFir/firUnit_1/operativeUnit_1/L[11]
+ SLICE_X153Y119 LUT6 (Prop_lut6_I0_O) 0.306 8.145 r rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3/O
+ net (fo=3, routed) 0.528 8.673 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3_n_0
+ SLICE_X152Y119 LUT4 (Prop_lut4_I1_O) 0.153 8.826 r rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_1/O
+ net (fo=1, routed) 0.000 8.826 rightFir/firUnit_1/operativeUnit_1/p_0_in[7]
+ SLICE_X152Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X152Y119 FDCE (Setup_fdce_C_D) 0.118 8.921 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]
+ -------------------------------------------------------------------
+ required time 8.921
+ arrival time -8.826
+ -------------------------------------------------------------------
+ slack 0.094
+
+Slack (MET) : 0.168ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.785ns (logic 4.502ns (46.011%) route 5.283ns (53.989%))
+ Logic Levels: 14 (CARRY4=4 LUT2=1 LUT3=2 LUT4=2 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.041ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -1.073ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.746 -1.073 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y117 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X145Y117 FDCE (Prop_fdce_C_Q) 0.419 -0.654 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.314 0.660 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.299 0.959 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50/O
+ net (fo=1, routed) 0.000 0.959 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I0_O) 0.241 1.200 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38/O
+ net (fo=1, routed) 0.000 1.200 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I0_O) 0.098 1.298 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_29/O
+ net (fo=8, routed) 0.755 2.053 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[5]
+ SLICE_X144Y117 LUT5 (Prop_lut5_I0_O) 0.319 2.372 f leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41/O
+ net (fo=2, routed) 0.417 2.790 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41_n_0
+ SLICE_X145Y119 LUT3 (Prop_lut3_I1_O) 0.124 2.914 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32/O
+ net (fo=2, routed) 0.560 3.474 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32_n_0
+ SLICE_X147Y117 LUT4 (Prop_lut4_I0_O) 0.124 3.598 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36/O
+ net (fo=1, routed) 0.000 3.598 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36_n_0
+ SLICE_X147Y117 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 3.999 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/CO[3]
+ net (fo=1, routed) 0.000 3.999 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_0
+ SLICE_X147Y118 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 4.221 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14/O[0]
+ net (fo=3, routed) 0.731 4.952 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14_n_7
+ SLICE_X147Y120 LUT4 (Prop_lut4_I3_O) 0.299 5.251 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 5.251 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X147Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.831 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.334 6.165 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X148Y120 LUT2 (Prop_lut2_I0_O) 0.302 6.467 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.467 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X148Y120 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 7.110 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[3]
+ net (fo=2, routed) 0.640 7.750 leftFir/firUnit_1/operativeUnit_1/L[11]
+ SLICE_X151Y120 LUT6 (Prop_lut6_I0_O) 0.307 8.057 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3/O
+ net (fo=3, routed) 0.530 8.588 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3_n_0
+ SLICE_X150Y120 LUT3 (Prop_lut3_I0_O) 0.124 8.712 r leftFir/firUnit_1/operativeUnit_1/SR_Y[6]_i_1/O
+ net (fo=1, routed) 0.000 8.712 leftFir/firUnit_1/operativeUnit_1/p_0_in[6]
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X150Y120 FDCE (Setup_fdce_C_D) 0.077 8.880 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[6]
+ -------------------------------------------------------------------
+ required time 8.880
+ arrival time -8.712
+ -------------------------------------------------------------------
+ slack 0.168
+
+Slack (MET) : 0.185ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.809ns (logic 4.526ns (46.143%) route 5.283ns (53.857%))
+ Logic Levels: 14 (CARRY4=4 LUT2=1 LUT3=1 LUT4=3 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.041ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -1.073ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.746 -1.073 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y117 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X145Y117 FDCE (Prop_fdce_C_Q) 0.419 -0.654 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.314 0.660 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.299 0.959 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50/O
+ net (fo=1, routed) 0.000 0.959 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I0_O) 0.241 1.200 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38/O
+ net (fo=1, routed) 0.000 1.200 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I0_O) 0.098 1.298 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_29/O
+ net (fo=8, routed) 0.755 2.053 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[5]
+ SLICE_X144Y117 LUT5 (Prop_lut5_I0_O) 0.319 2.372 f leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41/O
+ net (fo=2, routed) 0.417 2.790 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41_n_0
+ SLICE_X145Y119 LUT3 (Prop_lut3_I1_O) 0.124 2.914 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32/O
+ net (fo=2, routed) 0.560 3.474 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32_n_0
+ SLICE_X147Y117 LUT4 (Prop_lut4_I0_O) 0.124 3.598 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36/O
+ net (fo=1, routed) 0.000 3.598 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36_n_0
+ SLICE_X147Y117 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 3.999 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/CO[3]
+ net (fo=1, routed) 0.000 3.999 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_0
+ SLICE_X147Y118 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 4.221 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14/O[0]
+ net (fo=3, routed) 0.731 4.952 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14_n_7
+ SLICE_X147Y120 LUT4 (Prop_lut4_I3_O) 0.299 5.251 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 5.251 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X147Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.831 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.334 6.165 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X148Y120 LUT2 (Prop_lut2_I0_O) 0.302 6.467 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.467 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X148Y120 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 7.110 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[3]
+ net (fo=2, routed) 0.640 7.750 leftFir/firUnit_1/operativeUnit_1/L[11]
+ SLICE_X151Y120 LUT6 (Prop_lut6_I0_O) 0.307 8.057 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3/O
+ net (fo=3, routed) 0.530 8.588 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3_n_0
+ SLICE_X150Y120 LUT4 (Prop_lut4_I1_O) 0.148 8.736 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_1/O
+ net (fo=1, routed) 0.000 8.736 leftFir/firUnit_1/operativeUnit_1/p_0_in[7]
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X150Y120 FDCE (Setup_fdce_C_D) 0.118 8.921 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]
+ -------------------------------------------------------------------
+ required time 8.921
+ arrival time -8.736
+ -------------------------------------------------------------------
+ slack 0.185
+
+Slack (MET) : 0.290ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.539ns (logic 4.359ns (45.697%) route 5.180ns (54.303%))
+ Logic Levels: 12 (CARRY4=3 LUT2=2 LUT4=1 LUT5=1 LUT6=3 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.118ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.823 -0.996 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y115 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y115 FDCE (Prop_fdce_C_Q) 0.419 -0.577 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.245 0.668 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X158Y120 LUT6 (Prop_lut6_I2_O) 0.297 0.965 f rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57/O
+ net (fo=1, routed) 0.000 0.965 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57_n_0
+ SLICE_X158Y120 MUXF7 (Prop_muxf7_I1_O) 0.214 1.179 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41/O
+ net (fo=1, routed) 0.000 1.179 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41_n_0
+ SLICE_X158Y120 MUXF8 (Prop_muxf8_I1_O) 0.088 1.267 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_30/O
+ net (fo=8, routed) 0.512 1.779 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[4]
+ SLICE_X161Y120 LUT5 (Prop_lut5_I0_O) 0.319 2.098 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48/O
+ net (fo=3, routed) 0.985 3.083 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48_n_0
+ SLICE_X157Y118 LUT6 (Prop_lut6_I0_O) 0.124 3.207 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38/O
+ net (fo=1, routed) 0.000 3.207 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38_n_0
+ SLICE_X157Y118 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 3.847 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/O[3]
+ net (fo=4, routed) 0.813 4.660 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_4
+ SLICE_X156Y119 LUT4 (Prop_lut4_I1_O) 0.306 4.966 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 4.966 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X156Y119 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.546 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.531 6.077 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X155Y119 LUT2 (Prop_lut2_I0_O) 0.302 6.379 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.379 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X155Y119 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 7.019 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[3]
+ net (fo=2, routed) 0.820 7.839 rightFir/firUnit_1/operativeUnit_1/L[11]
+ SLICE_X153Y119 LUT6 (Prop_lut6_I0_O) 0.306 8.145 r rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3/O
+ net (fo=3, routed) 0.274 8.419 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3_n_0
+ SLICE_X153Y119 LUT2 (Prop_lut2_I0_O) 0.124 8.543 r rightFir/firUnit_1/operativeUnit_1/SR_Y[5]_i_1/O
+ net (fo=1, routed) 0.000 8.543 rightFir/firUnit_1/operativeUnit_1/p_0_in[5]
+ SLICE_X153Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X153Y119 FDCE (Setup_fdce_C_D) 0.031 8.834 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]
+ -------------------------------------------------------------------
+ required time 8.834
+ arrival time -8.543
+ -------------------------------------------------------------------
+ slack 0.290
+
+Slack (MET) : 0.340ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.614ns (logic 4.502ns (46.827%) route 5.112ns (53.173%))
+ Logic Levels: 14 (CARRY4=4 LUT2=2 LUT3=1 LUT4=2 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.041ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -1.073ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.746 -1.073 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y117 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X145Y117 FDCE (Prop_fdce_C_Q) 0.419 -0.654 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.314 0.660 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.299 0.959 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50/O
+ net (fo=1, routed) 0.000 0.959 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I0_O) 0.241 1.200 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38/O
+ net (fo=1, routed) 0.000 1.200 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I0_O) 0.098 1.298 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_29/O
+ net (fo=8, routed) 0.755 2.053 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[5]
+ SLICE_X144Y117 LUT5 (Prop_lut5_I0_O) 0.319 2.372 f leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41/O
+ net (fo=2, routed) 0.417 2.790 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41_n_0
+ SLICE_X145Y119 LUT3 (Prop_lut3_I1_O) 0.124 2.914 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32/O
+ net (fo=2, routed) 0.560 3.474 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32_n_0
+ SLICE_X147Y117 LUT4 (Prop_lut4_I0_O) 0.124 3.598 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36/O
+ net (fo=1, routed) 0.000 3.598 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36_n_0
+ SLICE_X147Y117 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 3.999 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/CO[3]
+ net (fo=1, routed) 0.000 3.999 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_0
+ SLICE_X147Y118 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 4.221 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14/O[0]
+ net (fo=3, routed) 0.731 4.952 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14_n_7
+ SLICE_X147Y120 LUT4 (Prop_lut4_I3_O) 0.299 5.251 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 5.251 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X147Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.831 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.334 6.165 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X148Y120 LUT2 (Prop_lut2_I0_O) 0.302 6.467 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.467 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X148Y120 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.643 7.110 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[3]
+ net (fo=2, routed) 0.640 7.750 leftFir/firUnit_1/operativeUnit_1/L[11]
+ SLICE_X151Y120 LUT6 (Prop_lut6_I0_O) 0.307 8.057 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3/O
+ net (fo=3, routed) 0.360 8.417 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_3_n_0
+ SLICE_X150Y120 LUT2 (Prop_lut2_I0_O) 0.124 8.541 r leftFir/firUnit_1/operativeUnit_1/SR_Y[5]_i_1/O
+ net (fo=1, routed) 0.000 8.541 leftFir/firUnit_1/operativeUnit_1/p_0_in[5]
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X150Y120 FDCE (Setup_fdce_C_D) 0.079 8.882 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[5]
+ -------------------------------------------------------------------
+ required time 8.882
+ arrival time -8.541
+ -------------------------------------------------------------------
+ slack 0.340
+
+Slack (MET) : 0.686ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.264ns (logic 4.335ns (46.792%) route 4.929ns (53.208%))
+ Logic Levels: 13 (CARRY4=4 LUT2=1 LUT3=1 LUT4=2 LUT5=2 LUT6=1 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.041ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -1.073ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.746 -1.073 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y117 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X145Y117 FDCE (Prop_fdce_C_Q) 0.419 -0.654 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.314 0.660 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.299 0.959 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50/O
+ net (fo=1, routed) 0.000 0.959 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I0_O) 0.241 1.200 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38/O
+ net (fo=1, routed) 0.000 1.200 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I0_O) 0.098 1.298 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_29/O
+ net (fo=8, routed) 0.755 2.053 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[5]
+ SLICE_X144Y117 LUT5 (Prop_lut5_I0_O) 0.319 2.372 f leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41/O
+ net (fo=2, routed) 0.417 2.790 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41_n_0
+ SLICE_X145Y119 LUT3 (Prop_lut3_I1_O) 0.124 2.914 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32/O
+ net (fo=2, routed) 0.560 3.474 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32_n_0
+ SLICE_X147Y117 LUT4 (Prop_lut4_I0_O) 0.124 3.598 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36/O
+ net (fo=1, routed) 0.000 3.598 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36_n_0
+ SLICE_X147Y117 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 3.999 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/CO[3]
+ net (fo=1, routed) 0.000 3.999 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_0
+ SLICE_X147Y118 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 4.221 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14/O[0]
+ net (fo=3, routed) 0.731 4.952 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14_n_7
+ SLICE_X147Y120 LUT4 (Prop_lut4_I3_O) 0.299 5.251 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 5.251 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X147Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.831 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.334 6.165 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X148Y120 LUT2 (Prop_lut2_I0_O) 0.302 6.467 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.467 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X148Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.578 7.045 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[2]
+ net (fo=3, routed) 0.817 7.863 leftFir/firUnit_1/operativeUnit_1/L[10]
+ SLICE_X151Y120 LUT5 (Prop_lut5_I4_O) 0.329 8.192 r leftFir/firUnit_1/operativeUnit_1/SR_Y[3]_i_1/O
+ net (fo=1, routed) 0.000 8.192 leftFir/firUnit_1/operativeUnit_1/p_0_in[3]
+ SLICE_X151Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X151Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X151Y120 FDCE (Setup_fdce_C_D) 0.075 8.878 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]
+ -------------------------------------------------------------------
+ required time 8.878
+ arrival time -8.192
+ -------------------------------------------------------------------
+ slack 0.686
+
+Slack (MET) : 0.756ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.161ns (logic 4.197ns (45.815%) route 4.964ns (54.185%))
+ Logic Levels: 11 (CARRY4=3 LUT2=1 LUT4=1 LUT5=2 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.118ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.823 -0.996 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y115 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y115 FDCE (Prop_fdce_C_Q) 0.419 -0.577 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.245 0.668 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X158Y120 LUT6 (Prop_lut6_I2_O) 0.297 0.965 f rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57/O
+ net (fo=1, routed) 0.000 0.965 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57_n_0
+ SLICE_X158Y120 MUXF7 (Prop_muxf7_I1_O) 0.214 1.179 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41/O
+ net (fo=1, routed) 0.000 1.179 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41_n_0
+ SLICE_X158Y120 MUXF8 (Prop_muxf8_I1_O) 0.088 1.267 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_30/O
+ net (fo=8, routed) 0.512 1.779 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[4]
+ SLICE_X161Y120 LUT5 (Prop_lut5_I0_O) 0.319 2.098 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48/O
+ net (fo=3, routed) 0.985 3.083 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48_n_0
+ SLICE_X157Y118 LUT6 (Prop_lut6_I0_O) 0.124 3.207 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38/O
+ net (fo=1, routed) 0.000 3.207 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38_n_0
+ SLICE_X157Y118 CARRY4 (Prop_carry4_S[1]_O[3])
+ 0.640 3.847 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/O[3]
+ net (fo=4, routed) 0.813 4.660 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_4
+ SLICE_X156Y119 LUT4 (Prop_lut4_I1_O) 0.306 4.966 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 4.966 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X156Y119 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.546 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.531 6.077 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X155Y119 LUT2 (Prop_lut2_I0_O) 0.302 6.379 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.379 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X155Y119 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 6.959 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[2]
+ net (fo=3, routed) 0.878 7.837 rightFir/firUnit_1/operativeUnit_1/L[10]
+ SLICE_X152Y119 LUT5 (Prop_lut5_I4_O) 0.328 8.165 r rightFir/firUnit_1/operativeUnit_1/SR_Y[3]_i_1/O
+ net (fo=1, routed) 0.000 8.165 rightFir/firUnit_1/operativeUnit_1/p_0_in[3]
+ SLICE_X152Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X152Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X152Y119 FDCE (Setup_fdce_C_D) 0.118 8.921 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[3]
+ -------------------------------------------------------------------
+ required time 8.921
+ arrival time -8.165
+ -------------------------------------------------------------------
+ slack 0.756
+
+Slack (MET) : 0.926ns (required time - arrival time)
+ Source: leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 9.030ns (logic 4.307ns (47.694%) route 4.723ns (52.306%))
+ Logic Levels: 13 (CARRY4=4 LUT2=1 LUT3=1 LUT4=2 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.041ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -1.073ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.746 -1.073 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X145Y117 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X145Y117 FDCE (Prop_fdce_C_Q) 0.419 -0.654 r leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.314 0.660 leftFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X146Y123 LUT6 (Prop_lut6_I2_O) 0.299 0.959 r leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50/O
+ net (fo=1, routed) 0.000 0.959 leftFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_50_n_0
+ SLICE_X146Y123 MUXF7 (Prop_muxf7_I0_O) 0.241 1.200 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38/O
+ net (fo=1, routed) 0.000 1.200 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_38_n_0
+ SLICE_X146Y123 MUXF8 (Prop_muxf8_I0_O) 0.098 1.298 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_29/O
+ net (fo=8, routed) 0.755 2.053 leftFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[5]
+ SLICE_X144Y117 LUT5 (Prop_lut5_I0_O) 0.319 2.372 f leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41/O
+ net (fo=2, routed) 0.417 2.790 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_41_n_0
+ SLICE_X145Y119 LUT3 (Prop_lut3_I1_O) 0.124 2.914 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32/O
+ net (fo=2, routed) 0.560 3.474 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_32_n_0
+ SLICE_X147Y117 LUT4 (Prop_lut4_I0_O) 0.124 3.598 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36/O
+ net (fo=1, routed) 0.000 3.598 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_36_n_0
+ SLICE_X147Y117 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 3.999 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/CO[3]
+ net (fo=1, routed) 0.000 3.999 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_0
+ SLICE_X147Y118 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 4.221 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14/O[0]
+ net (fo=3, routed) 0.731 4.952 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_14_n_7
+ SLICE_X147Y120 LUT4 (Prop_lut4_I3_O) 0.299 5.251 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21/O
+ net (fo=1, routed) 0.000 5.251 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_21_n_0
+ SLICE_X147Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 5.831 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[2]
+ net (fo=4, routed) 0.334 6.165 leftFir/firUnit_1/operativeUnit_1/SC_MultResult[9]
+ SLICE_X148Y120 LUT2 (Prop_lut2_I0_O) 0.302 6.467 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7/O
+ net (fo=1, routed) 0.000 6.467 leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_7_n_0
+ SLICE_X148Y120 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.578 7.045 r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[2]
+ net (fo=3, routed) 0.611 7.657 leftFir/firUnit_1/operativeUnit_1/L[10]
+ SLICE_X150Y120 LUT6 (Prop_lut6_I4_O) 0.301 7.958 r leftFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_1/O
+ net (fo=1, routed) 0.000 7.958 leftFir/firUnit_1/operativeUnit_1/p_0_in[4]
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 leftFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X150Y120 FDCE r leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X150Y120 FDCE (Setup_fdce_C_D) 0.081 8.884 leftFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]
+ -------------------------------------------------------------------
+ required time 8.884
+ arrival time -7.958
+ -------------------------------------------------------------------
+ slack 0.926
+
+Slack (MET) : 1.037ns (required time - arrival time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (clk_out1_clk_wiz_0 rise@10.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 8.792ns (logic 4.303ns (48.940%) route 4.489ns (51.060%))
+ Logic Levels: 13 (CARRY4=5 LUT2=1 LUT3=1 LUT5=1 LUT6=3 MUXF7=1 MUXF8=1)
+ Clock Path Skew: -0.118ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.667ns = ( 8.333 - 10.000 )
+ Source Clock Delay (SCD): -0.996ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.084ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.151ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.823 -0.996 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X156Y115 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y115 FDCE (Prop_fdce_C_Q) 0.419 -0.577 r rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg[1]/Q
+ net (fo=77, routed) 1.245 0.668 rightFir/firUnit_1/operativeUnit_1/SR_readAddress_reg__0[1]
+ SLICE_X158Y120 LUT6 (Prop_lut6_I2_O) 0.297 0.965 f rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57/O
+ net (fo=1, routed) 0.000 0.965 rightFir/firUnit_1/operativeUnit_1/SR_Y[7]_i_57_n_0
+ SLICE_X158Y120 MUXF7 (Prop_muxf7_I1_O) 0.214 1.179 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41/O
+ net (fo=1, routed) 0.000 1.179 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_41_n_0
+ SLICE_X158Y120 MUXF8 (Prop_muxf8_I1_O) 0.088 1.267 f rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[7]_i_30/O
+ net (fo=8, routed) 0.512 1.779 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister[0]_0[4]
+ SLICE_X161Y120 LUT5 (Prop_lut5_I0_O) 0.319 2.098 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48/O
+ net (fo=3, routed) 0.985 3.083 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_48_n_0
+ SLICE_X157Y118 LUT6 (Prop_lut6_I0_O) 0.124 3.207 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38/O
+ net (fo=1, routed) 0.000 3.207 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_38_n_0
+ SLICE_X157Y118 CARRY4 (Prop_carry4_S[1]_O[2])
+ 0.580 3.787 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27/O[2]
+ net (fo=2, routed) 0.511 4.298 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_27_n_5
+ SLICE_X156Y118 LUT3 (Prop_lut3_I2_O) 0.302 4.600 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_28/O
+ net (fo=1, routed) 0.000 4.600 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_28_n_0
+ SLICE_X156Y118 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 5.001 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_10/CO[3]
+ net (fo=1, routed) 0.000 5.001 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_10_n_0
+ SLICE_X156Y119 CARRY4 (Prop_carry4_CI_O[0])
+ 0.222 5.223 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_4/O[0]
+ net (fo=4, routed) 0.546 5.768 rightFir/firUnit_1/operativeUnit_1/SC_MultResult[7]
+ SLICE_X155Y118 LUT2 (Prop_lut2_I0_O) 0.299 6.067 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_11/O
+ net (fo=1, routed) 0.000 6.067 rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_11_n_0
+ SLICE_X155Y118 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 6.468 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_3/CO[3]
+ net (fo=1, routed) 0.000 6.468 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_3_n_0
+ SLICE_X155Y119 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 6.802 r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]_i_2/O[1]
+ net (fo=4, routed) 0.691 7.494 rightFir/firUnit_1/operativeUnit_1/L[9]
+ SLICE_X153Y119 LUT6 (Prop_lut6_I0_O) 0.303 7.797 r rightFir/firUnit_1/operativeUnit_1/SR_Y[4]_i_1/O
+ net (fo=1, routed) 0.000 7.797 rightFir/firUnit_1/operativeUnit_1/p_0_in[4]
+ SLICE_X153Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 10.000 10.000 r
+ R4 0.000 10.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 10.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 12.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.674 4.893 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.723 6.616 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 6.707 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 1.625 8.333 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X153Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]/C
+ clock pessimism 0.554 8.886
+ clock uncertainty -0.084 8.803
+ SLICE_X153Y119 FDCE (Setup_fdce_C_D) 0.031 8.834 rightFir/firUnit_1/operativeUnit_1/SR_Y_reg[4]
+ -------------------------------------------------------------------
+ required time 8.834
+ arrival time -7.797
+ -------------------------------------------------------------------
+ slack 1.037
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.132ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[3]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[10]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.266ns (logic 0.186ns (69.897%) route 0.080ns (30.103%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.909ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.635 -0.665 audio_inout/clk_out1
+ SLICE_X159Y126 FDRE r audio_inout/D_L_O_int_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.524 r audio_inout/D_L_O_int_reg[3]/Q
+ net (fo=1, routed) 0.080 -0.444 audio_inout/in_audioL[3]
+ SLICE_X158Y126 LUT6 (Prop_lut6_I1_O) 0.045 -0.399 r audio_inout/Data_Out_int[10]_i_1/O
+ net (fo=1, routed) 0.000 -0.399 audio_inout/Data_Out_int[10]_i_1_n_0
+ SLICE_X158Y126 FDRE r audio_inout/Data_Out_int_reg[10]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.905 -0.909 audio_inout/clk_out1
+ SLICE_X158Y126 FDRE r audio_inout/Data_Out_int_reg[10]/C
+ clock pessimism 0.257 -0.652
+ SLICE_X158Y126 FDRE (Hold_fdre_C_D) 0.121 -0.531 audio_inout/Data_Out_int_reg[10]
+ -------------------------------------------------------------------
+ required time 0.531
+ arrival time -0.399
+ -------------------------------------------------------------------
+ slack 0.132
+
+Slack (MET) : 0.140ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[7]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[14]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.273ns (logic 0.186ns (68.106%) route 0.087ns (31.894%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.910ns
+ Source Clock Delay (SCD): -0.666ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.634 -0.666 audio_inout/clk_out1
+ SLICE_X159Y125 FDRE r audio_inout/D_L_O_int_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.525 r audio_inout/D_L_O_int_reg[7]/Q
+ net (fo=1, routed) 0.087 -0.438 audio_inout/in_audioL[7]
+ SLICE_X158Y125 LUT6 (Prop_lut6_I1_O) 0.045 -0.393 r audio_inout/Data_Out_int[14]_i_1/O
+ net (fo=1, routed) 0.000 -0.393 audio_inout/Data_Out_int[14]_i_1_n_0
+ SLICE_X158Y125 FDRE r audio_inout/Data_Out_int_reg[14]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.904 -0.910 audio_inout/clk_out1
+ SLICE_X158Y125 FDRE r audio_inout/Data_Out_int_reg[14]/C
+ clock pessimism 0.257 -0.653
+ SLICE_X158Y125 FDRE (Hold_fdre_C_D) 0.120 -0.533 audio_inout/Data_Out_int_reg[14]
+ -------------------------------------------------------------------
+ required time 0.533
+ arrival time -0.393
+ -------------------------------------------------------------------
+ slack 0.140
+
+Slack (MET) : 0.140ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[11]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[18]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.245ns (logic 0.186ns (75.768%) route 0.059ns (24.232%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.909ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.635 -0.665 audio_inout/clk_out1
+ SLICE_X157Y126 FDRE r audio_inout/D_L_O_int_reg[11]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.524 r audio_inout/D_L_O_int_reg[11]/Q
+ net (fo=1, routed) 0.059 -0.464 audio_inout/in_audioL[11]
+ SLICE_X156Y126 LUT6 (Prop_lut6_I1_O) 0.045 -0.419 r audio_inout/Data_Out_int[18]_i_1/O
+ net (fo=1, routed) 0.000 -0.419 audio_inout/Data_Out_int[18]_i_1_n_0
+ SLICE_X156Y126 FDRE r audio_inout/Data_Out_int_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.905 -0.909 audio_inout/clk_out1
+ SLICE_X156Y126 FDRE r audio_inout/Data_Out_int_reg[18]/C
+ clock pessimism 0.257 -0.652
+ SLICE_X156Y126 FDRE (Hold_fdre_C_D) 0.092 -0.560 audio_inout/Data_Out_int_reg[18]
+ -------------------------------------------------------------------
+ required time 0.560
+ arrival time -0.419
+ -------------------------------------------------------------------
+ slack 0.140
+
+Slack (MET) : 0.140ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[8]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[15]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.244ns (logic 0.186ns (76.078%) route 0.058ns (23.922%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.909ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.635 -0.665 audio_inout/clk_out1
+ SLICE_X157Y126 FDRE r audio_inout/D_L_O_int_reg[8]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.524 r audio_inout/D_L_O_int_reg[8]/Q
+ net (fo=1, routed) 0.058 -0.465 audio_inout/in_audioL[8]
+ SLICE_X156Y126 LUT6 (Prop_lut6_I1_O) 0.045 -0.420 r audio_inout/Data_Out_int[15]_i_1/O
+ net (fo=1, routed) 0.000 -0.420 audio_inout/Data_Out_int[15]_i_1_n_0
+ SLICE_X156Y126 FDRE r audio_inout/Data_Out_int_reg[15]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.905 -0.909 audio_inout/clk_out1
+ SLICE_X156Y126 FDRE r audio_inout/Data_Out_int_reg[15]/C
+ clock pessimism 0.257 -0.652
+ SLICE_X156Y126 FDRE (Hold_fdre_C_D) 0.091 -0.561 audio_inout/Data_Out_int_reg[15]
+ -------------------------------------------------------------------
+ required time 0.561
+ arrival time -0.420
+ -------------------------------------------------------------------
+ slack 0.140
+
+Slack (MET) : 0.159ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.252ns (logic 0.141ns (55.869%) route 0.111ns (44.131%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.643 -0.657 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y114 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y114 FDCE (Prop_fdce_C_Q) 0.141 -0.516 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7][2]/Q
+ net (fo=2, routed) 0.111 -0.404 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[7]__0[2]
+ SLICE_X157Y114 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.915 -0.899 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X157Y114 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]/C
+ clock pessimism 0.257 -0.642
+ SLICE_X157Y114 FDCE (Hold_fdce_C_D) 0.078 -0.564 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][2]
+ -------------------------------------------------------------------
+ required time 0.564
+ arrival time -0.404
+ -------------------------------------------------------------------
+ slack 0.159
+
+Slack (MET) : 0.163ns (arrival time - required time)
+ Source: audio_inout/D_L_O_int_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/Data_Out_int_reg[7]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.296ns (logic 0.186ns (62.801%) route 0.110ns (37.199%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.012ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.910ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.635 -0.665 audio_inout/clk_out1
+ SLICE_X159Y126 FDRE r audio_inout/D_L_O_int_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.524 r audio_inout/D_L_O_int_reg[0]/Q
+ net (fo=1, routed) 0.110 -0.414 audio_inout/in_audioL[0]
+ SLICE_X158Y125 LUT6 (Prop_lut6_I4_O) 0.045 -0.369 r audio_inout/Data_Out_int[7]_i_1/O
+ net (fo=1, routed) 0.000 -0.369 audio_inout/Data_Out_int[7]_i_1_n_0
+ SLICE_X158Y125 FDRE r audio_inout/Data_Out_int_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.904 -0.910 audio_inout/clk_out1
+ SLICE_X158Y125 FDRE r audio_inout/Data_Out_int_reg[7]/C
+ clock pessimism 0.257 -0.653
+ SLICE_X158Y125 FDRE (Hold_fdre_C_D) 0.121 -0.532 audio_inout/Data_Out_int_reg[7]
+ -------------------------------------------------------------------
+ required time 0.532
+ arrival time -0.369
+ -------------------------------------------------------------------
+ slack 0.163
+
+Slack (MET) : 0.166ns (arrival time - required time)
+ Source: audio_inout/Data_In_int_reg[22]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: audio_inout/D_R_O_int_reg[14]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.271ns (logic 0.141ns (52.003%) route 0.130ns (47.997%))
+ Logic Levels: 0
+ Clock Path Skew: 0.035ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.910ns
+ Source Clock Delay (SCD): -0.665ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.635 -0.665 audio_inout/clk_out1
+ SLICE_X160Y125 FDRE r audio_inout/Data_In_int_reg[22]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.524 r audio_inout/Data_In_int_reg[22]/Q
+ net (fo=3, routed) 0.130 -0.394 audio_inout/p_0_in__0[14]
+ SLICE_X157Y125 FDRE r audio_inout/D_R_O_int_reg[14]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.904 -0.910 audio_inout/clk_out1
+ SLICE_X157Y125 FDRE r audio_inout/D_R_O_int_reg[14]/C
+ clock pessimism 0.280 -0.630
+ SLICE_X157Y125 FDRE (Hold_fdre_C_D) 0.070 -0.560 audio_inout/D_R_O_int_reg[14]
+ -------------------------------------------------------------------
+ required time 0.560
+ arrival time -0.394
+ -------------------------------------------------------------------
+ slack 0.166
+
+Slack (MET) : 0.168ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.232ns (logic 0.164ns (70.680%) route 0.068ns (29.320%))
+ Logic Levels: 0
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.904ns
+ Source Clock Delay (SCD): -0.661ns
+ Clock Pessimism Removal (CPR): -0.243ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.639 -0.661 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X158Y119 FDCE (Prop_fdce_C_Q) 0.164 -0.497 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8][4]/Q
+ net (fo=2, routed) 0.068 -0.429 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[8]__0[4]
+ SLICE_X158Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.910 -0.904 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X158Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][4]/C
+ clock pessimism 0.243 -0.661
+ SLICE_X158Y119 FDCE (Hold_fdce_C_D) 0.064 -0.597 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][4]
+ -------------------------------------------------------------------
+ required time 0.597
+ arrival time -0.429
+ -------------------------------------------------------------------
+ slack 0.168
+
+Slack (MET) : 0.171ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][0]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.256ns (logic 0.141ns (55.090%) route 0.115ns (44.910%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.904ns
+ Source Clock Delay (SCD): -0.660ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.640 -0.660 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X161Y119 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y119 FDCE (Prop_fdce_C_Q) 0.141 -0.519 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9][0]/Q
+ net (fo=2, routed) 0.115 -0.404 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[9]__0[0]
+ SLICE_X160Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.910 -0.904 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X160Y120 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][0]/C
+ clock pessimism 0.257 -0.647
+ SLICE_X160Y120 FDCE (Hold_fdce_C_D) 0.072 -0.575 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[10][0]
+ -------------------------------------------------------------------
+ required time 0.575
+ arrival time -0.404
+ -------------------------------------------------------------------
+ slack 0.171
+
+Slack (MET) : 0.171ns (arrival time - required time)
+ Source: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.255ns (logic 0.141ns (55.264%) route 0.114ns (44.736%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.906ns
+ Source Clock Delay (SCD): -0.663ns
+ Clock Pessimism Removal (CPR): -0.257ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.637 -0.663 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X157Y121 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X157Y121 FDCE (Prop_fdce_C_Q) 0.141 -0.522 r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2][5]/Q
+ net (fo=2, routed) 0.114 -0.408 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[2]__0[5]
+ SLICE_X159Y121 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout1_buf/O
+ net (fo=459, routed) 0.908 -0.906 rightFir/firUnit_1/operativeUnit_1/clk_out1
+ SLICE_X159Y121 FDCE r rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][5]/C
+ clock pessimism 0.257 -0.649
+ SLICE_X159Y121 FDCE (Hold_fdce_C_D) 0.070 -0.579 rightFir/firUnit_1/operativeUnit_1/SR_shiftRegister_reg[3][5]
+ -------------------------------------------------------------------
+ required time 0.579
+ arrival time -0.408
+ -------------------------------------------------------------------
+ slack 0.171
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out1_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT0 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_1/inst/clkout1_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X152Y126 lrclkD1_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y126 lrclkD2_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y126 lrclkcnt_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X149Y126 lrclkcnt_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y126 lrclkcnt_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X150Y126 lrclkcnt_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X151Y126 pulse48kHz_reg/C
+Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X160Y124 audio_inout/BCLK_int_reg/C
+Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT0
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X152Y126 lrclkD1_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X152Y126 lrclkD1_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y126 lrclkD2_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y126 lrclkD2_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y126 lrclkcnt_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y126 lrclkcnt_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X152Y126 lrclkD1_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X152Y126 lrclkD1_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y126 lrclkD2_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X151Y126 lrclkD2_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X149Y126 lrclkcnt_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y126 lrclkcnt_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X150Y126 lrclkcnt_reg[2]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out3_clk_wiz_0
+ To Clock: clk_out3_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 81.178ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out3_clk_wiz_0
+Waveform(ns): { 0.000 41.667 }
+Period(ns): 83.333
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT2 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 83.333 81.178 BUFGCTRL_X0Y0 clk_1/inst/clkout3_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT2 n/a 1.249 83.333 82.084 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT2
+Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 83.333 130.027 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT2
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out4_clk_wiz_0
+ To Clock: clk_out4_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 14.404ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.151ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 14.404ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[2]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 5.279ns (logic 1.014ns (19.208%) route 4.265ns (80.792%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.922 4.280 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[2]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[2]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y113 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[2]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -4.280
+ -------------------------------------------------------------------
+ slack 14.404
+
+Slack (MET) : 14.404ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[3]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 5.279ns (logic 1.014ns (19.208%) route 4.265ns (80.792%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.922 4.280 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[3]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[3]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y113 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[3]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -4.280
+ -------------------------------------------------------------------
+ slack 14.404
+
+Slack (MET) : 14.404ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[4]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 5.279ns (logic 1.014ns (19.208%) route 4.265ns (80.792%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.922 4.280 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[4]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[4]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y113 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[4]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -4.280
+ -------------------------------------------------------------------
+ slack 14.404
+
+Slack (MET) : 14.404ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[5]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 5.279ns (logic 1.014ns (19.208%) route 4.265ns (80.792%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.922 4.280 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y113 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[5]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -4.280
+ -------------------------------------------------------------------
+ slack 14.404
+
+Slack (MET) : 14.717ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[0]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.966ns (logic 1.014ns (20.420%) route 3.952ns (79.580%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.609 3.967 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y114 FDRE r initialize_audio/twi_controller/dataByte_reg[0]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y114 FDRE r initialize_audio/twi_controller/dataByte_reg[0]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y114 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[0]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -3.967
+ -------------------------------------------------------------------
+ slack 14.717
+
+Slack (MET) : 14.717ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[1]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.966ns (logic 1.014ns (20.420%) route 3.952ns (79.580%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.609 3.967 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y114 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y114 FDRE r initialize_audio/twi_controller/dataByte_reg[1]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y114 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[1]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -3.967
+ -------------------------------------------------------------------
+ slack 14.717
+
+Slack (MET) : 14.717ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[7]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.966ns (logic 1.014ns (20.420%) route 3.952ns (79.580%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.018ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.584ns = ( 18.416 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.609 3.967 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X160Y114 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.708 18.416 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y114 FDRE r initialize_audio/twi_controller/dataByte_reg[7]/C
+ clock pessimism 0.568 18.983
+ clock uncertainty -0.094 18.889
+ SLICE_X160Y114 FDRE (Setup_fdre_C_CE) -0.205 18.684 initialize_audio/twi_controller/dataByte_reg[7]
+ -------------------------------------------------------------------
+ required time 18.684
+ arrival time -3.967
+ -------------------------------------------------------------------
+ slack 14.717
+
+Slack (MET) : 14.759ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[6]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.944ns (logic 1.014ns (20.509%) route 3.930ns (79.491%))
+ Logic Levels: 4 (LUT2=2 LUT6=2)
+ Clock Path Skew: -0.034ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.586ns = ( 18.414 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.244 2.664 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I3_O) 0.124 2.788 r initialize_audio/twi_controller/dataByte[7]_i_4/O
+ net (fo=4, routed) 0.446 3.234 initialize_audio/twi_controller/dataByte0
+ SLICE_X161Y114 LUT2 (Prop_lut2_I1_O) 0.124 3.358 r initialize_audio/twi_controller/dataByte[7]_i_1/O
+ net (fo=8, routed) 0.587 3.945 initialize_audio/twi_controller/dataByte[7]_i_1_n_0
+ SLICE_X158Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.706 18.414 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
+ clock pessimism 0.554 18.967
+ clock uncertainty -0.094 18.873
+ SLICE_X158Y113 FDRE (Setup_fdre_C_CE) -0.169 18.704 initialize_audio/twi_controller/dataByte_reg[6]
+ -------------------------------------------------------------------
+ required time 18.704
+ arrival time -3.945
+ -------------------------------------------------------------------
+ slack 14.759
+
+Slack (MET) : 14.966ns (required time - arrival time)
+ Source: initialize_audio/twi_controller/sclCnt_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/bitCount_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.952ns (logic 1.014ns (20.475%) route 3.938ns (79.525%))
+ Logic Levels: 4 (LUT2=1 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.019ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.585ns = ( 18.415 - 20.000 )
+ Source Clock Delay (SCD): -0.999ns
+ Clock Pessimism Removal (CPR): 0.568ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.820 -0.999 initialize_audio/twi_controller/clk_out4
+ SLICE_X162Y119 FDSE r initialize_audio/twi_controller/sclCnt_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X162Y119 FDSE (Prop_fdse_C_Q) 0.518 -0.481 f initialize_audio/twi_controller/sclCnt_reg[2]/Q
+ net (fo=5, routed) 0.815 0.334 initialize_audio/twi_controller/sclCnt[2]
+ SLICE_X162Y118 LUT6 (Prop_lut6_I1_O) 0.124 0.458 r initialize_audio/twi_controller/sclCnt[6]_i_4/O
+ net (fo=2, routed) 0.838 1.296 initialize_audio/twi_controller/sclCnt[6]_i_4_n_0
+ SLICE_X162Y119 LUT2 (Prop_lut2_I0_O) 0.124 1.420 r initialize_audio/twi_controller/FSM_gray_state[3]_i_5/O
+ net (fo=11, routed) 1.446 2.867 initialize_audio/twi_controller/FSM_gray_state[3]_i_5_n_0
+ SLICE_X161Y114 LUT6 (Prop_lut6_I5_O) 0.124 2.991 r initialize_audio/twi_controller/dataByte[7]_i_3/O
+ net (fo=4, routed) 0.839 3.830 initialize_audio/twi_controller/dataByte1
+ SLICE_X160Y115 LUT5 (Prop_lut5_I4_O) 0.124 3.954 r initialize_audio/twi_controller/bitCount[2]_i_1/O
+ net (fo=1, routed) 0.000 3.954 initialize_audio/twi_controller/bitCount[2]_i_1_n_0
+ SLICE_X160Y115 FDRE r initialize_audio/twi_controller/bitCount_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.707 18.415 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y115 FDRE r initialize_audio/twi_controller/bitCount_reg[2]/C
+ clock pessimism 0.568 18.982
+ clock uncertainty -0.094 18.888
+ SLICE_X160Y115 FDRE (Setup_fdre_C_D) 0.031 18.919 initialize_audio/twi_controller/bitCount_reg[2]
+ -------------------------------------------------------------------
+ required time 18.919
+ arrival time -3.954
+ -------------------------------------------------------------------
+ slack 14.966
+
+Slack (MET) : 15.008ns (required time - arrival time)
+ Source: initialize_audio/delaycnt_reg[29]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/state_reg[0]/CE
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_out4_clk_wiz_0 rise@20.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 4.658ns (logic 0.952ns (20.440%) route 3.706ns (79.560%))
+ Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1)
+ Clock Path Skew: -0.035ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.582ns = ( 18.418 - 20.000 )
+ Source Clock Delay (SCD): -0.994ns
+ Clock Pessimism Removal (CPR): 0.554ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.174ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.708 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.432 -4.724 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.808 -2.915 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.096 -2.819 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.825 -0.994 initialize_audio/clk_out4
+ SLICE_X156Y114 FDRE r initialize_audio/delaycnt_reg[29]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X156Y114 FDRE (Prop_fdre_C_Q) 0.456 -0.538 f initialize_audio/delaycnt_reg[29]/Q
+ net (fo=3, routed) 0.982 0.444 initialize_audio/delaycnt_reg_n_0_[29]
+ SLICE_X157Y111 LUT4 (Prop_lut4_I3_O) 0.124 0.568 f initialize_audio/initA[6]_i_15/O
+ net (fo=1, routed) 0.667 1.235 initialize_audio/initA[6]_i_15_n_0
+ SLICE_X157Y111 LUT5 (Prop_lut5_I4_O) 0.124 1.359 f initialize_audio/initA[6]_i_11/O
+ net (fo=1, routed) 0.823 2.182 initialize_audio/initA[6]_i_11_n_0
+ SLICE_X158Y111 LUT4 (Prop_lut4_I3_O) 0.124 2.306 r initialize_audio/initA[6]_i_4/O
+ net (fo=4, routed) 0.529 2.835 initialize_audio/twi_controller/initEn_reg
+ SLICE_X159Y111 LUT6 (Prop_lut6_I1_O) 0.124 2.959 r initialize_audio/twi_controller/state[3]_i_1/O
+ net (fo=4, routed) 0.705 3.664 initialize_audio/twi_controller_n_6
+ SLICE_X161Y111 FDRE r initialize_audio/state_reg[0]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 20.000 20.000 r
+ R4 0.000 20.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 20.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 22.567 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -7.674 14.893 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 1.723 16.616 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.091 16.707 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 1.710 18.418 initialize_audio/clk_out4
+ SLICE_X161Y111 FDRE r initialize_audio/state_reg[0]/C
+ clock pessimism 0.554 18.971
+ clock uncertainty -0.094 18.877
+ SLICE_X161Y111 FDRE (Setup_fdre_C_CE) -0.205 18.672 initialize_audio/state_reg[0]
+ -------------------------------------------------------------------
+ required time 18.672
+ arrival time -3.664
+ -------------------------------------------------------------------
+ slack 15.008
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.151ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[23]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[7]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.256ns (logic 0.186ns (72.524%) route 0.070ns (27.476%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X161Y110 FDRE r initialize_audio/initWord_reg[23]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initWord_reg[23]/Q
+ net (fo=2, routed) 0.070 -0.442 initialize_audio/data1[7]
+ SLICE_X160Y110 LUT6 (Prop_lut6_I5_O) 0.045 -0.397 r initialize_audio/data_i[7]_i_1/O
+ net (fo=1, routed) 0.000 -0.397 initialize_audio/data_i[7]_i_1_n_0
+ SLICE_X160Y110 FDRE r initialize_audio/data_i_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X160Y110 FDRE r initialize_audio/data_i_reg[7]/C
+ clock pessimism 0.254 -0.641
+ SLICE_X160Y110 FDRE (Hold_fdre_C_D) 0.092 -0.549 initialize_audio/data_i_reg[7]
+ -------------------------------------------------------------------
+ required time 0.549
+ arrival time -0.397
+ -------------------------------------------------------------------
+ slack 0.151
+
+Slack (MET) : 0.171ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/dataByte_reg[5]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/dataByte_reg[6]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.329ns (logic 0.186ns (56.469%) route 0.143ns (43.531%))
+ Logic Levels: 1 (LUT4=1)
+ Clock Path Skew: 0.037ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.899ns
+ Source Clock Delay (SCD): -0.656ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.644 -0.656 initialize_audio/twi_controller/clk_out4
+ SLICE_X160Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X160Y113 FDRE (Prop_fdre_C_Q) 0.141 -0.515 r initialize_audio/twi_controller/dataByte_reg[5]/Q
+ net (fo=1, routed) 0.143 -0.371 initialize_audio/twi_controller/dataByte[5]
+ SLICE_X158Y113 LUT4 (Prop_lut4_I3_O) 0.045 -0.326 r initialize_audio/twi_controller/dataByte[6]_i_1/O
+ net (fo=1, routed) 0.000 -0.326 initialize_audio/twi_controller/p_1_in[6]
+ SLICE_X158Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.915 -0.899 initialize_audio/twi_controller/clk_out4
+ SLICE_X158Y113 FDRE r initialize_audio/twi_controller/dataByte_reg[6]/C
+ clock pessimism 0.280 -0.619
+ SLICE_X158Y113 FDRE (Hold_fdre_C_D) 0.121 -0.498 initialize_audio/twi_controller/dataByte_reg[6]
+ -------------------------------------------------------------------
+ required time 0.498
+ arrival time -0.326
+ -------------------------------------------------------------------
+ slack 0.171
+
+Slack (MET) : 0.210ns (arrival time - required time)
+ Source: initialize_audio/initWord_reg[9]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[1]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.342ns (logic 0.186ns (54.411%) route 0.156ns (45.589%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.040ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.655ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.645 -0.655 initialize_audio/clk_out4
+ SLICE_X159Y110 FDRE r initialize_audio/initWord_reg[9]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y110 FDRE (Prop_fdre_C_Q) 0.141 -0.514 r initialize_audio/initWord_reg[9]/Q
+ net (fo=1, routed) 0.156 -0.358 initialize_audio/data2[1]
+ SLICE_X160Y110 LUT6 (Prop_lut6_I2_O) 0.045 -0.313 r initialize_audio/data_i[1]_i_1/O
+ net (fo=1, routed) 0.000 -0.313 initialize_audio/data_i[1]_i_1_n_0
+ SLICE_X160Y110 FDRE r initialize_audio/data_i_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X160Y110 FDRE r initialize_audio/data_i_reg[1]/C
+ clock pessimism 0.280 -0.615
+ SLICE_X160Y110 FDRE (Hold_fdre_C_D) 0.092 -0.523 initialize_audio/data_i_reg[1]
+ -------------------------------------------------------------------
+ required time 0.523
+ arrival time -0.313
+ -------------------------------------------------------------------
+ slack 0.210
+
+Slack (MET) : 0.211ns (arrival time - required time)
+ Source: initialize_audio/initA_reg[2]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initWord_reg[9]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.316ns (logic 0.209ns (66.192%) route 0.107ns (33.808%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.896ns
+ Source Clock Delay (SCD): -0.655ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.645 -0.655 initialize_audio/clk_out4
+ SLICE_X158Y110 FDRE r initialize_audio/initA_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X158Y110 FDRE (Prop_fdre_C_Q) 0.164 -0.491 r initialize_audio/initA_reg[2]/Q
+ net (fo=22, routed) 0.107 -0.384 initialize_audio/initA_reg_n_0_[2]
+ SLICE_X159Y110 LUT6 (Prop_lut6_I4_O) 0.045 -0.339 r initialize_audio/initWord[9]_i_1/O
+ net (fo=1, routed) 0.000 -0.339 initialize_audio/initWord[9]_i_1_n_0
+ SLICE_X159Y110 FDRE r initialize_audio/initWord_reg[9]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.918 -0.896 initialize_audio/clk_out4
+ SLICE_X159Y110 FDRE r initialize_audio/initWord_reg[9]/C
+ clock pessimism 0.254 -0.642
+ SLICE_X159Y110 FDRE (Hold_fdre_C_D) 0.092 -0.550 initialize_audio/initWord_reg[9]
+ -------------------------------------------------------------------
+ required time 0.550
+ arrival time -0.339
+ -------------------------------------------------------------------
+ slack 0.211
+
+Slack (MET) : 0.214ns (arrival time - required time)
+ Source: initialize_audio/state_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.318ns (logic 0.186ns (58.446%) route 0.132ns (41.554%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X161Y111 FDRE r initialize_audio/state_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y111 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/state_reg[0]/Q
+ net (fo=21, routed) 0.132 -0.381 initialize_audio/state_reg_n_0_[0]
+ SLICE_X160Y111 LUT6 (Prop_lut6_I1_O) 0.045 -0.336 r initialize_audio/data_i[2]_i_1/O
+ net (fo=1, routed) 0.000 -0.336 initialize_audio/data_i[2]_i_1_n_0
+ SLICE_X160Y111 FDRE r initialize_audio/data_i_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X160Y111 FDRE r initialize_audio/data_i_reg[2]/C
+ clock pessimism 0.254 -0.641
+ SLICE_X160Y111 FDRE (Hold_fdre_C_D) 0.091 -0.550 initialize_audio/data_i_reg[2]
+ -------------------------------------------------------------------
+ required time 0.550
+ arrival time -0.336
+ -------------------------------------------------------------------
+ slack 0.214
+
+Slack (MET) : 0.218ns (arrival time - required time)
+ Source: initialize_audio/initA_reg[5]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initA_reg[6]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.349ns (logic 0.186ns (53.360%) route 0.163ns (46.640%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.040ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.894ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X159Y109 FDRE r initialize_audio/initA_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y109 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initA_reg[5]/Q
+ net (fo=23, routed) 0.163 -0.350 initialize_audio/initA_reg_n_0_[5]
+ SLICE_X161Y109 LUT6 (Prop_lut6_I1_O) 0.045 -0.305 r initialize_audio/initA[6]_i_3/O
+ net (fo=1, routed) 0.000 -0.305 initialize_audio/initA[6]_i_3_n_0
+ SLICE_X161Y109 FDRE r initialize_audio/initA_reg[6]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.920 -0.894 initialize_audio/clk_out4
+ SLICE_X161Y109 FDRE r initialize_audio/initA_reg[6]/C
+ clock pessimism 0.280 -0.614
+ SLICE_X161Y109 FDRE (Hold_fdre_C_D) 0.091 -0.523 initialize_audio/initA_reg[6]
+ -------------------------------------------------------------------
+ required time 0.523
+ arrival time -0.305
+ -------------------------------------------------------------------
+ slack 0.218
+
+Slack (MET) : 0.219ns (arrival time - required time)
+ Source: initialize_audio/initA_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initWord_reg[18]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.351ns (logic 0.186ns (53.034%) route 0.165ns (46.966%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.040ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.894ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X159Y109 FDRE r initialize_audio/initA_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y109 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initA_reg[1]/Q
+ net (fo=25, routed) 0.165 -0.348 initialize_audio/initA_reg_n_0_[1]
+ SLICE_X160Y109 LUT6 (Prop_lut6_I3_O) 0.045 -0.303 r initialize_audio/initWord[18]_i_1/O
+ net (fo=1, routed) 0.000 -0.303 initialize_audio/initWord[18]_i_1_n_0
+ SLICE_X160Y109 FDRE r initialize_audio/initWord_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.920 -0.894 initialize_audio/clk_out4
+ SLICE_X160Y109 FDRE r initialize_audio/initWord_reg[18]/C
+ clock pessimism 0.280 -0.614
+ SLICE_X160Y109 FDRE (Hold_fdre_C_D) 0.092 -0.522 initialize_audio/initWord_reg[18]
+ -------------------------------------------------------------------
+ required time 0.522
+ arrival time -0.303
+ -------------------------------------------------------------------
+ slack 0.219
+
+Slack (MET) : 0.221ns (arrival time - required time)
+ Source: initialize_audio/initA_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/initWord_reg[17]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.352ns (logic 0.186ns (52.883%) route 0.166ns (47.117%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.040ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.894ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.280ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X159Y109 FDRE r initialize_audio/initA_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X159Y109 FDRE (Prop_fdre_C_Q) 0.141 -0.513 r initialize_audio/initA_reg[1]/Q
+ net (fo=25, routed) 0.166 -0.347 initialize_audio/initA_reg_n_0_[1]
+ SLICE_X160Y109 LUT6 (Prop_lut6_I2_O) 0.045 -0.302 r initialize_audio/initWord[17]_i_1/O
+ net (fo=1, routed) 0.000 -0.302 initialize_audio/initWord[17]_i_1_n_0
+ SLICE_X160Y109 FDRE r initialize_audio/initWord_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.920 -0.894 initialize_audio/clk_out4
+ SLICE_X160Y109 FDRE r initialize_audio/initWord_reg[17]/C
+ clock pessimism 0.280 -0.614
+ SLICE_X160Y109 FDRE (Hold_fdre_C_D) 0.091 -0.523 initialize_audio/initWord_reg[17]
+ -------------------------------------------------------------------
+ required time 0.523
+ arrival time -0.302
+ -------------------------------------------------------------------
+ slack 0.221
+
+Slack (MET) : 0.232ns (arrival time - required time)
+ Source: initialize_audio/state_reg[1]/C
+ (rising edge-triggered cell FDSE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/data_i_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.337ns (logic 0.186ns (55.160%) route 0.151ns (44.840%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.895ns
+ Source Clock Delay (SCD): -0.654ns
+ Clock Pessimism Removal (CPR): -0.254ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.646 -0.654 initialize_audio/clk_out4
+ SLICE_X161Y111 FDSE r initialize_audio/state_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X161Y111 FDSE (Prop_fdse_C_Q) 0.141 -0.513 r initialize_audio/state_reg[1]/Q
+ net (fo=21, routed) 0.151 -0.362 initialize_audio/state_reg_n_0_[1]
+ SLICE_X160Y111 LUT6 (Prop_lut6_I2_O) 0.045 -0.317 r initialize_audio/data_i[0]_i_1/O
+ net (fo=1, routed) 0.000 -0.317 initialize_audio/data_i[0]_i_1_n_0
+ SLICE_X160Y111 FDRE r initialize_audio/data_i_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.919 -0.895 initialize_audio/clk_out4
+ SLICE_X160Y111 FDRE r initialize_audio/data_i_reg[0]/C
+ clock pessimism 0.254 -0.641
+ SLICE_X160Y111 FDRE (Hold_fdre_C_D) 0.092 -0.549 initialize_audio/data_i_reg[0]
+ -------------------------------------------------------------------
+ required time 0.549
+ arrival time -0.317
+ -------------------------------------------------------------------
+ slack 0.232
+
+Slack (MET) : 0.236ns (arrival time - required time)
+ Source: initialize_audio/twi_controller/dSda_reg/C
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: initialize_audio/twi_controller/busState_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out4_clk_wiz_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_out4_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out4_clk_wiz_0 rise@0.000ns - clk_out4_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.327ns (logic 0.227ns (69.392%) route 0.100ns (30.608%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.900ns
+ Source Clock Delay (SCD): -0.657ns
+ Clock Pessimism Removal (CPR): -0.243ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -2.540 -1.856 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.531 -1.325 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 -1.299 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.643 -0.657 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/dSda_reg/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X163Y116 FDRE (Prop_fdre_C_Q) 0.128 -0.529 r initialize_audio/twi_controller/dSda_reg/Q
+ net (fo=9, routed) 0.100 -0.429 initialize_audio/twi_controller/p_0_in_0[0]
+ SLICE_X163Y116 LUT6 (Prop_lut6_I1_O) 0.099 -0.330 r initialize_audio/twi_controller/busState[0]_i_1/O
+ net (fo=1, routed) 0.000 -0.330 initialize_audio/twi_controller/busState[0]_i_1_n_0
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/busState_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out4_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ R4 0.000 0.000 r CLK100MHZ (IN)
+ net (fo=0) 0.000 0.000 clk_1/inst/clk_in1
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r clk_1/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.911 clk_1/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
+ -3.332 -2.421 r clk_1/inst/mmcm_adv_inst/CLKOUT3
+ net (fo=1, routed) 0.579 -1.843 clk_1/inst/clk_out4_clk_wiz_0
+ BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.029 -1.814 r clk_1/inst/clkout4_buf/O
+ net (fo=120, routed) 0.914 -0.900 initialize_audio/twi_controller/clk_out4
+ SLICE_X163Y116 FDRE r initialize_audio/twi_controller/busState_reg[0]/C
+ clock pessimism 0.243 -0.657
+ SLICE_X163Y116 FDRE (Hold_fdre_C_D) 0.091 -0.566 initialize_audio/twi_controller/busState_reg[0]
+ -------------------------------------------------------------------
+ required time 0.566
+ arrival time -0.330
+ -------------------------------------------------------------------
+ slack 0.236
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out4_clk_wiz_0
+Waveform(ns): { 0.000 10.000 }
+Period(ns): 20.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKOUT3 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y2 clk_1/inst/clkout4_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT3 n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y111 initialize_audio/data_i_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y110 initialize_audio/data_i_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y111 initialize_audio/data_i_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y111 initialize_audio/data_i_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y110 initialize_audio/data_i_reg[4]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y111 initialize_audio/data_i_reg[5]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y110 initialize_audio/data_i_reg[6]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X160Y110 initialize_audio/data_i_reg[7]/C
+Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 20.000 193.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKOUT3
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[1]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[2]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[3]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[4]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[4]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[2]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[2]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[3]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y111 initialize_audio/data_i_reg[3]/C
+High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[4]/C
+High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X160Y110 initialize_audio/data_i_reg[4]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clkfbout_clk_wiz_0
+ To Clock: clkfbout_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clkfbout_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk_1/inst/mmcm_adv_inst/CLKFBOUT }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y3 clk_1/inst/clkf_buf/I
+Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBOUT
+Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clk_1/inst/mmcm_adv_inst/CLKFBOUT
+
+
+
diff --git a/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..0da1bf46a5d1a488ca4f9422516c4de7231a45f1
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_timing_summary_routed.rpx differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..fa28f1e478ad80b4c4e493f33514006f2cdab27a
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.pb differ
diff --git a/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..db45a5dbb85828bbd3fa0fee14bf024bc3304909
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/audioProc_utilization_placed.rpt
@@ -0,0 +1,227 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:41:00 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs | 571 | 0 | 800 | 133800 | 0.43 |
+| LUT as Logic | 571 | 0 | 800 | 133800 | 0.43 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register as Flip Flop | 579 | 0 | 1600 | 267600 | 0.22 |
+| Register as Latch | 10 | 0 | 1600 | 267600 | <0.01 |
+| F7 Muxes | 34 | 0 | 400 | 66900 | 0.05 |
+| F8 Muxes | 16 | 0 | 200 | 33450 | 0.05 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 328 | Yes | - | Reset |
+| 20 | Yes | Set | - |
+| 239 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice | 239 | 0 | 200 | 33450 | 0.71 |
+| SLICEL | 153 | 0 | | | |
+| SLICEM | 86 | 0 | | | |
+| LUT as Logic | 571 | 0 | 800 | 133800 | 0.43 |
+| using O5 output only | 1 | | | | |
+| using O6 output only | 486 | | | | |
+| using O5 and O6 | 84 | | | | |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| LUT as Distributed RAM | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| LUT as Shift Register | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| Slice Registers | 589 | 0 | 1600 | 267600 | 0.22 |
+| Register driven from within the Slice | 260 | | | | |
+| Register driven from outside the Slice | 329 | | | | |
+| LUT in front of the register is unused | 262 | | | | |
+| LUT in front of the register is used | 67 | | | | |
+| Unique Control Sets | 33 | | 200 | 33450 | 0.10 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 20 | 20 | 0 | 285 | 7.02 |
+| IOB Master Pads | 8 | | | | |
+| IOB Slave Pads | 10 | | | | |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 0 | 10 | 10.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| FDCE | 318 | Flop & Latch |
+| FDRE | 239 | Flop & Latch |
+| LUT6 | 237 | LUT |
+| LUT2 | 113 | LUT |
+| LUT5 | 95 | LUT |
+| LUT3 | 95 | LUT |
+| LUT4 | 74 | LUT |
+| CARRY4 | 46 | CarryLogic |
+| LUT1 | 41 | LUT |
+| MUXF7 | 34 | MuxFx |
+| FDSE | 20 | Flop & Latch |
+| MUXF8 | 16 | MuxFx |
+| IBUF | 11 | IO |
+| LDCE | 10 | Flop & Latch |
+| OBUF | 9 | IO |
+| BUFG | 4 | Clock |
+| OBUFT | 2 | IO |
+| FDPE | 2 | Flop & Latch |
+| MMCME2_ADV | 1 | Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
diff --git a/proj/AudioProc.runs/impl_1/clockInfo.txt b/proj/AudioProc.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000000000000000000000000000000000000..a81f5521f7dc5577561f8087479330aa3fa1e198
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.1
+| Date : Wed Feb 26 11:40:52 2025
+| Host : fl-tp-br-608
+| Design : design_1
+| Device : xc7a200t-sbg484-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/proj/AudioProc.runs/impl_1/gen_run.xml b/proj/AudioProc.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..56fef274888ecb4a87dac75e0db74c54df427f23
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/gen_run.xml
@@ -0,0 +1,208 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1740566203">
+ <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS" Name="audioProc_postroute_physopted.rqs"/>
+ <File Type="ROUTE-RQS" Name="audioProc_routed.rqs"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BG-BGN" Name="audioProc.bgn"/>
+ <File Type="BITSTR-SYSDEF" Name="audioProc.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="audioProc.ltx"/>
+ <File Type="RBD_FILE" Name="audioProc.rbd"/>
+ <File Type="NPI_FILE" Name="audioProc.npi"/>
+ <File Type="RNPI_FILE" Name="audioProc.rnpi"/>
+ <File Type="CFI_FILE" Name="audioProc.cfi"/>
+ <File Type="RCFI_FILE" Name="audioProc.rcfi"/>
+ <File Type="PL-PDI-FILE" Name="audioProc_pld.pdi"/>
+ <File Type="BOOT-PDI-FILE" Name="audioProc_boot.pdi"/>
+ <File Type="RDI-RDI" Name="audioProc.vdi"/>
+ <File Type="PDI-FILE" Name="audioProc.pdi"/>
+ <File Type="BITSTR-MMI" Name="audioProc.mmi"/>
+ <File Type="BITSTR-BMM" Name="audioProc_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="audioProc.nky"/>
+ <File Type="BITSTR-RBT" Name="audioProc.rbt"/>
+ <File Type="BITSTR-MSK" Name="audioProc.msk"/>
+ <File Type="BG-BIN" Name="audioProc.bin"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+ <File Type="BG-BIT" Name="audioProc.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="audioProc_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="audioProc_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="audioProc_bus_skew_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="audioProc_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="audioProc_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="audioProc_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="audioProc_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="audioProc_postroute_physopt.dcp"/>
+ <File Type="BG-DRC" Name="audioProc.drc"/>
+ <File Type="ROUTE-RQS-PB" Name="audioProc_rqs_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="audioProc_bus_skew_routed.rpx"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="audioProc_bus_skew_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW" Name="audioProc_bus_skew_routed.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="audioProc_utilization_placed.pb"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="audioProc_methodology_drc_opted.rpt"/>
+ <File Type="PLACE-UTIL" Name="audioProc_utilization_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="audioProc_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-IO" Name="audioProc_io_placed.rpt"/>
+ <File Type="PHYSOPT-TIMING" Name="audioProc_timing_summary_physopted.rpt"/>
+ <File Type="PWROPT-DRC" Name="audioProc_drc_pwropted.rpt"/>
+ <File Type="PWROPT-TIMING" Name="audioProc_timing_summary_pwropted.rpt"/>
+ <File Type="OPT-DRC" Name="audioProc_drc_opted.rpt"/>
+ <File Type="PLACE-TIMING" Name="audioProc_timing_summary_placed.rpt"/>
+ <File Type="INIT-TIMING" Name="audioProc_timing_summary_init.rpt"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
+ <File Type="PLACE-CTRL" Name="audioProc_control_sets_placed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="audioProc_methodology_drc_routed.rpt"/>
+ <File Type="OPT-DCP" Name="audioProc_opt.dcp"/>
+ <File Type="OPT-RQA-PB" Name="audioProc_rqa_opted.pb"/>
+ <File Type="OPT-HWDEF" Name="audioProc.hwdef"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="audioProc_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="OPT-TIMING" Name="audioProc_timing_summary_opted.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="audioProc_incremental_reuse_placed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="audioProc_methodology_drc_routed.pb"/>
+ <File Type="PLACE-DCP" Name="audioProc_placed.dcp"/>
+ <File Type="PLACE-RQA-PB" Name="audioProc_rqa_placed.pb"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="audioProc_incremental_reuse_pre_placed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="audioProc_drc_routed.rpx"/>
+ <File Type="PWROPT-DCP" Name="audioProc_pwropt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="audioProc_postplace_pwropt.dcp"/>
+ <File Type="PHYSOPT-DCP" Name="audioProc_physopt.dcp"/>
+ <File Type="PHYSOPT-DRC" Name="audioProc_drc_physopted.rpt"/>
+ <File Type="ROUTE-ERROR-DCP" Name="audioProc_routed_error.dcp"/>
+ <File Type="ROUTE-DCP" Name="audioProc_routed.dcp"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="audioProc_routed_bb.dcp"/>
+ <File Type="ROUTE-DRC" Name="audioProc_drc_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="audioProc_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="audioProc_drc_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="audioProc_power_routed.rpt"/>
+ <File Type="ROUTE-PWR-SUM" Name="audioProc_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR-RPX" Name="audioProc_power_routed.rpx"/>
+ <File Type="ROUTE-STATUS" Name="audioProc_route_status.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="audioProc_route_status.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="audioProc_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-TIMING-PB" Name="audioProc_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMING-RPX" Name="audioProc_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-SIMILARITY" Name="audioProc_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="audioProc_clock_utilization_routed.rpt"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+ <Desc>Vivado Implementation Defaults</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+</GenRun>
diff --git a/proj/AudioProc.runs/impl_1/htr.txt b/proj/AudioProc.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2498e464293307c0340b7226ed1775e71d1403fc
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/init_design.pb b/proj/AudioProc.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4049ac9cac1b611952464defd4cee6e2e372eeb9
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/init_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/opt_design.pb b/proj/AudioProc.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3f186bdc24ec1d63c9a8aa778fc651d1bc45f54b
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/opt_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/place_design.pb b/proj/AudioProc.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..22425af86d421d0a05d3a4975e4e7d86bce9e710
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/place_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/project.wdf b/proj/AudioProc.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..8d1818322cb70792d13bf981b21f413fba5fe4da
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3132:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:466c6f775f506572664f7074696d697a65645f48696768:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
+70726f6a656374:69705f636f72655f636f6e7461696e65725c3c6970636f72656e616d653e5c636c6b5f77697a5f30:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3135:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3431393938336662323231313439306638323765623433303764333232656238:506172656e742050412070726f6a656374204944:00
+eof:4271444909
diff --git a/proj/AudioProc.runs/impl_1/route_design.pb b/proj/AudioProc.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3d72a8429802714798bdf5563b1ff6965543f36a
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/route_design.pb differ
diff --git a/proj/AudioProc.runs/impl_1/rundef.js b/proj/AudioProc.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..52db31ee15cfd6fce55ef683261e82bb3df928c0
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/rundef.js
@@ -0,0 +1,45 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/impl_1/runme.bat b/proj/AudioProc.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/impl_1/runme.log b/proj/AudioProc.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..4ff7c301584f77561d2056a5875b3523dcd57d3a
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.log
@@ -0,0 +1,797 @@
+
+*** Running vivado
+ with args -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 26 11:38:26 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:19 ; elapsed = 00:01:03 . Memory (MB): peak = 1680.586 ; gain = 325.840 ; free physical = 6642 ; free virtual = 15003
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+update_ip_catalog: Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:09 . Memory (MB): peak = 1686.523 ; gain = 5.938 ; free physical = 6628 ; free virtual = 14988
+Command: link_design -top audioProc -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_1'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2097.469 ; gain = 0.000 ; free physical = 6212 ; free virtual = 14573
+INFO: [Netlist 29-17] Analyzing 99 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2015.3
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+INFO: [Timing 38-2] Deriving generated clocks [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc:56]
+get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 2870.988 ; gain = 624.930 ; free physical = 5626 ; free virtual = 13996
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_1/inst'
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.dcp'
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2870.988 ; gain = 0.000 ; free physical = 5626 ; free virtual = 13996
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 2 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+
+14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:37 . Memory (MB): peak = 2870.988 ; gain = 1176.527 ; free physical = 5626 ; free virtual = 13996
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2935.020 ; gain = 64.031 ; free physical = 5601 ; free virtual = 13972
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2935.020 ; gain = 0.000 ; free physical = 5601 ; free virtual = 13972
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 1 Initialization | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 2 Timer Update And Timing Data Collection | Checksum: 1c260a500
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 4 pins
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 153e10ba0
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Retarget | Checksum: 153e10ba0
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 153e10ba0
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Constant propagation | Checksum: 153e10ba0
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 1af9906b9
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Sweep | Checksum: 1af9906b9
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells
+
+Phase 6 BUFG optimization
+INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells
+Phase 6 BUFG optimization | Checksum: 16d99f34e
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+BUFG optimization | Checksum: 16d99f34e
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 16d99f34e
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Shift Register Optimization | Checksum: 16d99f34e
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 1d945ff79
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Post Processing Netlist | Checksum: 1d945ff79
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Phase 9 Finalization | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 2 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 1 | 0 |
+| BUFG optimization | 0 | 2 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+Ending Netlist Obfuscation Task | Checksum: 2143204f5
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3228.684 ; gain = 0.000 ; free physical = 5286 ; free virtual = 13658
+INFO: [Common 17-83] Releasing license: Implementation
+35 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+Command: report_drc -file audioProc_drc_opted.rpt -pb audioProc_drc_opted.pb -rpx audioProc_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_drc_opted.rpt.
+report_drc completed successfully
+report_drc: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 88.043 ; free physical = 5289 ; free virtual = 13661
+generate_parallel_reports: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 88.043 ; free physical = 5289 ; free virtual = 13661
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5289 ; free virtual = 13662
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5289 ; free virtual = 13662
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5284 ; free virtual = 13657
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13655
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13655
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13655
+Write Physdb Complete: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5281 ; free virtual = 13655
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13656
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1bab39224
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13656
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5282 ; free virtual = 13656
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 173dcc833
+
+Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5255 ; free virtual = 13632
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1e2170656
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5249 ; free virtual = 13628
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1e2170656
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5249 ; free virtual = 13628
+Phase 1 Placer Initialization | Checksum: 1e2170656
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5249 ; free virtual = 13628
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1d7e80512
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5259 ; free virtual = 13638
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 202ebee6b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5273 ; free virtual = 13652
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 202ebee6b
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5273 ; free virtual = 13652
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 18ccd01ad
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5271 ; free virtual = 13651
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 18 LUTNM shape to break, 85 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 12, two critical 6, total 18, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 54 nets or LUTs. Breaked 18 LUTs, combined 36 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
+INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
+INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13648
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 18 | 36 | 54 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 18 | 36 | 54 | 0 | 9 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 15eef931f
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13649
+Phase 2.4 Global Placement Core | Checksum: 129c76092
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13648
+Phase 2 Global Placement | Checksum: 129c76092
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5267 ; free virtual = 13648
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 16420d5ef
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5266 ; free virtual = 13648
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 21934284e
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5266 ; free virtual = 13648
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1eade4b9d
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5266 ; free virtual = 13648
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 16ab41fd8
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5265 ; free virtual = 13647
+
+Phase 3.5 Fast Optimization
+Phase 3.5 Fast Optimization | Checksum: 1b1008a71
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5262 ; free virtual = 13644
+
+Phase 3.6 Small Shape Detail Placement
+Phase 3.6 Small Shape Detail Placement | Checksum: 1d31c1c21
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5256 ; free virtual = 13638
+
+Phase 3.7 Re-assign LUT pins
+Phase 3.7 Re-assign LUT pins | Checksum: 1c522d8e8
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5256 ; free virtual = 13638
+
+Phase 3.8 Pipeline Register Optimization
+Phase 3.8 Pipeline Register Optimization | Checksum: 1f3ec45b6
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5256 ; free virtual = 13638
+
+Phase 3.9 Fast Optimization
+Phase 3.9 Fast Optimization | Checksum: 209647115
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5250 ; free virtual = 13632
+Phase 3 Detail Placement | Checksum: 209647115
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5250 ; free virtual = 13632
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 2f05449ba
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.026 | TNS=-2.986 |
+Phase 1 Physical Synthesis Initialization | Checksum: 22717f216
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5248 ; free virtual = 13630
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 26ff54906
+
+Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5248 ; free virtual = 13630
+Phase 4.1.1.1 BUFG Insertion | Checksum: 2f05449ba
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5248 ; free virtual = 13630
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.229. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13629
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Phase 4.1 Post Commit Optimization | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Phase 4.3 Placer Reporting | Checksum: 2043611cf
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14e62cb1f
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+Ending Placer Task | Checksum: 10e1e419b
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+78 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5247 ; free virtual = 13630
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file audioProc_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5226 ; free virtual = 13609
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_placed.rpt -pb audioProc_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file audioProc_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5215 ; free virtual = 13598
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5215 ; free virtual = 13597
+Wrote PlaceDB: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5214 ; free virtual = 13598
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5213 ; free virtual = 13597
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5213 ; free virtual = 13597
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5213 ; free virtual = 13597
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5211 ; free virtual = 13596
+Write Physdb Complete: Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3316.727 ; gain = 0.000 ; free physical = 5211 ; free virtual = 13596
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_placed.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 381a9127 ConstDB: 0 ShapeSum: 3de8c510 RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: 6bbe2e5b | NumContArr: 178c64c5 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2089c885a
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3501.484 ; gain = 184.758 ; free physical = 4970 ; free virtual = 13356
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2089c885a
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3501.484 ; gain = 184.758 ; free physical = 4970 ; free virtual = 13356
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2089c885a
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 3501.484 ; gain = 184.758 ; free physical = 4970 ; free virtual = 13356
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 26c584cde
+
+Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 3569.242 ; gain = 252.516 ; free physical = 4900 ; free virtual = 13286
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.084 | TNS=-0.157 | WHS=-0.121 | THS=-17.691|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.000263185 %
+ Global Horizontal Routing Utilization = 0.000727032 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 976
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 966
+ Number of Partially Routed Nets = 10
+ Number of Node Overlaps = 7
+
+Phase 2 Router Initialization | Checksum: 336dd4049
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 336dd4049
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 248795aa0
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 4 Initial Routing | Checksum: 248795aa0
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 356
+ Number of Nodes with overlaps = 184
+ Number of Nodes with overlaps = 88
+ Number of Nodes with overlaps = 43
+ Number of Nodes with overlaps = 31
+ Number of Nodes with overlaps = 16
+ Number of Nodes with overlaps = 7
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.323 | TNS=-1.133 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 1a850c44d
+
+Time (s): cpu = 00:00:45 ; elapsed = 00:00:36 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4895 ; free virtual = 13282
+
+Phase 5.2 Global Iteration 1
+ Number of Nodes with overlaps = 137
+ Number of Nodes with overlaps = 71
+ Number of Nodes with overlaps = 47
+ Number of Nodes with overlaps = 34
+ Number of Nodes with overlaps = 25
+ Number of Nodes with overlaps = 8
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 3
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.031 | TNS=-0.051 | WHS=N/A | THS=N/A |
+
+Phase 5.2 Global Iteration 1 | Checksum: 2adbc2af9
+
+Time (s): cpu = 00:00:48 ; elapsed = 00:00:37 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 5.3 Global Iteration 2
+ Number of Nodes with overlaps = 136
+ Number of Nodes with overlaps = 79
+ Number of Nodes with overlaps = 43
+ Number of Nodes with overlaps = 37
+ Number of Nodes with overlaps = 25
+ Number of Nodes with overlaps = 16
+ Number of Nodes with overlaps = 25
+ Number of Nodes with overlaps = 19
+ Number of Nodes with overlaps = 5
+ Number of Nodes with overlaps = 4
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.001 | TNS=-0.001 | WHS=N/A | THS=N/A |
+
+Phase 5.3 Global Iteration 2 | Checksum: 22f6ec8ac
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 5 Rip-up And Reroute | Checksum: 22f6ec8ac
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.078 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 6.1 Delay CleanUp | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 6 Delay and Skew Optimization | Checksum: 200893ff9
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.078 | TNS=0.000 | WHS=0.131 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Phase 7 Post Hold Fix | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0763438 %
+ Global Horizontal Routing Utilization = 0.0985459 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 259c6825a
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 24cf8f2b5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 24cf8f2b5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.078 | TNS=0.000 | WHS=0.131 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 24cf8f2b5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+Total Elapsed time in route_design: 39.73 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 116e977f9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 116e977f9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+99 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:41 . Memory (MB): peak = 3576.633 ; gain = 259.906 ; free physical = 4896 ; free virtual = 13283
+INFO: [Vivado 12-24828] Executing command : report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+Command: report_drc -file audioProc_drc_routed.rpt -pb audioProc_drc_routed.pb -rpx audioProc_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+Command: report_methodology -file audioProc_methodology_drc_routed.rpt -pb audioProc_methodology_drc_routed.pb -rpx audioProc_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file audioProc_timing_summary_routed.rpt -pb audioProc_timing_summary_routed.pb -rpx audioProc_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file audioProc_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file audioProc_route_status.rpt -pb audioProc_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file audioProc_bus_skew_routed.rpt -pb audioProc_bus_skew_routed.pb -rpx audioProc_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Command: report_power -file audioProc_power_routed.rpt -pb audioProc_power_summary_routed.pb -rpx audioProc_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+119 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file audioProc_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4873 ; free virtual = 13262
+Wrote PlaceDB: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4872 ; free virtual = 13262
+Write Physdb Complete: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3664.676 ; gain = 0.000 ; free physical = 4871 ; free virtual = 13262
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc_routed.dcp' has been generated.
+Command: write_bitstream -force audioProc.bit -bin_file
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+WARNING: [DRC PDRC-153] Gated clock check: Net leftFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin leftFir/firUnit_1/controlUnit_1/__2/i_/O, cell leftFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+WARNING: [DRC PDRC-153] Gated clock check: Net rightFir/firUnit_1/controlUnit_1/SR_futurState is a gated clock net sourced by a combinational pin rightFir/firUnit_1/controlUnit_1/__2/i_/O, cell rightFir/firUnit_1/controlUnit_1/__2/i_. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./audioProc.bit...
+Writing bitstream ./audioProc.bin...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+130 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3915.500 ; gain = 250.824 ; free physical = 4561 ; free virtual = 12964
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 11:42:01 2025...
diff --git a/proj/AudioProc.runs/impl_1/runme.sh b/proj/AudioProc.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..2a1a86113e62988e4667c60c0196a3b1b654e939
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log audioProc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+
+
diff --git a/proj/AudioProc.runs/impl_1/vivado.jou b/proj/AudioProc.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..63c35e6f3b7f26ac1bc586679ec036762daf64fb
--- /dev/null
+++ b/proj/AudioProc.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 11:38:26 2025
+# Process ID: 34927
+# Current directory: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1
+# Command line: vivado -log audioProc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source audioProc.tcl -notrace
+# Log file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/audioProc.vdi
+# Journal file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-608
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :1499.709 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :16357 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/impl_1/vivado.pb b/proj/AudioProc.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e798a57237af6c3a6ff5119fc5938ba3aee7d799
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/vivado.pb differ
diff --git a/proj/AudioProc.runs/impl_1/write_bitstream.pb b/proj/AudioProc.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..af6f2d2b212f9e43b03052342370831391961344
Binary files /dev/null and b/proj/AudioProc.runs/impl_1/write_bitstream.pb differ
diff --git a/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst b/proj/AudioProc.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc b/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..29b1462b91803ad57a5a4328b646e44102ea4d38
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.Xil/audioProc_propImpl.xdc
@@ -0,0 +1,51 @@
+set_property SRC_FILE_INFO {cfile:/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc rfile:../../../../src/constraints/NexysVideo_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports { led3 }];#[get_ports {LED[3]}]
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports { led4 }];#[get_ports {LED[4]}]
+set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports { led5 }];#[get_ports {LED[5]}]
+set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports { led6 }];#[get_ports {LED[6]}]
+set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports { led7 }];#[get_ports {LED[7]}]
+set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports BTNC]
+set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports BTND]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports BTNL]
+set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports BTNR]
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports BTNU]
+set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports rstn]
+set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports sw]
+set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports { sw3 }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports { sw4 }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports { sw5 }]; #IO_0_15 Sch=sw[5]
+set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { sw6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { sw7 }]; #IO_25_15 Sch=sw[7]
+set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ac_adc_sdata]
+set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ac_bclk]
+set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ac_dac_sdata]
+set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ac_lrclk]
+set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ac_mclk]
+set_property src_info {type:XDC file:1 line:202 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports scl]
+set_property src_info {type:XDC file:1 line:203 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports sda]
diff --git a/proj/AudioProc.runs/synth_1/.vivado.begin.rst b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3ca2a5ef4f35c6928a1f9d1e611defd80de238f5
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="l23debac" Host="fl-tp-br-608" Pid="33948" HostCore="12" HostMemory="16081428">
+ </Process>
+</ProcessHandle>
diff --git a/proj/AudioProc.runs/synth_1/.vivado.end.rst b/proj/AudioProc.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.js b/proj/AudioProc.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/proj/AudioProc.runs/synth_1/ISEWrap.sh b/proj/AudioProc.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/proj/AudioProc.runs/synth_1/__synthesis_is_complete__ b/proj/AudioProc.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.runs/synth_1/audioProc.dcp b/proj/AudioProc.runs/synth_1/audioProc.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..788be83a419baaf89f4af00aca817c30264d745d
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/audioProc.dcp differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc.tcl b/proj/AudioProc.runs/synth_1/audioProc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2bd2b27a164c3869b0f92d8aa76f553f0f00aea0
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc.tcl
@@ -0,0 +1,129 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/audioProc.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a200tsbg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.cache/wt [current_project]
+set_property parent.project_path /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_repo_paths /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/repo [current_project]
+update_ip_catalog
+set_property ip_output_repo /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_verilog -library xil_defaultlib {
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/debounce.v
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v
+}
+read_vhdl -library xil_defaultlib {
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd
+ /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/i2s_ctl.vhd
+}
+read_ip -quiet /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc
+set_property used_in_implementation false [get_files /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+
+read_xdc dont_touch.xdc
+set_property used_in_implementation false [get_files dont_touch.xdc]
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef audioProc.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/proj/AudioProc.runs/synth_1/audioProc.vds b/proj/AudioProc.runs/synth_1/audioProc.vds
new file mode 100644
index 0000000000000000000000000000000000000000..c5e3fe16ff6762e6154ab7ee3f146b390f0462a8
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc.vds
@@ -0,0 +1,758 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 11:36:46 2025
+# Process ID: 34020
+# Current directory: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1
+# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+# Log file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/audioProc.vds
+# Journal file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-608
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4377.582 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :16340 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.613 ; gain = 326.840 ; free physical = 6668 ; free virtual = 14973
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+WARNING: [Vivado_Tcl 4-393] The 'Implementation' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+INFO: [IP_Flow 19-2162] IP 'clk_wiz_0' is locked:
+* IP definition 'Clocking Wizard (5.2)' for IP 'clk_wiz_0' (customized with software release 2015.3) has a newer major version in the IP Catalog.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 34628
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2500.789 ; gain = 419.492 ; free physical = 5505 ; free virtual = 13838
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:13]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/.Xil/Vivado-34020-fl-tp-br-608/realtime/clk_wiz_0_stub.vhdl:18]
+WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:85]
+WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:85]
+INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:24]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:51]
+INFO: [Synth 8-638] synthesizing module 'TWICtl' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:330]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:363]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:381]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:399]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:417]
+INFO: [Synth 8-256] done synthesizing module 'TWICtl' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:151]
+INFO: [Synth 8-6155] done synthesizing module 'audio_init' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:24]
+INFO: [Synth 8-6157] synthesizing module 'debounce' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/debounce.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'debounce' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/debounce.v:23]
+INFO: [Synth 8-638] synthesizing module 'i2s_ctl' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-256] done synthesizing module 'i2s_ctl' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'fir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:28]
+ Parameter dwidth bound to: 24 - type: integer
+ Parameter ntaps bound to: 16 - type: integer
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-6157] synthesizing module 'operativeUnit' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:16]
+INFO: [Synth 8-6157] synthesizing module 'GND' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
+INFO: [Synth 8-6155] done synthesizing module 'GND' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6157] synthesizing module 'OBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
+INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
+INFO: [Synth 8-6157] synthesizing module 'LUT3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b10000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b0110
+INFO: [Synth 8-6155] done synthesizing module 'LUT2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b01111000
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0111111110000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01111111111111111000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0111111111111111111111111111111110000000000000000000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b1000
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b1110
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b1001
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b1000011101111000
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b1110000100011110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0110100110011001
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b10010110
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b00010111
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0110100110010110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0001011111101000111010000001011111101000000101110001011111101000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11110101111111010111111101011111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01010101011111010111110101010101
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11111111011111010111110111111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1111111111110101010111111111111111011101111101010101111101110111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11111101110111010111011101111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1101110111000000000000110111011111111111111111111111111111111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0011001100111010101011001100110000100010000010101010000010001000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11010011001011000110000001100000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00101100110100111001111110011111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0001001101000000000000011100010000000000000000000000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b01110001
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1100111000111111111111001011001111011101011111111111110101110111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1000000101110001111111000000110000011110111011100011110011001100
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0101010000101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0111001001001110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0110000000000110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1010111110100000110011111100111110101111101000001100000011000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'FDCE' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
+ Parameter INIT bound to: 1'b0
+INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
+INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
+INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
+WARNING: [Synth 8-7071] port 'O' of module 'CARRY4' is unconnected for instance 'SR_Y_reg[4]_i_9' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1283]
+WARNING: [Synth 8-7023] instance 'SR_Y_reg[4]_i_9' of module 'CARRY4' has 6 connections declared, but only 5 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1283]
+WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1322]
+WARNING: [Synth 8-689] width (2) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1325]
+WARNING: [Synth 8-689] width (2) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1329]
+WARNING: [Synth 8-689] width (3) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1332]
+INFO: [Synth 8-6157] synthesizing module 'MUXF8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
+INFO: [Synth 8-6155] done synthesizing module 'MUXF8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
+INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
+INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
+WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1386]
+WARNING: [Synth 8-689] width (2) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1403]
+WARNING: [Synth 8-689] width (3) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1406]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b0001
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b00000110
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0000000001101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00000000000000000110101010101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b00010010
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81887]
+ Parameter INIT bound to: 2'b01
+INFO: [Synth 8-6155] done synthesizing module 'LUT1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81887]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01110010010011100000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized9' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0000001000100010100010001000000011111101110111010111011101111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized9' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized10' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1100111011010010100001111011001111111101110111010111011101111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized10' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized11' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0001000100111010101011000100010000100010000010101010000010001000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized11' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00000010100010101010001010000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b01101001
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized12' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1001101101001010101000011110011010101000100010101010001000101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized12' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized9' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01100000000001100000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized9' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized13' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0110011010010110100101101001011001100110011001100110011001100110
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized13' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized14' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1001011010101010101010101001011010101010101010101010101010101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized14' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized15' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1111011111000001010000111101111100001000000000101000000000100000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized15' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized10' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00000000100000101000001000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized10' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b1111100110011111
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized9' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0101100000011010
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized9' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b0010
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized10' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0000100100000110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized10' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+WARNING: [Synth 8-689] width (2) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:3161]
+WARNING: [Synth 8-689] width (3) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:3164]
+INFO: [Synth 8-6157] synthesizing module 'VCC' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
+INFO: [Synth 8-6155] done synthesizing module 'VCC' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
+INFO: [Synth 8-6155] done synthesizing module 'operativeUnit' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:16]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:28]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7023] instance 'leftFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7023] instance 'rightFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+INFO: [Synth 8-6155] done synthesizing module 'audioProc' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:13]
+WARNING: [Synth 8-6014] Unused sequential element timeOutCnt_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:236]
+WARNING: [Synth 8-6014] Unused sequential element errTypeR_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:313]
+WARNING: [Synth 8-6014] Unused sequential element regData1_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:135]
+WARNING: [Synth 8-6014] Unused sequential element initFbWe_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:150]
+WARNING: [Synth 8-3848] Net O_FilteredSampleValid in module/entity controlUnit does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:39]
+WARNING: [Synth 8-3848] Net dbg_output_0 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:18]
+WARNING: [Synth 8-3848] Net dbg_output_1 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:19]
+WARNING: [Synth 8-3848] Net dbg_output_2 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:20]
+WARNING: [Synth 8-3848] Net dbg_output_3 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:21]
+WARNING: [Synth 8-3848] Net dbg_output_4 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:22]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataL_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:225]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataR_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:226]
+WARNING: [Synth 8-7129] Port O_FilteredSampleValid in module controlUnit is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2588.758 ; gain = 507.461 ; free physical = 5385 ; free virtual = 13722
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2606.570 ; gain = 525.273 ; free physical = 5385 ; free virtual = 13722
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2606.570 ; gain = 525.273 ; free physical = 5385 ; free virtual = 13722
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2612.508 ; gain = 0.000 ; free physical = 5378 ; free virtual = 13714
+INFO: [Netlist 29-17] Analyzing 82 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/audioProc_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/audioProc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2754.320 ; gain = 0.000 ; free physical = 5361 ; free virtual = 13711
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2754.320 ; gain = 0.000 ; free physical = 5361 ; free virtual = 13712
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2754.320 ; gain = 673.023 ; free physical = 5358 ; free virtual = 13717
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5358 ; free virtual = 13717
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
+Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5358 ; free virtual = 13717
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ stidle | 0001 | 0000
+ ststart | 0100 | 0001
+ stwrite | 0000 | 0011
+ stsack | 0011 | 0110
+ stread | 0010 | 0010
+ stmnackstart | 0110 | 1001
+ stmack | 0111 | 0111
+ stmnackstop | 0101 | 1000
+ ststop | 1100 | 0101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'gray' in module 'TWICtl'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00001 | 000
+ store | 00010 | 001
+ processing_loop | 00100 | 010
+ output | 01000 | 011
+ wait_end_sample | 10000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:57]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5369 ; free virtual = 13721
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 32 Bit Adders := 1
+ 2 Input 31 Bit Adders := 1
+ 2 Input 13 Bit Adders := 5
+ 2 Input 8 Bit Adders := 2
+ 2 Input 7 Bit Adders := 5
+ 2 Input 6 Bit Adders := 2
+ 2 Input 5 Bit Adders := 4
+ 2 Input 4 Bit Adders := 3
+ 2 Input 3 Bit Adders := 3
+ 2 Input 2 Bit Adders := 3
++---Registers :
+ 33 Bit Registers := 1
+ 32 Bit Registers := 3
+ 31 Bit Registers := 1
+ 24 Bit Registers := 2
+ 13 Bit Registers := 5
+ 8 Bit Registers := 3
+ 7 Bit Registers := 3
+ 5 Bit Registers := 4
+ 4 Bit Registers := 2
+ 3 Bit Registers := 1
+ 2 Bit Registers := 2
+ 1 Bit Registers := 18
++---Muxes :
+ 2 Input 32 Bit Muxes := 3
+ 2 Input 24 Bit Muxes := 2
+ 2 Input 8 Bit Muxes := 16
+ 2 Input 5 Bit Muxes := 9
+ 8 Input 5 Bit Muxes := 1
+ 5 Input 5 Bit Muxes := 2
+ 9 Input 4 Bit Muxes := 1
+ 21 Input 4 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 7
+ 5 Input 3 Bit Muxes := 2
+ 3 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 39
+ 4 Input 1 Bit Muxes := 21
+ 3 Input 1 Bit Muxes := 5
+ 9 Input 1 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 6
+ 36 Input 1 Bit Muxes := 1
+ 5 Input 1 Bit Muxes := 4
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:22 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5356 ; free virtual = 13715
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5347 ; free virtual = 13713
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5347 ; free virtual = 13713
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5347 ; free virtual = 13713
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |clk_wiz | 1|
+|2 |BUFG | 2|
+|3 |CARRY4 | 46|
+|4 |LUT1 | 43|
+|5 |LUT2 | 113|
+|6 |LUT3 | 95|
+|7 |LUT4 | 74|
+|8 |LUT5 | 95|
+|9 |LUT6 | 237|
+|10 |MUXF7 | 34|
+|11 |MUXF8 | 16|
+|12 |FDCE | 318|
+|13 |FDPE | 2|
+|14 |FDRE | 239|
+|15 |FDSE | 20|
+|16 |LD | 10|
+|17 |IBUF | 40|
+|18 |IOBUF | 2|
+|19 |OBUF | 27|
++------+--------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 1 critical warnings and 39 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2762.324 ; gain = 533.277 ; free physical = 5350 ; free virtual = 13716
+Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.332 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2762.332 ; gain = 0.000 ; free physical = 5666 ; free virtual = 14032
+INFO: [Netlist 29-17] Analyzing 108 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadY_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadY_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[0]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[1]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[2]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[3]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[4]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[5]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[6]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[7]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[0]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[1]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[2]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[3]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[4]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[5]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[6]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[7]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2818.352 ; gain = 0.000 ; free physical = 5668 ; free virtual = 14034
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 12 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+ LD => LDCE: 10 instances
+
+Synth Design complete | Checksum: 19d5df0d
+INFO: [Common 17-83] Releasing license: Synthesis
+182 Infos, 167 Warnings, 1 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:48 . Memory (MB): peak = 2818.352 ; gain = 1124.863 ; free physical = 5668 ; free virtual = 14034
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2291.419; main = 1922.301; forked = 418.619
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3867.035; main = 2818.355; forked = 1104.707
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.363 ; gain = 0.000 ; free physical = 5668 ; free virtual = 14034
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 11:38:21 2025...
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e762cfca3ddc249bd14f0c89af4dc9b719530c19
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.pb differ
diff --git a/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c08b4e0bf0ca79313728e171fe19ce9b504b9868
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/audioProc_utilization_synth.rpt
@@ -0,0 +1,193 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 26 11:38:21 2025
+| Host : fl-tp-br-608 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+| Design : audioProc
+| Device : xc7a200tsbg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 591 | 0 | 0 | 134600 | 0.44 |
+| LUT as Logic | 591 | 0 | 0 | 134600 | 0.44 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 589 | 0 | 0 | 269200 | 0.22 |
+| Register as Flip Flop | 579 | 0 | 0 | 269200 | 0.22 |
+| Register as Latch | 10 | 0 | 0 | 269200 | <0.01 |
+| F7 Muxes | 34 | 0 | 0 | 67300 | 0.05 |
+| F8 Muxes | 16 | 0 | 0 | 33650 | 0.05 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 328 | Yes | - | Reset |
+| 20 | Yes | Set | - |
+| 239 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 19 | 0 | 0 | 285 | 6.67 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 318 | Flop & Latch |
+| FDRE | 239 | Flop & Latch |
+| LUT6 | 237 | LUT |
+| LUT2 | 113 | LUT |
+| LUT5 | 95 | LUT |
+| LUT3 | 95 | LUT |
+| LUT4 | 74 | LUT |
+| CARRY4 | 46 | CarryLogic |
+| LUT1 | 43 | LUT |
+| MUXF7 | 34 | MuxFx |
+| FDSE | 20 | Flop & Latch |
+| MUXF8 | 16 | MuxFx |
+| LDCE | 10 | Flop & Latch |
+| IBUF | 10 | IO |
+| OBUF | 9 | IO |
+| OBUFT | 2 | IO |
+| FDPE | 2 | Flop & Latch |
+| BUFG | 2 | Clock |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/proj/AudioProc.runs/synth_1/dont_touch.xdc b/proj/AudioProc.runs/synth_1/dont_touch.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..22203023094b7e6d7261fb5317cc2793ad7e6db6
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/dont_touch.xdc
@@ -0,0 +1,7 @@
+# This file is automatically generated.
+# It contains project source information necessary for synthesis and implementation.
+
+# XDC: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc
+
+# IP: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==clk_wiz_0 || ORIG_REF_NAME==clk_wiz_0} -quiet] -quiet
diff --git a/proj/AudioProc.runs/synth_1/gen_run.xml b/proj/AudioProc.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ff296837712eb82b20f51b34f44b5a1a7cc053f0
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/gen_run.xml
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1740566203">
+ <File Type="VDS-TIMINGSUMMARY" Name="audioProc_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="audioProc.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="audioProc_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="audioProc_utilization_synth.rpt"/>
+ <File Type="VDS-TIMING-PB" Name="audioProc_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="audioProc.tcl"/>
+ <File Type="REPORTS-TCL" Name="audioProc_reports.tcl"/>
+ <File Type="RDS-RDS" Name="audioProc.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="audioProc_drc_synth.rpt"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UserDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
+ <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
+ </StratHandle>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+</GenRun>
diff --git a/proj/AudioProc.runs/synth_1/htr.txt b/proj/AudioProc.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6eaa206564a408917c3a3780eaa04c938f0a3fb9
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
diff --git a/proj/AudioProc.runs/synth_1/rundef.js b/proj/AudioProc.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..aff081c0d785dcdfe807351ed4a33a8d2902062e
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/proj/AudioProc.runs/synth_1/runme.bat b/proj/AudioProc.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/proj/AudioProc.runs/synth_1/runme.log b/proj/AudioProc.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..cf8e52c61199a9f878ac4bed09fc33076cc212bb
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.log
@@ -0,0 +1,748 @@
+
+*** Running vivado
+ with args -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 26 11:36:46 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source audioProc.tcl -notrace
+create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:24 . Memory (MB): peak = 1680.613 ; gain = 326.840 ; free physical = 6668 ; free virtual = 14973
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/repo'; Can't find the specified path.
+If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
+Command: synth_design -top audioProc -part xc7a200tsbg484-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
+Starting synth_design
+WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+WARNING: [Vivado_Tcl 4-393] The 'Implementation' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design.
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0.xci
+
+INFO: [IP_Flow 19-2162] IP 'clk_wiz_0' is locked:
+* IP definition 'Clocking Wizard (5.2)' for IP 'clk_wiz_0' (customized with software release 2015.3) has a newer major version in the IP Catalog.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 34628
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2500.789 ; gain = 419.492 ; free physical = 5505 ; free virtual = 13838
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'audioProc' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:13]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/.Xil/Vivado-34020-fl-tp-br-608/realtime/clk_wiz_0_stub.vhdl:18]
+WARNING: [Synth 8-7071] port 'reset' of module 'clk_wiz_0' is unconnected for instance 'clk_1' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:85]
+WARNING: [Synth 8-7023] instance 'clk_1' of module 'clk_wiz_0' has 7 connections declared, but only 6 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:85]
+INFO: [Synth 8-6157] synthesizing module 'audio_init' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:24]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:51]
+INFO: [Synth 8-638] synthesizing module 'TWICtl' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:330]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:363]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:381]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:399]
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:417]
+INFO: [Synth 8-256] done synthesizing module 'TWICtl' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:119]
+INFO: [Synth 8-155] case statement is not full and has no default [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:151]
+INFO: [Synth 8-6155] done synthesizing module 'audio_init' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:24]
+INFO: [Synth 8-6157] synthesizing module 'debounce' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/debounce.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'debounce' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/debounce.v:23]
+INFO: [Synth 8-638] synthesizing module 'i2s_ctl' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-256] done synthesizing module 'i2s_ctl' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/i2s_ctl.vhd:63]
+INFO: [Synth 8-638] synthesizing module 'fir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:28]
+ Parameter dwidth bound to: 24 - type: integer
+ Parameter ntaps bound to: 16 - type: integer
+INFO: [Synth 8-226] default block is never used [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'firUnit' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-638] synthesizing module 'controlUnit' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-256] done synthesizing module 'controlUnit' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:43]
+INFO: [Synth 8-6157] synthesizing module 'operativeUnit' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:16]
+INFO: [Synth 8-6157] synthesizing module 'GND' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
+INFO: [Synth 8-6155] done synthesizing module 'GND' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:41993]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951]
+INFO: [Synth 8-6157] synthesizing module 'IBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643]
+INFO: [Synth 8-6157] synthesizing module 'OBUF' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
+INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458]
+INFO: [Synth 8-6157] synthesizing module 'LUT3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b10000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b0110
+INFO: [Synth 8-6155] done synthesizing module 'LUT2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b01111000
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0111111110000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01111111111111111000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0111111111111111111111111111111110000000000000000000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b1000
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b1110
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b1001
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b1000011101111000
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b1110000100011110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0110100110011001
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b10010110
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b00010111
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0110100110010110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0001011111101000111010000001011111101000000101110001011111101000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized0' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11110101111111010111111101011111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized0' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01010101011111010111110101010101
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11111111011111010111110111111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1111111111110101010111111111111111011101111101010101111101110111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11111101110111010111011101111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized2' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1101110111000000000000110111011111111111111111111111111111111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized2' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0011001100111010101011001100110000100010000010101010000010001000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b11010011001011000110000001100000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00101100110100111001111110011111
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0001001101000000000000011100010000000000000000000000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b01110001
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1100111000111111111111001011001111011101011111111111110101110111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1000000101110001111111000000110000011110111011100011110011001100
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0101010000101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0111001001001110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0110000000000110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1010111110100000110011111100111110101111101000001100000011000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'FDCE' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
+ Parameter INIT bound to: 1'b0
+INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:40798]
+INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
+INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2367]
+WARNING: [Synth 8-7071] port 'O' of module 'CARRY4' is unconnected for instance 'SR_Y_reg[4]_i_9' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1283]
+WARNING: [Synth 8-7023] instance 'SR_Y_reg[4]_i_9' of module 'CARRY4' has 6 connections declared, but only 5 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1283]
+WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1322]
+WARNING: [Synth 8-689] width (2) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1325]
+WARNING: [Synth 8-689] width (2) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1329]
+WARNING: [Synth 8-689] width (3) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1332]
+INFO: [Synth 8-6157] synthesizing module 'MUXF8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
+INFO: [Synth 8-6155] done synthesizing module 'MUXF8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88674]
+INFO: [Synth 8-6157] synthesizing module 'MUXF7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
+INFO: [Synth 8-6155] done synthesizing module 'MUXF7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:88637]
+WARNING: [Synth 8-689] width (3) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1386]
+WARNING: [Synth 8-689] width (2) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1403]
+WARNING: [Synth 8-689] width (3) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1406]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized3' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b0001
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized3' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b00000110
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0000000001101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00000000000000000110101010101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized5' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b00010010
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized5' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT1' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81887]
+ Parameter INIT bound to: 2'b01
+INFO: [Synth 8-6155] done synthesizing module 'LUT1' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81887]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized7' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01110010010011100000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized7' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized9' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0000001000100010100010001000000011111101110111010111011101111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized9' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized10' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1100111011010010100001111011001111111101110111010111011101111111
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized10' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized11' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0001000100111010101011000100010000100010000010101010000010001000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized11' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00000010100010101010001010000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT3__parameterized6' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+ Parameter INIT bound to: 8'b01101001
+INFO: [Synth 8-6155] done synthesizing module 'LUT3__parameterized6' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81959]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized12' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1001101101001010101000011110011010101000100010101010001000101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized12' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized9' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b01100000000001100000000000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized9' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized13' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b0110011010010110100101101001011001100110011001100110011001100110
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized13' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized14' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1001011010101010101010101001011010101010101010101010101010101010
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized14' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT6__parameterized15' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+ Parameter INIT bound to: 64'b1111011111000001010000111101111100001000000000101000000000100000
+INFO: [Synth 8-6155] done synthesizing module 'LUT6__parameterized15' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82097]
+INFO: [Synth 8-6157] synthesizing module 'LUT5__parameterized10' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+ Parameter INIT bound to: 32'b00000000100000101000001000000000
+INFO: [Synth 8-6155] done synthesizing module 'LUT5__parameterized10' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82047]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized8' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b1111100110011111
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized8' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized9' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0101100000011010
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized9' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+INFO: [Synth 8-6157] synthesizing module 'LUT2__parameterized4' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+ Parameter INIT bound to: 4'b0010
+INFO: [Synth 8-6155] done synthesizing module 'LUT2__parameterized4' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:81921]
+INFO: [Synth 8-6157] synthesizing module 'LUT4__parameterized10' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+ Parameter INIT bound to: 16'b0000100100000110
+INFO: [Synth 8-6155] done synthesizing module 'LUT4__parameterized10' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82001]
+WARNING: [Synth 8-689] width (2) of port connection 'CO' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:3161]
+WARNING: [Synth 8-689] width (3) of port connection 'O' does not match port width (4) of module 'CARRY4' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:3164]
+INFO: [Synth 8-6157] synthesizing module 'VCC' [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
+INFO: [Synth 8-6155] done synthesizing module 'VCC' (0#1) [/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/scripts/rt/data/unisim_comp.v:140953]
+INFO: [Synth 8-6155] done synthesizing module 'operativeUnit' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:16]
+INFO: [Synth 8-256] done synthesizing module 'firUnit' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd:39]
+INFO: [Synth 8-256] done synthesizing module 'fir' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:28]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'leftFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7023] instance 'leftFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:195]
+WARNING: [Synth 8-7071] port 'dbg_output_0' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_1' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_2' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_3' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7071] port 'dbg_output_4' of module 'fir' is unconnected for instance 'rightFir' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+WARNING: [Synth 8-7023] instance 'rightFir' of module 'fir' has 11 connections declared, but only 6 given [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:204]
+INFO: [Synth 8-6155] done synthesizing module 'audioProc' (0#1) [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:13]
+WARNING: [Synth 8-6014] Unused sequential element timeOutCnt_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:236]
+WARNING: [Synth 8-6014] Unused sequential element errTypeR_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/TWICtl.vhd:313]
+WARNING: [Synth 8-6014] Unused sequential element regData1_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:135]
+WARNING: [Synth 8-6014] Unused sequential element initFbWe_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audio_init.v:150]
+WARNING: [Synth 8-3848] Net O_FilteredSampleValid in module/entity controlUnit does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:39]
+WARNING: [Synth 8-3848] Net dbg_output_0 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:18]
+WARNING: [Synth 8-3848] Net dbg_output_1 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:19]
+WARNING: [Synth 8-3848] Net dbg_output_2 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:20]
+WARNING: [Synth 8-3848] Net dbg_output_3 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:21]
+WARNING: [Synth 8-3848] Net dbg_output_4 in module/entity fir does not have driver. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/fir.vhd:22]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataL_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:225]
+WARNING: [Synth 8-6014] Unused sequential element sound_dataR_reg was removed. [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/audioProc.v:226]
+WARNING: [Synth 8-7129] Port O_FilteredSampleValid in module controlUnit is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2588.758 ; gain = 507.461 ; free physical = 5385 ; free virtual = 13722
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2606.570 ; gain = 525.273 ; free physical = 5385 ; free virtual = 13722
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2606.570 ; gain = 525.273 ; free physical = 5385 ; free virtual = 13722
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2612.508 ; gain = 0.000 ; free physical = 5378 ; free virtual = 13714
+INFO: [Netlist 29-17] Analyzing 82 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'clk_1'
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/constraints/NexysVideo_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/audioProc_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/audioProc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2754.320 ; gain = 0.000 ; free physical = 5361 ; free virtual = 13711
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2754.320 ; gain = 0.000 ; free physical = 5361 ; free virtual = 13712
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2754.320 ; gain = 673.023 ; free physical = 5358 ; free virtual = 13717
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tsbg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5358 ; free virtual = 13717
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for CLK100MHZ. (constraint file /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 6).
+Applied set_property KEEP_HIERARCHY = SOFT for clk_1. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5358 ; free virtual = 13717
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'TWICtl'
+INFO: [Synth 8-802] inferred FSM for state register 'SR_presentState_reg' in module 'controlUnit'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ stidle | 0001 | 0000
+ ststart | 0100 | 0001
+ stwrite | 0000 | 0011
+ stsack | 0011 | 0110
+ stread | 0010 | 0010
+ stmnackstart | 0110 | 1001
+ stmack | 0111 | 0111
+ stmnackstop | 0101 | 1000
+ ststop | 1100 | 0101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'gray' in module 'TWICtl'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ wait_sample | 00001 | 000
+ store | 00010 | 001
+ processing_loop | 00100 | 010
+ output | 01000 | 011
+ wait_end_sample | 10000 | 100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_presentState_reg' using encoding 'one-hot' in module 'controlUnit'
+WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_SR_futurState_reg' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd:57]
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5369 ; free virtual = 13721
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 32 Bit Adders := 1
+ 2 Input 31 Bit Adders := 1
+ 2 Input 13 Bit Adders := 5
+ 2 Input 8 Bit Adders := 2
+ 2 Input 7 Bit Adders := 5
+ 2 Input 6 Bit Adders := 2
+ 2 Input 5 Bit Adders := 4
+ 2 Input 4 Bit Adders := 3
+ 2 Input 3 Bit Adders := 3
+ 2 Input 2 Bit Adders := 3
++---Registers :
+ 33 Bit Registers := 1
+ 32 Bit Registers := 3
+ 31 Bit Registers := 1
+ 24 Bit Registers := 2
+ 13 Bit Registers := 5
+ 8 Bit Registers := 3
+ 7 Bit Registers := 3
+ 5 Bit Registers := 4
+ 4 Bit Registers := 2
+ 3 Bit Registers := 1
+ 2 Bit Registers := 2
+ 1 Bit Registers := 18
++---Muxes :
+ 2 Input 32 Bit Muxes := 3
+ 2 Input 24 Bit Muxes := 2
+ 2 Input 8 Bit Muxes := 16
+ 2 Input 5 Bit Muxes := 9
+ 8 Input 5 Bit Muxes := 1
+ 5 Input 5 Bit Muxes := 2
+ 9 Input 4 Bit Muxes := 1
+ 21 Input 4 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 7
+ 5 Input 3 Bit Muxes := 2
+ 3 Input 2 Bit Muxes := 1
+ 2 Input 1 Bit Muxes := 39
+ 4 Input 1 Bit Muxes := 21
+ 3 Input 1 Bit Muxes := 5
+ 9 Input 1 Bit Muxes := 1
+ 10 Input 1 Bit Muxes := 6
+ 36 Input 1 Bit Muxes := 1
+ 5 Input 1 Bit Muxes := 4
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-7129] Port dbg_output_0[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_0[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_1[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_2 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_3 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port dbg_output_4 in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[15] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[14] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[13] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[12] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[11] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[10] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[9] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[8] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[7] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[6] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[5] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[4] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[3] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[2] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[1] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port din[0] in module fir is either unconnected or has no load
+WARNING: [Synth 8-7129] Port MM_I in module i2s_ctl is either unconnected or has no load
+WARNING: [Synth 8-7129] Port sw in module audioProc is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:22 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5356 ; free virtual = 13715
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5347 ; free virtual = 13713
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5347 ; free virtual = 13713
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5347 ; free virtual = 13713
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+WARNING: synth_design option "-fanout_limit" is deprecated.
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+CRITICAL WARNING: [Synth 8-4442] BlackBox module clk_1 has unconnected pin reset
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+--------+------+
+| |Cell |Count |
++------+--------+------+
+|1 |clk_wiz | 1|
+|2 |BUFG | 2|
+|3 |CARRY4 | 46|
+|4 |LUT1 | 43|
+|5 |LUT2 | 113|
+|6 |LUT3 | 95|
+|7 |LUT4 | 74|
+|8 |LUT5 | 95|
+|9 |LUT6 | 237|
+|10 |MUXF7 | 34|
+|11 |MUXF8 | 16|
+|12 |FDCE | 318|
+|13 |FDPE | 2|
+|14 |FDRE | 239|
+|15 |FDSE | 20|
+|16 |LD | 10|
+|17 |IBUF | 40|
+|18 |IOBUF | 2|
+|19 |OBUF | 27|
++------+--------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.324 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 1 critical warnings and 39 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2762.324 ; gain = 533.277 ; free physical = 5350 ; free virtual = 13716
+Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2762.332 ; gain = 681.027 ; free physical = 5350 ; free virtual = 13716
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2762.332 ; gain = 0.000 ; free physical = 5666 ; free virtual = 14032
+INFO: [Netlist 29-17] Analyzing 108 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_loadY_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. leftFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_clock_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_incrAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initAddress_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_initSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[0]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[1]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[2]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[3]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[4]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[5]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[6]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_inputSample_IBUF[7]_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadShift_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadSum_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_loadY_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. rightFir/firUnit_1/operativeUnit_1/I_reset_IBUF_inst
+Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[0]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[1]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[2]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[3]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[4]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[5]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[6]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_Y_OBUF[7]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. leftFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[0]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[1]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[2]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[3]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[4]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[5]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[6]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_Y_OBUF[7]_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+WARNING: [Opt 31-33] Removing redundant OBUF since it is not driving a top-level port. rightFir/firUnit_1/operativeUnit_1/O_processingDone_OBUF_inst
+Resolution: The tool has removed redundant OBUF. To resolve this warning, check for redundant OBUF in the input design.
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2818.352 ; gain = 0.000 ; free physical = 5668 ; free virtual = 14034
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 12 instances were transformed.
+ IOBUF => IOBUF (IBUF, OBUFT): 2 instances
+ LD => LDCE: 10 instances
+
+Synth Design complete | Checksum: 19d5df0d
+INFO: [Common 17-83] Releasing license: Synthesis
+182 Infos, 167 Warnings, 1 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:48 . Memory (MB): peak = 2818.352 ; gain = 1124.863 ; free physical = 5668 ; free virtual = 14034
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2291.419; main = 1922.301; forked = 418.619
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3867.035; main = 2818.355; forked = 1104.707
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.363 ; gain = 0.000 ; free physical = 5668 ; free virtual = 14034
+INFO: [Common 17-1381] The checkpoint '/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/audioProc.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file audioProc_utilization_synth.rpt -pb audioProc_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 26 11:38:21 2025...
diff --git a/proj/AudioProc.runs/synth_1/runme.sh b/proj/AudioProc.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e0afb9d93ab7e06fe55cfd5f57a923922d29f3ce
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vitis/2024.1/bin:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log audioProc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
diff --git a/proj/AudioProc.runs/synth_1/vivado.jou b/proj/AudioProc.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..f6c01773d46958655bfd615efd2d9b883d2bc222
--- /dev/null
+++ b/proj/AudioProc.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 26 11:36:46 2025
+# Process ID: 34020
+# Current directory: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1
+# Command line: vivado -log audioProc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source audioProc.tcl
+# Log file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/audioProc.vds
+# Journal file: /homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-608
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency :4377.582 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory :16467 MB
+# Swap memory :4294 MB
+# Total Virtual :20762 MB
+# Available Virtual :16340 MB
+#-----------------------------------------------------------
+source audioProc.tcl -notrace
diff --git a/proj/AudioProc.runs/synth_1/vivado.pb b/proj/AudioProc.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..dea0c16a8f73872bb8a066e1a1e11cc54f5b4fac
Binary files /dev/null and b/proj/AudioProc.runs/synth_1/vivado.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3e5b19b052cf38b3fef374879e048ca37106b551
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Feb 26 11:23:23 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj tb_firUnit_vlog.prj"
+xvlog --incr --relax -prj tb_firUnit_vlog.prj 2>&1 | tee compile.log
+
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+xvhdl --incr --relax -prj tb_firUnit_vhdl.prj 2>&1 | tee -a compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000000000000000000000000000000000000..9da6b2e8ec7146b4257abd6b240062d2098dcc53
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,49 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'CO' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1322]
+WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 4 for port 'O' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1325]
+WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 4 for port 'CO' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1329]
+WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'O' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1332]
+WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'CO' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1386]
+WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 4 for port 'CO' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1403]
+WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'O' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:1406]
+WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 4 for port 'CO' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:3161]
+WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 4 for port 'O' [/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v:3164]
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package vl.vl_types
+Compiling module xil_defaultlib.glbl
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling module unisims_ver.GND
+Compiling module unisims_ver.BUFG
+Compiling module unisims_ver.IBUF
+Compiling module unisims_ver.OBUF
+Compiling module unisims_ver.x_lut3_mux8
+Compiling module unisims_ver.LUT3
+Compiling module unisims_ver.x_lut2_mux4
+Compiling module unisims_ver.LUT2
+Compiling module unisims_ver.LUT4
+Compiling module unisims_ver.LUT5
+Compiling module unisims_ver.LUT6
+Compiling module unisims_ver.FDCE_default
+Compiling module unisims_ver.CARRY4
+Compiling module unisims_ver.MUXF8
+Compiling module unisims_ver.MUXF7
+Compiling module unisims_ver.x_lut1_mux2
+Compiling module unisims_ver.LUT1(INIT=2'b01)
+Compiling module unisims_ver.VCC
+Compiling module xil_defaultlib.operativeUnit
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..5b30de44d6c4e4dfcb78e77cfc2e79c1746d2a58
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Feb 26 11:23:28 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl -log elaborate.log
+
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
new file mode 100755
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..2daa52d6956fe55f888f234d222b45907a0784ca
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Feb 26 10:41:42 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..857c621c4866e6f9dd011ead34051eb769ef6570
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..f5164303db8b7813dd76fdb363b7c18c0c679809
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -0,0 +1,8 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/firUnit.vhd" \
+"../../../../../src/hdl/tb_firUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
new file mode 100644
index 0000000000000000000000000000000000000000..234b2fbc3ab1859782a11e7792d1a0108ad6a57b
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/tb_firUnit_vlog.prj
@@ -0,0 +1,9 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib \
+"../../../../../src/hdl/processingUnitIP.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..cb7576b685017f526edfb6860bde4bc45d696a9e
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2965ab3b73825075d89f3fba7755ebff3606c69a
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" "xil_defaultlib.glbl" -log "elaborate.log"
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..aa81763fad689b1d497ed3a4dd379b28a72de795
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..f0349f083611af35e5e9e6d2d52eeec61939cced
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -0,0 +1,571 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_2(char*, char *);
+IKI_DLLESPEC extern void execute_3(char*, char *);
+IKI_DLLESPEC extern void execute_4(char*, char *);
+IKI_DLLESPEC extern void execute_5(char*, char *);
+IKI_DLLESPEC extern void execute_6(char*, char *);
+IKI_DLLESPEC extern void execute_7(char*, char *);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_21(char*, char *);
+IKI_DLLESPEC extern void execute_22(char*, char *);
+IKI_DLLESPEC extern void execute_23(char*, char *);
+IKI_DLLESPEC extern void execute_24(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_29(char*, char *);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_31(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_2776(char*, char *);
+IKI_DLLESPEC extern void execute_2777(char*, char *);
+IKI_DLLESPEC extern void execute_2778(char*, char *);
+IKI_DLLESPEC extern void execute_2779(char*, char *);
+IKI_DLLESPEC extern void execute_2780(char*, char *);
+IKI_DLLESPEC extern void execute_2781(char*, char *);
+IKI_DLLESPEC extern void execute_2782(char*, char *);
+IKI_DLLESPEC extern void execute_2783(char*, char *);
+IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_1389(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_1390(char*, char *);
+IKI_DLLESPEC extern void execute_72(char*, char *);
+IKI_DLLESPEC extern void execute_1406(char*, char *);
+IKI_DLLESPEC extern void execute_1407(char*, char *);
+IKI_DLLESPEC extern void execute_1408(char*, char *);
+IKI_DLLESPEC extern void execute_91(char*, char *);
+IKI_DLLESPEC extern void execute_1434(char*, char *);
+IKI_DLLESPEC extern void execute_1435(char*, char *);
+IKI_DLLESPEC extern void execute_1436(char*, char *);
+IKI_DLLESPEC extern void execute_1437(char*, char *);
+IKI_DLLESPEC extern void execute_1438(char*, char *);
+IKI_DLLESPEC extern void execute_1439(char*, char *);
+IKI_DLLESPEC extern void execute_1440(char*, char *);
+IKI_DLLESPEC extern void execute_1441(char*, char *);
+IKI_DLLESPEC extern void execute_1433(char*, char *);
+IKI_DLLESPEC extern void execute_94(char*, char *);
+IKI_DLLESPEC extern void execute_1443(char*, char *);
+IKI_DLLESPEC extern void execute_1444(char*, char *);
+IKI_DLLESPEC extern void execute_1445(char*, char *);
+IKI_DLLESPEC extern void execute_1446(char*, char *);
+IKI_DLLESPEC extern void execute_1442(char*, char *);
+IKI_DLLESPEC extern void execute_100(char*, char *);
+IKI_DLLESPEC extern void execute_101(char*, char *);
+IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
+IKI_DLLESPEC extern void execute_105(char*, char *);
+IKI_DLLESPEC extern void execute_106(char*, char *);
+IKI_DLLESPEC extern void execute_109(char*, char *);
+IKI_DLLESPEC extern void execute_110(char*, char *);
+IKI_DLLESPEC extern void execute_442(char*, char *);
+IKI_DLLESPEC extern void execute_443(char*, char *);
+IKI_DLLESPEC extern void execute_444(char*, char *);
+IKI_DLLESPEC extern void execute_1705(char*, char *);
+IKI_DLLESPEC extern void execute_1706(char*, char *);
+IKI_DLLESPEC extern void execute_1707(char*, char *);
+IKI_DLLESPEC extern void execute_1708(char*, char *);
+IKI_DLLESPEC extern void execute_1725(char*, char *);
+IKI_DLLESPEC extern void execute_1726(char*, char *);
+IKI_DLLESPEC extern void execute_1727(char*, char *);
+IKI_DLLESPEC extern void execute_1730(char*, char *);
+IKI_DLLESPEC extern void execute_1731(char*, char *);
+IKI_DLLESPEC extern void execute_1732(char*, char *);
+IKI_DLLESPEC extern void execute_1733(char*, char *);
+IKI_DLLESPEC extern void execute_483(char*, char *);
+IKI_DLLESPEC extern void execute_491(char*, char *);
+IKI_DLLESPEC extern void execute_1062(char*, char *);
+IKI_DLLESPEC extern void execute_2412(char*, char *);
+IKI_DLLESPEC extern void execute_2413(char*, char *);
+IKI_DLLESPEC extern void execute_2411(char*, char *);
+IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_49(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_50(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_53(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_55(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_56(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_87(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_88(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_89(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_90(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_91(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_92(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_93(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_94(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_95(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_96(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_97(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_98(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_99(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_100(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_101(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_103(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_116(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_126(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_127(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_128(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_129(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_130(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_131(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_132(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_133(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_134(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_153(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_154(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_156(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_157(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_158(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_159(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_160(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_161(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_162(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_163(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_164(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_166(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_167(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_169(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_176(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_178(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_179(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_182(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_185(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_186(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_189(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_191(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_212(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_213(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_214(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_238(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_239(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_240(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_241(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_242(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_243(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_244(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_245(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_247(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_248(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_249(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_252(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_253(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_337(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_338(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_339(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_340(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_341(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_342(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_343(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_344(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_345(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_346(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_347(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_349(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_350(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_351(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_352(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_354(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_362(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1030(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1036(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1042(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1048(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1054(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1116(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1122(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1128(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1226(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1232(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1238(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1244(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1250(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1256(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1262(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1268(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1274(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1280(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1286(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1292(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1298(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1304(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1310(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1316(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1322(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1328(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1334(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1340(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1346(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1352(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1358(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1364(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1370(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1376(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1382(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1388(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1394(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1400(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1406(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1412(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1418(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1424(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1430(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1436(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1442(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1448(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1454(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1460(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1466(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1472(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1478(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1484(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1490(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1496(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1502(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1508(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1514(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1520(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1526(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1532(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1538(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1544(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1550(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1556(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1562(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1568(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1574(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1580(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1586(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1592(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1598(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1604(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1610(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1616(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1622(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1628(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1634(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1640(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1646(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1652(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1658(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1664(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1670(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1676(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1682(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1688(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1694(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1700(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1706(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1712(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1718(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1724(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1730(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1736(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1742(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1748(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1754(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1760(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1766(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1772(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1778(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1784(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1790(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1796(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1802(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1808(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1814(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1820(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1826(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1832(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1838(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1844(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1850(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1856(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1862(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1868(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1874(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1880(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1886(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1892(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1898(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1904(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1910(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1916(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1922(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1928(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1934(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1940(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1946(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1952(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1958(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1964(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1970(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1976(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1982(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1988(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_1994(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2000(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2006(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2012(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2500(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2548(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2554(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2560(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2574(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2580(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2586(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2592(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2598(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2604(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2620(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2626(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2632(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2638(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_2654(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[438] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_2776, (funcp)execute_2777, (funcp)execute_2778, (funcp)execute_2779, (funcp)execute_2780, (funcp)execute_2781, (funcp)execute_2782, (funcp)execute_2783, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_1389, (funcp)execute_40, (funcp)execute_1390, (funcp)execute_72, (funcp)execute_1406, (funcp)execute_1407, (funcp)execute_1408, (funcp)execute_91, (funcp)execute_1434, (funcp)execute_1435, (funcp)execute_1436, (funcp)execute_1437, (funcp)execute_1438, (funcp)execute_1439, (funcp)execute_1440, (funcp)execute_1441, (funcp)execute_1433, (funcp)execute_94, (funcp)execute_1443, (funcp)execute_1444, (funcp)execute_1445, (funcp)execute_1446, (funcp)execute_1442, (funcp)execute_100, (funcp)execute_101, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_105, (funcp)execute_106, (funcp)execute_109, (funcp)execute_110, (funcp)execute_442, (funcp)execute_443, (funcp)execute_444, (funcp)execute_1705, (funcp)execute_1706, (funcp)execute_1707, (funcp)execute_1708, (funcp)execute_1725, (funcp)execute_1726, (funcp)execute_1727, (funcp)execute_1730, (funcp)execute_1731, (funcp)execute_1732, (funcp)execute_1733, (funcp)execute_483, (funcp)execute_491, (funcp)execute_1062, (funcp)execute_2412, (funcp)execute_2413, (funcp)execute_2411, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_38, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)transaction_46, (funcp)transaction_49, (funcp)transaction_50, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_53, (funcp)transaction_54, (funcp)transaction_55, (funcp)transaction_56, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_72, (funcp)transaction_75, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_87, (funcp)transaction_88, (funcp)transaction_89, (funcp)transaction_90, (funcp)transaction_91, (funcp)transaction_92, (funcp)transaction_93, (funcp)transaction_94, (funcp)transaction_95, (funcp)transaction_96, (funcp)transaction_97, (funcp)transaction_98, (funcp)transaction_99, (funcp)transaction_100, (funcp)transaction_101, (funcp)transaction_102, (funcp)transaction_103, (funcp)transaction_116, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_126, (funcp)transaction_127, (funcp)transaction_128, (funcp)transaction_129, (funcp)transaction_130, (funcp)transaction_131, (funcp)transaction_132, (funcp)transaction_133, (funcp)transaction_134, (funcp)transaction_152, (funcp)transaction_153, (funcp)transaction_154, (funcp)transaction_155, (funcp)transaction_156, (funcp)transaction_157, (funcp)transaction_158, (funcp)transaction_159, (funcp)transaction_160, (funcp)transaction_161, (funcp)transaction_162, (funcp)transaction_163, (funcp)transaction_164, (funcp)transaction_165, (funcp)transaction_166, (funcp)transaction_167, (funcp)transaction_168, (funcp)transaction_169, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_176, (funcp)transaction_177, (funcp)transaction_178, (funcp)transaction_179, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_182, (funcp)transaction_183, (funcp)transaction_184, (funcp)transaction_185, (funcp)transaction_186, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_189, (funcp)transaction_190, (funcp)transaction_191, (funcp)transaction_192, (funcp)transaction_212, (funcp)transaction_213, (funcp)transaction_214, (funcp)transaction_238, (funcp)transaction_239, (funcp)transaction_240, (funcp)transaction_241, (funcp)transaction_242, (funcp)transaction_243, (funcp)transaction_244, (funcp)transaction_245, (funcp)transaction_247, (funcp)transaction_248, (funcp)transaction_249, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_252, (funcp)transaction_253, (funcp)transaction_258, (funcp)transaction_264, (funcp)transaction_275, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_337, (funcp)transaction_338, (funcp)transaction_339, (funcp)transaction_340, (funcp)transaction_341, (funcp)transaction_342, (funcp)transaction_343, (funcp)transaction_344, (funcp)transaction_345, (funcp)transaction_346, (funcp)transaction_347, (funcp)transaction_348, (funcp)transaction_349, (funcp)transaction_350, (funcp)transaction_351, (funcp)transaction_352, (funcp)transaction_354, (funcp)transaction_355, (funcp)transaction_362, (funcp)transaction_1030, (funcp)transaction_1036, (funcp)transaction_1042, (funcp)transaction_1048, (funcp)transaction_1054, (funcp)transaction_1116, (funcp)transaction_1122, (funcp)transaction_1128, (funcp)transaction_1226, (funcp)transaction_1232, (funcp)transaction_1238, (funcp)transaction_1244, (funcp)transaction_1250, (funcp)transaction_1256, (funcp)transaction_1262, (funcp)transaction_1268, (funcp)transaction_1274, (funcp)transaction_1280, (funcp)transaction_1286, (funcp)transaction_1292, (funcp)transaction_1298, (funcp)transaction_1304, (funcp)transaction_1310, (funcp)transaction_1316, (funcp)transaction_1322, (funcp)transaction_1328, (funcp)transaction_1334, (funcp)transaction_1340, (funcp)transaction_1346, (funcp)transaction_1352, (funcp)transaction_1358, (funcp)transaction_1364, (funcp)transaction_1370, (funcp)transaction_1376, (funcp)transaction_1382, (funcp)transaction_1388, (funcp)transaction_1394, (funcp)transaction_1400, (funcp)transaction_1406, (funcp)transaction_1412, (funcp)transaction_1418, (funcp)transaction_1424, (funcp)transaction_1430, (funcp)transaction_1436, (funcp)transaction_1442, (funcp)transaction_1448, (funcp)transaction_1454, (funcp)transaction_1460, (funcp)transaction_1466, (funcp)transaction_1472, (funcp)transaction_1478, (funcp)transaction_1484, (funcp)transaction_1490, (funcp)transaction_1496, (funcp)transaction_1502, (funcp)transaction_1508, (funcp)transaction_1514, (funcp)transaction_1520, (funcp)transaction_1526, (funcp)transaction_1532, (funcp)transaction_1538, (funcp)transaction_1544, (funcp)transaction_1550, (funcp)transaction_1556, (funcp)transaction_1562, (funcp)transaction_1568, (funcp)transaction_1574, (funcp)transaction_1580, (funcp)transaction_1586, (funcp)transaction_1592, (funcp)transaction_1598, (funcp)transaction_1604, (funcp)transaction_1610, (funcp)transaction_1616, (funcp)transaction_1622, (funcp)transaction_1628, (funcp)transaction_1634, (funcp)transaction_1640, (funcp)transaction_1646, (funcp)transaction_1652, (funcp)transaction_1658, (funcp)transaction_1664, (funcp)transaction_1670, (funcp)transaction_1676, (funcp)transaction_1682, (funcp)transaction_1688, (funcp)transaction_1694, (funcp)transaction_1700, (funcp)transaction_1706, (funcp)transaction_1712, (funcp)transaction_1718, (funcp)transaction_1724, (funcp)transaction_1730, (funcp)transaction_1736, (funcp)transaction_1742, (funcp)transaction_1748, (funcp)transaction_1754, (funcp)transaction_1760, (funcp)transaction_1766, (funcp)transaction_1772, (funcp)transaction_1778, (funcp)transaction_1784, (funcp)transaction_1790, (funcp)transaction_1796, (funcp)transaction_1802, (funcp)transaction_1808, (funcp)transaction_1814, (funcp)transaction_1820, (funcp)transaction_1826, (funcp)transaction_1832, (funcp)transaction_1838, (funcp)transaction_1844, (funcp)transaction_1850, (funcp)transaction_1856, (funcp)transaction_1862, (funcp)transaction_1868, (funcp)transaction_1874, (funcp)transaction_1880, (funcp)transaction_1886, (funcp)transaction_1892, (funcp)transaction_1898, (funcp)transaction_1904, (funcp)transaction_1910, (funcp)transaction_1916, (funcp)transaction_1922, (funcp)transaction_1928, (funcp)transaction_1934, (funcp)transaction_1940, (funcp)transaction_1946, (funcp)transaction_1952, (funcp)transaction_1958, (funcp)transaction_1964, (funcp)transaction_1970, (funcp)transaction_1976, (funcp)transaction_1982, (funcp)transaction_1988, (funcp)transaction_1994, (funcp)transaction_2000, (funcp)transaction_2006, (funcp)transaction_2012, (funcp)transaction_2500, (funcp)transaction_2548, (funcp)transaction_2554, (funcp)transaction_2560, (funcp)transaction_2574, (funcp)transaction_2580, (funcp)transaction_2586, (funcp)transaction_2592, (funcp)transaction_2598, (funcp)transaction_2604, (funcp)transaction_2620, (funcp)transaction_2626, (funcp)transaction_2632, (funcp)transaction_2638, (funcp)transaction_2654};
+const int NumRelocateId= 438;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 438);
+ iki_vhdl_file_variable_register(dp + 561640);
+ iki_vhdl_file_variable_register(dp + 561696);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+}
+
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+
+void wrapper_func_0(char *dp)
+
+{
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 566968, dp + 571104, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 567024, dp + 572056, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 567080, dp + 571608, 0, 7, 0, 7, 8, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 568344, dp + 571720, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 568400, dp + 571384, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 568456, dp + 571272, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 568512, dp + 571496, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 568568, dp + 571832, 0, 0, 0, 0, 1, 1);
+
+ iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 568624, dp + 571944, 0, 0, 0, 0, 1, 1);
+
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+ wrapper_func_0(dp);
+
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_firUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_firUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_firUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..0596e4302e52bf05b0363c76641172351ad03f06
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..78d1c504d140bfac69d0820e84d9aec21d5628e7
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..3566057bc2769670b9fdb6be482eded97c3d341a
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..2184d67cd5e91450226e178863069e33b350ade7
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..b07b9ab5e157b2edca83bfc84912441da867c996
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 10509317868776623946 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit xil_defaultlib.glbl" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_firUnit_behav/xsimk\" \"xsim.dir/tb_firUnit_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.lnx64.o\" -L\"/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..3468a3f54f67439a7cec1716348317a7c5072b31
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..57a1c98a5f6d4cad2df1f5c52fb8d6f99ce7db99
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..b6c17a51f0760d7896f3e40ea46dbc6815759bd4
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..13cc75048254588c0324948508f8df58ebacfd3b
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..8e0dcd5e02ff023aabfeff84a9ad7d11b5a42de2
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=dec
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=174
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=103
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=198
+OBJECT_NAME_COLUMN_WIDTH=183
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..a73cb413d468200ab5321bce7da134a22536233f
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..d5a58a9415e87e1e340c103b5749f7a6bd0ee969
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -0,0 +1,4 @@
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 48427
+Design successfully loaded
+Design Loading Memory Usage: 21708 KB (Peak: 21716 KB)
+Design Loading CPU Usage: 60 ms
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..b0e5d6e2461a5a7a22804ccad6988693c7511288
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..7e2f547126f80344240901e4bd245a3d8f5813af
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb
new file mode 100644
index 0000000000000000000000000000000000000000..ebdac3c93edf0ca665a14fd335a932475a1465b9
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operative@unit.sdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operative@unit.sdb
new file mode 100644
index 0000000000000000000000000000000000000000..d4bf79102a5658cd7bf7736748ebeb608aaec6c3
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operative@unit.sdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..6e428673e3f91be45b73f78bc517514fcee8ca79
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..17f661c5f8988062c4611f10b449c0de8ad135e6
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,9 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.sim/sim_1/behav/xsim/glbl.v,1708598507,verilog,,,,glbl,,,,,,,,
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd,1740565399,vhdl,/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd,1740559357,vhdl,/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/processingUnitIP.v,1740559357,verilog,/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd,,,\operativeUnit\,,,,,,,,
+/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/tb_firUnit.vhd,1740559357,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..65c1bae3d8499ab13e863c8b22ed50ca77e3133e
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,490 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak
new file mode 100644
index 0000000000000000000000000000000000000000..65c1bae3d8499ab13e863c8b22ed50ca77e3133e
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -0,0 +1,490 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+axi_epu_v1_0_4=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_4
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+emb_fifo_gen_v1_0_5=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+c_mux_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_9
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+v_smpte_uhdsdi_tx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_4
+cam_v3_0_0=$RDI_DATADIR/xsim/ip/cam_v3_0_0
+microblaze_v11_0_13=$RDI_DATADIR/xsim/ip/microblaze_v11_0_13
+axi_fifo_mm_s_v4_3_3=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_3
+v_hdmi_rx1_v1_0_9=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_9
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+axis_clock_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_32
+psx_vip_v1_0_4=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_4
+g975_efec_i4_v1_0_22=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_22
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+ethernet_1_10_25g_v2_7_15=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_15
+an_lt_v1_0_12=$RDI_DATADIR/xsim/ip/an_lt_v1_0_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+axi_cdma_v4_1_31=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_31
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+mdm_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_2
+axi_uartlite_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_35
+axi_perf_mon_v5_0_33=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_33
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+ibert_lib_v1_0_11=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_11
+axi_datamover_v5_1_33=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_33
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+xbip_dsp48_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_9
+v_axi4s_vid_out_v4_0_18=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_18
+axi_chip2chip_v5_0_22=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_22
+gtwizard_ultrascale_v1_7_18=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_18
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+switch_core_top_v1_0_16=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_16
+vitis_net_p4_v2_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_1_0
+axi_sideband_util_v1_0_15=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_15
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+shell_utils_addr_remap_v1_0_10=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_10
+xbip_addsub_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_9
+dds_compiler_v6_0_25=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_25
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
+fifo_generator_v13_2_10=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_10
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+pcie_axi4lite_tap_v1_0_2=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_2
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+polar_v1_1_4=$RDI_DATADIR/xsim/ip/polar_v1_1_4
+v_tpg_v8_2_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_5
+tcc_encoder_3gpplte_v4_0_19=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_19
+axis_accelerator_adapter_v2_1_18=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_18
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+perf_axi_tg_v1_0_13=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_13
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+axi_pcie_v2_9_11=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_11
+axi_emc_v3_0_31=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_31
+tsn_endpoint_ethernet_mac_block_v1_0_16=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_16
+soft_ecc_proxy_v1_1_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_1
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+axis_broadcaster_v1_1_30=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_30
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+vid_edid_v1_0_2=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_2
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+v_vid_in_axi4s_v5_0_4=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_4
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_frmbuf_wr_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_2
+v_smpte_uhdsdi_rx_v1_0_3=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_3
+mpegtsmux_v1_1_9=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_9
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+v_multi_scaler_v1_2_6=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_6
+x5io_wizard_v1_0_4=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_4
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+sem_ultra_v3_1_26=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_26
+axi_utils_v2_0_9=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_9
+v_tc_v6_2_8=$RDI_DATADIR/xsim/ip/v_tc_v6_2_8
+ieee802d3_clause74_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_18
+jesd204c_v4_2_14=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_14
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+nvme_tc_v3_0_6=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_6
+axi4svideo_bridge_v1_0_18=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_18
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+axi_intc_v4_1_19=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_19
+v_demosaic_v1_1_11=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_11
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+axi_vfifo_ctrl_v2_0_34=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_34
+gmii_to_rgmii_v4_1_14=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_14
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+nvmeha_v1_0_12=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_12
+axi_c2c_v1_0_9=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_9
+ft_prach_v1_2_2=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_2
+v_smpte_uhdsdi_v1_0_11=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_11
+axi_pmon_v1_0_1=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_1
+gtwizard_ultrascale_v1_6_16=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_16
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+displayport_v7_0_24=$RDI_DATADIR/xsim/ip/displayport_v7_0_24
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+v_frmbuf_wr_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_10
+fast_adapter_v1_0_8=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_8
+rst_vip_v1_0_6=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_6
+v_hdmi_phy1_v1_0_12=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_12
+pcie_qdma_mailbox_v1_0_5=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_5
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+v_hdmi_tx1_v1_0_8=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_8
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+v_tpg_v8_1_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_10
+v_hcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+axi_timebase_wdt_v3_0_23=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_23
+floating_point_v7_0_23=$RDI_DATADIR/xsim/ip/floating_point_v7_0_23
+displayport_v9_0_9=$RDI_DATADIR/xsim/ip/displayport_v9_0_9
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+versal_cips_ps_vip_v1_0_9=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_9
+amm_axi_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_17
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+v_gamma_lut_v1_1_11=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_11
+rld3_pl_v1_0_14=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_14
+l_ethernet_v3_3_10=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_10
+ernic_v4_0_3=$RDI_DATADIR/xsim/ip/ernic_v4_0_3
+fec_5g_common_v1_1_4=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_4
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+dfx_bitstream_monitor_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_5
+axi_mmu_v2_1_29=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_29
+v_sdi_rx_vid_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_2
+v_csc_v1_1_11=$RDI_DATADIR/xsim/ip/v_csc_v1_1_11
+usxgmii_v1_2_17=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_17
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+ieee802d3_rs_fec_v2_0_22=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_22
+v_hdmi_tx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_4
+ldpc_5gnr_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_3
+rama_v1_1_17_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_17_lib
+rs_decoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_22
+ieee802d3_400g_rs_fec_v3_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_2
+xscl=$RDI_DATADIR/xsim/ip/xscl
+iomodule_v3_1_10=$RDI_DATADIR/xsim/ip/iomodule_v3_1_10
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+axi_tft_v2_0_28=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_28
+fc32_rs_fec_v1_0_27=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_27
+axi_remapper_tx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_2
+dfx_axi_shutdown_manager_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_amm_bridge_v1_0_21=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_21
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+c_accum_v12_0_18=$RDI_DATADIR/xsim/ip/c_accum_v12_0_18
+cmac_v2_6_15=$RDI_DATADIR/xsim/ip/cmac_v2_6_15
+axi_firewall_v1_2_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_6
+dft_v4_2_8=$RDI_DATADIR/xsim/ip/dft_v4_2_8
+ernic_v3_1_5=$RDI_DATADIR/xsim/ip/ernic_v3_1_5
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+axi_timer_v2_0_33=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_33
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+v_deinterlacer_v5_1_4=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_4
+axis_data_fifo_v1_1_32=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_32
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_17
+mipi_dphy_v4_3_11=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_11
+ieee802d3_50g_rs_fec_v2_0_17=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_17
+xdfe_equalizer_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_9
+flexo_100g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_28
+v_uhdsdi_audio_v2_0_8=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_8
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+c_shift_ram_v12_0_17=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_17
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+high_speed_selectio_wiz_v3_6_9=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_9
+emc_common_v3_0_7=$RDI_DATADIR/xsim/ip/emc_common_v3_0_7
+fir_compiler_v7_2_22=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_22
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+oran_radio_if_v3_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_0
+i2s_transmitter_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_8
+floating_point_v7_1_18=$RDI_DATADIR/xsim/ip/floating_point_v7_1_18
+sim_trig_v1_0_12=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_12
+hbm2e_pl_v1_0_1=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_1
+axis_protocol_checker_v2_0_15=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_15
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axi_msg_v1_0_11=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_11
+c_compare_v12_0_9=$RDI_DATADIR/xsim/ip/c_compare_v12_0_9
+c_mux_bus_v12_0_9=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_9
+xsdbm_v3_0_2=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_2
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mpram_v1_0_4=$RDI_DATADIR/xsim/ip/mpram_v1_0_4
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+dfx_controller_v1_0_7=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_7
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+rs_toolbox_v9_0_13=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_13
+pc_cfr_v8_0_2=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_2
+multi_channel_25g_rs_fec_v1_0_26=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_26
+lmb_bram_if_cntlr_v4_0_24=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_24
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+compact_gt_v1_0_17=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_17
+v_vcresampler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_11
+mipi_dsi2_rx_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_0
+axi_quad_spi_v3_2_30=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_30
+div_gen_v5_1_22=$RDI_DATADIR/xsim/ip/div_gen_v5_1_22
+v_frmbuf_rd_v2_2_10=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_10
+can_v5_1_3=$RDI_DATADIR/xsim/ip/can_v5_1_3
+axi_pcie3_v3_0_30=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_30
+emb_mem_gen_v1_0_9=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_9
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xbip_counter_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_9
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+tmr_manager_v1_0_12=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_12
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+mipi_csi2_rx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_10
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+axi_gpio_v2_0_33=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_33
+rs_encoder_v9_0_21=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_21
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_bram_ctrl_v4_1_10=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_10
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+lib_fifo_v1_0_19=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_19
+canfd_v3_0_10=$RDI_DATADIR/xsim/ip/canfd_v3_0_10
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+xfft_v9_1_12=$RDI_DATADIR/xsim/ip/xfft_v9_1_12
+axi_memory_init_v1_0_12=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_12
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+c_reg_fd_v12_0_9=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_9
+axi_mm2s_mapper_v1_1_30=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_30
+ldpc_v2_0_15=$RDI_DATADIR/xsim/ip/ldpc_v2_0_15
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+axi_data_fifo_v2_1_30=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_30
+g709_fec_v2_4_10=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_10
+axi_mcdma_v1_1_12=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_12
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+lte_fft_v2_1_10=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_10
+axi_interconnect_v1_7_23=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_23
+axi_dwidth_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_31
+axi_usb2_device_v5_0_32=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_32
+axi_hwicap_v3_0_35=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_35
+ldpc_5gnr_lite_v1_0_2=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_2
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+axi_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_17
+c_counter_binary_v12_0_19=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_19
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+mem_tg_v1_0_13=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_13
+xbip_utils_v3_0_13=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_13
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+cmac_usplus_v3_1_17=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_17
+xdfe_common_v1_0_3=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_3
+viterbi_v9_1_17=$RDI_DATADIR/xsim/ip/viterbi_v9_1_17
+xdfe_nr_prach_v2_0_3=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_3
+v_smpte_sdi_v3_0_11=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_11
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+clk_vip_v1_0_4=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_4
+mdm_v3_2_26=$RDI_DATADIR/xsim/ip/mdm_v3_2_26
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+xbip_dsp48_multadd_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_9
+noc2_nsu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_1
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+dcmac_v2_4_0=$RDI_DATADIR/xsim/ip/dcmac_v2_4_0
+v_dp_axi4s_vid_out_v1_0_8=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_8
+xbip_dsp48_acc_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_9
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+sd_fec_v1_1_14=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_14
+xbip_accum_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_9
+displayport_v8_1_9=$RDI_DATADIR/xsim/ip/displayport_v8_1_9
+ilknf_v1_3_4=$RDI_DATADIR/xsim/ip/ilknf_v1_3_4
+v_letterbox_v1_1_11=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_11
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+cpm5_v1_0_16=$RDI_DATADIR/xsim/ip/cpm5_v1_0_16
+ieee802d3_25g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_30
+jesd204_v7_2_20=$RDI_DATADIR/xsim/ip/jesd204_v7_2_20
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+g709_rs_decoder_v2_2_14=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_14
+cpri_v8_11_20=$RDI_DATADIR/xsim/ip/cpri_v8_11_20
+ieee802d3_200g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_11
+v_warp_init_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_4
+v_hscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_11
+spdif_v2_0_29=$RDI_DATADIR/xsim/ip/spdif_v2_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+axi_uart16550_v2_0_33=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_33
+axi_clock_converter_v2_1_30=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_30
+dprx_v1_0_4=$RDI_DATADIR/xsim/ip/dprx_v1_0_4
+mrmac_v2_3_0=$RDI_DATADIR/xsim/ip/mrmac_v2_3_0
+cic_compiler_v4_0_19=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_19
+c_gate_bit_v12_0_9=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_9
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+ten_gig_eth_pcs_pma_v6_0_27=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_27
+xdfe_cc_filter_v1_1_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_4
+axi_crossbar_v2_1_32=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_32
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+xbip_pipe_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_9
+tsn_temac_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_11
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+ecc_v2_0_16=$RDI_DATADIR/xsim/ip/ecc_v2_0_16
+mutex_v2_1_13=$RDI_DATADIR/xsim/ip/mutex_v2_1_13
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+ahblite_axi_bridge_v3_0_26=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_26
+tmr_inject_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_6
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+tcc_decoder_3gppmm_v2_0_27=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_27
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+etrnic_v1_1_8=$RDI_DATADIR/xsim/ip/etrnic_v1_1_8
+axi_ahblite_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_28
+ieee802d3_50g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_24
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+dfx_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_9
+dsp_macro_v1_0_6=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_6
+cpm5n_v1_0_8=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_8
+axi_dma_v7_1_32=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_32
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+hdcp_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp_v1_0_5
+axi_epc_v2_0_34=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_34
+tmr_comparator_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_7
+v_warp_filter_v1_1_4=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_4
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+xdfe_nlf_v1_1_1=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_1
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+vfb_v1_0_25=$RDI_DATADIR/xsim/ip/vfb_v1_0_25
+axis_interconnect_v1_1_23=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_23
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+mult_gen_v12_0_21=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_21
+i2s_receiver_v1_0_8=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_8
+qdriv_pl_v1_0_13=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_13
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+vid_phy_controller_v2_2_18=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_18
+advanced_io_wizard_phy_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_3
+uhdsdi_gt_v2_1_4=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_4
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+xxv_ethernet_v4_1_10=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_10
+cdcam_v1_1_0=$RDI_DATADIR/xsim/ip/cdcam_v1_1_0
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+v_mix_v5_2_9=$RDI_DATADIR/xsim/ip/v_mix_v5_2_9
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+in_system_ibert_v1_0_22=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_22
+proc_sys_reset_v5_0_15=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_15
+axis_dwidth_converter_v1_1_30=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_30
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+axi_traffic_gen_v3_0_17=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_17
+v_hdmi_rx_v3_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_4
+xdfe_resampler_v1_0_9=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_9
+zynq_ultra_ps_e_v3_3_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_12
+axi_i3c_v1_0_0=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_0
+g709_rs_encoder_v2_2_12=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_12
+xpm=$RDI_DATADIR/xsim/ip/xpm
+dptx_v1_0_4=$RDI_DATADIR/xsim/ip/dptx_v1_0_4
+v_axi4s_remap_v1_1_10=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_10
+tri_mode_ethernet_mac_v9_0_32=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_32
+xbip_bram18k_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_9
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+cordic_v6_0_22=$RDI_DATADIR/xsim/ip/cordic_v6_0_22
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+axi_hbicap_v1_0_7=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_7
+zynq_ultra_ps_e_vip_v1_0_17=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_17
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+axi_vdma_v6_3_19=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_19
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+tcc_encoder_3gpp_v5_0_22=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_22
+axis_combiner_v1_1_29=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_29
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+advanced_io_wizard_v1_0_13=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_13
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+qdma_v5_0_9=$RDI_DATADIR/xsim/ip/qdma_v5_0_9
+ddr4_pl_v1_0_14=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_14
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+axi_sg_v4_1_18=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_18
+xdfe_cc_mixer_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_4
+processing_system7_vip_v1_0_19=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_19
+mipi_dsi_tx_ctrl_v1_0_9=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_9
+microblaze_riscv_v1_0_2=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_2
+cpm4_v1_0_16=$RDI_DATADIR/xsim/ip/cpm4_v1_0_16
+xbip_multadd_v3_0_20=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_20
+axis_data_fifo_v2_0_13=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_13
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+sim_clk_gen_v1_0_4=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_4
+xdfe_fft_v1_0_7=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_7
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+blk_mem_gen_v8_4_8=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_8
+cam_blk_lib_v1_1_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_1_0
+tmr_voter_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_6
+util_ff_v1_0_3=$RDI_DATADIR/xsim/ip/util_ff_v1_0_3
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+xdfe_ofdm_v2_1_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_1_0
+audio_clock_recovery_unit_v1_0_4=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_4
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+axi_protocol_converter_v2_1_31=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_31
+xbip_dsp48_mult_v3_0_9=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_9
+tmr_sem_v1_0_26=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_26
+v_frmbuf_rd_v2_4_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_3
+cmpy_v6_0_24=$RDI_DATADIR/xsim/ip/cmpy_v6_0_24
+ta_dma_v1_0_15=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_15
+v_tpg_v8_0_14=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_14
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_iic_v2_1_7=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_7
+c_addsub_v12_0_18=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_18
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+v_vid_sdi_tx_bridge_v2_0_2=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_register_slice_v2_1_31=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_31
+axis_switch_v1_1_31=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_31
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+audio_formatter_v1_0_13=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_13
+axis_vio_v1_0_11=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_11
+interlaken_v2_4_17=$RDI_DATADIR/xsim/ip/interlaken_v2_4_17
+axis_register_slice_v1_1_31=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_31
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+picxo_fracxo_v2_0_2=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_2
+xdma_v4_1_29=$RDI_DATADIR/xsim/ip/xdma_v4_1_29
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+roe_framer_v3_0_8=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_8
+g975_efec_i7_v2_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_23
+quadsgmii_v3_5_18=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_18
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mailbox_v2_1_17=$RDI_DATADIR/xsim/ip/mailbox_v2_1_17
+v_vscaler_v1_1_11=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_11
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+av_pat_gen_v1_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_2
+v_frmbuf_rd_v2_5_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_2
+mipi_rx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_0
+gig_ethernet_pcs_pma_v16_2_18=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_18
+noc2_nmu_v1_0_1=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_1
+ats_switch_v1_0_10=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_10
+axi_ethernetlite_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_30
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+vby1hs_v1_0_5=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_5
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+convolution_v9_0_20=$RDI_DATADIR/xsim/ip/convolution_v9_0_20
+axi4stream_vip_v1_1_17=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_17
+axis_subset_converter_v1_1_31=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_31
+srio_gen2_v4_1_19=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_19
+lib_bmg_v1_0_17=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_17
+system_cache_v5_0_11=$RDI_DATADIR/xsim/ip/system_cache_v5_0_11
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+sid_v8_0_21=$RDI_DATADIR/xsim/ip/sid_v8_0_21
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+noc2_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_sc_v1_0_0
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000000000000000000000000000000000000..601d638102002078b8f1d640142cfd0edc429099
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,6 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/controlUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'controlUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'firUnit'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/src/hdl/tb_firUnit.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tb_firUnit'
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8f9ee2b2ffe7bb53faacdb5a5170723f5e0c58ca
Binary files /dev/null and b/proj/AudioProc.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b155e40f06a230303a04d2a77f07560e35c5dc93
--- /dev/null
+++ b/proj/AudioProc.sim/sim_1/behav/xsim/xvlog.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/proj/AudioProc.xpr b/proj/AudioProc.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..b3a64d30ea587d26ae8677fa0277942fa41c8399
--- /dev/null
+++ b/proj/AudioProc.xpr
@@ -0,0 +1,307 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/l23debac/2A/MedCon/Filtre/tp-filtre-etudiant-l23debac/proj/AudioProc.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="419983fb2211490f827eb4307d322eb8"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="15"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_firUnit"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014">
+ <Desc>Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold</Desc>
+ </StratHandle>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014">
+ <Desc>Vivado Implementation Defaults</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/src/hdl/controlUnit.vhd b/src/hdl/controlUnit.vhd
index 705905d8efbad8482d22e650f8cce92ef78290f4..08a258cad9b42093dc7bae6a5d794bb65f2e03e2 100644
--- a/src/hdl/controlUnit.vhd
+++ b/src/hdl/controlUnit.vhd
@@ -49,33 +49,57 @@ architecture archi_operativeUnit of controlUnit is
begin
- process (_BLANK_) is
+ process (I_reset, I_clock) is -- si horloge alors synchrone séquentiel
begin
if I_reset = '1' then -- asynchronous reset (active high)
- SR_presentState <= _BLANK_
+ SR_presentState <= WAIT_SAMPLE;
elsif rising_edge(I_clock) then -- rising clock edge
- _BLANK_
+ SR_presentState <= SR_futurState;
end if;
end process;
- process (_BLANK_) is
+ process (SR_presentState,I_processingDone,I_inputSampleValid) is --logique combinatoire
begin
case SR_presentState is
when WAIT_SAMPLE =>
- _BLANK_
+ if I_inputSampleValid = '1' then
+ SR_futurState <= STORE;
+ else
+ SR_futurState <= WAIT_SAMPLE;
+ end if;
+
+ when STORE =>
+ SR_futurState <= PROCESSING_LOOP;
+
+ when PROCESSING_LOOP =>
+ if I_processingDone = '1' then
+ SR_futurState <= OUTPUT;
+ else
+ SR_futurState <= PROCESSING_LOOP;
+ end if;
+
+ when OUTPUT =>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+ when WAIT_END_SAMPLE =>
+ if I_inputSampleValid = '0' then
+ SR_futurState <= WAIT_SAMPLE;
+ else
+ SR_futurState <= WAIT_END_SAMPLE;
+ end if;
when others => null;
end case;
end process;
- O_loadShift <= '1' when _BLANK_ ;
- O_initAddress <= '1' when _BLANK_ ;
- O_incrAddress <= '1' when _BLANK_ ;
- O_initSum <= '1' when _BLANK_ ;
- O_loadSum <= '1' when _BLANK_ ;
- O_loadY <= '1' when _BLANK_ ;
- O_FilteredSampleValid <= '1' when _BLANK_ ;
+ O_loadShift <= '1' when SR_presentState = STORE else '0';
+ O_initAddress <= '1' when SR_presentState = STORE else '0';
+ O_incrAddress <= '1' when SR_presentState = PROCESSING_LOOP else '0';
+ O_initSum <= '1' when SR_presentState = STORE else '0';
+ O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP else '0';
+ O_loadY <= '1' when SR_presentState = OUTPUT else '0';
+ --O_FilteredSampleValid <= '1' when SR_presentState = ;
diff --git a/src/hdl/operativeUnit.vhd b/src/hdl/operativeUnit.vhd
index 1286aff5a65b975b333b4136df7781bb98c0742e..ef6918e62e34c421588f66617b4aba830cfcfe6e 100644
--- a/src/hdl/operativeUnit.vhd
+++ b/src/hdl/operativeUnit.vhd
@@ -85,21 +85,24 @@ begin
to_signed(2, 8)
);
- shift : process (_BLANK_) is
+ shift : process (I_reset, I_clock) is
begin -- process shift
if I_reset = '1' then -- asynchronous reset (active high)
SR_shiftRegister <= (others => (others => '0'));
- elsif _BLANK_
-
+ elsif rising_edge(I_clock) then
+ if I_loadShift='1' then
+ SR_shiftRegister(0) <= signed(I_inputSample);
+ SR_shiftRegister(1 to 15) <= SR_shiftRegister(0 to 14);
+ end if;
end if;
end process shift;
- incr_address : process (_BLANK_) is
+ incr_address : process (I_clock, I_reset) is
begin
if I_reset = '1' then -- asynchronous reset (active high)
SR_readAddress <= 0;
- elsif _BLANK_
-
+ elsif rising_edge(I_clock) then
+ SR_readAddress <=
end if;
end process incr_address;