From f501ec471518c98bf196effac6cc428ccfabeff7 Mon Sep 17 00:00:00 2001
From: Marc KLING <m22kling@fl-tp-br-637.imta.fr>
Date: Wed, 12 Feb 2025 12:23:34 +0100
Subject: [PATCH] fin sceance 1
---
docs/Schematic.png | Bin 0 -> 72942 bytes
docs/compte-rendu.md | 27 +-
loto/loto.cache/sim/ssm.db | 10 +
loto/loto.cache/wt/project.wpc | 3 +
loto/loto.cache/wt/synthesis.wdf | 52 +
loto/loto.cache/wt/synthesis_details.wdf | 3 +
loto/loto.cache/wt/webtalk_pa.xml | 21 +
loto/loto.cache/wt/xsim.wdf | 4 +
loto/loto.hw/hw_1/hw.xml | 18 +
loto/loto.hw/loto.lpr | 9 +
loto/loto.ip_user_files/README.txt | 1 +
loto/loto.runs/.jobs/vrs_config_1.xml | 15 +
loto/loto.runs/.jobs/vrs_config_2.xml | 15 +
.../impl_1/.Vivado_Implementation.queue.rst | 0
loto/loto.runs/impl_1/.init_design.begin.rst | 5 +
loto/loto.runs/impl_1/.init_design.end.rst | 0
loto/loto.runs/impl_1/.opt_design.begin.rst | 5 +
loto/loto.runs/impl_1/.opt_design.end.rst | 0
.../impl_1/.phys_opt_design.begin.rst | 5 +
.../loto.runs/impl_1/.phys_opt_design.end.rst | 0
loto/loto.runs/impl_1/.place_design.begin.rst | 5 +
loto/loto.runs/impl_1/.place_design.end.rst | 0
loto/loto.runs/impl_1/.route_design.begin.rst | 5 +
loto/loto.runs/impl_1/.route_design.end.rst | 0
loto/loto.runs/impl_1/.vivado.begin.rst | 10 +
loto/loto.runs/impl_1/.vivado.end.rst | 0
.../impl_1/.write_bitstream.begin.rst | 5 +
.../loto.runs/impl_1/.write_bitstream.end.rst | 0
loto/loto.runs/impl_1/ISEWrap.js | 270 +
loto/loto.runs/impl_1/ISEWrap.sh | 85 +
loto/loto.runs/impl_1/clockInfo.txt | 10 +
loto/loto.runs/impl_1/gen_run.xml | 231 +
loto/loto.runs/impl_1/htr.txt | 10 +
loto/loto.runs/impl_1/init_design.pb | Bin 0 -> 2471 bytes
loto/loto.runs/impl_1/loto.bit | Bin 0 -> 3825889 bytes
loto/loto.runs/impl_1/loto.tcl | 316 ++
loto/loto.runs/impl_1/loto.vdi | 740 +++
loto/loto.runs/impl_1/loto_bus_skew_routed.pb | Bin 0 -> 30 bytes
.../loto.runs/impl_1/loto_bus_skew_routed.rpt | 16 +
.../loto.runs/impl_1/loto_bus_skew_routed.rpx | Bin 0 -> 1038 bytes
.../impl_1/loto_clock_utilization_routed.rpt | 242 +
.../impl_1/loto_control_sets_placed.rpt | 88 +
loto/loto.runs/impl_1/loto_drc_opted.pb | Bin 0 -> 37 bytes
loto/loto.runs/impl_1/loto_drc_opted.rpt | 49 +
loto/loto.runs/impl_1/loto_drc_opted.rpx | Bin 0 -> 1625 bytes
loto/loto.runs/impl_1/loto_drc_routed.pb | Bin 0 -> 37 bytes
loto/loto.runs/impl_1/loto_drc_routed.rpt | 49 +
loto/loto.runs/impl_1/loto_drc_routed.rpx | Bin 0 -> 1626 bytes
loto/loto.runs/impl_1/loto_io_placed.rpt | 366 ++
.../impl_1/loto_methodology_drc_routed.pb | Bin 0 -> 52 bytes
.../impl_1/loto_methodology_drc_routed.rpt | 356 ++
.../impl_1/loto_methodology_drc_routed.rpx | Bin 0 -> 18532 bytes
loto/loto.runs/impl_1/loto_opt.dcp | Bin 0 -> 188524 bytes
loto/loto.runs/impl_1/loto_physopt.dcp | Bin 0 -> 221581 bytes
loto/loto.runs/impl_1/loto_placed.dcp | Bin 0 -> 221272 bytes
loto/loto.runs/impl_1/loto_power_routed.rpt | 148 +
loto/loto.runs/impl_1/loto_power_routed.rpx | Bin 0 -> 68741 bytes
.../impl_1/loto_power_summary_routed.pb | Bin 0 -> 868 bytes
loto/loto.runs/impl_1/loto_route_status.pb | Bin 0 -> 44 bytes
loto/loto.runs/impl_1/loto_route_status.rpt | 11 +
loto/loto.runs/impl_1/loto_routed.dcp | Bin 0 -> 234272 bytes
.../impl_1/loto_timing_summary_routed.pb | Bin 0 -> 106 bytes
.../impl_1/loto_timing_summary_routed.rpt | 2807 +++++++++++
.../impl_1/loto_timing_summary_routed.rpx | Bin 0 -> 198589 bytes
.../impl_1/loto_utilization_placed.pb | Bin 0 -> 242 bytes
.../impl_1/loto_utilization_placed.rpt | 215 +
loto/loto.runs/impl_1/opt_design.pb | Bin 0 -> 15410 bytes
loto/loto.runs/impl_1/phys_opt_design.pb | Bin 0 -> 3421 bytes
loto/loto.runs/impl_1/place_design.pb | Bin 0 -> 22639 bytes
loto/loto.runs/impl_1/project.wdf | 31 +
loto/loto.runs/impl_1/route_design.pb | Bin 0 -> 16154 bytes
loto/loto.runs/impl_1/rundef.js | 45 +
loto/loto.runs/impl_1/runme.bat | 12 +
loto/loto.runs/impl_1/runme.log | 730 +++
loto/loto.runs/impl_1/runme.sh | 44 +
loto/loto.runs/impl_1/vivado.jou | 24 +
loto/loto.runs/impl_1/vivado.pb | Bin 0 -> 112 bytes
loto/loto.runs/impl_1/write_bitstream.pb | Bin 0 -> 2775 bytes
.../synth_1/.Vivado_Synthesis.queue.rst | 0
loto/loto.runs/synth_1/.Xil/loto_propImpl.xdc | 43 +
loto/loto.runs/synth_1/.vivado.begin.rst | 5 +
loto/loto.runs/synth_1/.vivado.end.rst | 0
loto/loto.runs/synth_1/ISEWrap.js | 270 +
loto/loto.runs/synth_1/ISEWrap.sh | 85 +
.../synth_1/__synthesis_is_complete__ | 0
loto/loto.runs/synth_1/gen_run.xml | 148 +
loto/loto.runs/synth_1/htr.txt | 10 +
loto/loto.runs/synth_1/incr_synth_reason.pb | 1 +
loto/loto.runs/synth_1/loto.dcp | Bin 0 -> 43325 bytes
loto/loto.runs/synth_1/loto.tcl | 130 +
loto/loto.runs/synth_1/loto.vds | 302 ++
.../synth_1/loto_utilization_synth.pb | Bin 0 -> 242 bytes
.../synth_1/loto_utilization_synth.rpt | 182 +
loto/loto.runs/synth_1/rundef.js | 41 +
loto/loto.runs/synth_1/runme.bat | 12 +
loto/loto.runs/synth_1/runme.log | 292 ++
loto/loto.runs/synth_1/runme.sh | 40 +
loto/loto.runs/synth_1/vivado.jou | 24 +
loto/loto.runs/synth_1/vivado.pb | Bin 0 -> 31307 bytes
loto/loto.sim/sim_1/behav/xsim/compile.sh | 24 +
.../xsim/compteur_modulo6_tb_arch_cfg.tcl | 11 +
.../compteur_modulo6_tb_arch_cfg_behav.wdb | Bin 0 -> 7947 bytes
loto/loto.sim/sim_1/behav/xsim/elaborate.log | 8 +
loto/loto.sim/sim_1/behav/xsim/elaborate.sh | 22 +
.../sim_1/behav/xsim/loto_tb_ar_cfg.tcl | 11 +
.../sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb | Bin 0 -> 33507 bytes
.../sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj | 18 +
.../sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl | 11 +
.../behav/xsim/mux6_1_tb_arch_cfg_behav.wdb | Bin 0 -> 8735 bytes
loto/loto.sim/sim_1/behav/xsim/simulate.log | 0
loto/loto.sim/sim_1/behav/xsim/simulate.sh | 22 +
loto/loto.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 854 bytes
.../Compile_Options.txt | 1 +
.../TempBreakPointFile.txt | 1 +
.../obj/xsim_0.lnx64.o | Bin 0 -> 5304 bytes
.../obj/xsim_1.c | 113 +
.../obj/xsim_1.lnx64.o | Bin 0 -> 4496 bytes
.../xsim.dbg | Bin 0 -> 3440 bytes
.../xsim.mem | Bin 0 -> 2711 bytes
.../xsim.reloc | Bin 0 -> 279 bytes
.../xsim.rlx | 12 +
.../xsim.rtti | Bin 0 -> 358 bytes
.../xsim.svtype | Bin 0 -> 16 bytes
.../xsim.type | Bin 0 -> 6824 bytes
.../xsim.xdbg | Bin 0 -> 400 bytes
.../xsimSettings.ini | 50 +
.../xsimcrash.log | 0
.../compteur_modulo6_tb_arch_cfg_behav/xsimk | Bin 0 -> 18008 bytes
.../xsimkernel.log | 7 +
.../loto_tb_ar_cfg_behav/Compile_Options.txt | 1 +
.../TempBreakPointFile.txt | 1 +
.../loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o | Bin 0 -> 33920 bytes
.../loto_tb_ar_cfg_behav/obj/xsim_1.c | 152 +
.../loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o | Bin 0 -> 7088 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.dbg | Bin 0 -> 23888 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.mem | Bin 0 -> 4856 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc | Bin 0 -> 2530 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx | 12 +
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.rtti | Bin 0 -> 555 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype | Bin 0 -> 16 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.type | Bin 0 -> 7016 bytes
.../xsim.dir/loto_tb_ar_cfg_behav/xsim.xdbg | Bin 0 -> 8096 bytes
.../loto_tb_ar_cfg_behav/xsimSettings.ini | 50 +
.../loto_tb_ar_cfg_behav/xsimcrash.log | 0
.../xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimk | Bin 0 -> 45296 bytes
.../loto_tb_ar_cfg_behav/xsimkernel.log | 4 +
.../Compile_Options.txt | 1 +
.../TempBreakPointFile.txt | 1 +
.../obj/xsim_0.lnx64.o | Bin 0 -> 8648 bytes
.../mux6_1_tb_arch_cfg_behav/obj/xsim_1.c | 111 +
.../obj/xsim_1.lnx64.o | Bin 0 -> 4336 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.dbg | Bin 0 -> 4320 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.mem | Bin 0 -> 2721 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.reloc | Bin 0 -> 360 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.rlx | 12 +
.../mux6_1_tb_arch_cfg_behav/xsim.rtti | Bin 0 -> 318 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.svtype | Bin 0 -> 16 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.type | Bin 0 -> 6824 bytes
.../mux6_1_tb_arch_cfg_behav/xsim.xdbg | Bin 0 -> 592 bytes
.../mux6_1_tb_arch_cfg_behav/xsimSettings.ini | 50 +
.../mux6_1_tb_arch_cfg_behav/xsimcrash.log | 0
.../xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk | Bin 0 -> 26568 bytes
.../mux6_1_tb_arch_cfg_behav/xsimkernel.log | 7 +
.../xsim/xsim.dir/xil_defaultlib/automate.vdb | Bin 0 -> 9272 bytes
.../xsim.dir/xil_defaultlib/compteur1_49.vdb | Bin 0 -> 3743 bytes
.../xil_defaultlib/compteur_modulo6.vdb | Bin 0 -> 3731 bytes
.../xil_defaultlib/compteur_modulo6_tb.vdb | Bin 0 -> 4213 bytes
.../compteur_modulo6_tb_arch_cfg.vdb | Bin 0 -> 1179 bytes
.../xil_defaultlib/compteur_valid.vdb | Bin 0 -> 3974 bytes
.../xsim.dir/xil_defaultlib/diviseur_freq.vdb | Bin 0 -> 3560 bytes
.../xsim/xsim.dir/xil_defaultlib/led_pwm.vdb | Bin 0 -> 4564 bytes
.../xsim/xsim.dir/xil_defaultlib/loto.vdb | Bin 0 -> 22819 bytes
.../xsim/xsim.dir/xil_defaultlib/loto_tb.vdb | Bin 0 -> 6789 bytes
.../xil_defaultlib/loto_tb_ar_cfg.vdb | Bin 0 -> 1047 bytes
.../xsim/xsim.dir/xil_defaultlib/modulo4.vdb | Bin 0 -> 4960 bytes
.../xsim/xsim.dir/xil_defaultlib/mux6_1.vdb | Bin 0 -> 3968 bytes
.../xsim.dir/xil_defaultlib/mux6_1_tb.vdb | Bin 0 -> 6639 bytes
.../xil_defaultlib/mux6_1_tb_arch_cfg.vdb | Bin 0 -> 1127 bytes
.../xsim.dir/xil_defaultlib/registres.vdb | Bin 0 -> 6268 bytes
.../xsim/xsim.dir/xil_defaultlib/tirage.vdb | Bin 0 -> 22373 bytes
.../xil_defaultlib/transcodeur7s_d_u.vdb | Bin 0 -> 10348 bytes
.../xil_defaultlib/xil_defaultlib.rlx | 19 +
loto/loto.sim/sim_1/behav/xsim/xsim.ini | 1 +
loto/loto.sim/sim_1/behav/xsim/xvhdl.log | 0
loto/loto.sim/sim_1/behav/xsim/xvhdl.pb | 4 +
.../utils_1/imports/synth_1/loto.dcp | Bin 0 -> 43140 bytes
loto/loto.xpr | 330 ++
src/automate.vhd | 69 +-
src/compteur_modulo6.vhd | 16 +-
src/mux6_1.vhd | 9 +-
vivado.jou | 120 +
vivado.log | 1896 +++++++
vivado_pid13301.str | 4488 +++++++++++++++++
193 files changed, 16341 insertions(+), 22 deletions(-)
create mode 100644 docs/Schematic.png
create mode 100644 loto/loto.cache/sim/ssm.db
create mode 100644 loto/loto.cache/wt/project.wpc
create mode 100644 loto/loto.cache/wt/synthesis.wdf
create mode 100644 loto/loto.cache/wt/synthesis_details.wdf
create mode 100644 loto/loto.cache/wt/webtalk_pa.xml
create mode 100644 loto/loto.cache/wt/xsim.wdf
create mode 100644 loto/loto.hw/hw_1/hw.xml
create mode 100644 loto/loto.hw/loto.lpr
create mode 100644 loto/loto.ip_user_files/README.txt
create mode 100644 loto/loto.runs/.jobs/vrs_config_1.xml
create mode 100644 loto/loto.runs/.jobs/vrs_config_2.xml
create mode 100644 loto/loto.runs/impl_1/.Vivado_Implementation.queue.rst
create mode 100644 loto/loto.runs/impl_1/.init_design.begin.rst
create mode 100644 loto/loto.runs/impl_1/.init_design.end.rst
create mode 100644 loto/loto.runs/impl_1/.opt_design.begin.rst
create mode 100644 loto/loto.runs/impl_1/.opt_design.end.rst
create mode 100644 loto/loto.runs/impl_1/.phys_opt_design.begin.rst
create mode 100644 loto/loto.runs/impl_1/.phys_opt_design.end.rst
create mode 100644 loto/loto.runs/impl_1/.place_design.begin.rst
create mode 100644 loto/loto.runs/impl_1/.place_design.end.rst
create mode 100644 loto/loto.runs/impl_1/.route_design.begin.rst
create mode 100644 loto/loto.runs/impl_1/.route_design.end.rst
create mode 100644 loto/loto.runs/impl_1/.vivado.begin.rst
create mode 100644 loto/loto.runs/impl_1/.vivado.end.rst
create mode 100644 loto/loto.runs/impl_1/.write_bitstream.begin.rst
create mode 100644 loto/loto.runs/impl_1/.write_bitstream.end.rst
create mode 100755 loto/loto.runs/impl_1/ISEWrap.js
create mode 100755 loto/loto.runs/impl_1/ISEWrap.sh
create mode 100644 loto/loto.runs/impl_1/clockInfo.txt
create mode 100644 loto/loto.runs/impl_1/gen_run.xml
create mode 100644 loto/loto.runs/impl_1/htr.txt
create mode 100644 loto/loto.runs/impl_1/init_design.pb
create mode 100644 loto/loto.runs/impl_1/loto.bit
create mode 100644 loto/loto.runs/impl_1/loto.tcl
create mode 100644 loto/loto.runs/impl_1/loto.vdi
create mode 100644 loto/loto.runs/impl_1/loto_bus_skew_routed.pb
create mode 100644 loto/loto.runs/impl_1/loto_bus_skew_routed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_bus_skew_routed.rpx
create mode 100644 loto/loto.runs/impl_1/loto_clock_utilization_routed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_control_sets_placed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_drc_opted.pb
create mode 100644 loto/loto.runs/impl_1/loto_drc_opted.rpt
create mode 100644 loto/loto.runs/impl_1/loto_drc_opted.rpx
create mode 100644 loto/loto.runs/impl_1/loto_drc_routed.pb
create mode 100644 loto/loto.runs/impl_1/loto_drc_routed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_drc_routed.rpx
create mode 100644 loto/loto.runs/impl_1/loto_io_placed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_methodology_drc_routed.pb
create mode 100644 loto/loto.runs/impl_1/loto_methodology_drc_routed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_methodology_drc_routed.rpx
create mode 100644 loto/loto.runs/impl_1/loto_opt.dcp
create mode 100644 loto/loto.runs/impl_1/loto_physopt.dcp
create mode 100644 loto/loto.runs/impl_1/loto_placed.dcp
create mode 100644 loto/loto.runs/impl_1/loto_power_routed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_power_routed.rpx
create mode 100644 loto/loto.runs/impl_1/loto_power_summary_routed.pb
create mode 100644 loto/loto.runs/impl_1/loto_route_status.pb
create mode 100644 loto/loto.runs/impl_1/loto_route_status.rpt
create mode 100644 loto/loto.runs/impl_1/loto_routed.dcp
create mode 100644 loto/loto.runs/impl_1/loto_timing_summary_routed.pb
create mode 100644 loto/loto.runs/impl_1/loto_timing_summary_routed.rpt
create mode 100644 loto/loto.runs/impl_1/loto_timing_summary_routed.rpx
create mode 100644 loto/loto.runs/impl_1/loto_utilization_placed.pb
create mode 100644 loto/loto.runs/impl_1/loto_utilization_placed.rpt
create mode 100644 loto/loto.runs/impl_1/opt_design.pb
create mode 100644 loto/loto.runs/impl_1/phys_opt_design.pb
create mode 100644 loto/loto.runs/impl_1/place_design.pb
create mode 100644 loto/loto.runs/impl_1/project.wdf
create mode 100644 loto/loto.runs/impl_1/route_design.pb
create mode 100644 loto/loto.runs/impl_1/rundef.js
create mode 100644 loto/loto.runs/impl_1/runme.bat
create mode 100644 loto/loto.runs/impl_1/runme.log
create mode 100755 loto/loto.runs/impl_1/runme.sh
create mode 100644 loto/loto.runs/impl_1/vivado.jou
create mode 100644 loto/loto.runs/impl_1/vivado.pb
create mode 100644 loto/loto.runs/impl_1/write_bitstream.pb
create mode 100644 loto/loto.runs/synth_1/.Vivado_Synthesis.queue.rst
create mode 100644 loto/loto.runs/synth_1/.Xil/loto_propImpl.xdc
create mode 100644 loto/loto.runs/synth_1/.vivado.begin.rst
create mode 100644 loto/loto.runs/synth_1/.vivado.end.rst
create mode 100755 loto/loto.runs/synth_1/ISEWrap.js
create mode 100755 loto/loto.runs/synth_1/ISEWrap.sh
create mode 100644 loto/loto.runs/synth_1/__synthesis_is_complete__
create mode 100644 loto/loto.runs/synth_1/gen_run.xml
create mode 100644 loto/loto.runs/synth_1/htr.txt
create mode 100644 loto/loto.runs/synth_1/incr_synth_reason.pb
create mode 100644 loto/loto.runs/synth_1/loto.dcp
create mode 100644 loto/loto.runs/synth_1/loto.tcl
create mode 100644 loto/loto.runs/synth_1/loto.vds
create mode 100644 loto/loto.runs/synth_1/loto_utilization_synth.pb
create mode 100644 loto/loto.runs/synth_1/loto_utilization_synth.rpt
create mode 100644 loto/loto.runs/synth_1/rundef.js
create mode 100644 loto/loto.runs/synth_1/runme.bat
create mode 100644 loto/loto.runs/synth_1/runme.log
create mode 100755 loto/loto.runs/synth_1/runme.sh
create mode 100644 loto/loto.runs/synth_1/vivado.jou
create mode 100644 loto/loto.runs/synth_1/vivado.pb
create mode 100755 loto/loto.sim/sim_1/behav/xsim/compile.sh
create mode 100644 loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl
create mode 100644 loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg_behav.wdb
create mode 100644 loto/loto.sim/sim_1/behav/xsim/elaborate.log
create mode 100755 loto/loto.sim/sim_1/behav/xsim/elaborate.sh
create mode 100644 loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl
create mode 100644 loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb
create mode 100644 loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj
create mode 100644 loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl
create mode 100644 loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg_behav.wdb
create mode 100644 loto/loto.sim/sim_1/behav/xsim/simulate.log
create mode 100755 loto/loto.sim/sim_1/behav/xsim/simulate.sh
create mode 100644 loto/loto.sim/sim_1/behav/xsim/xelab.pb
create mode 100644 loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt
create mode 100644 loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt
create mode 100644 loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o
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diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index bcc655d..a56410a 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -3,39 +3,50 @@
Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+Dans le cas on on utilise un process, il faut inclure les signaux I_sel et tous les signaux de I_0 à I_5 a la liste de sensibilité. (Il et cependant possible de tout faire de façon combinatoire).
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
-
+Dans ce cas, le signal renvoie la valeur précédente. Il doit donc ajouter un élément mémoire ce qui rajoute un comportement non souhaité en plus d'ajouter de la complexité. Cependant, dnas notre cas, ce n'est pas critique car le cas n'arrive pas.
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+Le test est concluant. Cependant, il n'est pas suffisant pour valider le modèle car certains cas ne sont pas traités (valeur 6, 7, X...). Cela ne nous dérange pas car dans notre cas, toutes les combinaisons des entrées pouvant être générées par le reste du circuit sont traitées (le circuit étant combinatoire, il suffit de traiter les combinaisons des entrées).
## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+On inclut I_clk et I_rst carce sont les seuls signaux pouvant changer l'état du module.
## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
-
+Si nous n'ajoutons pas la ligne SR_counter <= SR_counter lorsque le compteur est bloqué, SR_counter gardera la même valeur, car SR_counter est stocké dans un registre et cela n'ajoutera pas de latch.
## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
-
+Le test est concluant. Cependant, il faudrait théoriquement ajouter des cas pour valider l'intégriter du module; certaines combinaisons input-signaux internes ne sont pas présents (ex I_rst = 1 et SR_counter = 4). Pourtant, comme les comportements des différentes entrées sont indépendantes de l'état du compteur, ce dernier ne va pas altérer leur comportement.
## Question Loto 7 : Combien de processus avez-vous décris ?
-
+Nous avons utilisé un unique processus séquentiel qui, à chaque cycle d'horloge gère toutes les variables O_l_green, O_l_red, O_counting et Sr_State en fonction de l'état actuel de la FSM.
## Question Loto 8 : De quel(s) type(s) sont-ils
-
+C'est un processus séquentiel.
## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
-
+On aurait pu utiliser un processus séquentiel uniquement pour gérer l'état et un ou plusieurs processus combinatoire pour gérer les autres sorties.
## Question Loto 10 : Ce test est-il concluant ? Justifiez.
-
+Le test est concluant. Cependant, par soucis de clarté, on peut modifier le TB afin de s'assurer que les pression du boutton sont espacées de plusieurs signaux d'horloge. On vérifie la présence des valeures dans les registres, en analysant les signaux du 7-segment, on vérfie également l'affichage.
## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
-
+Il est parfaitement conforme:
+
+On observe bien que tous les modules sont présents avec les bonnes entrées/sorties.
## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+LUT 72/63400 0.11%
+FF 89/126800 0.07%
+IO 21/210
+ IL n’y a pas de latch ce qui est une bonne chose. Cela montre que l'abscence de comportement inattendu dans le code.
+2 BUFG pour l'horloge sur 32
## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
+Ce loto est aléatoire pour un humain. Cependant, une machine serait capable de suivre l'horloge de 100MHz et dans ce cas, le process est détermininste.
diff --git a/loto/loto.cache/sim/ssm.db b/loto/loto.cache/sim/ssm.db
new file mode 100644
index 0000000..b9d860d
--- /dev/null
+++ b/loto/loto.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Feb 12 10:09:19 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
diff --git a/loto/loto.cache/wt/project.wpc b/loto/loto.cache/wt/project.wpc
new file mode 100644
index 0000000..6888ede
--- /dev/null
+++ b/loto/loto.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
+eof:
diff --git a/loto/loto.cache/wt/synthesis.wdf b/loto/loto.cache/wt/synthesis.wdf
new file mode 100644
index 0000000..da48581
--- /dev/null
+++ b/loto/loto.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
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diff --git a/loto/loto.cache/wt/synthesis_details.wdf b/loto/loto.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000..78f8d66
--- /dev/null
+++ b/loto/loto.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/loto/loto.cache/wt/webtalk_pa.xml b/loto/loto.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000..e1ce28f
--- /dev/null
+++ b/loto/loto.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Feb 12 11:22:49 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="94fb0400f1af4ac9b292d5cecc065205" type="ProjectID"/>
+<property name="ProjectIteration" value="2" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/loto/loto.cache/wt/xsim.wdf b/loto/loto.cache/wt/xsim.wdf
new file mode 100644
index 0000000..51d5206
--- /dev/null
+++ b/loto/loto.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
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+eof:2427094519
diff --git a/loto/loto.hw/hw_1/hw.xml b/loto/loto.hw/hw_1/hw.xml
new file mode 100644
index 0000000..6a35837
--- /dev/null
+++ b/loto/loto.hw/hw_1/hw.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<hwsession version="1" minor="2">
+ <device name="xc7a100t_0" gui_info=""/>
+ <ObjectList object_type="hw_device" gui_info="">
+ <Object name="xc7a100t_0" gui_info="">
+ <Properties Property="FULL_PROBES.FILE" value=""/>
+ <Properties Property="PROBES.FILE" value=""/>
+ <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/$_project_name_.bit"/>
+ <Properties Property="SLR.COUNT" value="1"/>
+ </Object>
+ </ObjectList>
+ <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/loto/loto.hw/loto.lpr b/loto/loto.hw/loto.lpr
new file mode 100644
index 0000000..aa18adc
--- /dev/null
+++ b/loto/loto.hw/loto.lpr
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0">
+ <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/loto/loto.ip_user_files/README.txt b/loto/loto.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/loto/loto.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/loto/loto.runs/.jobs/vrs_config_1.xml b/loto/loto.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000..486e184
--- /dev/null
+++ b/loto/loto.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/loto/loto.runs/.jobs/vrs_config_2.xml b/loto/loto.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000..486e184
--- /dev/null
+++ b/loto/loto.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/loto/loto.runs/impl_1/.Vivado_Implementation.queue.rst b/loto/loto.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.init_design.begin.rst b/loto/loto.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000..5012ecb
--- /dev/null
+++ b/loto/loto.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="m22kling" Host="" Pid="50768">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.init_design.end.rst b/loto/loto.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.opt_design.begin.rst b/loto/loto.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000..5012ecb
--- /dev/null
+++ b/loto/loto.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="m22kling" Host="" Pid="50768">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.opt_design.end.rst b/loto/loto.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.phys_opt_design.begin.rst b/loto/loto.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 0000000..5012ecb
--- /dev/null
+++ b/loto/loto.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="m22kling" Host="" Pid="50768">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.phys_opt_design.end.rst b/loto/loto.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.place_design.begin.rst b/loto/loto.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000..5012ecb
--- /dev/null
+++ b/loto/loto.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="m22kling" Host="" Pid="50768">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.place_design.end.rst b/loto/loto.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.route_design.begin.rst b/loto/loto.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000..5012ecb
--- /dev/null
+++ b/loto/loto.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="m22kling" Host="" Pid="50768">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.route_design.end.rst b/loto/loto.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.vivado.begin.rst b/loto/loto.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000..04550d1
--- /dev/null
+++ b/loto/loto.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,10 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="m22kling" Host="fl-tp-br-637" Pid="46380" HostCore="4" HostMemory="16257804">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="m22kling" Host="fl-tp-br-637" Pid="50696" HostCore="4" HostMemory="16257804">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.vivado.end.rst b/loto/loto.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/.write_bitstream.begin.rst b/loto/loto.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000..5012ecb
--- /dev/null
+++ b/loto/loto.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="m22kling" Host="" Pid="50768">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/impl_1/.write_bitstream.end.rst b/loto/loto.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/impl_1/ISEWrap.js b/loto/loto.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000..61806d0
--- /dev/null
+++ b/loto/loto.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/loto/loto.runs/impl_1/ISEWrap.sh b/loto/loto.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000..05d5381
--- /dev/null
+++ b/loto/loto.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/loto/loto.runs/impl_1/clockInfo.txt b/loto/loto.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000..9ea57ca
--- /dev/null
+++ b/loto/loto.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.1
+| Date : Wed Feb 12 11:24:34 2025
+| Host : fl-tp-br-637
+| Design : design_1
+| Device : xc7a100t-csg324-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/loto/loto.runs/impl_1/gen_run.xml b/loto/loto.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000..552c665
--- /dev/null
+++ b/loto/loto.runs/impl_1/gen_run.xml
@@ -0,0 +1,231 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1739355769">
+ <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS" Name="loto_postroute_physopted.rqs"/>
+ <File Type="ROUTE-RQS" Name="loto_routed.rqs"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BG-BGN" Name="loto.bgn"/>
+ <File Type="BITSTR-SYSDEF" Name="loto.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="loto.ltx"/>
+ <File Type="RBD_FILE" Name="loto.rbd"/>
+ <File Type="NPI_FILE" Name="loto.npi"/>
+ <File Type="RNPI_FILE" Name="loto.rnpi"/>
+ <File Type="CFI_FILE" Name="loto.cfi"/>
+ <File Type="RCFI_FILE" Name="loto.rcfi"/>
+ <File Type="PL-PDI-FILE" Name="loto_pld.pdi"/>
+ <File Type="BOOT-PDI-FILE" Name="loto_boot.pdi"/>
+ <File Type="RDI-RDI" Name="loto.vdi"/>
+ <File Type="PDI-FILE" Name="loto.pdi"/>
+ <File Type="BITSTR-MMI" Name="loto.mmi"/>
+ <File Type="BITSTR-BMM" Name="loto_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="loto.nky"/>
+ <File Type="BITSTR-RBT" Name="loto.rbt"/>
+ <File Type="BITSTR-MSK" Name="loto.msk"/>
+ <File Type="BG-BIN" Name="loto.bin"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+ <File Type="BG-BIT" Name="loto.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="loto_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="loto_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="loto_bus_skew_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="loto_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="loto_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="loto_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="loto_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="loto_postroute_physopt.dcp"/>
+ <File Type="BG-DRC" Name="loto.drc"/>
+ <File Type="ROUTE-RQS-PB" Name="loto_rqs_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="loto_bus_skew_routed.rpx"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="loto_bus_skew_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW" Name="loto_bus_skew_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="loto_clock_utilization_routed.rpt"/>
+ <File Type="ROUTE-SIMILARITY" Name="loto_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-TIMING-RPX" Name="loto_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-TIMING-PB" Name="loto_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="loto_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="loto_route_status.pb"/>
+ <File Type="ROUTE-STATUS" Name="loto_route_status.rpt"/>
+ <File Type="ROUTE-PWR-RPX" Name="loto_power_routed.rpx"/>
+ <File Type="ROUTE-PWR-SUM" Name="loto_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="loto_power_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="loto_methodology_drc_routed.pb"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="loto_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="loto_methodology_drc_routed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="loto_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="loto_drc_routed.pb"/>
+ <File Type="ROUTE-DRC" Name="loto_drc_routed.rpt"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="loto_routed_bb.dcp"/>
+ <File Type="ROUTE-DCP" Name="loto_routed.dcp"/>
+ <File Type="ROUTE-ERROR-DCP" Name="loto_routed_error.dcp"/>
+ <File Type="PHYSOPT-TIMING" Name="loto_timing_summary_physopted.rpt"/>
+ <File Type="PHYSOPT-DRC" Name="loto_drc_physopted.rpt"/>
+ <File Type="PHYSOPT-DCP" Name="loto_physopt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="loto_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="loto_postplace_pwropt.dcp"/>
+ <File Type="PLACE-RQA-PB" Name="loto_rqa_placed.pb"/>
+ <File Type="PLACE-TIMING" Name="loto_timing_summary_placed.rpt"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="loto_incremental_reuse_pre_placed.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="loto_incremental_reuse_placed.rpt"/>
+ <File Type="PLACE-CTRL" Name="loto_control_sets_placed.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="loto_utilization_placed.pb"/>
+ <File Type="PLACE-UTIL" Name="loto_utilization_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="loto_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-IO" Name="loto_io_placed.rpt"/>
+ <File Type="PLACE-DCP" Name="loto_placed.dcp"/>
+ <File Type="PWROPT-TIMING" Name="loto_timing_summary_pwropted.rpt"/>
+ <File Type="PWROPT-DRC" Name="loto_drc_pwropted.rpt"/>
+ <File Type="PWROPT-DCP" Name="loto_pwropt.dcp"/>
+ <File Type="OPT-RQA-PB" Name="loto_rqa_opted.pb"/>
+ <File Type="OPT-HWDEF" Name="loto.hwdef"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="loto_methodology_drc_opted.rpt"/>
+ <File Type="OPT-DRC" Name="loto_drc_opted.rpt"/>
+ <File Type="OPT-DCP" Name="loto_opt.dcp"/>
+ <File Type="OPT-TIMING" Name="loto_timing_summary_opted.rpt"/>
+ <File Type="REPORTS-TCL" Name="loto_reports.tcl"/>
+ <File Type="INIT-TIMING" Name="loto_timing_summary_init.rpt"/>
+ <File Type="PA-TCL" Name="loto.tcl"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/automate.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur1_49.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_valid.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/diviseur_freq.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/led_pwm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/registres.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/tirage.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_d_u.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/modulo4.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/loto.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo4.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
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+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1_tb.vhd">
+ <FileInfo>
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+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/loto.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+</GenRun>
diff --git a/loto/loto.runs/impl_1/htr.txt b/loto/loto.runs/impl_1/htr.txt
new file mode 100644
index 0000000..0691ed2
--- /dev/null
+++ b/loto/loto.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
diff --git a/loto/loto.runs/impl_1/init_design.pb b/loto/loto.runs/impl_1/init_design.pb
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diff --git a/loto/loto.runs/impl_1/loto.tcl b/loto/loto.runs/impl_1/loto.tcl
new file mode 100644
index 0000000..58d9b80
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto.tcl
@@ -0,0 +1,316 @@
+namespace eval ::optrace {
+ variable script "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+set_msg_config -id {Common 17-41} -limit 10000000
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param checkpoint.writeSynthRtdsInDcp 1
+ set_param chipscope.maxJobs 1
+ set_param xicom.use_bs_reader 1
+ set_param synth.incrementalSynthesisCache ./.Xil/Vivado-13301-fl-tp-br-637/incrSyn
+ set_param runs.launchOptions { -jobs 4 }
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7a100tcsg324-1
+ set_property board_part digilentinc.com:nexys4_ddr:part0:1.1 [current_project]
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.cache/wt [current_project]
+ set_property parent.project_path /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr [current_project]
+ set_property ip_output_repo /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.dcp
+OPTRACE "read constraints: implementation" START { }
+ read_xdc /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ link_design -top loto -part xc7a100tcsg324-1
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx" }
+ set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_io -file loto_io_placed.rpt" "report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb" "report_control_sets -verbose -file loto_control_sets_placed.rpt" }
+ set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+ create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+ phys_opt_design
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+ close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed phys_opt_design
+ return -code error $RESULT
+} else {
+ end_step phys_opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx" "report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx" "report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx" "report_route_status -file loto_route_status.rpt -pb loto_route_status.pb" "report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file loto_incremental_reuse_routed.rpt" "report_clock_utilization -file loto_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx" }
+ set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+ write_checkpoint -force loto_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ catch { write_mem_info -force -no_partial_mmi loto.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force loto.bit
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force loto}
+ catch {file copy -force loto.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/loto/loto.runs/impl_1/loto.vdi b/loto/loto.runs/impl_1/loto.vdi
new file mode 100644
index 0000000..d2f1030
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto.vdi
@@ -0,0 +1,740 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:23:53 2025
+# Process ID: 50768
+# Current directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1
+# Command line: vivado -log loto.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+# Log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.vdi
+# Journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-637
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3300.030 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :15504 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.883 ; gain = 202.840 ; free physical = 1413 ; free virtual = 14279
+Command: link_design -top loto -part xc7a100tcsg324-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1931.945 ; gain = 0.000 ; free physical = 1066 ; free virtual = 13933
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2141.410 ; gain = 0.000 ; free physical = 953 ; free virtual = 13819
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2141.410 ; gain = 569.527 ; free physical = 953 ; free virtual = 13819
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2153.988 ; gain = 12.578 ; free physical = 919 ; free virtual = 13786
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 211085630
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2652.816 ; gain = 498.828 ; free physical = 503 ; free virtual = 13371
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 211085630
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 211085630
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 1 Initialization | Checksum: 211085630
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 2 Timer Update And Timing Data Collection | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Retarget | Checksum: 211085630
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Constant propagation | Checksum: 211085630
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Sweep | Checksum: 251a8a732
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+BUFG optimization | Checksum: 251a8a732
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Shift Register Optimization | Checksum: 251a8a732
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Post Processing Netlist | Checksum: 251a8a732
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 9 Finalization | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 0 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Ending Netlist Obfuscation Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+INFO: [Common 17-83] Releasing license: Implementation
+26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2966.652 ; gain = 825.242 ; free physical = 193 ; free virtual = 13059
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+Command: report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Write Physdb Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 180 ; free virtual = 13069
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 161 ; free virtual = 13086
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19b090d25
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 161 ; free virtual = 13086
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 161 ; free virtual = 13086
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196a652db
+
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 189 ; free virtual = 13088
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 206d57cc6
+
+Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 173 ; free virtual = 13080
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 206d57cc6
+
+Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 173 ; free virtual = 13080
+Phase 1 Placer Initialization | Checksum: 206d57cc6
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 158 ; free virtual = 13073
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 21c3f6b22
+
+Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.5 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 193 ; free virtual = 13060
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19c2f5c99
+
+Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 193 ; free virtual = 13060
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 19c2f5c99
+
+Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 193 ; free virtual = 13060
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1acd71bcf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1acd71bcf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+Phase 2.4 Global Placement Core | Checksum: 233028bb0
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+Phase 2 Global Placement | Checksum: 233028bb0
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 1f43e3888
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b44da236
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 22ffbc78e
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1e47ff1ff
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1f038efdd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1af4f748a
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 17bb44ef9
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+Phase 3 Detail Placement | Checksum: 17bb44ef9
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 1ba5038a9
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=6.007 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 19735b1a7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 2223fa4bd
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1ba5038a9
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=6.007. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4.1 Post Commit Optimization | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4.3 Placer Reporting | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f7e5a539
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Ending Placer Task | Checksum: 195b01157
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file loto_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 166 ; free virtual = 13037
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file loto_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 167 ; free virtual = 13038
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 168 ; free virtual = 13039
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 168 ; free virtual = 13039
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Write Physdb Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 188 ; free virtual = 13038
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 6.007 | TNS= 0.000 |
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 186 ; free virtual = 13036
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13035
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 180 ; free virtual = 13030
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 178 ; free virtual = 13028
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 176 ; free virtual = 13027
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 176 ; free virtual = 13027
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 172 ; free virtual = 13023
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 2039d80e ConstDB: 0 ShapeSum: c3a3d9b3 RouteDB: b1d25f96
+Post Restoration Checksum: NetGraph: 98d52cf6 | NumContArr: 788702f8 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 296ae2528
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3122.594 ; gain = 107.918 ; free physical = 187 ; free virtual = 12883
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 296ae2528
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3122.594 ; gain = 107.918 ; free physical = 187 ; free virtual = 12883
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 296ae2528
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3122.594 ; gain = 107.918 ; free physical = 187 ; free virtual = 12883
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 2b4755bdc
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3144.172 ; gain = 129.496 ; free physical = 229 ; free virtual = 12885
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.766 | TNS=0.000 | WHS=0.004 | THS=0.000 |
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 4.35218e-05 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 167
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 165
+ Number of Partially Routed Nets = 2
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 256318032
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 256318032
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 274f4de13
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 4 Initial Routing | Checksum: 274f4de13
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 11
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.914 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 5 Rip-up And Reroute | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 6 Delay and Skew Optimization | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.010 | TNS=0.000 | WHS=0.306 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 7 Post Hold Fix | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0221091 %
+ Global Horizontal Routing Utilization = 0.0471725 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 22ea9d0de
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 22ea9d0de
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=6.010 | TNS=0.000 | WHS=0.306 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 22ea9d0de
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Total Elapsed time in route_design: 21.31 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 190db45f2
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 190db45f2
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+Command: report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+Command: report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 4 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file loto_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file loto_route_status.rpt -pb loto_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Command: report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+107 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file loto_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 167 ; free virtual = 12822
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 167 ; free virtual = 12823
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 167 ; free virtual = 12822
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_routed.dcp' has been generated.
+Command: write_bitstream -force loto.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./loto.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+118 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3496.727 ; gain = 276.914 ; free physical = 204 ; free virtual = 12506
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:25:13 2025...
diff --git a/loto/loto.runs/impl_1/loto_bus_skew_routed.pb b/loto/loto.runs/impl_1/loto_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
GIT binary patch
literal 30
lcmd;LGcqu=&@-IGEZ|gHtWcbtTCPx(T3nh_Qapp10RVJW2(bVF
literal 0
HcmV?d00001
diff --git a/loto/loto.runs/impl_1/loto_bus_skew_routed.rpt b/loto/loto.runs/impl_1/loto_bus_skew_routed.rpt
new file mode 100644
index 0000000..c468636
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:25:00 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx
+| Design : loto
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/loto/loto.runs/impl_1/loto_bus_skew_routed.rpx b/loto/loto.runs/impl_1/loto_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..11c5852ba5e0841f54d53e96e11fce399043f1e8
GIT binary patch
literal 1038
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qoI!v=f<b}7fI*6Zfq_>eJI_ymQG!u{L4(17!Ggho!Gj?b<aGf5-$YFS
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HcmV?d00001
diff --git a/loto/loto.runs/impl_1/loto_clock_utilization_routed.rpt b/loto/loto.runs/impl_1/loto_clock_utilization_routed.rpt
new file mode 100644
index 0000000..05fe270
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_clock_utilization_routed.rpt
@@ -0,0 +1,242 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:25:00 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_clock_utilization -file loto_clock_utilization_routed.rpt
+| Design : loto
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Local Clock Details
+5. Clock Regions: Key Resource Utilization
+6. Clock Regions : Global Clock Summary
+7. Device Cell Placement Summary for Global Clock g0
+8. Device Cell Placement Summary for Global Clock g1
+9. Clock Region Cell Placement per Global Clock: Region X0Y1
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+11. Clock Region Cell Placement per Global Clock: Region X0Y2
+12. Clock Region Cell Placement per Global Clock: Region X1Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 96 | 0 | 0 | 0 |
+| BUFIO | 0 | 24 | 0 | 0 | 0 |
+| BUFMR | 0 | 12 | 0 | 0 | 0 |
+| BUFR | 0 | 24 | 0 | 0 | 0 |
+| MMCM | 0 | 6 | 0 | 0 | 0 |
+| PLL | 0 | 6 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-----------------------------+----------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-----------------------------+----------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 4 | 60 | 1 | | | SC_clk_BUFG_inst/O | SC_clk_BUFG |
+| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 26 | 0 | 10.000 | sys_clk_pin | I_clk_100m_IBUF_BUFG_inst/O | I_clk_100m_IBUF_BUFG |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-----------------------------+----------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+------------------------+
+| src0 | g0 | FDCE/Q | None | SLICE_X52Y96 | X1Y1 | 1 | 0 | | | diviseur_freq_1/SR_counter_reg[15]/Q | diviseur_freq_1/out[0] |
+| src1 | g1 | IBUF/O | IOB_X1Y126 | IOB_X1Y126 | X1Y2 | 1 | 0 | 10.000 | sys_clk_pin | I_clk_100m_IBUF_inst/O | I_clk_100m_IBUF |
++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Local Clock Details
+----------------------
+
++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------------------------+------------------------+
+| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------------------------+------------------------+
+| 0 | FDCE/Q | None | SLICE_X52Y99/BFF | X1Y1 | 3 | 3 | | | diviseur_freq_1/SR_counter_reg[25]/Q | diviseur_freq_1/out[1] |
++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------------------------+------------------------+
+* Local Clocks in this context represents only clocks driven by non-global buffers
+** Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+*** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+5. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 39 | 1900 | 3 | 650 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 6 | 2000 | 3 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 43 | 1900 | 10 | 650 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+6. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y3 | 0 | 0 |
+| Y2 | 0 | 0 |
+| Y1 | 0 | 0 |
+| Y0 | 0 | 0 |
++----+----+----+
+
+
+7. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+| g0 | BUFG/O | n/a | | | | 61 | 0 | 0 | 0 | SC_clk_BUFG |
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+-----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+-----+-----------------------+
+| Y3 | 0 | 0 | - |
+| Y2 | 6 | 43 | 0 |
+| Y1 | 1 | 11 | 0 |
+| Y0 | 0 | 0 | - |
++----+----+-----+-----------------------+
+
+
+8. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
+| g1 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | 26 | 0 | 0 | 0 | I_clk_100m_IBUF_BUFG |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+-----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+-----+-----------------------+
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 0 | - |
+| Y1 | 0 | 26 | 0 |
+| Y0 | 0 | 0 | - |
++----+----+-----+-----------------------+
+
+
+9. Clock Region Cell Placement per Global Clock: Region X0Y1
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+| g0 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SC_clk_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+| g0 | n/a | BUFG/O | None | 10 | 1 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SC_clk_BUFG |
+| g1 | n/a | BUFG/O | None | 26 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | I_clk_100m_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+11. Clock Region Cell Placement per Global Clock: Region X0Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+| g0 | n/a | BUFG/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SC_clk_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+12. Clock Region Cell Placement per Global Clock: Region X1Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+| g0 | n/a | BUFG/O | None | 43 | 0 | 43 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SC_clk_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y0 [get_cells SC_clk_BUFG_inst]
+set_property LOC BUFGCTRL_X0Y16 [get_cells I_clk_100m_IBUF_BUFG_inst]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y126 [get_ports I_clk_100m]
+
+# Clock net "SC_clk_BUFG" driven by instance "SC_clk_BUFG_inst" located at site "BUFGCTRL_X0Y0"
+#startgroup
+create_pblock {CLKAG_SC_clk_BUFG}
+add_cells_to_pblock [get_pblocks {CLKAG_SC_clk_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="SC_clk_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_SC_clk_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
+#endgroup
+
+# Clock net "I_clk_100m_IBUF_BUFG" driven by instance "I_clk_100m_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
+#startgroup
+create_pblock {CLKAG_I_clk_100m_IBUF_BUFG}
+add_cells_to_pblock [get_pblocks {CLKAG_I_clk_100m_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="I_clk_100m_IBUF_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_I_clk_100m_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
+#endgroup
diff --git a/loto/loto.runs/impl_1/loto_control_sets_placed.rpt b/loto/loto.runs/impl_1/loto_control_sets_placed.rpt
new file mode 100644
index 0000000..7b59b46
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_control_sets_placed.rpt
@@ -0,0 +1,88 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:24:35 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_control_sets -verbose -file loto_control_sets_placed.rpt
+| Design : loto
+| Device : xc7a100t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 10 |
+| Minimum number of control sets | 10 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 31 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 10 |
+| >= 0 to < 4 | 1 |
+| >= 4 to < 6 | 0 |
+| >= 6 to < 8 | 7 |
+| >= 8 to < 10 | 0 |
+| >= 10 to < 12 | 0 |
+| >= 12 to < 14 | 0 |
+| >= 14 to < 16 | 0 |
+| >= 16 | 2 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 0 | 0 |
+| No | No | Yes | 47 | 15 |
+| No | Yes | No | 0 | 0 |
+| Yes | No | No | 0 | 0 |
+| Yes | No | Yes | 42 | 13 |
+| Yes | Yes | No | 0 | 0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++-------------------------+--------------------------------------------------+------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++-------------------------+--------------------------------------------------+------------------+------------------+----------------+--------------+
+| diviseur_freq_1/out[1] | | I_rst_IBUF | 1 | 3 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[2]_1[0] | I_rst_IBUF | 1 | 6 | 6.00 |
+| SC_clk_BUFG | tirage_1/automate_1/E[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/E[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[0]_0[0] | I_rst_IBUF | 3 | 6 | 2.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[1]_0[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[1]_1[0] | I_rst_IBUF | 1 | 6 | 6.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[2]_0[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | | I_rst_IBUF | 7 | 18 | 2.57 |
+| I_clk_100m_IBUF_BUFG | | I_rst_IBUF | 7 | 26 | 3.71 |
++-------------------------+--------------------------------------------------+------------------+------------------+----------------+--------------+
+
+
diff --git a/loto/loto.runs/impl_1/loto_drc_opted.pb b/loto/loto.runs/impl_1/loto_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
GIT binary patch
literal 37
scmd;LGcqtV(KDRH%<U57tPqr1T$)o-e1M1Hfe=H3B*OxE#sjJh0Ia$Rz5oCK
literal 0
HcmV?d00001
diff --git a/loto/loto.runs/impl_1/loto_drc_opted.rpt b/loto/loto.runs/impl_1/loto_drc_opted.rpt
new file mode 100644
index 0000000..3c54560
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:24:31 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/loto/loto.runs/impl_1/loto_drc_opted.rpx b/loto/loto.runs/impl_1/loto_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..19b93ae59f3aadce0d167580f56b71b7679ac61e
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diff --git a/loto/loto.runs/impl_1/loto_drc_routed.pb b/loto/loto.runs/impl_1/loto_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
GIT binary patch
literal 37
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literal 0
HcmV?d00001
diff --git a/loto/loto.runs/impl_1/loto_drc_routed.rpt b/loto/loto.runs/impl_1/loto_drc_routed.rpt
new file mode 100644
index 0000000..ac6e279
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_drc_routed.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:24:59 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/loto/loto.runs/impl_1/loto_drc_routed.rpx b/loto/loto.runs/impl_1/loto_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..433ced1d950e8da2e0f5545e4ab06e472e48d209
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/loto/loto.runs/impl_1/loto_io_placed.rpt b/loto/loto.runs/impl_1/loto_io_placed.rpt
new file mode 100644
index 0000000..a15b971
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_io_placed.rpt
@@ -0,0 +1,366 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:24:35 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_io -file loto_io_placed.rpt
+| Design : loto
+| Device : xc7a100t
+| Speed File : -1
+| Package : csg324
+| Package Version : FINAL 2012-07-17
+| Package Pin Delay Version : VERS. 2.0 2012-07-17
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 21 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+----------------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+----------------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
+| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | I_clk_100m | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E16 | I_button | High Range | IO_L11N_T1_SRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | O_green | High Range | IO_L24P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | O_7segmentDisplay[4] | High Range | IO_L2P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| K5 | O_red | High Range | IO_L5P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L1 | O_7segmentSelect[6] | High Range | IO_L1P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | O_7segmentDisplay[0] | High Range | IO_L2N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L4 | O_7segmentDisplay[3] | High Range | IO_L5N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L5 | O_7segmentDisplay[2] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L6 | O_7segmentDisplay[6] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M1 | O_7segmentSelect[7] | High Range | IO_L1N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M2 | O_7segmentDisplay[5] | High Range | IO_L4N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M3 | O_7segmentSelect[2] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M6 | O_7segmentSelect[1] | High Range | IO_L18P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N1 | O_7segmentDisplay[1] | High Range | IO_L3N_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N2 | O_7segmentSelect[4] | High Range | IO_L3P_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| N4 | O_7segmentSelect[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N5 | O_7segmentSelect[3] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N6 | O_7segmentSelect[0] | High Range | IO_L18N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P4 | I_block | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V10 | I_rst | High Range | IO_L21P_T3_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
+| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
++------------+----------------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/loto/loto.runs/impl_1/loto_methodology_drc_routed.pb b/loto/loto.runs/impl_1/loto_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..f66a4238534222d6a9fd3a8e4ef5b4622c10c0a1
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpt b/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpt
new file mode 100644
index 0000000..cbeec55
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpt
@@ -0,0 +1,356 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:25:00 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 64
++-----------+------------------+-------------------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+------------------+-------------------------------+------------+
+| TIMING-17 | Critical Warning | Non-clocked sequential cell | 63 |
+| TIMING-18 | Warning | Missing input or output delay | 1 |
++-----------+------------------+-------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-17#1 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo4_2/SR_Counter_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#2 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo4_2/SR_Counter_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#3 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo6_1/SR_Counter_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#4 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo6_1/SR_Counter_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#5 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo6_1/SR_Counter_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#6 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#7 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/FSM_sequential_SR_STATE_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#8 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#9 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_counting_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#10 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_l_green_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#11 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_l_red_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#12 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_store_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#13 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#14 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#15 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#16 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#17 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#18 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#19 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_valid_1/SR_Counter_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#20 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_valid_1/SR_Counter_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#21 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_valid_1/SR_Counter_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#22 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#23 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#24 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#25 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#26 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#27 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#28 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#29 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#30 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#31 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#32 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#33 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#34 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#35 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#36 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#37 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#38 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#39 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#40 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#41 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#42 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#43 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#44 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#45 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#46 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#47 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#48 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#49 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#50 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#51 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#52 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#53 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#54 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#55 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#56 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#57 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#58 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#59 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#60 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#61 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#62 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#63 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-18#1 Warning
+Missing input or output delay
+An input delay is missing on I_rst relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+
diff --git a/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpx b/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpx
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diff --git a/loto/loto.runs/impl_1/loto_opt.dcp b/loto/loto.runs/impl_1/loto_opt.dcp
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diff --git a/loto/loto.runs/impl_1/loto_power_routed.rpt b/loto/loto.runs/impl_1/loto_power_routed.rpt
new file mode 100644
index 0000000..870d969
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_power_routed.rpt
@@ -0,0 +1,148 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:25:00 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 0.131 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 0.034 |
+| Device Static (W) | 0.097 |
+| Effective TJA (C/W) | 4.6 |
+| Max Ambient (C) | 84.4 |
+| Junction Temperature (C) | 25.6 |
+| Confidence Level | Low |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks | <0.001 | 3 | --- | --- |
+| Slice Logic | <0.001 | 198 | --- | --- |
+| LUT as Logic | <0.001 | 72 | 63400 | 0.11 |
+| Register | <0.001 | 89 | 126800 | 0.07 |
+| CARRY4 | <0.001 | 7 | 15850 | 0.04 |
+| BUFG | <0.001 | 1 | 32 | 3.13 |
+| Others | 0.000 | 8 | --- | --- |
+| Signals | 0.001 | 167 | --- | --- |
+| I/O | 0.032 | 21 | 210 | 10.00 |
+| Static Power | 0.097 | | | |
+| Total | 0.131 | | | |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.017 | 0.002 | 0.015 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.019 | 0.001 | 0.018 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.013 | 0.009 | 0.004 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
+| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Low | | |
++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 4.6 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------------+------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++-------------+------------+-----------------+
+| sys_clk_pin | I_clk_100m | 10.0 |
++-------------+------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++------------+-----------+
+| Name | Power (W) |
++------------+-----------+
+| loto | 0.034 |
+| tirage_1 | 0.001 |
++------------+-----------+
+
+
diff --git a/loto/loto.runs/impl_1/loto_power_routed.rpx b/loto/loto.runs/impl_1/loto_power_routed.rpx
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diff --git a/loto/loto.runs/impl_1/loto_route_status.rpt b/loto/loto.runs/impl_1/loto_route_status.rpt
new file mode 100644
index 0000000..1420bf3
--- /dev/null
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@@ -0,0 +1,11 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 243 :
+ # of nets not needing routing.......... : 72 :
+ # of internally routed nets........ : 72 :
+ # of routable nets..................... : 171 :
+ # of fully routed nets............. : 171 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
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diff --git a/loto/loto.runs/impl_1/loto_timing_summary_routed.pb b/loto/loto.runs/impl_1/loto_timing_summary_routed.pb
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diff --git a/loto/loto.runs/impl_1/loto_timing_summary_routed.rpt b/loto/loto.runs/impl_1/loto_timing_summary_routed.rpt
new file mode 100644
index 0000000..393530e
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_timing_summary_routed.rpt
@@ -0,0 +1,2807 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:25:00 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation
+| Design : loto
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+ Inter-SLR Compensation : Conservative
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule Severity Description Violations
+--------- ---------------- ----------------------------- ----------
+TIMING-17 Critical Warning Non-clocked sequential cell 63
+TIMING-18 Warning Missing input or output delay 1
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (63)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (168)
+5. checking no_input_delay (3)
+6. checking no_output_delay (13)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (63)
+-------------------------
+ There are 60 register/latch pins with no clock driven by root clock pin: diviseur_freq_1/SR_counter_reg[15]/Q (HIGH)
+
+ There are 3 register/latch pins with no clock driven by root clock pin: diviseur_freq_1/SR_counter_reg[25]/Q (HIGH)
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (168)
+--------------------------------------------------
+ There are 168 pins that are not constrained for maximum delay. (HIGH)
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (3)
+------------------------------
+ There are 3 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (13)
+--------------------------------
+ There are 13 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 6.012 0.000 0 26 0.324 0.000 0 26 4.500 0.000 0 27
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+sys_clk_pin {0.000 5.000} 10.000 100.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+sys_clk_pin 6.012 0.000 0 26 0.324 0.000 0 26 4.500 0.000 0 27
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock
+---------- ---------- --------
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock
+---------- ---------- --------
+(none)
+(none) sys_clk_pin
+(none) sys_clk_pin
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: sys_clk_pin
+ To Clock: sys_clk_pin
+
+Setup : 0 Failing Endpoints, Worst Slack 6.012ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.324ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 6.012ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[25]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.991ns (logic 1.639ns (41.068%) route 2.352ns (58.932%))
+ Logic Levels: 5 (BUFG=1 CARRY4=4)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.771 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.771 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X52Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.885 r diviseur_freq_1/SR_counter_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.885 diviseur_freq_1/SR_counter_reg[20]_i_1_n_0
+ SLICE_X52Y99 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 9.219 r diviseur_freq_1/SR_counter_reg[24]_i_1/O[1]
+ net (fo=1, routed) 0.000 9.219 diviseur_freq_1/SR_counter_reg[24]_i_1_n_6
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y99 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[25]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -9.219
+ -------------------------------------------------------------------
+ slack 6.012
+
+Slack (MET) : 6.123ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[24]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.880ns (logic 1.528ns (39.382%) route 2.352ns (60.618%))
+ Logic Levels: 5 (BUFG=1 CARRY4=4)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.771 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.771 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X52Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.885 r diviseur_freq_1/SR_counter_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.885 diviseur_freq_1/SR_counter_reg[20]_i_1_n_0
+ SLICE_X52Y99 CARRY4 (Prop_carry4_CI_O[0])
+ 0.223 9.108 r diviseur_freq_1/SR_counter_reg[24]_i_1/O[0]
+ net (fo=1, routed) 0.000 9.108 diviseur_freq_1/SR_counter_reg[24]_i_1_n_7
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[24]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[24]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y99 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[24]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -9.108
+ -------------------------------------------------------------------
+ slack 6.123
+
+Slack (MET) : 6.126ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[21]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.877ns (logic 1.525ns (39.335%) route 2.352ns (60.665%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.771 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.771 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X52Y98 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 9.105 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[1]
+ net (fo=1, routed) 0.000 9.105 diviseur_freq_1/SR_counter_reg[20]_i_1_n_6
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[21]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[21]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y98 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[21]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -9.105
+ -------------------------------------------------------------------
+ slack 6.126
+
+Slack (MET) : 6.147ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[23]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.856ns (logic 1.504ns (39.004%) route 2.352ns (60.996%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.771 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.771 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X52Y98 CARRY4 (Prop_carry4_CI_O[3])
+ 0.313 9.084 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[3]
+ net (fo=1, routed) 0.000 9.084 diviseur_freq_1/SR_counter_reg[20]_i_1_n_4
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[23]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y98 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[23]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -9.084
+ -------------------------------------------------------------------
+ slack 6.147
+
+Slack (MET) : 6.221ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[22]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.782ns (logic 1.430ns (37.811%) route 2.352ns (62.189%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.771 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.771 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X52Y98 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 9.010 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[2]
+ net (fo=1, routed) 0.000 9.010 diviseur_freq_1/SR_counter_reg[20]_i_1_n_5
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[22]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[22]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y98 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[22]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -9.010
+ -------------------------------------------------------------------
+ slack 6.221
+
+Slack (MET) : 6.237ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[20]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.766ns (logic 1.414ns (37.547%) route 2.352ns (62.453%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.771 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.771 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X52Y98 CARRY4 (Prop_carry4_CI_O[0])
+ 0.223 8.994 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[0]
+ net (fo=1, routed) 0.000 8.994 diviseur_freq_1/SR_counter_reg[20]_i_1_n_7
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[20]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[20]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y98 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[20]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -8.994
+ -------------------------------------------------------------------
+ slack 6.237
+
+Slack (MET) : 6.240ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[17]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.763ns (logic 1.411ns (37.497%) route 2.352ns (62.503%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 8.991 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[1]
+ net (fo=1, routed) 0.000 8.991 diviseur_freq_1/SR_counter_reg[16]_i_1_n_6
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[17]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y97 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[17]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -8.991
+ -------------------------------------------------------------------
+ slack 6.240
+
+Slack (MET) : 6.261ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[19]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.742ns (logic 1.390ns (37.146%) route 2.352ns (62.854%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_O[3])
+ 0.313 8.970 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[3]
+ net (fo=1, routed) 0.000 8.970 diviseur_freq_1/SR_counter_reg[16]_i_1_n_4
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y97 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[19]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -8.970
+ -------------------------------------------------------------------
+ slack 6.261
+
+Slack (MET) : 6.335ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[18]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.668ns (logic 1.316ns (35.878%) route 2.352ns (64.122%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 8.896 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[2]
+ net (fo=1, routed) 0.000 8.896 diviseur_freq_1/SR_counter_reg[16]_i_1_n_5
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[18]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y97 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[18]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -8.896
+ -------------------------------------------------------------------
+ slack 6.335
+
+Slack (MET) : 6.351ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[16]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.652ns (logic 1.300ns (35.597%) route 2.352ns (64.403%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.024ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns = ( 14.928 - 10.000 )
+ Source Clock Delay (SCD): 5.228ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.625 5.228 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.456 5.684 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.570 6.254 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.350 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.132 diviseur_freq_1/CLK
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.657 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.657 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X52Y97 CARRY4 (Prop_carry4_CI_O[0])
+ 0.223 8.880 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[0]
+ net (fo=1, routed) 0.000 8.880 diviseur_freq_1/SR_counter_reg[16]_i_1_n_7
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[16]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 14.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[16]/C
+ clock pessimism 0.276 15.204
+ clock uncertainty -0.035 15.168
+ SLICE_X52Y97 FDCE (Setup_fdce_C_D) 0.062 15.230 diviseur_freq_1/SR_counter_reg[16]
+ -------------------------------------------------------------------
+ required time 15.230
+ arrival time -8.880
+ -------------------------------------------------------------------
+ slack 6.351
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.324ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[0]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.429ns (logic 0.256ns (59.730%) route 0.173ns (40.270%))
+ Logic Levels: 2 (CARRY4=1 LUT1=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 1.483ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.564 1.483 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.141 1.624 f diviseur_freq_1/SR_counter_reg[0]/Q
+ net (fo=1, routed) 0.173 1.797 diviseur_freq_1/SR_counter_reg_n_0_[0]
+ SLICE_X52Y93 LUT1 (Prop_lut1_I0_O) 0.045 1.842 r diviseur_freq_1/SR_counter[0]_i_2/O
+ net (fo=1, routed) 0.000 1.842 diviseur_freq_1/SR_counter[0]_i_2_n_0
+ SLICE_X52Y93 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.070 1.912 r diviseur_freq_1/SR_counter_reg[0]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.912 diviseur_freq_1/SR_counter_reg[0]_i_1_n_7
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[0]/C
+ clock pessimism -0.515 1.483
+ SLICE_X52Y93 FDCE (Hold_fdce_C_D) 0.105 1.588 diviseur_freq_1/SR_counter_reg[0]
+ -------------------------------------------------------------------
+ required time -1.588
+ arrival time 1.912
+ -------------------------------------------------------------------
+ slack 0.324
+
+Slack (MET) : 0.327ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[11]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[11]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.249ns (57.658%) route 0.183ns (42.342%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 1.483ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.564 1.483 diviseur_freq_1/I15
+ SLICE_X52Y95 FDCE r diviseur_freq_1/SR_counter_reg[11]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y95 FDCE (Prop_fdce_C_Q) 0.141 1.624 r diviseur_freq_1/SR_counter_reg[11]/Q
+ net (fo=1, routed) 0.183 1.807 diviseur_freq_1/SR_counter_reg_n_0_[11]
+ SLICE_X52Y95 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.915 r diviseur_freq_1/SR_counter_reg[8]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.915 diviseur_freq_1/SR_counter_reg[8]_i_1_n_4
+ SLICE_X52Y95 FDCE r diviseur_freq_1/SR_counter_reg[11]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y95 FDCE r diviseur_freq_1/SR_counter_reg[11]/C
+ clock pessimism -0.515 1.483
+ SLICE_X52Y95 FDCE (Hold_fdce_C_D) 0.105 1.588 diviseur_freq_1/SR_counter_reg[11]
+ -------------------------------------------------------------------
+ required time -1.588
+ arrival time 1.915
+ -------------------------------------------------------------------
+ slack 0.327
+
+Slack (MET) : 0.327ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[19]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[19]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.249ns (57.658%) route 0.183ns (42.342%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y97 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[19]/Q
+ net (fo=1, routed) 0.183 1.808 diviseur_freq_1/SR_counter_reg_n_0_[19]
+ SLICE_X52Y97 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.916 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.916 diviseur_freq_1/SR_counter_reg[16]_i_1_n_4
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+ clock pessimism -0.515 1.484
+ SLICE_X52Y97 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[19]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.916
+ -------------------------------------------------------------------
+ slack 0.327
+
+Slack (MET) : 0.327ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[3]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.249ns (57.658%) route 0.183ns (42.342%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 1.483ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.564 1.483 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.141 1.624 r diviseur_freq_1/SR_counter_reg[3]/Q
+ net (fo=1, routed) 0.183 1.807 diviseur_freq_1/SR_counter_reg_n_0_[3]
+ SLICE_X52Y93 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.915 r diviseur_freq_1/SR_counter_reg[0]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.915 diviseur_freq_1/SR_counter_reg[0]_i_1_n_4
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[3]/C
+ clock pessimism -0.515 1.483
+ SLICE_X52Y93 FDCE (Hold_fdce_C_D) 0.105 1.588 diviseur_freq_1/SR_counter_reg[3]
+ -------------------------------------------------------------------
+ required time -1.588
+ arrival time 1.915
+ -------------------------------------------------------------------
+ slack 0.327
+
+Slack (MET) : 0.327ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.249ns (57.658%) route 0.183ns (42.342%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 1.483ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.564 1.483 diviseur_freq_1/I15
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y94 FDCE (Prop_fdce_C_Q) 0.141 1.624 r diviseur_freq_1/SR_counter_reg[7]/Q
+ net (fo=1, routed) 0.183 1.807 diviseur_freq_1/SR_counter_reg_n_0_[7]
+ SLICE_X52Y94 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.915 r diviseur_freq_1/SR_counter_reg[4]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.915 diviseur_freq_1/SR_counter_reg[4]_i_1_n_4
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[7]/C
+ clock pessimism -0.515 1.483
+ SLICE_X52Y94 FDCE (Hold_fdce_C_D) 0.105 1.588 diviseur_freq_1/SR_counter_reg[7]
+ -------------------------------------------------------------------
+ required time -1.588
+ arrival time 1.915
+ -------------------------------------------------------------------
+ slack 0.327
+
+Slack (MET) : 0.360ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[1]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.465ns (logic 0.292ns (62.850%) route 0.173ns (37.150%))
+ Logic Levels: 2 (CARRY4=1 LUT1=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 1.483ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.564 1.483 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.141 1.624 f diviseur_freq_1/SR_counter_reg[0]/Q
+ net (fo=1, routed) 0.173 1.797 diviseur_freq_1/SR_counter_reg_n_0_[0]
+ SLICE_X52Y93 LUT1 (Prop_lut1_I0_O) 0.045 1.842 r diviseur_freq_1/SR_counter[0]_i_2/O
+ net (fo=1, routed) 0.000 1.842 diviseur_freq_1/SR_counter[0]_i_2_n_0
+ SLICE_X52Y93 CARRY4 (Prop_carry4_S[0]_O[1])
+ 0.106 1.948 r diviseur_freq_1/SR_counter_reg[0]_i_1/O[1]
+ net (fo=1, routed) 0.000 1.948 diviseur_freq_1/SR_counter_reg[0]_i_1_n_6
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[1]/C
+ clock pessimism -0.515 1.483
+ SLICE_X52Y93 FDCE (Hold_fdce_C_D) 0.105 1.588 diviseur_freq_1/SR_counter_reg[1]
+ -------------------------------------------------------------------
+ required time -1.588
+ arrival time 1.948
+ -------------------------------------------------------------------
+ slack 0.360
+
+Slack (MET) : 0.372ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[23]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[23]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.477ns (logic 0.249ns (52.216%) route 0.228ns (47.784%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y98 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[23]/Q
+ net (fo=1, routed) 0.228 1.853 diviseur_freq_1/SR_counter_reg_n_0_[23]
+ SLICE_X52Y98 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.961 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.961 diviseur_freq_1/SR_counter_reg[20]_i_1_n_4
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[23]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ clock pessimism -0.515 1.484
+ SLICE_X52Y98 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[23]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.961
+ -------------------------------------------------------------------
+ slack 0.372
+
+Slack (MET) : 0.373ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[12]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[12]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.478ns (logic 0.256ns (53.516%) route 0.222ns (46.484%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 1.483ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.564 1.483 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[12]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y96 FDCE (Prop_fdce_C_Q) 0.141 1.624 r diviseur_freq_1/SR_counter_reg[12]/Q
+ net (fo=1, routed) 0.222 1.847 diviseur_freq_1/SR_counter_reg_n_0_[12]
+ SLICE_X52Y96 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.115 1.962 r diviseur_freq_1/SR_counter_reg[12]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.962 diviseur_freq_1/SR_counter_reg[12]_i_1_n_7
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[12]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y96 FDCE r diviseur_freq_1/SR_counter_reg[12]/C
+ clock pessimism -0.515 1.483
+ SLICE_X52Y96 FDCE (Hold_fdce_C_D) 0.105 1.588 diviseur_freq_1/SR_counter_reg[12]
+ -------------------------------------------------------------------
+ required time -1.588
+ arrival time 1.962
+ -------------------------------------------------------------------
+ slack 0.373
+
+Slack (MET) : 0.373ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[16]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[16]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.478ns (logic 0.256ns (53.516%) route 0.222ns (46.484%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[16]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y97 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[16]/Q
+ net (fo=1, routed) 0.222 1.848 diviseur_freq_1/SR_counter_reg_n_0_[16]
+ SLICE_X52Y97 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.115 1.963 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.963 diviseur_freq_1/SR_counter_reg[16]_i_1_n_7
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[16]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[16]/C
+ clock pessimism -0.515 1.484
+ SLICE_X52Y97 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[16]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.963
+ -------------------------------------------------------------------
+ slack 0.373
+
+Slack (MET) : 0.373ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[20]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[20]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.478ns (logic 0.256ns (53.516%) route 0.222ns (46.484%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[20]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y98 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[20]/Q
+ net (fo=1, routed) 0.222 1.848 diviseur_freq_1/SR_counter_reg_n_0_[20]
+ SLICE_X52Y98 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.115 1.963 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.963 diviseur_freq_1/SR_counter_reg[20]_i_1_n_7
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[20]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[20]/C
+ clock pessimism -0.515 1.484
+ SLICE_X52Y98 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[20]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.963
+ -------------------------------------------------------------------
+ slack 0.373
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: sys_clk_pin
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { I_clk_100m }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y16 I_clk_100m_IBUF_BUFG_inst/I
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y93 diviseur_freq_1/SR_counter_reg[0]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[10]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[11]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[12]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[13]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[14]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[15]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y97 diviseur_freq_1/SR_counter_reg[16]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X52Y97 diviseur_freq_1/SR_counter_reg[17]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y93 diviseur_freq_1/SR_counter_reg[0]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y93 diviseur_freq_1/SR_counter_reg[0]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[10]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[10]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[11]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[11]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[12]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[12]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[13]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[13]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y93 diviseur_freq_1/SR_counter_reg[0]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y93 diviseur_freq_1/SR_counter_reg[0]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[10]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[10]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[11]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y95 diviseur_freq_1/SR_counter_reg[11]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[12]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[12]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[13]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X52Y96 diviseur_freq_1/SR_counter_reg[13]/C
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock:
+ To Clock:
+
+Max Delay 181 Endpoints
+Min Delay 181 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.220ns (logic 4.704ns (38.495%) route 7.516ns (61.505%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.195 4.105 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X55Y98 LUT5 (Prop_lut5_I4_O) 0.152 4.257 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2/O
+ net (fo=3, routed) 0.980 5.237 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2_n_0
+ SLICE_X55Y97 LUT6 (Prop_lut6_I1_O) 0.326 5.563 r tirage_1/registres_2/O_7segmentDisplay_OBUF[0]_inst_i_1/O
+ net (fo=1, routed) 3.135 8.698 O_7segmentDisplay_OBUF[0]
+ L3 OBUF (Prop_obuf_I_O) 3.522 12.220 r O_7segmentDisplay_OBUF[0]_inst/O
+ net (fo=0) 0.000 12.220 O_7segmentDisplay[0]
+ L3 r O_7segmentDisplay[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.023ns (logic 4.706ns (39.141%) route 7.317ns (60.859%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.195 4.105 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X55Y98 LUT5 (Prop_lut5_I4_O) 0.152 4.257 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2/O
+ net (fo=3, routed) 0.985 5.242 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2_n_0
+ SLICE_X55Y97 LUT6 (Prop_lut6_I2_O) 0.326 5.568 r tirage_1/registres_2/O_7segmentDisplay_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 2.932 8.499 O_7segmentDisplay_OBUF[3]
+ L4 OBUF (Prop_obuf_I_O) 3.524 12.023 r O_7segmentDisplay_OBUF[3]_inst/O
+ net (fo=0) 0.000 12.023 O_7segmentDisplay[3]
+ L4 r O_7segmentDisplay[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[4]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.907ns (logic 4.727ns (39.698%) route 7.180ns (60.302%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.006 3.916 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X54Y99 LUT5 (Prop_lut5_I4_O) 0.152 4.068 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5/O
+ net (fo=3, routed) 0.984 5.052 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5_n_0
+ SLICE_X54Y97 LUT6 (Prop_lut6_I0_O) 0.348 5.400 r tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_1/O
+ net (fo=1, routed) 2.984 8.384 O_7segmentDisplay_OBUF[4]
+ K3 OBUF (Prop_obuf_I_O) 3.523 11.907 r O_7segmentDisplay_OBUF[4]_inst/O
+ net (fo=0) 0.000 11.907 O_7segmentDisplay[4]
+ K3 r O_7segmentDisplay[4] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[5]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.863ns (logic 4.484ns (37.796%) route 7.379ns (62.204%))
+ Logic Levels: 6 (FDCE=1 LUT5=2 LUT6=2 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.195 4.105 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X55Y98 LUT5 (Prop_lut5_I0_O) 0.124 4.229 r tirage_1/registres_2/O_7segmentDisplay_OBUF[5]_inst_i_3/O
+ net (fo=1, routed) 0.936 5.165 tirage_1/registres_2/O_7segmentDisplay_OBUF[5]_inst_i_3_n_0
+ SLICE_X55Y99 LUT5 (Prop_lut5_I3_O) 0.124 5.289 r tirage_1/registres_2/O_7segmentDisplay_OBUF[5]_inst_i_1/O
+ net (fo=1, routed) 3.042 8.331 O_7segmentDisplay_OBUF[5]
+ M2 OBUF (Prop_obuf_I_O) 3.532 11.863 r O_7segmentDisplay_OBUF[5]_inst/O
+ net (fo=0) 0.000 11.863 O_7segmentDisplay[5]
+ M2 r O_7segmentDisplay[5] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[6]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.851ns (logic 4.727ns (39.885%) route 7.124ns (60.115%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.006 3.916 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X54Y99 LUT5 (Prop_lut5_I4_O) 0.152 4.068 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5/O
+ net (fo=3, routed) 1.003 5.071 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5_n_0
+ SLICE_X54Y97 LUT6 (Prop_lut6_I4_O) 0.348 5.419 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_1/O
+ net (fo=1, routed) 2.910 8.328 O_7segmentDisplay_OBUF[6]
+ L6 OBUF (Prop_obuf_I_O) 3.523 11.851 r O_7segmentDisplay_OBUF[6]_inst/O
+ net (fo=0) 0.000 11.851 O_7segmentDisplay[6]
+ L6 r O_7segmentDisplay[6] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[2]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.520ns (logic 4.462ns (38.734%) route 7.058ns (61.266%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.006 3.916 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X54Y99 LUT5 (Prop_lut5_I1_O) 0.124 4.040 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_4/O
+ net (fo=4, routed) 0.613 4.653 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_4_n_0
+ SLICE_X54Y98 LUT6 (Prop_lut6_I0_O) 0.124 4.777 r tirage_1/registres_2/O_7segmentDisplay_OBUF[2]_inst_i_1/O
+ net (fo=1, routed) 3.233 8.010 O_7segmentDisplay_OBUF[2]
+ L5 OBUF (Prop_obuf_I_O) 3.510 11.520 r O_7segmentDisplay_OBUF[2]_inst/O
+ net (fo=0) 0.000 11.520 O_7segmentDisplay[2]
+ L5 r O_7segmentDisplay[2] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/registres_2/O_reg2_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.428ns (logic 4.737ns (41.451%) route 6.691ns (58.549%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE 0.000 0.000 r tirage_1/registres_2/O_reg2_reg[2]/C
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 0.456 r tirage_1/registres_2/O_reg2_reg[2]/Q
+ net (fo=2, routed) 1.388 1.844 tirage_1/registres_2/O_reg2[2]
+ SLICE_X52Y101 LUT6 (Prop_lut6_I1_O) 0.124 1.968 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19/O
+ net (fo=1, routed) 0.818 2.786 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_19_n_0
+ SLICE_X54Y100 LUT6 (Prop_lut6_I0_O) 0.124 2.910 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 1.006 3.916 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X54Y99 LUT5 (Prop_lut5_I4_O) 0.152 4.068 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5/O
+ net (fo=3, routed) 0.302 4.370 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5_n_0
+ SLICE_X54Y99 LUT6 (Prop_lut6_I2_O) 0.348 4.718 r tirage_1/registres_2/O_7segmentDisplay_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.177 7.895 O_7segmentDisplay_OBUF[1]
+ N1 OBUF (Prop_obuf_I_O) 3.533 11.428 r O_7segmentDisplay_OBUF[1]_inst/O
+ net (fo=0) 0.000 11.428 O_7segmentDisplay[1]
+ N1 r O_7segmentDisplay[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo4_2/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentSelect[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 8.853ns (logic 4.111ns (46.438%) route 4.742ns (53.562%))
+ Logic Levels: 3 (FDCE=1 LUT2=1 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X53Y97 FDCE 0.000 0.000 r modulo4_2/SR_Counter_reg[0]/C
+ SLICE_X53Y97 FDCE (Prop_fdce_C_Q) 0.456 0.456 f modulo4_2/SR_Counter_reg[0]/Q
+ net (fo=18, routed) 0.856 1.312 modulo4_2/Q[0]
+ SLICE_X55Y97 LUT2 (Prop_lut2_I1_O) 0.124 1.436 r modulo4_2/O_7segmentSelect_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.886 5.322 O_7segmentSelect_OBUF[1]
+ M6 OBUF (Prop_obuf_I_O) 3.531 8.853 r O_7segmentSelect_OBUF[1]_inst/O
+ net (fo=0) 0.000 8.853 O_7segmentSelect[1]
+ M6 r O_7segmentSelect[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo4_2/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentSelect[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 8.683ns (logic 4.107ns (47.292%) route 4.577ns (52.708%))
+ Logic Levels: 3 (FDCE=1 LUT2=1 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X53Y97 FDCE 0.000 0.000 r modulo4_2/SR_Counter_reg[0]/C
+ SLICE_X53Y97 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo4_2/SR_Counter_reg[0]/Q
+ net (fo=18, routed) 0.652 1.108 modulo4_2/Q[0]
+ SLICE_X54Y97 LUT2 (Prop_lut2_I1_O) 0.124 1.232 r modulo4_2/O_7segmentSelect_OBUF[0]_inst_i_1/O
+ net (fo=3, routed) 3.925 5.157 O_7segmentSelect_OBUF[0]
+ N6 OBUF (Prop_obuf_I_O) 3.527 8.683 r O_7segmentSelect_OBUF[0]_inst/O
+ net (fo=0) 0.000 8.683 O_7segmentSelect[0]
+ N6 r O_7segmentSelect[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo4_2/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentSelect[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 8.291ns (logic 4.111ns (49.589%) route 4.180ns (50.411%))
+ Logic Levels: 3 (FDCE=1 LUT2=1 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X53Y97 FDCE 0.000 0.000 r modulo4_2/SR_Counter_reg[0]/C
+ SLICE_X53Y97 FDCE (Prop_fdce_C_Q) 0.456 0.456 f modulo4_2/SR_Counter_reg[0]/Q
+ net (fo=18, routed) 0.649 1.105 modulo4_2/Q[0]
+ SLICE_X54Y97 LUT2 (Prop_lut2_I0_O) 0.124 1.229 r modulo4_2/O_7segmentSelect_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.530 4.760 O_7segmentSelect_OBUF[3]
+ N5 OBUF (Prop_obuf_I_O) 3.531 8.291 r O_7segmentSelect_OBUF[3]_inst/O
+ net (fo=0) 0.000 8.291 O_7segmentSelect[3]
+ N5 r O_7segmentSelect[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[0]/C
+ (rising edge-triggered cell FDPE)
+ Destination: tirage_1/registres_2/O_reg0_reg[0]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.302ns (logic 0.141ns (46.682%) route 0.161ns (53.318%))
+ Logic Levels: 1 (FDPE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDPE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[0]/C
+ SLICE_X52Y100 FDPE (Prop_fdpe_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[0]/Q
+ net (fo=17, routed) 0.161 0.302 tirage_1/registres_2/O_reg1_reg[5]_0[0]
+ SLICE_X55Y101 FDCE r tirage_1/registres_2/O_reg0_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[5]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg3_reg[5]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.303ns (logic 0.141ns (46.583%) route 0.162ns (53.417%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[5]/C
+ SLICE_X52Y100 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[5]/Q
+ net (fo=15, routed) 0.162 0.303 tirage_1/registres_2/O_reg1_reg[5]_0[5]
+ SLICE_X53Y102 FDCE r tirage_1/registres_2/O_reg3_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg2_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.312ns (logic 0.141ns (45.173%) route 0.171ns (54.827%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ SLICE_X52Y100 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[4]/Q
+ net (fo=15, routed) 0.171 0.312 tirage_1/registres_2/O_reg1_reg[5]_0[4]
+ SLICE_X52Y101 FDCE r tirage_1/registres_2/O_reg2_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg1_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.319ns (logic 0.141ns (44.170%) route 0.178ns (55.830%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ SLICE_X52Y100 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[4]/Q
+ net (fo=15, routed) 0.178 0.319 tirage_1/registres_2/O_reg1_reg[5]_0[4]
+ SLICE_X53Y101 FDCE r tirage_1/registres_2/O_reg1_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg4_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.335ns (logic 0.141ns (42.145%) route 0.194ns (57.855%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ SLICE_X52Y100 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[4]/Q
+ net (fo=15, routed) 0.194 0.335 tirage_1/registres_2/O_reg1_reg[5]_0[4]
+ SLICE_X53Y99 FDCE r tirage_1/registres_2/O_reg4_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg5_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.342ns (logic 0.141ns (41.216%) route 0.201ns (58.784%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ SLICE_X52Y100 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[4]/Q
+ net (fo=15, routed) 0.201 0.342 tirage_1/registres_2/O_reg1_reg[5]_0[4]
+ SLICE_X53Y100 FDCE r tirage_1/registres_2/O_reg5_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/led_pwm_1/SR_cpt_leds_reg_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.342ns (logic 0.148ns (43.251%) route 0.194ns (56.749%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X54Y102 FDCE 0.000 0.000 r tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/C
+ SLICE_X54Y102 FDCE (Prop_fdce_C_Q) 0.148 0.148 r tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/Q
+ net (fo=4, routed) 0.194 0.342 tirage_1/led_pwm_1/p_0_in
+ SLICE_X55Y102 FDCE r tirage_1/led_pwm_1/SR_cpt_leds_reg_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.345ns (logic 0.208ns (60.272%) route 0.137ns (39.728%))
+ Logic Levels: 2 (FDCE=1 LUT5=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X54Y102 FDCE 0.000 0.000 r tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/C
+ SLICE_X54Y102 FDCE (Prop_fdce_C_Q) 0.164 0.164 r tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/Q
+ net (fo=2, routed) 0.137 0.301 tirage_1/led_pwm_1/SR_cpt_leds_reg_n_0_[3]
+ SLICE_X54Y102 LUT5 (Prop_lut5_I4_O) 0.044 0.345 r tirage_1/led_pwm_1/SR_cpt_leds[4]_i_1/O
+ net (fo=1, routed) 0.000 0.345 tirage_1/led_pwm_1/plusOp[4]
+ SLICE_X54Y102 FDCE r tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.346ns (logic 0.209ns (60.386%) route 0.137ns (39.614%))
+ Logic Levels: 2 (FDCE=1 LUT4=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X54Y102 FDCE 0.000 0.000 r tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/C
+ SLICE_X54Y102 FDCE (Prop_fdce_C_Q) 0.164 0.164 r tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/Q
+ net (fo=2, routed) 0.137 0.301 tirage_1/led_pwm_1/SR_cpt_leds_reg_n_0_[3]
+ SLICE_X54Y102 LUT4 (Prop_lut4_I0_O) 0.045 0.346 r tirage_1/led_pwm_1/SR_cpt_leds[3]_i_1/O
+ net (fo=1, routed) 0.000 0.346 tirage_1/led_pwm_1/plusOp[3]
+ SLICE_X54Y102 FDCE r tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[3]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg2_reg[3]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.351ns (logic 0.128ns (36.426%) route 0.223ns (63.574%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[3]/C
+ SLICE_X52Y100 FDCE (Prop_fdce_C_Q) 0.128 0.128 r tirage_1/compteur_1/SR_cpt_val_reg[3]/Q
+ net (fo=16, routed) 0.223 0.351 tirage_1/registres_2/O_reg1_reg[5]_0[3]
+ SLICE_X52Y101 FDCE r tirage_1/registres_2/O_reg2_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock: sys_clk_pin
+ To Clock:
+
+Max Delay 2 Endpoints
+Min Delay 2 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 2.478ns (logic 0.704ns (28.410%) route 1.774ns (71.590%))
+ Logic Levels: 2 (LUT5=1 LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.626 5.229 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y99 FDCE (Prop_fdce_C_Q) 0.456 5.685 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 1.330 7.015 tirage_1/automate_1/out[0]
+ SLICE_X52Y103 LUT5 (Prop_lut5_I0_O) 0.124 7.139 r tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_4/O
+ net (fo=1, routed) 0.444 7.583 tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_4_n_0
+ SLICE_X52Y103 LUT6 (Prop_lut6_I4_O) 0.124 7.707 r tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1/O
+ net (fo=1, routed) 0.000 7.707 tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1_n_0
+ SLICE_X52Y103 FDCE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 1.745ns (logic 0.580ns (33.241%) route 1.165ns (66.759%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.626 5.229 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y99 FDCE (Prop_fdce_C_Q) 0.456 5.685 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 1.165 6.850 tirage_1/automate_1/out[0]
+ SLICE_X52Y103 LUT6 (Prop_lut6_I1_O) 0.124 6.974 r tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1/O
+ net (fo=1, routed) 0.000 6.974 tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1_n_0
+ SLICE_X52Y103 FDCE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.609ns (logic 0.186ns (30.551%) route 0.423ns (69.449%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y99 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.423 2.048 tirage_1/automate_1/out[0]
+ SLICE_X52Y103 LUT6 (Prop_lut6_I1_O) 0.045 2.093 r tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1/O
+ net (fo=1, routed) 0.000 2.093 tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1_n_0
+ SLICE_X52Y103 FDCE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.859ns (logic 0.231ns (26.893%) route 0.628ns (73.107%))
+ Logic Levels: 2 (LUT5=1 LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X52Y99 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.482 2.107 tirage_1/automate_1/out[0]
+ SLICE_X52Y103 LUT5 (Prop_lut5_I0_O) 0.045 2.152 r tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_4/O
+ net (fo=1, routed) 0.146 2.298 tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_4_n_0
+ SLICE_X52Y103 LUT6 (Prop_lut6_I4_O) 0.045 2.343 r tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1/O
+ net (fo=1, routed) 0.000 2.343 tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1_n_0
+ SLICE_X52Y103 FDCE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock:
+ To Clock: sys_clk_pin
+
+Max Delay 26 Endpoints
+Min Delay 26 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[24]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.770ns (logic 1.524ns (26.414%) route 4.246ns (73.586%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 4.246 5.770 diviseur_freq_1/AR[0]
+ SLICE_X52Y99 FDCE f diviseur_freq_1/SR_counter_reg[24]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[24]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[25]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.770ns (logic 1.524ns (26.414%) route 4.246ns (73.586%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 4.246 5.770 diviseur_freq_1/AR[0]
+ SLICE_X52Y99 FDCE f diviseur_freq_1/SR_counter_reg[25]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y99 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[20]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.624ns (logic 1.524ns (27.099%) route 4.100ns (72.901%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 4.100 5.624 diviseur_freq_1/AR[0]
+ SLICE_X52Y98 FDCE f diviseur_freq_1/SR_counter_reg[20]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[20]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[21]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.624ns (logic 1.524ns (27.099%) route 4.100ns (72.901%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 4.100 5.624 diviseur_freq_1/AR[0]
+ SLICE_X52Y98 FDCE f diviseur_freq_1/SR_counter_reg[21]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[21]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[22]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.624ns (logic 1.524ns (27.099%) route 4.100ns (72.901%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 4.100 5.624 diviseur_freq_1/AR[0]
+ SLICE_X52Y98 FDCE f diviseur_freq_1/SR_counter_reg[22]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[22]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[23]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.624ns (logic 1.524ns (27.099%) route 4.100ns (72.901%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 4.100 5.624 diviseur_freq_1/AR[0]
+ SLICE_X52Y98 FDCE f diviseur_freq_1/SR_counter_reg[23]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y98 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[16]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.469ns (logic 1.524ns (27.870%) route 3.944ns (72.130%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 3.944 5.469 diviseur_freq_1/AR[0]
+ SLICE_X52Y97 FDCE f diviseur_freq_1/SR_counter_reg[16]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[16]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[17]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.469ns (logic 1.524ns (27.870%) route 3.944ns (72.130%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 3.944 5.469 diviseur_freq_1/AR[0]
+ SLICE_X52Y97 FDCE f diviseur_freq_1/SR_counter_reg[17]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[17]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[18]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.469ns (logic 1.524ns (27.870%) route 3.944ns (72.130%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 3.944 5.469 diviseur_freq_1/AR[0]
+ SLICE_X52Y97 FDCE f diviseur_freq_1/SR_counter_reg[18]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[18]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[19]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.469ns (logic 1.524ns (27.870%) route 3.944ns (72.130%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.928ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.928ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 3.944 5.469 diviseur_freq_1/AR[0]
+ SLICE_X52Y97 FDCE f diviseur_freq_1/SR_counter_reg[19]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.505 4.928 diviseur_freq_1/I15
+ SLICE_X52Y97 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[0]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.763ns (logic 0.292ns (16.531%) route 1.472ns (83.469%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.472 1.763 diviseur_freq_1/AR[0]
+ SLICE_X52Y93 FDCE f diviseur_freq_1/SR_counter_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[0]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[1]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.763ns (logic 0.292ns (16.531%) route 1.472ns (83.469%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.472 1.763 diviseur_freq_1/AR[0]
+ SLICE_X52Y93 FDCE f diviseur_freq_1/SR_counter_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[1]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[2]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.763ns (logic 0.292ns (16.531%) route 1.472ns (83.469%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.472 1.763 diviseur_freq_1/AR[0]
+ SLICE_X52Y93 FDCE f diviseur_freq_1/SR_counter_reg[2]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[2]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[3]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.763ns (logic 0.292ns (16.531%) route 1.472ns (83.469%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.472 1.763 diviseur_freq_1/AR[0]
+ SLICE_X52Y93 FDCE f diviseur_freq_1/SR_counter_reg[3]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y93 FDCE r diviseur_freq_1/SR_counter_reg[3]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[4]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.827ns (logic 0.292ns (15.958%) route 1.535ns (84.042%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.535 1.827 diviseur_freq_1/AR[0]
+ SLICE_X52Y94 FDCE f diviseur_freq_1/SR_counter_reg[4]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[4]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[5]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.827ns (logic 0.292ns (15.958%) route 1.535ns (84.042%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.535 1.827 diviseur_freq_1/AR[0]
+ SLICE_X52Y94 FDCE f diviseur_freq_1/SR_counter_reg[5]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[5]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[6]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.827ns (logic 0.292ns (15.958%) route 1.535ns (84.042%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.535 1.827 diviseur_freq_1/AR[0]
+ SLICE_X52Y94 FDCE f diviseur_freq_1/SR_counter_reg[6]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[6]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[7]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.827ns (logic 0.292ns (15.958%) route 1.535ns (84.042%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.535 1.827 diviseur_freq_1/AR[0]
+ SLICE_X52Y94 FDCE f diviseur_freq_1/SR_counter_reg[7]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y94 FDCE r diviseur_freq_1/SR_counter_reg[7]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[10]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.900ns (logic 0.292ns (15.343%) route 1.608ns (84.657%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.608 1.900 diviseur_freq_1/AR[0]
+ SLICE_X52Y95 FDCE f diviseur_freq_1/SR_counter_reg[10]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y95 FDCE r diviseur_freq_1/SR_counter_reg[10]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[11]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 1.900ns (logic 0.292ns (15.343%) route 1.608ns (84.657%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 1.999ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.999ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=89, routed) 1.608 1.900 diviseur_freq_1/AR[0]
+ SLICE_X52Y95 FDCE f diviseur_freq_1/SR_counter_reg[11]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.834 1.999 diviseur_freq_1/I15
+ SLICE_X52Y95 FDCE r diviseur_freq_1/SR_counter_reg[11]/C
+
+
+
+
+
diff --git a/loto/loto.runs/impl_1/loto_timing_summary_routed.rpx b/loto/loto.runs/impl_1/loto_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..bdbffaa27edcf8ccbcfba95d49b2d660ede08f1d
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diff --git a/loto/loto.runs/impl_1/loto_utilization_placed.pb b/loto/loto.runs/impl_1/loto_utilization_placed.pb
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index 0000000000000000000000000000000000000000..722e79994a0d02b7eec8e1ab6a90ff5c840e3f9a
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diff --git a/loto/loto.runs/impl_1/loto_utilization_placed.rpt b/loto/loto.runs/impl_1/loto_utilization_placed.rpt
new file mode 100644
index 0000000..54001c4
--- /dev/null
+++ b/loto/loto.runs/impl_1/loto_utilization_placed.rpt
@@ -0,0 +1,215 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:24:35 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs | 72 | 0 | 0 | 63400 | 0.11 |
+| LUT as Logic | 72 | 0 | 0 | 63400 | 0.11 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Flip Flop | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 1 | Yes | - | Set |
+| 88 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 0 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice | 32 | 0 | 0 | 15850 | 0.20 |
+| SLICEL | 25 | 0 | | | |
+| SLICEM | 7 | 0 | | | |
+| LUT as Logic | 72 | 0 | 0 | 63400 | 0.11 |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 51 | | | | |
+| using O5 and O6 | 21 | | | | |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| LUT as Distributed RAM | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| LUT as Shift Register | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| Slice Registers | 89 | 0 | 0 | 126800 | 0.07 |
+| Register driven from within the Slice | 51 | | | | |
+| Register driven from outside the Slice | 38 | | | | |
+| LUT in front of the register is unused | 14 | | | | |
+| LUT in front of the register is used | 24 | | | | |
+| Unique Control Sets | 10 | | 0 | 15850 | 0.06 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 21 | 21 | 0 | 210 | 10.00 |
+| IOB Master Pads | 12 | | | | |
+| IOB Slave Pads | 9 | | | | |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 88 | Flop & Latch |
+| LUT6 | 41 | LUT |
+| LUT4 | 18 | LUT |
+| OBUF | 17 | IO |
+| LUT5 | 11 | LUT |
+| LUT3 | 10 | LUT |
+| LUT2 | 10 | LUT |
+| CARRY4 | 7 | CarryLogic |
+| IBUF | 4 | IO |
+| LUT1 | 3 | LUT |
+| BUFG | 2 | Clock |
+| FDPE | 1 | Flop & Latch |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/loto/loto.runs/impl_1/opt_design.pb b/loto/loto.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..f48897163dbc753b3cf7374b74c7470da92fa856
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diff --git a/loto/loto.runs/impl_1/phys_opt_design.pb b/loto/loto.runs/impl_1/phys_opt_design.pb
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diff --git a/loto/loto.runs/impl_1/route_design.pb b/loto/loto.runs/impl_1/route_design.pb
new file mode 100644
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diff --git a/loto/loto.runs/impl_1/rundef.js b/loto/loto.runs/impl_1/rundef.js
new file mode 100644
index 0000000..8476515
--- /dev/null
+++ b/loto/loto.runs/impl_1/rundef.js
@@ -0,0 +1,45 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/loto/loto.runs/impl_1/runme.bat b/loto/loto.runs/impl_1/runme.bat
new file mode 100644
index 0000000..637899f
--- /dev/null
+++ b/loto/loto.runs/impl_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/loto/loto.runs/impl_1/runme.log b/loto/loto.runs/impl_1/runme.log
new file mode 100644
index 0000000..8e96ad8
--- /dev/null
+++ b/loto/loto.runs/impl_1/runme.log
@@ -0,0 +1,730 @@
+
+*** Running vivado
+ with args -log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 12 11:23:53 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.883 ; gain = 202.840 ; free physical = 1413 ; free virtual = 14279
+Command: link_design -top loto -part xc7a100tcsg324-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1931.945 ; gain = 0.000 ; free physical = 1066 ; free virtual = 13933
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2141.410 ; gain = 0.000 ; free physical = 953 ; free virtual = 13819
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2141.410 ; gain = 569.527 ; free physical = 953 ; free virtual = 13819
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2153.988 ; gain = 12.578 ; free physical = 919 ; free virtual = 13786
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 211085630
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2652.816 ; gain = 498.828 ; free physical = 503 ; free virtual = 13371
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 211085630
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 211085630
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 1 Initialization | Checksum: 211085630
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 2 Timer Update And Timing Data Collection | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Retarget | Checksum: 211085630
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 211085630
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Constant propagation | Checksum: 211085630
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Sweep | Checksum: 251a8a732
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+BUFG optimization | Checksum: 251a8a732
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Shift Register Optimization | Checksum: 251a8a732
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 251a8a732
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Post Processing Netlist | Checksum: 251a8a732
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Phase 9 Finalization | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 0 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+Ending Netlist Obfuscation Task | Checksum: 249fabdc7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.652 ; gain = 0.000 ; free physical = 193 ; free virtual = 13059
+INFO: [Common 17-83] Releasing license: Implementation
+26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2966.652 ; gain = 825.242 ; free physical = 193 ; free virtual = 13059
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+Command: report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 185 ; free virtual = 13058
+Write Physdb Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 180 ; free virtual = 13069
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 161 ; free virtual = 13086
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19b090d25
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 161 ; free virtual = 13086
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 161 ; free virtual = 13086
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196a652db
+
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 189 ; free virtual = 13088
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 206d57cc6
+
+Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 173 ; free virtual = 13080
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 206d57cc6
+
+Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 173 ; free virtual = 13080
+Phase 1 Placer Initialization | Checksum: 206d57cc6
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 158 ; free virtual = 13073
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 21c3f6b22
+
+Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.5 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 193 ; free virtual = 13060
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19c2f5c99
+
+Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 193 ; free virtual = 13060
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 19c2f5c99
+
+Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.51 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 193 ; free virtual = 13060
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1acd71bcf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1acd71bcf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+Phase 2.4 Global Placement Core | Checksum: 233028bb0
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+Phase 2 Global Placement | Checksum: 233028bb0
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 1f43e3888
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b44da236
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 22ffbc78e
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1e47ff1ff
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 153 ; free virtual = 13050
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1f038efdd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1af4f748a
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 17bb44ef9
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+Phase 3 Detail Placement | Checksum: 17bb44ef9
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13049
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 1ba5038a9
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=6.007 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 19735b1a7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 2223fa4bd
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1ba5038a9
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=6.007. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4.1 Post Commit Optimization | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4.3 Placer Reporting | Checksum: 1d58387fd
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f7e5a539
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+Ending Placer Task | Checksum: 195b01157
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 187 ; free virtual = 13058
+62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file loto_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 166 ; free virtual = 13037
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file loto_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 167 ; free virtual = 13038
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 168 ; free virtual = 13039
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 168 ; free virtual = 13039
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+Write Physdb Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 165 ; free virtual = 13037
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 188 ; free virtual = 13038
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 6.007 | TNS= 0.000 |
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 186 ; free virtual = 13036
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 184 ; free virtual = 13035
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 180 ; free virtual = 13030
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 178 ; free virtual = 13028
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 176 ; free virtual = 13027
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 176 ; free virtual = 13027
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3014.676 ; gain = 0.000 ; free physical = 172 ; free virtual = 13023
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 2039d80e ConstDB: 0 ShapeSum: c3a3d9b3 RouteDB: b1d25f96
+Post Restoration Checksum: NetGraph: 98d52cf6 | NumContArr: 788702f8 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 296ae2528
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3122.594 ; gain = 107.918 ; free physical = 187 ; free virtual = 12883
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 296ae2528
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3122.594 ; gain = 107.918 ; free physical = 187 ; free virtual = 12883
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 296ae2528
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3122.594 ; gain = 107.918 ; free physical = 187 ; free virtual = 12883
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 2b4755bdc
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3144.172 ; gain = 129.496 ; free physical = 229 ; free virtual = 12885
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.766 | TNS=0.000 | WHS=0.004 | THS=0.000 |
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 4.35218e-05 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 167
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 165
+ Number of Partially Routed Nets = 2
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 256318032
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 256318032
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 274f4de13
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 4 Initial Routing | Checksum: 274f4de13
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 11
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.914 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 5 Rip-up And Reroute | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 6 Delay and Skew Optimization | Checksum: 207761928
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.010 | TNS=0.000 | WHS=0.306 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Phase 7 Post Hold Fix | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0221091 %
+ Global Horizontal Routing Utilization = 0.0471725 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 1c3c4fa22
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 22ea9d0de
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 22ea9d0de
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=6.010 | TNS=0.000 | WHS=0.306 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 22ea9d0de
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+Total Elapsed time in route_design: 21.31 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 190db45f2
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 190db45f2
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 3149.141 ; gain = 134.465 ; free physical = 221 ; free virtual = 12878
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+Command: report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+Command: report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 4 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file loto_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file loto_route_status.rpt -pb loto_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Command: report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+107 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file loto_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 168 ; free virtual = 12822
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 167 ; free virtual = 12822
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 167 ; free virtual = 12823
+Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3219.812 ; gain = 0.000 ; free physical = 167 ; free virtual = 12822
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto_routed.dcp' has been generated.
+Command: write_bitstream -force loto.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./loto.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+118 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3496.727 ; gain = 276.914 ; free physical = 204 ; free virtual = 12506
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:25:13 2025...
diff --git a/loto/loto.runs/impl_1/runme.sh b/loto/loto.runs/impl_1/runme.sh
new file mode 100755
index 0000000..d5d4fc5
--- /dev/null
+++ b/loto/loto.runs/impl_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+
+
diff --git a/loto/loto.runs/impl_1/vivado.jou b/loto/loto.runs/impl_1/vivado.jou
new file mode 100644
index 0000000..224dd2e
--- /dev/null
+++ b/loto/loto.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:23:53 2025
+# Process ID: 50768
+# Current directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1
+# Command line: vivado -log loto.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+# Log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.vdi
+# Journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-637
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3300.030 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :15504 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
diff --git a/loto/loto.runs/impl_1/vivado.pb b/loto/loto.runs/impl_1/vivado.pb
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diff --git a/loto/loto.runs/impl_1/write_bitstream.pb b/loto/loto.runs/impl_1/write_bitstream.pb
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diff --git a/loto/loto.runs/synth_1/.Vivado_Synthesis.queue.rst b/loto/loto.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/synth_1/.Xil/loto_propImpl.xdc b/loto/loto.runs/synth_1/.Xil/loto_propImpl.xdc
new file mode 100644
index 0000000..ec103c3
--- /dev/null
+++ b/loto/loto.runs/synth_1/.Xil/loto_propImpl.xdc
@@ -0,0 +1,43 @@
+set_property SRC_FILE_INFO {cfile:/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc rfile:../../../../src/Nexys4_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E16 [get_ports I_button]
+set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P4 [get_ports I_block]
+set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E3 [get_ports I_clk_100m]
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V10 [get_ports I_rst]
+set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN K5 [get_ports O_red]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN H6 [get_ports O_green]
+set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L3 [get_ports {O_7segmentDisplay[0]}]
+set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N1 [get_ports {O_7segmentDisplay[1]}]
+set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L5 [get_ports {O_7segmentDisplay[2]}]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L4 [get_ports {O_7segmentDisplay[3]}]
+set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN K3 [get_ports {O_7segmentDisplay[4]}]
+set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M2 [get_ports {O_7segmentDisplay[5]}]
+set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L6 [get_ports {O_7segmentDisplay[6]}]
+set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N6 [get_ports {O_7segmentSelect[0]}]
+set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M6 [get_ports {O_7segmentSelect[1]}]
+set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M3 [get_ports {O_7segmentSelect[2]}]
+set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N5 [get_ports {O_7segmentSelect[3]}]
+set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N2 [get_ports {O_7segmentSelect[4]}]
+set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N4 [get_ports {O_7segmentSelect[5]}]
+set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L1 [get_ports {O_7segmentSelect[6]}]
+set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M1 [get_ports {O_7segmentSelect[7]}]
diff --git a/loto/loto.runs/synth_1/.vivado.begin.rst b/loto/loto.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000..b02dec8
--- /dev/null
+++ b/loto/loto.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="m22kling" Host="fl-tp-br-637" Pid="50135" HostCore="4" HostMemory="16257804">
+ </Process>
+</ProcessHandle>
diff --git a/loto/loto.runs/synth_1/.vivado.end.rst b/loto/loto.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/synth_1/ISEWrap.js b/loto/loto.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000..61806d0
--- /dev/null
+++ b/loto/loto.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/loto/loto.runs/synth_1/ISEWrap.sh b/loto/loto.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000..05d5381
--- /dev/null
+++ b/loto/loto.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/loto/loto.runs/synth_1/__synthesis_is_complete__ b/loto/loto.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.runs/synth_1/gen_run.xml b/loto/loto.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000..c4d68cd
--- /dev/null
+++ b/loto/loto.runs/synth_1/gen_run.xml
@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1739355769" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/loto.dcp">
+ <File Type="VDS-TIMINGSUMMARY" Name="loto_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="loto.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="loto_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="loto_utilization_synth.rpt"/>
+ <File Type="RDS-PROPCONSTRS" Name="loto_drc_synth.rpt"/>
+ <File Type="RDS-RDS" Name="loto.vds"/>
+ <File Type="REPORTS-TCL" Name="loto_reports.tcl"/>
+ <File Type="VDS-TIMING-PB" Name="loto_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="loto.tcl"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/automate.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur1_49.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_valid.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/diviseur_freq.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/led_pwm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/registres.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/tirage.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_d_u.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/modulo4.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/loto.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo4.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_u.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/loto.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+</GenRun>
diff --git a/loto/loto.runs/synth_1/htr.txt b/loto/loto.runs/synth_1/htr.txt
new file mode 100644
index 0000000..9c114a1
--- /dev/null
+++ b/loto/loto.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
diff --git a/loto/loto.runs/synth_1/incr_synth_reason.pb b/loto/loto.runs/synth_1/incr_synth_reason.pb
new file mode 100644
index 0000000..4cb4ed4
--- /dev/null
+++ b/loto/loto.runs/synth_1/incr_synth_reason.pb
@@ -0,0 +1 @@
+� 6No compile time benefit to using incremental synthesis
\ No newline at end of file
diff --git a/loto/loto.runs/synth_1/loto.dcp b/loto/loto.runs/synth_1/loto.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..aea71f735b6930deab8fe5a6314738f4a0797e96
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diff --git a/loto/loto.runs/synth_1/loto.tcl b/loto/loto.runs/synth_1/loto.tcl
new file mode 100644
index 0000000..d394ddf
--- /dev/null
+++ b/loto/loto.runs/synth_1/loto.tcl
@@ -0,0 +1,130 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param checkpoint.writeSynthRtdsInDcp 1
+set_param chipscope.maxJobs 1
+set_param xicom.use_bs_reader 1
+set_param synth.incrementalSynthesisCache ./.Xil/Vivado-13301-fl-tp-br-637/incrSyn
+set_msg_config -id {Common 17-41} -limit 10000000
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a100tcsg324-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.cache/wt [current_project]
+set_property parent.project_path /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property board_part digilentinc.com:nexys4_ddr:part0:1.1 [current_project]
+set_property ip_output_repo /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib {
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd
+ /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd
+}
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc
+set_property used_in_implementation false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1/loto.dcp
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top loto -part xc7a100tcsg324-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef loto.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/loto/loto.runs/synth_1/loto.vds b/loto/loto.runs/synth_1/loto.vds
new file mode 100644
index 0000000..30dfb05
--- /dev/null
+++ b/loto/loto.runs/synth_1/loto.vds
@@ -0,0 +1,302 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:22:53 2025
+# Process ID: 50207
+# Current directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1
+# Command line: vivado -log loto.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
+# Log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.vds
+# Journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-637
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3378.515 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :15430 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.879 ; gain = 203.840 ; free physical = 689 ; free virtual = 14272
+Command: read_checkpoint -auto_incremental -incremental /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1/loto.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1/loto.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top loto -part xc7a100tcsg324-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 50389
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2353.500 ; gain = 422.527 ; free physical = 165 ; free virtual = 13242
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'loto' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'tirage' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'automate' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [Synth 8-256] done synthesizing module 'automate' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'registres' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'registres' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd:23]
+INFO: [Synth 8-638] synthesizing module 'compteur_valid' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd:15]
+INFO: [Synth 8-256] done synthesizing module 'compteur_valid' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd:15]
+INFO: [Synth 8-638] synthesizing module 'compteur1_49' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'compteur1_49' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:16]
+INFO: [Synth 8-638] synthesizing module 'led_pwm' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'led_pwm' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'tirage' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'compteur_modulo6' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-256] done synthesizing module 'compteur_modulo6' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-638] synthesizing module 'diviseur_freq' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd:18]
+ Parameter n_fast bound to: 15 - type: integer
+ Parameter n_slow bound to: 25 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'diviseur_freq' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd:18]
+INFO: [Synth 8-638] synthesizing module 'mux6_1' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:20]
+INFO: [Synth 8-256] done synthesizing module 'mux6_1' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:20]
+INFO: [Synth 8-638] synthesizing module 'transcodeur7s_d_u_transcod_int' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-256] done synthesizing module 'transcodeur7s_d_u_transcod_int' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-638] synthesizing module 'modulo4' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'modulo4' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'loto' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:21]
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2431.438 ; gain = 500.465 ; free physical = 167 ; free virtual = 13162
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2446.281 ; gain = 515.309 ; free physical = 165 ; free virtual = 13160
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2446.281 ; gain = 515.309 ; free physical = 165 ; free virtual = 13160
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2446.281 ; gain = 0.000 ; free physical = 165 ; free virtual = 13160
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/loto_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/loto_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.031 ; gain = 0.000 ; free physical = 154 ; free virtual = 13141
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2596.031 ; gain = 0.000 ; free physical = 154 ; free virtual = 13141
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 172 ; free virtual = 13123
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 172 ; free virtual = 13123
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 173 ; free virtual = 13123
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_STATE_reg' in module 'automate'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ st_wait_success | 000 | 001
+ st_counting | 001 | 010
+ st_compar | 010 | 011
+ st_store | 011 | 100
+ st_end_red | 100 | 110
+ st_end_green | 101 | 101
+ iSTATE | 110 | 000
+*
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_STATE_reg' using encoding 'sequential' in module 'automate'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 170 ; free virtual = 13121
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 6 Bit Adders := 1
+ 2 Input 5 Bit Adders := 1
+ 2 Input 3 Bit Adders := 2
+ 2 Input 2 Bit Adders := 1
++---Registers :
+ 6 Bit Registers := 7
+ 5 Bit Registers := 2
+ 3 Bit Registers := 2
+ 2 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 7 Bit Muxes := 1
+ 4 Input 7 Bit Muxes := 1
+ 4 Input 4 Bit Muxes := 1
+ 7 Input 3 Bit Muxes := 1
+ 2 Input 3 Bit Muxes := 4
+ 2 Input 2 Bit Muxes := 1
+ 7 Input 1 Bit Muxes := 11
+ 2 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 170 ; free virtual = 13131
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 232 ; free virtual = 13104
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 239 ; free virtual = 13110
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 239 ; free virtual = 13110
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-------+------+
+| |Cell |Count |
++------+-------+------+
+|1 |BUFG | 2|
+|2 |CARRY4 | 7|
+|3 |LUT1 | 3|
+|4 |LUT2 | 10|
+|5 |LUT3 | 10|
+|6 |LUT4 | 18|
+|7 |LUT5 | 11|
+|8 |LUT6 | 41|
+|9 |FDCE | 88|
+|10 |FDPE | 1|
+|11 |IBUF | 4|
+|12 |OBUF | 17|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2596.031 ; gain = 515.309 ; free physical = 224 ; free virtual = 13096
+Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.039 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.039 ; gain = 0.000 ; free physical = 391 ; free virtual = 13263
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.039 ; gain = 0.000 ; free physical = 460 ; free virtual = 13332
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: 794d6e6c
+INFO: [Common 17-83] Releasing license: Synthesis
+48 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2596.039 ; gain = 1017.223 ; free physical = 460 ; free virtual = 13332
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2098.045; main = 1746.857; forked = 399.907
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3657.113; main = 2596.035; forked = 1061.078
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2620.043 ; gain = 0.000 ; free physical = 471 ; free virtual = 13343
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:23:48 2025...
diff --git a/loto/loto.runs/synth_1/loto_utilization_synth.pb b/loto/loto.runs/synth_1/loto_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..722e79994a0d02b7eec8e1ab6a90ff5c840e3f9a
GIT binary patch
literal 242
zcmd;LGcqtT(KDRHtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp-
z<zZmh<TRI;Va0d%r@X2A`)%I}F)&PU+AGYkqTIbzWX6;iw!M-J3=9l+B^e5)xGj|e
zvDeBoFsyL=E6>0X<a|_tfkDCXtSU%+t{MXayYo{u5WCk1MBX)GU?^~2Y7AnpwP0Xi
zaQF)%osL>EFr09hWX0hW>gMho66AB%4y0tRJp;o5ho|-+_FESaxz`mW(&`3cuMGr|
Oe*+m98tjh-f!F|loI)7@
literal 0
HcmV?d00001
diff --git a/loto/loto.runs/synth_1/loto_utilization_synth.rpt b/loto/loto.runs/synth_1/loto_utilization_synth.rpt
new file mode 100644
index 0000000..d1f8c5e
--- /dev/null
+++ b/loto/loto.runs/synth_1/loto_utilization_synth.rpt
@@ -0,0 +1,182 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:23:48 2025
+| Host : fl-tp-br-637 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 72 | 0 | 0 | 63400 | 0.11 |
+| LUT as Logic | 72 | 0 | 0 | 63400 | 0.11 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Flip Flop | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 1 | Yes | - | Set |
+| 88 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 0 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 21 | 0 | 0 | 210 | 10.00 |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 88 | Flop & Latch |
+| LUT6 | 41 | LUT |
+| LUT4 | 18 | LUT |
+| OBUF | 17 | IO |
+| LUT5 | 11 | LUT |
+| LUT3 | 10 | LUT |
+| LUT2 | 10 | LUT |
+| CARRY4 | 7 | CarryLogic |
+| IBUF | 4 | IO |
+| LUT1 | 3 | LUT |
+| BUFG | 2 | Clock |
+| FDPE | 1 | Flop & Latch |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/loto/loto.runs/synth_1/rundef.js b/loto/loto.runs/synth_1/rundef.js
new file mode 100644
index 0000000..1e14633
--- /dev/null
+++ b/loto/loto.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/loto/loto.runs/synth_1/runme.bat b/loto/loto.runs/synth_1/runme.bat
new file mode 100644
index 0000000..637899f
--- /dev/null
+++ b/loto/loto.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/loto/loto.runs/synth_1/runme.log b/loto/loto.runs/synth_1/runme.log
new file mode 100644
index 0000000..d516235
--- /dev/null
+++ b/loto/loto.runs/synth_1/runme.log
@@ -0,0 +1,292 @@
+
+*** Running vivado
+ with args -log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 12 11:22:53 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.879 ; gain = 203.840 ; free physical = 689 ; free virtual = 14272
+Command: read_checkpoint -auto_incremental -incremental /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1/loto.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1/loto.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top loto -part xc7a100tcsg324-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 50389
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2353.500 ; gain = 422.527 ; free physical = 165 ; free virtual = 13242
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'loto' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'tirage' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'automate' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [Synth 8-256] done synthesizing module 'automate' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'registres' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'registres' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd:23]
+INFO: [Synth 8-638] synthesizing module 'compteur_valid' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd:15]
+INFO: [Synth 8-256] done synthesizing module 'compteur_valid' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd:15]
+INFO: [Synth 8-638] synthesizing module 'compteur1_49' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'compteur1_49' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:16]
+INFO: [Synth 8-638] synthesizing module 'led_pwm' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'led_pwm' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'tirage' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'compteur_modulo6' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-256] done synthesizing module 'compteur_modulo6' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-638] synthesizing module 'diviseur_freq' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd:18]
+ Parameter n_fast bound to: 15 - type: integer
+ Parameter n_slow bound to: 25 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'diviseur_freq' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd:18]
+INFO: [Synth 8-638] synthesizing module 'mux6_1' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:20]
+INFO: [Synth 8-256] done synthesizing module 'mux6_1' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:20]
+INFO: [Synth 8-638] synthesizing module 'transcodeur7s_d_u_transcod_int' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-256] done synthesizing module 'transcodeur7s_d_u_transcod_int' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-638] synthesizing module 'modulo4' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'modulo4' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'loto' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:21]
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2431.438 ; gain = 500.465 ; free physical = 167 ; free virtual = 13162
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2446.281 ; gain = 515.309 ; free physical = 165 ; free virtual = 13160
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2446.281 ; gain = 515.309 ; free physical = 165 ; free virtual = 13160
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2446.281 ; gain = 0.000 ; free physical = 165 ; free virtual = 13160
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/loto_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/loto_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.031 ; gain = 0.000 ; free physical = 154 ; free virtual = 13141
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2596.031 ; gain = 0.000 ; free physical = 154 ; free virtual = 13141
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 172 ; free virtual = 13123
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 172 ; free virtual = 13123
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 173 ; free virtual = 13123
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_STATE_reg' in module 'automate'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ st_wait_success | 000 | 001
+ st_counting | 001 | 010
+ st_compar | 010 | 011
+ st_store | 011 | 100
+ st_end_red | 100 | 110
+ st_end_green | 101 | 101
+ iSTATE | 110 | 000
+*
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_STATE_reg' using encoding 'sequential' in module 'automate'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 170 ; free virtual = 13121
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 6 Bit Adders := 1
+ 2 Input 5 Bit Adders := 1
+ 2 Input 3 Bit Adders := 2
+ 2 Input 2 Bit Adders := 1
++---Registers :
+ 6 Bit Registers := 7
+ 5 Bit Registers := 2
+ 3 Bit Registers := 2
+ 2 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 7 Bit Muxes := 1
+ 4 Input 7 Bit Muxes := 1
+ 4 Input 4 Bit Muxes := 1
+ 7 Input 3 Bit Muxes := 1
+ 2 Input 3 Bit Muxes := 4
+ 2 Input 2 Bit Muxes := 1
+ 7 Input 1 Bit Muxes := 11
+ 2 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 170 ; free virtual = 13131
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 232 ; free virtual = 13104
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 239 ; free virtual = 13110
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 239 ; free virtual = 13110
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-------+------+
+| |Cell |Count |
++------+-------+------+
+|1 |BUFG | 2|
+|2 |CARRY4 | 7|
+|3 |LUT1 | 3|
+|4 |LUT2 | 10|
+|5 |LUT3 | 10|
+|6 |LUT4 | 18|
+|7 |LUT5 | 11|
+|8 |LUT6 | 41|
+|9 |FDCE | 88|
+|10 |FDPE | 1|
+|11 |IBUF | 4|
+|12 |OBUF | 17|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.031 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2596.031 ; gain = 515.309 ; free physical = 224 ; free virtual = 13096
+Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2596.039 ; gain = 665.059 ; free physical = 224 ; free virtual = 13096
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.039 ; gain = 0.000 ; free physical = 391 ; free virtual = 13263
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.039 ; gain = 0.000 ; free physical = 460 ; free virtual = 13332
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: 794d6e6c
+INFO: [Common 17-83] Releasing license: Synthesis
+48 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2596.039 ; gain = 1017.223 ; free physical = 460 ; free virtual = 13332
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2098.045; main = 1746.857; forked = 399.907
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3657.113; main = 2596.035; forked = 1061.078
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2620.043 ; gain = 0.000 ; free physical = 471 ; free virtual = 13343
+INFO: [Common 17-1381] The checkpoint '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:23:48 2025...
diff --git a/loto/loto.runs/synth_1/runme.sh b/loto/loto.runs/synth_1/runme.sh
new file mode 100755
index 0000000..b5fc782
--- /dev/null
+++ b/loto/loto.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
diff --git a/loto/loto.runs/synth_1/vivado.jou b/loto/loto.runs/synth_1/vivado.jou
new file mode 100644
index 0000000..73216e1
--- /dev/null
+++ b/loto/loto.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:22:53 2025
+# Process ID: 50207
+# Current directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1
+# Command line: vivado -log loto.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
+# Log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.vds
+# Journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-637
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3378.515 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :15430 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
diff --git a/loto/loto.runs/synth_1/vivado.pb b/loto/loto.runs/synth_1/vivado.pb
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diff --git a/loto/loto.sim/sim_1/behav/xsim/compile.sh b/loto/loto.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000..f6e5201
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Feb 12 12:10:22 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj"
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl b/loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg_behav.wdb b/loto/loto.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..fe720c772dbd3562393e6fd7895b400d5ca22da0
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diff --git a/loto/loto.sim/sim_1/behav/xsim/elaborate.log b/loto/loto.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000..95bbc23
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,8 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
diff --git a/loto/loto.sim/sim_1/behav/xsim/elaborate.sh b/loto/loto.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000..8388fae
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Feb 12 12:10:24 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+
diff --git a/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl b/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb b/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..5c5ee3e1117d3903b15c47aa0af9a7e16f378d0d
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diff --git a/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj b/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj
new file mode 100644
index 0000000..81dda96
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj
@@ -0,0 +1,18 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/automate.vhd" \
+"../../../../../src/compteur1_49.vhd" \
+"../../../../../src/compteur_modulo6.vhd" \
+"../../../../../src/compteur_valid.vhd" \
+"../../../../../src/diviseur_freq.vhd" \
+"../../../../../src/led_pwm.vhd" \
+"../../../../../src/registres.vhd" \
+"../../../../../src/tirage.vhd" \
+"../../../../../src/mux6_1.vhd" \
+"../../../../../src/transcodeur7s_d_u.vhd" \
+"../../../../../src/modulo4.vhd" \
+"../../../../../src/loto.vhd" \
+"../../../../../src/loto_tb.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl b/loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg_behav.wdb b/loto/loto.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg_behav.wdb
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diff --git a/loto/loto.sim/sim_1/behav/xsim/simulate.log b/loto/loto.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.sim/sim_1/behav/xsim/simulate.sh b/loto/loto.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000..835014c
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Feb 12 12:09:42 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch loto_tb_ar_cfg.tcl -log simulate.log"
+xsim loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch loto_tb_ar_cfg.tcl -log simulate.log
+
diff --git a/loto/loto.sim/sim_1/behav/xsim/xelab.pb b/loto/loto.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..92541f958acc185180fc626cbc5d164bea1f3fc8
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt
new file mode 100644
index 0000000..5ae6a8b
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "compteur_modulo6_tb_arch_cfg_behav" "xil_defaultlib.compteur_modulo6_tb_arch_cfg" -log "elaborate.log"
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..33f601b6faa95d4b991bca6b855d0f0107db484b
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.c b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.c
new file mode 100644
index 0000000..af323b5
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.c
@@ -0,0 +1,113 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_14(char*, char *);
+IKI_DLLESPEC extern void execute_15(char*, char *);
+IKI_DLLESPEC extern void execute_16(char*, char *);
+IKI_DLLESPEC extern void execute_12(char*, char *);
+IKI_DLLESPEC extern void execute_13(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[7] = {(funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_12, (funcp)execute_13, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_3};
+const int NumRelocateId= 7;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc", (void **)funcTab, 7);
+ iki_vhdl_file_variable_register(dp + 3016);
+ iki_vhdl_file_variable_register(dp + 3072);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rlx b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rlx
new file mode 100644
index 0000000..36a3d4f
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 8063398077642035437 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk\" \"xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rtti b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rtti
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.svtype b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.svtype
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.type b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.type
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.xdbg b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.xdbg
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimSettings.ini b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimSettings.ini
new file mode 100644
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--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=188
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=196
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
+OBJECT_NAME_COLUMN_WIDTH=176
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimcrash.log b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..66423301268eae54817c621570ef61bab62165cf
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimkernel.log b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimkernel.log
new file mode 100644
index 0000000..573fd3e
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk -simmode gui -wdb compteur_modulo6_tb_arch_cfg_behav.wdb -simrunnum 0 -socket 43139
+Design successfully loaded
+Design Loading Memory Usage: 20140 KB (Peak: 20732 KB)
+Design Loading CPU Usage: 30 ms
+Simulation completed
+Simulation Memory Usage: 105976 KB (Peak: 159408 KB)
+Simulation CPU Usage: 40 ms
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/Compile_Options.txt b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/Compile_Options.txt
new file mode 100644
index 0000000..2fb2e34
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "loto_tb_ar_cfg_behav" "xil_defaultlib.loto_tb_ar_cfg" -log "elaborate.log"
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/TempBreakPointFile.txt b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..17849baf4e23f4644d5caddd1bdccd0b71583625
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literal 0
HcmV?d00001
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.c b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.c
new file mode 100644
index 0000000..0f21118
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.c
@@ -0,0 +1,152 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_75(char*, char *);
+IKI_DLLESPEC extern void execute_76(char*, char *);
+IKI_DLLESPEC extern void execute_77(char*, char *);
+IKI_DLLESPEC extern void execute_78(char*, char *);
+IKI_DLLESPEC extern void execute_68(char*, char *);
+IKI_DLLESPEC extern void execute_69(char*, char *);
+IKI_DLLESPEC extern void execute_70(char*, char *);
+IKI_DLLESPEC extern void execute_71(char*, char *);
+IKI_DLLESPEC extern void execute_72(char*, char *);
+IKI_DLLESPEC extern void execute_73(char*, char *);
+IKI_DLLESPEC extern void execute_74(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_57(char*, char *);
+IKI_DLLESPEC extern void execute_59(char*, char *);
+IKI_DLLESPEC extern void execute_60(char*, char *);
+IKI_DLLESPEC extern void execute_61(char*, char *);
+IKI_DLLESPEC extern void execute_62(char*, char *);
+IKI_DLLESPEC extern void execute_63(char*, char *);
+IKI_DLLESPEC extern void execute_65(char*, char *);
+IKI_DLLESPEC extern void execute_66(char*, char *);
+IKI_DLLESPEC extern void execute_67(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_2(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_8(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_9(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[46] = {(funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_28, (funcp)execute_30, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_36, (funcp)execute_37, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_50, (funcp)execute_51, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_57, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_2, (funcp)transaction_8, (funcp)transaction_9};
+const int NumRelocateId= 46;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc", (void **)funcTab, 46);
+ iki_vhdl_file_variable_register(dp + 13864);
+ iki_vhdl_file_variable_register(dp + 13920);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/loto_tb_ar_cfg_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/loto_tb_ar_cfg_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx
new file mode 100644
index 0000000..6eb25f2
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 10787837244291083020 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/loto_tb_ar_cfg_behav/xsimk\" \"xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rtti b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rtti
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.type b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.type
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.xdbg b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..d318cf062cb00c3c93eec91ba18455fe97704643
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimSettings.ini b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimSettings.ini
new file mode 100644
index 0000000..cd8cadc
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=false
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+INOUT_OBJECT_FILTER=false
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=false
+VARIABLE_OBJECT_FILTER=false
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+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=95
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=84
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=83
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimcrash.log b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimk b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimk
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimkernel.log b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimkernel.log
new file mode 100644
index 0000000..9d8c974
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimkernel.log
@@ -0,0 +1,4 @@
+Running: xsim.dir/loto_tb_ar_cfg_behav/xsimk -simmode gui -wdb loto_tb_ar_cfg_behav.wdb -simrunnum 0 -socket 34211
+Design successfully loaded
+Design Loading Memory Usage: 20192 KB (Peak: 20752 KB)
+Design Loading CPU Usage: 50 ms
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/Compile_Options.txt b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/Compile_Options.txt
new file mode 100644
index 0000000..3523bba
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "mux6_1_tb_arch_cfg_behav" "xil_defaultlib.mux6_1_tb_arch_cfg" -log "elaborate.log"
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/TempBreakPointFile.txt b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_0.lnx64.o b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..78dbaa80dff146f8a569dfadaf3717276f55ee80
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.c b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.c
new file mode 100644
index 0000000..8998a5e
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.c
@@ -0,0 +1,111 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_22(char*, char *);
+IKI_DLLESPEC extern void execute_23(char*, char *);
+IKI_DLLESPEC extern void execute_21(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_8(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[5] = {(funcp)execute_22, (funcp)execute_23, (funcp)execute_21, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_8};
+const int NumRelocateId= 5;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc", (void **)funcTab, 5);
+ iki_vhdl_file_variable_register(dp + 3592);
+ iki_vhdl_file_variable_register(dp + 3648);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.lnx64.o b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..b7efc309c9184c9e4aa6bae6e628adf7b336f9ef
GIT binary patch
literal 4336
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literal 0
HcmV?d00001
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.dbg b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.dbg
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.mem b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.mem
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rlx b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rlx
new file mode 100644
index 0000000..746ee1a
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 9777259282487627216 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg" ,
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+ buildTime : "18:54:44" ,
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+ [
+ ]
+}
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rtti b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rtti
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.svtype b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.svtype
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.type b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.type
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.xdbg b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..7452e56202ff15af3de30ff5f486f66412a0a12b
GIT binary patch
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HcmV?d00001
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimSettings.ini b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimSettings.ini
new file mode 100644
index 0000000..6d0caa7
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=118
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=84
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=125
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=0
+PROCESS_TYPE_COLUMN_WIDTH=0
+FRAME_INDEX_COLUMN_WIDTH=0
+FRAME_NAME_COLUMN_WIDTH=0
+FRAME_FILE_NAME_COLUMN_WIDTH=0
+FRAME_LINE_NUM_COLUMN_WIDTH=0
+LOCAL_NAME_COLUMN_WIDTH=0
+LOCAL_VALUE_COLUMN_WIDTH=0
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimcrash.log b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..6bea91c6e7c2beabe6072050b6016d77b3031c25
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimkernel.log b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimkernel.log
new file mode 100644
index 0000000..a0608fb
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk -simmode gui -wdb mux6_1_tb_arch_cfg_behav.wdb -simrunnum 0 -socket 35111
+Design successfully loaded
+Design Loading Memory Usage: 20148 KB (Peak: 20740 KB)
+Design Loading CPU Usage: 30 ms
+Simulation completed
+Simulation Memory Usage: 110084 KB (Peak: 159416 KB)
+Simulation CPU Usage: 30 ms
diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/automate.vdb b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/automate.vdb
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/compteur_modulo6.vdb b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/compteur_modulo6.vdb
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new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/compteur_modulo6_tb_arch_cfg.vdb b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/compteur_modulo6_tb_arch_cfg.vdb
new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/compteur_valid.vdb b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/compteur_valid.vdb
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..af41eb4
--- /dev/null
+++ b/loto/loto.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,19 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
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+/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd,1739350194,vhdl,/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd,,,compteur1_49,,,,,,,,
+/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd,1739352114,vhdl,/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd,,,compteur_modulo6,,,,,,,,
+/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd,1739350194,vhdl,,,,compteur_modulo6_tb;compteur_modulo6_tb_arch_cfg,,,,,,,,
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xsim.ini b/loto/loto.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e8199b2
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new file mode 100644
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diff --git a/loto/loto.sim/sim_1/behav/xsim/xvhdl.pb b/loto/loto.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
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diff --git a/loto/loto.xpr b/loto/loto.xpr
new file mode 100644
index 0000000..9d7d945
--- /dev/null
+++ b/loto/loto.xpr
@@ -0,0 +1,330 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="be2dd9e2a8cb4c8bb474c2474542e438"/>
+ <Option Name="Part" Val="xc7a100tcsg324-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val="digilentinc.com:nexys4_ddr:part0:1.1"/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSABoardId" Val="nexys4_ddr"/>
+ <Option Name="WTXSimLaunchSim" Val="19"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/automate.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur1_49.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_valid.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/diviseur_freq.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/led_pwm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/registres.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/tirage.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_d_u.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/modulo4.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/loto.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo4.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_u.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/loto_tb.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto_tb_ar_cfg"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/loto.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/loto.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board>
+ <Jumpers/>
+ </Board>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/src/automate.vhd b/src/automate.vhd
index 1ccb931..6dda5e1 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,23 +36,80 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
- __BLANK_TO_FILL__
+ SR_STATE <= st_wait_success;
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
elsif rising_edge(I_clk)then
case SR_STATE is
- case SR_STATE is
when st_wait_success =>
O_l_green <= '1';
- O_l_red <= '0';
+ O_l_red <= '0';
O_counting <= '0';
- O_store <= '0';
+ O_store <= '0';
if I_button = '1' then
SR_STATE <= st_counting;
end if;
- when __BLANK_TO_FILL__
+ when st_counting =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '1';
+ O_store <= '0';
+ if I_button = '0' then
+ SR_STATE <= st_compar;
+ end if;
+
+ when st_compar =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_invalide = '0' then
+ SR_STATE <= st_store;
+ else
+ SR_STATE <= st_wait_failed;
+ end if;
+
+ when st_store =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '1';
+ if I_end = '1' then
+ SR_STATE <= st_end_red;
+ else
+ SR_STATE <= st_wait_success;
+ end if;
+
+ when st_end_red =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_clk_display = '1' then
+ SR_STATE <= st_end_green;
+ end if;
+
+ when st_end_green =>
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_clk_display = '0' then
+ SR_STATE <= st_end_red;
+ end if;
- __BLANK_TO_FILL__
+ when others =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_button = '1' then
+ SR_STATE <= st_counting;
+ end if;
end case;
end if;
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 7962a90..e393461 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -16,19 +16,25 @@ end compteur_modulo6;
architecture modulo6_a of compteur_modulo6 is
- signal SR_Counter : unsigned(2 downto 0);
+ signal SR_Counter : integer range 0 to 5;
begin
- process (_BLANK_)
+ process (I_clk, I_rst)
begin
if I_rst = '1' then
- _BLANK_
+ SR_Counter <= 0;
elsif rising_edge(I_clk) then
- _BLANK_
+ if I_block='1' then
+ SR_Counter <= SR_Counter;
+ elsif SR_Counter = 5 then
+ SR_Counter <= 0;
+ else
+ SR_Counter <= SR_Counter +1;
+ end if;
end if;
end process;
- O_CounterMod6 <= std_logic_vector(SR_Counter);
+ O_CounterMod6 <= std_logic_vector(to_unsigned(SR_Counter,3));
end modulo6_a;
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
index a689bef..0673037 100644
--- a/src/mux6_1.vhd
+++ b/src/mux6_1.vhd
@@ -20,8 +20,11 @@ end mux6_1;
architecture a_mux6_1 of mux6_1 is
begin
-__BLANK_TO_FILL__
-
-
+O_mux6 <= I_0 when (I_sel = "000")
+ else I_1 when (I_sel = "001")
+ else I_2 when (I_sel = "010")
+ else I_3 when (I_sel = "011")
+ else I_4 when (I_sel = "100")
+ else I_5;
end a_mux6_1;
diff --git a/vivado.jou b/vivado.jou
new file mode 100644
index 0000000..afd8945
--- /dev/null
+++ b/vivado.jou
@@ -0,0 +1,120 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 09:58:51 2025
+# Process ID: 13301
+# Current directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling
+# Command line: vivado
+# Log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/vivado.log
+# Journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/vivado.jou
+# Running On :fl-tp-br-637
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3300.355 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :18672 MB
+#-----------------------------------------------------------
+start_gui
+open_project /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr
+update_compile_order -fileset sources_1
+set_property used_in_synthesis false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd]
+set_property used_in_synthesis false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd]
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top mux6_1_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source mux6_1_tb_arch_cfg.tcl
+close_sim
+launch_simulation
+source mux6_1_tb_arch_cfg.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top compteur_modulo6_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+launch_simulation
+launch_simulation
+launch_simulation
+source compteur_modulo6_tb_arch_cfg.tcl
+close_sim
+launch_simulation
+source compteur_modulo6_tb_arch_cfg.tcl
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top loto_tb_ar_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+update_compile_order -fileset sim_1
+launch_simulation
+launch_simulation
+launch_simulation
+launch_simulation
+source loto_tb_ar_cfg.tcl
+current_wave_config {Untitled 5}
+log_wave {/loto_tb}
+current_wave_config {Untitled 5}
+add_wave {{/loto_tb}}
+close_sim
+close_sim
+close_sim
+launch_simulation
+source loto_tb_ar_cfg.tcl
+current_wave_config {Untitled 6}
+add_wave {{/loto_tb/DUT/tirage_1/registres_2}}
+relaunch_sim
+current_wave_config {Untitled 6}
+add_wave {{/loto_tb/DUT/transcod_1}}
+relaunch_sim
+run all
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+wait_on_run impl_1
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+current_hw_device [get_hw_devices xc7a100t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+synth_design -rtl -rtl_skip_mlo -name rtl_1
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+update_files -from_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc -to_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc -filesets [get_filesets *]
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+wait_on_run impl_1
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+refresh_design
+open_run impl_1
+report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
+close_sim
+launch_simulation
+source loto_tb_ar_cfg.tcl
+current_wave_config {Untitled 7}
+add_wave {{/loto_tb/DUT/tirage_1/automate_1}}
+current_wave_config {Untitled 7}
+add_wave {{/loto_tb/DUT/tirage_1/registres_2}}
+relaunch_sim
diff --git a/vivado.log b/vivado.log
new file mode 100644
index 0000000..200ffb1
--- /dev/null
+++ b/vivado.log
@@ -0,0 +1,1896 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 09:58:51 2025
+# Process ID: 13301
+# Current directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling
+# Command line: vivado
+# Log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/vivado.log
+# Journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/vivado.jou
+# Running On :fl-tp-br-637
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3300.355 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16647 MB
+# Swap memory :4294 MB
+# Total Virtual :20942 MB
+# Available Virtual :18672 MB
+#-----------------------------------------------------------
+start_gui
+open_project /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa100_2ms:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa100_2ms/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa100_2ms:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa100_2ms/1.2/1.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa101_2ms:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa101_2ms/1.1/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa101_2ms:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa101_2ms/1.2/1.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admva600_dev:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admva600_dev/1.0/1.0/board.xml as part xcvc1902-vsva2197-1mp-i-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v1:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v1/1.2/1.2/board.xml as part xczu3eg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v2:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v2/1.1/1.1/board.xml as part xczu3eg-sbva484-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v2:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v2/1.2/1.2/board.xml as part xczu3eg-sbva484-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_7ev_cc:part0:1.5 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_7ev_cc/1.5/1.5/board.xml as part xczu7ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_eg_iocc_production:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_3eg_iocc/1.2/1.2/board.xml as part xczu3eg-sfva625-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_eg_pciecc_production:part0:1.3 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_3eg_pciecc/1.3/1.3/board.xml as part xczu3eg-sfva625-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:zuboard_1cg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/zub1cg/1.0/1.0/board.xml as part xczu1cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-25/E.0/1.0/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-25/1.1/1.1/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-50/B.0/1.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-50/1.1/1.1/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:cmod-s7-25:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/cmod-s7-25/B.0/1.0/board.xml as part xc7s25csga225-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys2/H/1.1/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-3eg/B.0/1.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-3eg/D.0/1.1/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_5ev:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-5ev/C.0/1.1/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4cg-4e002g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/2.4/board.xml as part xczu4cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4eg-4e002g-e008g-bid:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/2.C/board.xml as part xczu4eg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4ev-4e002g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4ev-4e002g-e008g-lia/1.0/2.8/board.xml as part xczu4ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c5ev-4e002g-e008g-bid:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/2.D/board.xml as part xczu5ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c5ev-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/2.5/board.xml as part xczu5ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7cg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/2.1/board.xml as part xczu7cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7cg-4e004g-e008g-liy:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/2.H/board.xml as part xczu7cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7ev-4e004g-e008g-lea:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lea/1.0/2.0/board.xml as part xczu7ev-fbvb900-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7ev-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/2.B/board.xml as part xczu7ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-11eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-11eg-4e004g-e008g-lia/1.0/1.2/board.xml as part xczu11eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-11eg-4e008g-e008g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/1.9/board.xml as part xczu11eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-17eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-17eg-4e004g-e008g-lia/1.0/1.1/board.xml as part xczu17eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bef:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/1.7/board.xml as part xczu19eg-ffvc1760-3-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-big:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/1.6/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bii:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/1.C/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bij:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/1.D/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-19eg-4e004g-e008g-lia/1.0/1.5/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lie:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/1.4/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lih:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/1.8/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e128g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/1.3/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e008g-bie:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/1.A/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e008g-bij:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/1.E/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e016g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/1.B/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-2cg1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-2cg1-4e002g-e008g-bee/1.0/2.2/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-3eg1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-3eg1-4e002g-e008g-bee/1.0/2.1/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-4ev1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-4ev1-4e002g-e008g-bee/1.0/2.0/board.xml as part xczu4ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-5ev1-4e002g-e008g-bed:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-5ev1-4e002g-e008g-bed/1.0/2.4/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-5ev1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-5ev1-4e002g-e008g-bee/1.0/2.3/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7cg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7CG/1.0/1.0/board.xml as part xczu7cg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7cg:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7CG/2.0/2.0/board.xml as part xczu7cg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7eg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EG/1.0/1.0/board.xml as part xczu7eg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7eg:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EG/2.0/2.0/board.xml as part xczu7eg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7ev:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EV/1.0/1.0/board.xml as part xczu7ev-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7ev:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EV/2.0/2.0/board.xml as part xczu7ev-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7305-s50:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7305-S50/1.0/1.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k160t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K160T/1.0/1.0/board.xml as part xc7k160tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k410t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K410T-3E/1.0/1.0/board.xml as part xc7k410tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k410t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K410T/1.0/1.0/board.xml as part xc7k410tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k70t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K70T/1.0/1.0/board.xml as part xc7k70tfbg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k160t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K160T-3E/1.0/1.0/board.xml as part xc7k160tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k160t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K160T/1.0/1.0/board.xml as part xc7k160tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k410t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K410T-3E/1.0/1.0/board.xml as part xc7k410tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k410t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K410T/1.0/1.0/board.xml as part xc7k410tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8305-au15p-1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8305-AU15P-1E/1.0/1.0/board.xml as part xcau15p-ffvb676-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8305-au15p-2e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8305-AU15P-2E/1.0/1.0/board.xml as part xcau15p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8310-au25p:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8310-AU25P/1.0/1.0/board.xml as part xcau25p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8320-au25p:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8320-AU25P/1.2/1.2/board.xml as part xcau25p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku060-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU060-3E/1.0/1.0/board.xml as part xcku060-ffva1517-3-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku060:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU060/1.0/1.0/board.xml as part xcku060-ffva1517-1-c specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku115:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU115/1.0/1.0/board.xml as part xcku115-flva1517-1-c specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8370-ku11p:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8370-KU11P/1.0/1.0/board.xml as part xcku11p-ffva1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:am0010_3eg_1i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/AM0010_3EG_1I/1.0/1.0/board.xml as part xczu3eg-sfvc784-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:am0010_4ev_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/AM0010_4EV_1E/1.0/1.0/board.xml as part xczu4ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_070_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_70_2C/1.0/1.0/board.xml as part xc7k70tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_070_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_70_2I/1.0/1.0/board.xml as part xc7k70tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2C/1.0/1.0/board.xml as part xc7k160tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2c:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2C/2.0/2.0/board.xml as part xc7k160tffg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2I/1.0/1.0/board.xml as part xc7k160tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_3e:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_3E/2.0/2.0/board.xml as part xc7k160tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_325_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_325_2C/1.0/1.0/board.xml as part xc7k325tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_325_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_325_2I/1.0/1.0/board.xml as part xc7k325tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_410_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_410_2C/1.0/1.0/board.xml as part xc7k410tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_410_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_410_2I/1.0/1.0/board.xml as part xc7k410tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0802_2cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0802_2CG_1E/1.0/1.0/board.xml as part xczu2cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0802_2cg_1e:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0802_2CG_1E/2.0/2.0/board.xml as part xczu2cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/1.0/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2cg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/2.0/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2eg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/1.0/board.xml as part xczu2eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2eg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/2.0/board.xml as part xczu2eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/1.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e:part0:5.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/5.0/5.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/2.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e_tebf0808:part0:6.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/6.0/6.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/1.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:3.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/3.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:5.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/5.0/5.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/2.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:4.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/4.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:6.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/6.0/6.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+INFO: [Common 17-14] Message 'Board 49-26' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Project 1-313] Project file moved from '/homes/m22kling/loto' since last save.
+INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.gen/sources_1'.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_u.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_u.vhd' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc' instead.
+WARNING: [Project 1-312] File not found as '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd'; using path '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd' instead.
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+open_project: Time (s): cpu = 00:00:29 ; elapsed = 00:00:19 . Memory (MB): peak = 8272.281 ; gain = 655.664 ; free physical = 8354 ; free virtual = 16422
+update_compile_order -fileset sources_1
+set_property used_in_synthesis false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd]
+set_property used_in_synthesis false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+set_property top mux6_1_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture arch of entity xil_defaultlib.mux6_1_tb [mux6_1_tb]
+Built simulation snapshot mux6_1_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source mux6_1_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 8677.988 ; gain = 82.109 ; free physical = 7907 ; free virtual = 16263
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture arch of entity xil_defaultlib.mux6_1_tb [mux6_1_tb]
+Built simulation snapshot mux6_1_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source mux6_1_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 8685.992 ; gain = 8.004 ; free physical = 7854 ; free virtual = 16263
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+set_property top compteur_modulo6_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+ERROR: [VRFC 10-8491] illegal identifier '_SR_Counter' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:26]
+ERROR: [VRFC 10-2989] '_sr_counter' is not declared [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:26]
+ERROR: [VRFC 10-3760] type 'unsigned' does not match with the integer literal [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:29]
+ERROR: [VRFC 10-2989] 'clk' is not declared [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:23]
+ERROR: [VRFC 10-9458] unit 'modulo6_a' is ignored due to previous errors [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [VRFC 10-8704] VHDL file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd' is ignored due to errors
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log'
+ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+ERROR: [VRFC 10-8491] illegal identifier '_SR_Counter' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:26]
+ERROR: [VRFC 10-2989] '_sr_counter' is not declared [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:26]
+ERROR: [VRFC 10-3760] type 'unsigned' does not match with the integer literal [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:29]
+ERROR: [VRFC 10-9458] unit 'modulo6_a' is ignored due to previous errors [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [VRFC 10-8704] VHDL file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd' is ignored due to errors
+INFO: [Common 17-344] 'execute_script' was cancelled
+INFO: [Vivado 12-5357] 'compile' step aborted
+INFO: [Common 17-344] 'launch_simulation' was cancelled
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+ERROR: [VRFC 10-3167] cannot convert type 'integer' to type 'unsigned' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:36]
+ERROR: [VRFC 10-2942] 'unsigned' is illegal in an expression [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:36]
+ERROR: [VRFC 10-9434] type conversion expression type for 'std_logic_vector' cannot be uniquely determined [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:36]
+ERROR: [VRFC 10-9458] unit 'modulo6_a' is ignored due to previous errors [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [VRFC 10-8704] VHDL file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd' is ignored due to errors
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log'
+ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture arch of entity xil_defaultlib.compteur_modulo6_tb [compteur_modulo6_tb]
+Built simulation snapshot compteur_modulo6_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "compteur_modulo6_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:compteur_modulo6_tb_arch_cfg} -tclbatch {compteur_modulo6_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source compteur_modulo6_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'compteur_modulo6_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8973.656 ; gain = 64.613 ; free physical = 7610 ; free virtual = 16156
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture arch of entity xil_defaultlib.compteur_modulo6_tb [compteur_modulo6_tb]
+Built simulation snapshot compteur_modulo6_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "compteur_modulo6_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:compteur_modulo6_tb_arch_cfg} -tclbatch {compteur_modulo6_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source compteur_modulo6_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'compteur_modulo6_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 8979.664 ; gain = 6.008 ; free physical = 7626 ; free virtual = 16194
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+set_property top loto_tb_ar_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+update_compile_order -fileset sim_1
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+ERROR: [VRFC 10-4982] syntax error near 'case' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:42]
+ERROR: [VRFC 10-9458] unit 'a_automate' is ignored due to previous errors [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [VRFC 10-8704] VHDL file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd' is ignored due to errors
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log'
+ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur1_49'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_valid'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'diviseur_freq'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'led_pwm'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'registres'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'transcodeur7s_d_u'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'modulo4'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-3219] choice 'st_end_red' is already covered [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:92]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-3219] choice 'st_end_red' is already covered [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:92]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_automate of entity xil_defaultlib.automate [automate_default]
+Compiling architecture a_registres of entity xil_defaultlib.registres [registres_default]
+Compiling architecture a_compteur_valid of entity xil_defaultlib.compteur_valid [compteur_valid_default]
+Compiling architecture compteur_a of entity xil_defaultlib.compteur1_49 [compteur1_49_default]
+Compiling architecture arch of entity xil_defaultlib.led_pwm [led_pwm_default]
+Compiling architecture a_tirage of entity xil_defaultlib.tirage [tirage_default]
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture behavioral of entity xil_defaultlib.diviseur_freq [\diviseur_freq(n_fast=0,n_slow=3...]
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture transcod_int of entity xil_defaultlib.transcodeur7s_d_u [transcodeur7s_d_u_default]
+Compiling architecture modulo4_a of entity xil_defaultlib.modulo4 [modulo4_default]
+Compiling architecture arch of entity xil_defaultlib.loto [\loto(n_fast=0,n_slow=3)\]
+Compiling architecture ar of entity xil_defaultlib.loto_tb [loto_tb]
+Built simulation snapshot loto_tb_ar_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source loto_tb_ar_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 9255.504 ; gain = 57.801 ; free physical = 7613 ; free virtual = 16165
+current_wave_config {Untitled 5}
+Untitled 5
+log_wave {/loto_tb}
+current_wave_config {Untitled 5}
+Untitled 5
+add_wave {{/loto_tb}}
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source loto_tb_ar_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9275.504 ; gain = 0.000 ; free physical = 7639 ; free virtual = 16194
+current_wave_config {Untitled 6}
+Untitled 6
+add_wave {{/loto_tb/DUT/tirage_1/registres_2}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 9275.504 ; gain = 0.000 ; free physical = 7678 ; free virtual = 16158
+current_wave_config {Untitled 6}
+Untitled 6
+add_wave {{/loto_tb/DUT/transcod_1}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 9275.504 ; gain = 0.000 ; free physical = 7742 ; free virtual = 16216
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+run all
+INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+run: Time (s): cpu = 00:04:46 ; elapsed = 00:04:57 . Memory (MB): peak = 9301.906 ; gain = 26.402 ; free physical = 866 ; free virtual = 15698
+INFO: [Common 17-344] 'run' was cancelled
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+[Wed Feb 12 11:14:31 2025] Launched synth_1...
+Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/runme.log
+[Wed Feb 12 11:14:31 2025] Launched impl_1...
+Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/runme.log
+open_hw_manager
+connect_hw_server -allow_non_jtag
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-2222] Launching hw_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+****** Xilinx hw_server v2024.1
+ **** Build date : May 22 2024 at 19:19:01
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+
+INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
+INFO: [Labtools 27-3417] Launching cs_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+
+******** Xilinx cs_server v2024.1.0
+ ****** Build date : Apr 27 2024-03:40:49
+ **** Build number : 2024.1.1714182049
+ ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+
+open_hw_target
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274675171A
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+current_hw_device [get_hw_devices xc7a100t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
+INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+synth_design -rtl -rtl_skip_mlo -name rtl_1
+Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
+Starting synth_design
+Using part: xc7a100tcsg324-1
+Top: loto
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 48722
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 10184.988 ; gain = 399.773 ; free physical = 1399 ; free virtual = 14895
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'loto' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'tirage' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'automate' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [Synth 8-256] done synthesizing module 'automate' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'registres' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'registres' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/registres.vhd:23]
+INFO: [Synth 8-638] synthesizing module 'compteur_valid' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd:15]
+INFO: [Synth 8-256] done synthesizing module 'compteur_valid' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_valid.vhd:15]
+INFO: [Synth 8-638] synthesizing module 'compteur1_49' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'compteur1_49' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:16]
+INFO: [Synth 8-638] synthesizing module 'led_pwm' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'led_pwm' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'tirage' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'compteur_modulo6' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-256] done synthesizing module 'compteur_modulo6' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-638] synthesizing module 'diviseur_freq' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd:18]
+ Parameter n_fast bound to: 15 - type: integer
+ Parameter n_slow bound to: 25 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'diviseur_freq' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/diviseur_freq.vhd:18]
+INFO: [Synth 8-638] synthesizing module 'mux6_1' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:20]
+INFO: [Synth 8-256] done synthesizing module 'mux6_1' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:20]
+INFO: [Synth 8-638] synthesizing module 'transcodeur7s_d_u_transcod_int' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-256] done synthesizing module 'transcodeur7s_d_u_transcod_int' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-638] synthesizing module 'modulo4' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'modulo4' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'loto' (0#1) [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:21]
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 10268.832 ; gain = 483.617 ; free physical = 1281 ; free virtual = 14778
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 10283.676 ; gain = 498.461 ; free physical = 1279 ; free virtual = 14776
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 10283.676 ; gain = 498.461 ; free physical = 1279 ; free virtual = 14776
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10283.684 ; gain = 0.000 ; free physical = 1287 ; free virtual = 14784
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc]
+Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10402.457 ; gain = 0.000 ; free physical = 1560 ; free virtual = 15059
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+RTL Elaboration Complete: : Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 10435.301 ; gain = 650.086 ; free physical = 1480 ; free virtual = 15012
+31 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 10435.301 ; gain = 1006.000 ; free physical = 1480 ; free virtual = 15012
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3071.865; main = 3061.524; forked = 10.341
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 10542.855; main = 10435.305; forked = 107.551
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+update_files -from_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc -to_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc -filesets [get_filesets *]
+INFO: [filemgmt 20-762] Replacing file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc' with file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc'.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur1_49.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo4.vhd:]
+INFO: [Common 17-14] Message 'filemgmt 56-199' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+reset_run synth_1
+INFO: [Project 1-1160] Copying file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.dcp to /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1 and adding it to utils fileset
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+[Wed Feb 12 11:22:49 2025] Launched synth_1...
+Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/runme.log
+[Wed Feb 12 11:22:50 2025] Launched impl_1...
+Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/runme.log
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+refresh_design
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc]
+Completed Processing XDC Constraints
+
+ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210274675171A
+open_run impl_1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10459.199 ; gain = 0.000 ; free physical = 2354 ; free virtual = 14805
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10459.199 ; gain = 0.000 ; free physical = 2428 ; free virtual = 14817
+INFO: [Timing 38-478] Restoring timing data from binary archive.
+INFO: [Timing 38-479] Binary timing data restore complete.
+INFO: [Project 1-856] Restoring constraints from binary archive.
+INFO: [Project 1-853] Binary constraint restore complete.
+INFO: [Designutils 20-5722] Start Reading Physical Databases.
+Reading placement.
+Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292
+Reading placer database...
+Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292
+Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292
+Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292
+Reading routing.
+Read RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1928 ; free virtual = 14290
+Read Physdb Files: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1928 ; free virtual = 14290
+Restored from archive | CPU: 0.030000 secs | Memory: 0.246185 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1928 ; free virtual = 14290
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1926 ; free virtual = 14288
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+open_run: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 10970.902 ; gain = 511.703 ; free physical = 1894 ; free virtual = 14277
+report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+close_sim
+INFO: xsimkernel Simulation Memory Usage: 110128 KB (Peak: 159460 KB), Simulation CPU Usage: 165610 ms
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_automate of entity xil_defaultlib.automate [automate_default]
+Compiling architecture a_registres of entity xil_defaultlib.registres [registres_default]
+Compiling architecture a_compteur_valid of entity xil_defaultlib.compteur_valid [compteur_valid_default]
+Compiling architecture compteur_a of entity xil_defaultlib.compteur1_49 [compteur1_49_default]
+Compiling architecture arch of entity xil_defaultlib.led_pwm [led_pwm_default]
+Compiling architecture a_tirage of entity xil_defaultlib.tirage [tirage_default]
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture behavioral of entity xil_defaultlib.diviseur_freq [\diviseur_freq(n_fast=0,n_slow=3...]
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture transcod_int of entity xil_defaultlib.transcodeur7s_d_u [transcodeur7s_d_u_default]
+Compiling architecture modulo4_a of entity xil_defaultlib.modulo4 [modulo4_default]
+Compiling architecture arch of entity xil_defaultlib.loto [\loto(n_fast=0,n_slow=3)\]
+Compiling architecture ar of entity xil_defaultlib.loto_tb [loto_tb]
+Built simulation snapshot loto_tb_ar_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source loto_tb_ar_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 11096.234 ; gain = 0.000 ; free physical = 4684 ; free virtual = 13201
+current_wave_config {Untitled 7}
+Untitled 7
+add_wave {{/loto_tb/DUT/tirage_1/automate_1}}
+current_wave_config {Untitled 7}
+Untitled 7
+add_wave {{/loto_tb/DUT/tirage_1/registres_2}}
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 11096.234 ; gain = 0.000 ; free physical = 4728 ; free virtual = 13171
diff --git a/vivado_pid13301.str b/vivado_pid13301.str
new file mode 100644
index 0000000..1fb3b22
--- /dev/null
+++ b/vivado_pid13301.str
@@ -0,0 +1,4488 @@
+/*
+
+AMD Vivado v2024.1 (64-bit) [Major: 2024, Minor: 1]
+SW Build: 5076996 on Wed May 22 18:36:09 MDT 2024
+IP Build: 5075265 on Wed May 22 21:45:21 MDT 2024
+IP Build: 5075265 on Wed May 22 21:45:21 MDT 2024
+
+Process ID (PID): 13301
+License: Customer
+Mode: GUI Mode
+
+Current time: Wed Feb 12 09:59:05 CET 2025
+Time zone: Central European Standard Time (Europe/Paris)
+
+OS: Ubuntu
+OS Version: 6.8.0-51-generic
+OS Architecture: amd64
+Available processors (cores): 4
+LSB Release Description: DISTRIB_ID=Ubuntu
+
+Display: 0
+Screen size: 2560x1440
+Local screen bounds: x = 66, y = 32, width = 2494, height = 1408
+Screen resolution (DPI): 100
+Available screens: 2
+Default font: family=Dialog,name=Dialog,style=plain,size=12
+Scale size: 12
+OS font scaling: 100%
+Anti-Alias Enabled: false
+
+Java version: 21.0.1 64-bit
+JavaFX version: 21.0.1
+Java home: /opt/img/Vivado2024.1/Vivado/2024.1/tps/lnx64/jre21.0.1_12
+Java executable: /opt/img/Vivado2024.1/Vivado/2024.1/tps/lnx64/jre21.0.1_12/bin/java
+Java arguments: [-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.uiScale.enabled=false, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, -XX:+UseStringDeduplication, -XX:MaxGCPauseMillis=200, -XX:+ParallelRefProcEnabled, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/java.awt.event=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.base/java.nio=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-exports=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-exports=java.desktop/sun.swing=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.table=ALL-UNNAMED, --add-exports=java.desktop/sun.swing.plaf.synth=ALL-UNNAMED, --add-exports=java.desktop/sun.awt.shell=ALL-UNNAMED, --add-exports=java.base/sun.security.action=ALL-UNNAMED, --add-exports=java.desktop/sun.font=ALL-UNNAMED, --add-opens=java.desktop/sun.awt.X11=ALL-UNNAMED, -XX:NewSize=80m, -XX:MaxNewSize=80m, -Xms512m, -Xmx4072m, -Xss10m, -Xrs]
+Java initial memory (-Xms): 512 MB
+Java maximum memory (-Xmx): 3 GB
+
+User name: m22kling
+User home directory: /homes/m22kling
+User working directory: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling
+User country: US
+User language: en
+User locale: en_US
+
+RDI_BASEROOT: /opt/img/Vivado2024.1/Vivado
+HDI_APPROOT: /opt/img/Vivado2024.1/Vivado/2024.1
+RDI_DATADIR: /opt/img/Vivado2024.1/Vivado/2024.1/data
+RDI_BINDIR: /opt/img/Vivado2024.1/Vivado/2024.1/bin
+
+Vivado preferences file: /homes/m22kling/.Xilinx/Vivado/2024.1/vivado.xml
+Vivado preferences directory: /homes/m22kling/.Xilinx/Vivado/2024.1/
+Vivado layouts directory: /homes/m22kling/.Xilinx/Vivado/2024.1/data/layouts
+PlanAhead jar file: /opt/img/Vivado2024.1/Vivado/2024.1/lib/classes/planAhead.jar
+Vivado log file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/vivado.log
+Vivado journal file: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/vivado.jou
+Engine tmp dir: ./.Xil/Vivado-13301-fl-tp-br-637
+Non-Default Parameters: []
+
+Xilinx & AMD Environment Variables
+--------------------------------------------------------------------------------------------
+GNOME_SHELL_SESSION_MODE: ubuntu
+RDI_APPROOT: /opt/img/Vivado2024.1/Vivado/2024.1
+RDI_BASEROOT: /opt/img/Vivado2024.1/Vivado
+RDI_BINROOT: /opt/img/Vivado2024.1/Vivado/2024.1/bin
+RDI_BUILD: yes
+RDI_DATADIR: /opt/img/Vivado2024.1/Vivado/2024.1/data
+RDI_INSTALLROOT: /opt/img/Vivado2024.1
+RDI_INSTALLVER: 2024.1
+RDI_JAVA_PLATFORM:
+RDI_JAVA_VERSION: 21.0.1_12
+RDI_LIBDIR: /opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/Ubuntu:/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o
+RDI_OPT_EXT: .o
+RDI_PATCHROOT:
+RDI_PLATFORM: lnx64
+RDI_PREPEND_PATH: /opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64
+RDI_PROG: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/vivado
+RDI_SESSION_INFO: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling:fl-tp-br-637_1739350729_13232
+RDI_SHARED_DATA: /opt/img/Vivado2024.1/SharedData/2024.1/data
+RDI_TPS_ROOT: /opt/img/Vivado2024.1/Vivado/2024.1/tps/lnx64
+RDI_USE_JDK21: True
+SHELL: /bin/bash
+XILINX: /opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE
+XILINXD_LICENSE_FILE: 27007@licence-01.imta.fr
+XILINX_DSP: /opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE
+XILINX_HLS: /opt/img/Vivado2024.1/Vitis_HLS/2024.1
+XILINX_PLANAHEAD: /opt/img/Vivado2024.1/Vivado/2024.1
+XILINX_SDK: /opt/img/Vivado2024.1/Vitis/2024.1
+XILINX_VITIS: /opt/img/Vivado2024.1/Vitis/2024.1
+XILINX_VIVADO: /opt/img/Vivado2024.1/Vivado/2024.1
+XILINX_VIVADO_HLS: /opt/img/Vivado2024.1/Vivado/2024.1
+
+
+GUI allocated memory: 512 MB
+GUI max memory: 4,072 MB
+Engine allocated memory: 1,362 MB
+
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+*/
+
+// TclEventType: START_GUI
+// Tcl Message: start_gui
+selectMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ah (PAResourceItoN.MainMenuMgr_FILE, File)
+selectMenu(PAResourceItoN.MainMenuMgr_PROJECT, "Project"); // am (PAResourceItoN.MainMenuMgr_PROJECT, Project)
+selectMenuItem(PAResourceCommand.PACommandNames_OPEN_PROJECT, "Open..."); // ap (PAResourceCommand.PACommandNames_OPEN_PROJECT, open_project_menu)
+dismissMenu(PAResourceItoN.MainMenuMgr_FILE, "File"); // ah (PAResourceItoN.MainMenuMgr_FILE, File)
+// Run Command: PAResourceCommand.PACommandNames_OPEN_PROJECT
+// HMemoryUtils.trashcanNow. Engine heap size: 1,425 MB. GUI used memory: 82 MB. Current time: 2/12/25, 9:59:06 AM CET
+setFileChooser("/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr");
+// Opening Vivado Project: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr. Version: Vivado v2024.1
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: FLOW_ADDED
+// Tcl Message: open_project /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr
+// Tcl Message: INFO: [Common 17-14] Message 'Board 49-26' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+// TclEventType: MSGMGR_MOVEMSG
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_NEW
+// TclEventType: RUN_CURRENT
+// TclEventType: PROJECT_DASHBOARD_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_NEW
+// HMemoryUtils.trashcanNow. Engine heap size: 2,016 MB. GUI used memory: 78 MB. Current time: 2/12/25, 9:59:26 AM CET
+// [GUI Memory]: 109 MB (+112128kb) [00:00:31]
+// [Engine Memory]: 2,041 MB (+1988270kb) [00:00:31]
+// [GUI Memory]: 147 MB (+34089kb) [00:00:32]
+// WARNING: HEventQueue.dispatchEvent() is taking 1744 ms.
+// Tcl Message: open_project /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.xpr
+// Tcl Message: INFO: [Common 17-14] Message 'Board 49-26' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-313] Project file moved from '/homes/m22kling/loto' since last save. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.gen/sources_1'.
+// Tcl Message: Scanning sources... Finished scanning sources
+// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+// [Engine Memory]: 2,144 MB (+1874kb) [00:00:33]
+// Project name: loto; location: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto; part: xc7a100tcsg324-1
+// Tcl Message: open_project: Time (s): cpu = 00:00:29 ; elapsed = 00:00:19 . Memory (MB): peak = 8272.281 ; gain = 655.664 ; free physical = 8354 ; free virtual = 16422
+// Elapsed time: 19 seconds
+dismissDialog("Open Project"); // bj (Open Project Progress)
+// Tcl Message: update_compile_order -fileset sources_1
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+// HMemoryUtils.trashcanNow. Engine heap size: 2,181 MB. GUI used memory: 83 MB. Current time: 2/12/25, 9:59:41 AM CET
+// Elapsed time: 12 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, mux6_1.vhd]", 4, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, mux6_1.vhd]", 4, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+selectCodeEditor("mux6_1.vhd", 177, 341); // ac (mux6_1.vhd)
+// WARNING: HSwingWorker (Refresh Filesets Swing Worker) is taking 2643 ms. Increasing delay to 7929 ms.
+// Elapsed time: 28 seconds
+selectCodeEditor("mux6_1.vhd", 129, 340); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 129, 340, false, false, false, false, true); // ac (mux6_1.vhd) - Double Click
+// Elapsed time: 137 seconds
+typeControlKey((HResource) null, "mux6_1.vhd", 'c'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+// Elapsed time: 17 seconds
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+// [Engine Memory]: 2,252 MB (+612kb) [00:04:11]
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 03m:46s
+// [GUI Memory]: 157 MB (+2404kb) [00:04:19]
+// HMemoryUtils.trashcanNow. Engine heap size: 2,289 MB. GUI used memory: 86 MB. Current time: 2/12/25, 10:03:16 AM CET
+// Elapsed Time for: 'L.f': 03m:50s
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 04m:04s
+// Elapsed time: 35 seconds
+selectCodeEditor("mux6_1.vhd", 48, 506); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 48, 506, false, false, false, false, true); // ac (mux6_1.vhd) - Double Click
+// Elapsed Time for: 'L.f': 04m:08s
+selectCodeEditor("mux6_1.vhd", 164, 353); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'c'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 11, 535); // ac (mux6_1.vhd)
+// Elapsed time: 30 seconds
+selectCodeEditor("mux6_1.vhd", 45, 334); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 79, 334); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 62, 351); // ac (mux6_1.vhd)
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+selectCodeEditor("mux6_1.vhd", 79, 539); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'c'); // ac (mux6_1.vhd)
+// Elapsed time: 27 seconds
+selectCodeEditor("mux6_1.vhd", 111, 352); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 111, 352, false, false, false, false, true); // ac (mux6_1.vhd) - Double Click
+selectCodeEditor("mux6_1.vhd", 137, 381); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 135, 417); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 141, 441); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 141, 477); // ac (mux6_1.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 06m:26s
+// HMemoryUtils.trashcanNow. Engine heap size: 2,327 MB. GUI used memory: 87 MB. Current time: 2/12/25, 10:05:56 AM CET
+// Elapsed Time for: 'L.f': 06m:30s
+// Elapsed time: 21 seconds
+selectCodeEditor("mux6_1.vhd", 104, 547); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'c'); // ac (mux6_1.vhd)
+// Elapsed time: 11 seconds
+selectCodeEditor("mux6_1.vhd", 405, 555); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 87, 547); // ac (mux6_1.vhd)
+// Elapsed time: 46 seconds
+typeControlKey((HResource) null, "mux6_1.vhd", 'c'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey(null, null, 'z');
+typeControlKey((HResource) null, "mux6_1.vhd", 'c'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+typeControlKey((HResource) null, "mux6_1.vhd", 'v'); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 80, 628); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 211, 581); // ac (mux6_1.vhd)
+// Elapsed time: 10 seconds
+selectCodeEditor("mux6_1.vhd", 273, 626); // ac (mux6_1.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 08m:14s
+selectCodeEditor("mux6_1.vhd", 67, 542); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 72, 530); // ac (mux6_1.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 08m:18s
+// HMemoryUtils.trashcanNow. Engine heap size: 2,373 MB. GUI used memory: 88 MB. Current time: 2/12/25, 10:07:46 AM CET
+// [Engine Memory]: 2,373 MB (+8233kb) [00:08:51]
+// Elapsed Time for: 'L.f': 08m:22s
+// Elapsed time: 11 seconds
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources]", 11); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1]", 12); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectCheckBox(PAResourceQtoS.SrcFilePropPanels_SYNTHESIS, "Synthesis", false); // f (PAResourceQtoS.SrcFilePropPanels_SYNTHESIS): FALSE
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Tcl Message: set_property used_in_synthesis false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd]
+// Elapsed Time for: 'L.f': 08m:42s
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+// Elapsed Time for: 'L.f': 08m:46s
+selectCodeEditor("mux6_1.vhd", 291, 617); // ac (mux6_1.vhd)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true, false, false, false, true, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Popup Trigger - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click - Node
+// HMemoryUtils.trashcanNow. Engine heap size: 2,415 MB. GUI used memory: 89 MB. Current time: 2/12/25, 10:08:36 AM CET
+// Elapsed time: 13 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true, false, false, false, true, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Popup Trigger - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 14, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, mux6_1_tb_arch_cfg(mux6_1_tb - arch) (mux6_1_tb.vhd)]", 18, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectCheckBox(PAResourceQtoS.SrcFilePropPanels_SYNTHESIS, "Synthesis", false); // f (PAResourceQtoS.SrcFilePropPanels_SYNTHESIS): FALSE
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Tcl Message: set_property used_in_synthesis false [get_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd]
+// Elapsed Time for: 'L.f': 09m:32s
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, mux6_1_tb_arch_cfg(mux6_1_tb - arch) (mux6_1_tb.vhd)]", 18, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, mux6_1_tb_arch_cfg(mux6_1_tb - arch) (mux6_1_tb.vhd)]", 18, true, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click - Node
+// HMemoryUtils.trashcanNow. Engine heap size: 2,465 MB. GUI used memory: 90 MB. Current time: 2/12/25, 10:09:01 AM CET
+// Elapsed Time for: 'L.f': 09m:36s
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, mux6_1_tb_arch_cfg(mux6_1_tb - arch) (mux6_1_tb.vhd)]", 17, true, false, false, false, true, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Popup Trigger - Node
+selectMenu(PAResourceCommand.PACommandNames_OPEN_FILE_WITH, "Open With"); // am (PAResourceCommand.PACommandNames_OPEN_FILE_WITH, Open With)
+selectMenu(PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, "Hierarchy Update"); // am (PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, Hierarchy Update)
+selectMenu(PAResourceQtoS.SrcMenu_IP_HIERARCHY, "IP Hierarchy"); // am (PAResourceQtoS.SrcMenu_IP_HIERARCHY, IP Hierarchy)
+selectMenuItem(PAResourceCommand.PACommandNames_SET_AS_TOP, "Set as Top"); // ap (PAResourceCommand.PACommandNames_SET_AS_TOP, set_as_top_menu)
+// Run Command: PAResourceCommand.PACommandNames_SET_AS_TOP
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: set_property top mux6_1_tb_arch_cfg [get_filesets sim_1]
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// TclEventType: DG_GRAPH_STALE
+// Tcl Message: set_property top_lib xil_defaultlib [get_filesets sim_1]
+// TclEventType: DG_GRAPH_STALE
+// Elapsed Time for: 'L.f': 09m:46s
+// Elapsed Time for: 'L.f': 09m:48s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'mux6_1' INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb' Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// TclEventType: LOAD_FEATURE
+// Tcl Message: Built simulation snapshot mux6_1_tb_arch_cfg_behav
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+// [Engine Memory]: 2,497 MB (+5426kb) [00:10:29]
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Tcl Message: source mux6_1_tb_arch_cfg.tcl
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 2,558 MB. GUI used memory: 104 MB. Current time: 2/12/25, 10:09:26 AM CET
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # }
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 2,558 MB. GUI used memory: 102 MB. Current time: 2/12/25, 10:09:27 AM CET
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 8677.988 ; gain = 82.109 ; free physical = 7907 ; free virtual = 16263
+// 'd' command handler elapsed time: 8 seconds
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 11 seconds
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 2,539 MB. GUI used memory: 102 MB. Current time: 2/12/25, 10:09:39 AM CET
+// Elapsed time: 14 seconds
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, S[5:0]]", 7); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_CLOSE_WCFG
+// Elapsed time: 22 seconds
+closeView(RDIResource.RDIViews_WAVEFORM_VIEWER, "Untitled 1"); // t (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer)
+// Elapsed time: 30 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "mux6_1.vhd", 0); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("mux6_1.vhd", 262, 396); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 99, 402); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 108, 415); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 108, 415, false, false, false, false, true); // ac (mux6_1.vhd) - Double Click
+selectCodeEditor("mux6_1.vhd", 108, 415); // ac (mux6_1.vhd)
+selectCodeEditor("mux6_1.vhd", 277, 396); // ac (mux6_1.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 11m:28s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// Elapsed Time for: 'L.f': 11m:32s
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// [GUI Memory]: 177 MB (+12943kb) [00:12:13]
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+selectButton("OptionPane.button", "Yes", "Simulation is Already Running"); // JButton (OptionPane.button)
+// TclEventType: SIMULATION_CLOSE_SIMULATION
+// Tcl Message: close_sim
+// Tcl Message: INFO: [Simtcl 6-16] Simulation closed
+dismissDialog("Close"); // bj (Close Progress)
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'mux6_1' INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/mux6_1_tb.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb' Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 2,569 MB. GUI used memory: 105 MB. Current time: 2/12/25, 10:11:17 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: source mux6_1_tb_arch_cfg.tcl
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 8685.992 ; gain = 8.004 ; free physical = 7854 ; free virtual = 16263
+// 'd' command handler elapsed time: 8 seconds
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, S[5:0]]", 7); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 2,569 MB. GUI used memory: 105 MB. Current time: 2/12/25, 10:11:21 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_CLOSE_WCFG
+// Elapsed time: 12 seconds
+closeView(RDIResource.RDIViews_WAVEFORM_VIEWER, "Untitled 2"); // t (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "mux6_1.vhd", 0); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+typeControlKey(null, null, 'z');
+selectCodeEditor("mux6_1.vhd", 313, 363, false, true, false, false, false); // ac (mux6_1.vhd) - Control Key
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 12m:20s
+// Elapsed Time for: 'L.f': 12m:24s
+// Elapsed time: 26 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "mux6_1_tb.vhd", 2); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 105 seconds
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, compteur_modulo6.vhd]", 3, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, compteur_modulo6.vhd]", 3, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+// HMemoryUtils.trashcanNow. Engine heap size: 2,605 MB. GUI used memory: 99 MB. Current time: 2/12/25, 10:14:01 AM CET
+selectCodeEditor("compteur_modulo6.vhd", 143, 344); // ac (compteur_modulo6.vhd)
+// Elapsed time: 14 seconds
+selectCodeEditor("compteur_modulo6.vhd", 304, 392); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 158, 379); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 149, 280); // ac (compteur_modulo6.vhd)
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+selectCodeEditor("compteur_modulo6.vhd", 153, 277); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'c'); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 125, 382); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'v'); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 174, 405); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'v'); // ac (compteur_modulo6.vhd)
+// Elapsed time: 31 seconds
+selectCodeEditor("compteur_modulo6.vhd", 335, 421); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 313, 413); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 113, 433); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 272, 421); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 269, 409); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'v'); // ac (compteur_modulo6.vhd)
+// Elapsed time: 16 seconds
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'v'); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'v'); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 475, 590); // ac (compteur_modulo6.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// [Engine Memory]: 2,625 MB (+4164kb) [00:17:19]
+// Elapsed Time for: 'L.f': 16m:48s
+// HMemoryUtils.trashcanNow. Engine heap size: 2,651 MB. GUI used memory: 99 MB. Current time: 2/12/25, 10:16:16 AM CET
+// Elapsed Time for: 'L.f': 16m:52s
+// Elapsed time: 13 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 17, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 17, true, false, false, false, true, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Popup Trigger - Node
+selectMenu(PAResourceCommand.PACommandNames_OPEN_FILE_WITH, "Open With"); // am (PAResourceCommand.PACommandNames_OPEN_FILE_WITH, Open With)
+selectMenu(PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, "Hierarchy Update"); // am (PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, Hierarchy Update)
+selectMenu(PAResourceQtoS.SrcMenu_IP_HIERARCHY, "IP Hierarchy"); // am (PAResourceQtoS.SrcMenu_IP_HIERARCHY, IP Hierarchy)
+selectMenuItem(PAResourceCommand.PACommandNames_SET_AS_TOP, "Set as Top"); // ap (PAResourceCommand.PACommandNames_SET_AS_TOP, set_as_top_menu)
+// Run Command: PAResourceCommand.PACommandNames_SET_AS_TOP
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: set_property top compteur_modulo6_tb_arch_cfg [get_filesets sim_1]
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// TclEventType: DG_GRAPH_STALE
+// Tcl Message: set_property top_lib xil_defaultlib [get_filesets sim_1]
+// TclEventType: DG_GRAPH_STALE
+// Elapsed Time for: 'L.f': 17m:02s
+// Elapsed Time for: 'L.f': 17m:04s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log'
+// Tcl Message: ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)'
+// 'd' command handler elapsed time: 17 seconds
+// Elapsed time: 17 seconds
+selectButton("OptionPane.button", "OK", "Run Simulation"); // JButton (OptionPane.button)
+selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK", "Critical Messages"); // f (PAResourceAtoD.CmdMsgDialog_OK)
+dismissDialog("Critical Messages"); // a (dialog1)
+selectCodeEditor("compteur_modulo6.vhd", 95, 333); // ac (compteur_modulo6.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// [Engine Memory]: 2,758 MB (+1080kb) [00:18:07]
+// Elapsed Time for: 'L.f': 17m:36s
+// HMemoryUtils.trashcanNow. Engine heap size: 2,785 MB. GUI used memory: 100 MB. Current time: 2/12/25, 10:17:06 AM CET
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// Elapsed Time for: 'L.f': 17m:40s
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+selectButton(RDIResource.ProgressDialog_CANCEL, "Cancel", "Run Simulation"); // a (RDIResource.ProgressDialog_CANCEL)
+// Tcl Message: INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+// CommandFailedException: ERROR: [Common 17-69] Command failed:
+// Tcl Message: INFO: [Common 17-344] 'execute_script' was cancelled INFO: [Vivado 12-5357] 'compile' step aborted INFO: [Common 17-344] 'launch_simulation' was cancelled
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// Elapsed time: 12 seconds
+selectCodeEditor("compteur_modulo6.vhd", 92, 390); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 144, 462); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 93, 390); // ac (compteur_modulo6.vhd)
+typeControlKey(null, null, 'z');
+selectCodeEditor("compteur_modulo6.vhd", 115, 429); // ac (compteur_modulo6.vhd)
+// Elapsed time: 15 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, compteur_modulo4(modulo4_a) (compteur_modulo4.vhd)]", 4, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, compteur_modulo4(modulo4_a) (compteur_modulo4.vhd)]", 4, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("compteur_modulo6.vhd", 190, 381); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 205, 278); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 205, 278, false, false, false, false, true); // ac (compteur_modulo6.vhd) - Double Click
+// Elapsed time: 15 seconds
+selectCodeEditor("compteur_modulo6.vhd", 299, 279); // ac (compteur_modulo6.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 19m:12s
+// Elapsed Time for: 'L.f': 19m:16s
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 19m:42s
+// Elapsed time: 52 seconds
+selectCodeEditor("compteur_modulo6.vhd", 263, 530); // ac (compteur_modulo6.vhd)
+// Elapsed Time for: 'L.f': 19m:46s
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 19m:54s
+selectCodeEditor("compteur_modulo6.vhd", 99, 528); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 99, 528, false, false, false, false, true); // ac (compteur_modulo6.vhd) - Double Click
+// Elapsed Time for: 'L.f': 19m:58s
+// Elapsed time: 10 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log'
+// Tcl Message: ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)'
+// 'd' command handler elapsed time: 4 seconds
+selectButton("OptionPane.button", "OK", "Run Simulation"); // JButton (OptionPane.button)
+selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK", "Critical Messages"); // f (PAResourceAtoD.CmdMsgDialog_OK)
+dismissDialog("Critical Messages"); // a (dialog2)
+selectCodeEditor("compteur_modulo6.vhd", 359, 635); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 323, 159); // ac (compteur_modulo6.vhd)
+// Elapsed time: 25 seconds
+selectCodeEditor("compteur_modulo6.vhd", 267, 534); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 417, 528); // ac (compteur_modulo6.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+selectCodeEditor("compteur_modulo6.vhd", 629, 285); // ac (compteur_modulo6.vhd)
+// Elapsed Time for: 'L.f': 20m:50s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6' INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6_tb' Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "compteur_modulo6_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:compteur_modulo6_tb_arch_cfg} -tclbatch {compteur_modulo6_tb_arch_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 2,851 MB. GUI used memory: 113 MB. Current time: 2/12/25, 10:20:27 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: source compteur_modulo6_tb_arch_cfg.tcl
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'compteur_modulo6_tb_arch_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8973.656 ; gain = 64.613 ; free physical = 7610 ; free virtual = 16156
+// 'd' command handler elapsed time: 6 seconds
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// Elapsed Time for: 'L.f': 21m:00s
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 2,851 MB. GUI used memory: 112 MB. Current time: 2/12/25, 10:20:30 AM CET
+// Elapsed time: 14 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 15 seconds
+selectCodeEditor("compteur_modulo6.vhd", 342, 392); // ac (compteur_modulo6.vhd)
+// Elapsed time: 27 seconds
+selectCodeEditor("compteur_modulo6.vhd", 273, 408); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 87, 430); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 245, 409); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 313, 492); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'c'); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 175, 433); // ac (compteur_modulo6.vhd)
+typeControlKey((HResource) null, "compteur_modulo6.vhd", 'v'); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 180, 416); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 85, 426); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 314, 428); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 375, 429); // ac (compteur_modulo6.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 22m:28s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+selectButton("OptionPane.button", "Yes", "Simulation is Already Running"); // JButton (OptionPane.button)
+// TclEventType: WAVEFORM_CLOSE_WCFG
+// TclEventType: SIMULATION_CLOSE_SIMULATION
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// Tcl Message: close_sim
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: INFO: [Simtcl 6-16] Simulation closed
+dismissDialog("Close"); // bj (Close Progress)
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6' INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/compteur_modulo6_tb.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6_tb' Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "compteur_modulo6_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:compteur_modulo6_tb_arch_cfg} -tclbatch {compteur_modulo6_tb_arch_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background", "Run Simulation"); // a (RDIResource.ProgressDialog_BACKGROUND)
+// 'd' command handler elapsed time: 6 seconds
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo4.vhd", 4); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: source compteur_modulo6_tb_arch_cfg.tcl
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'compteur_modulo6_tb_arch_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 8979.664 ; gain = 6.008 ; free physical = 7626 ; free virtual = 16194
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// Elapsed Time for: 'L.f': 22m:38s
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 35 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 4", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// HMemoryUtils.trashcanNow. Engine heap size: 2,856 MB. GUI used memory: 115 MB. Current time: 2/12/25, 10:22:43 AM CET
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 39 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo4.vhd", 4); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("compteur_modulo4.vhd", 270, 859); // ac (compteur_modulo4.vhd)
+selectCodeEditor("compteur_modulo4.vhd", 285, 730); // ac (compteur_modulo4.vhd)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 57 seconds
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, automate.vhd]", 2, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files, automate.vhd]", 2, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+// [GUI Memory]: 189 MB (+3201kb) [00:25:34]
+// HMemoryUtils.trashcanNow. Engine heap size: 2,886 MB. GUI used memory: 116 MB. Current time: 2/12/25, 10:24:31 AM CET
+// Elapsed time: 32 seconds
+selectCodeEditor("automate.vhd", 195, 763); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 142, 784); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+typeControlKey(null, null, 'z');
+selectCodeEditor("automate.vhd", 202, 702); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 292, 737); // ac (automate.vhd)
+// Elapsed time: 11 seconds
+selectCodeEditor("automate.vhd", 251, 776); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 292, 789); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 292, 789, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 292, 790); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 200, 805); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 227, 816); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+typeControlKey(null, null, 'z');
+selectCodeEditor("automate.vhd", 206, 765); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 122, 802); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 251, 534); // ac (automate.vhd)
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+typeControlKey(null, null, 'z');
+selectCodeEditor("automate.vhd", 250, 665); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 295, 682); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 296, 720); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 301, 719); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 207, 743); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 220, 741); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 310, 760); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 335, 759); // ac (automate.vhd)
+// Elapsed time: 28 seconds
+selectCodeEditor("automate.vhd", 371, 751); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 205, 777); // ac (automate.vhd)
+// Elapsed time: 23 seconds
+selectCodeEditor("automate.vhd", 171, 756); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 305, 780); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 276, 794); // ac (automate.vhd)
+// Elapsed time: 21 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("automate.vhd", 288, 770); // ac (automate.vhd)
+// Elapsed time: 17 seconds
+selectCodeEditor("automate.vhd", 230, 743); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// [Engine Memory]: 2,897 MB (+1101kb) [00:29:31]
+// Elapsed Time for: 'L.f': 29m:00s
+selectCodeEditor("automate.vhd", 266, 815); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 269, 807); // ac (automate.vhd)
+// HMemoryUtils.trashcanNow. Engine heap size: 2,923 MB. GUI used memory: 117 MB. Current time: 2/12/25, 10:28:31 AM CET
+selectCodeEditor("automate.vhd", 225, 806); // ac (automate.vhd)
+// Elapsed Time for: 'L.f': 29m:04s
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 148, 825); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 208, 776); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 208, 776, false, false, false, false, true); // ac (automate.vhd) - Double Click
+// Elapsed time: 11 seconds
+selectCodeEditor("automate.vhd", 231, 832); // ac (automate.vhd)
+// Elapsed time: 17 seconds
+selectCodeEditor("automate.vhd", 225, 760); // ac (automate.vhd)
+// Elapsed time: 12 seconds
+selectCodeEditor("automate.vhd", 307, 773); // ac (automate.vhd)
+// Elapsed time: 36 seconds
+selectCodeEditor("automate.vhd", 310, 806); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+selectCodeEditor("automate.vhd", 226, 814); // ac (automate.vhd)
+// Elapsed Time for: 'L.f': 30m:42s
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 23, 833); // ac (automate.vhd)
+// HMemoryUtils.trashcanNow. Engine heap size: 2,949 MB. GUI used memory: 117 MB. Current time: 2/12/25, 10:30:11 AM CET
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+// Elapsed Time for: 'L.f': 30m:46s
+selectCodeEditor("automate.vhd", 203, 683); // ac (automate.vhd)
+// Elapsed time: 11 seconds
+selectCodeEditor("automate.vhd", 246, 383); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 199, 411); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 198, 269); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 244, 240); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 247, 109); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 199, 142); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 244, 550); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 200, 579); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 239, 713); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 195, 742); // ac (automate.vhd)
+// Elapsed time: 10 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 66 seconds
+selectCodeEditor("compteur_modulo6.vhd", 317, 431); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 317, 431, false, false, false, false, true); // ac (compteur_modulo6.vhd) - Double Click
+selectCodeEditor("compteur_modulo6.vhd", 317, 431); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 317, 431, false, false, false, false, true); // ac (compteur_modulo6.vhd) - Double Click
+selectCodeEditor("compteur_modulo6.vhd", 317, 431); // ac (compteur_modulo6.vhd)
+selectCodeEditor("compteur_modulo6.vhd", 317, 431); // ac (compteur_modulo6.vhd)
+// Elapsed time: 24 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("automate.vhd", 201, 761); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 198, 761); // ac (automate.vhd)
+// Elapsed time: 13 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 3); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("automate.vhd", 324, 774); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 403, 808); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 219, 792); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 296, 785); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 293, 568); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 299, 690); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 288, 740); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 333, 759); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 34m:32s
+// Elapsed Time for: 'L.f': 34m:36s
+// Elapsed time: 11 seconds
+selectCodeEditor("automate.vhd", 344, 779); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 1, 791); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 213, 801); // ac (automate.vhd)
+// Elapsed time: 18 seconds
+selectCodeEditor("automate.vhd", 327, 728); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 296, 687); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 250, 743); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 340, 758); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 35m:30s
+selectCodeEditor("automate.vhd", 204, 536); // ac (automate.vhd)
+// HMemoryUtils.trashcanNow. Engine heap size: 2,975 MB. GUI used memory: 117 MB. Current time: 2/12/25, 10:35:01 AM CET
+// Elapsed Time for: 'L.f': 35m:34s
+selectCodeEditor("automate.vhd", 354, 699); // ac (automate.vhd)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 4", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 14 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 129, 185); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1350, 436, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 2,957 MB. GUI used memory: 118 MB. Current time: 2/12/25, 10:35:25 AM CET
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// Elapsed time: 25 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6_tb.vhd", 1); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "mux6_1.vhd", 0); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// [GUI Memory]: 205 MB (+7209kb) [00:37:03]
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 4", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("automate.vhd", 234, 570); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 242, 538); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 221, 539); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 221, 539, false, false, false, false, true); // ac (automate.vhd) - Double Click
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+typeControlKey(null, null, 'z');
+selectCodeEditor("automate.vhd", 334, 697); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 334, 697, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 334, 697); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'c'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 201, 533); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 201, 533, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 201, 533); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 172, 531); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 249, 532); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 37m:02s
+// Elapsed Time for: 'L.f': 37m:06s
+// Elapsed time: 39 seconds
+selectCodeEditor("automate.vhd", 259, 785); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 259, 785, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 259, 785); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 37m:38s
+// Elapsed Time for: 'L.f': 37m:42s
+// HMemoryUtils.trashcanNow. Engine heap size: 3,002 MB. GUI used memory: 119 MB. Current time: 2/12/25, 10:37:11 AM CET
+// Elapsed time: 45 seconds
+selectCodeEditor("automate.vhd", 28, 169); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 135, 693); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 142, 702); // ac (automate.vhd)
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 234 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, loto_tb_ar_cfg(loto_tb - ar) (loto_tb.vhd)]", 17, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, loto_tb_ar_cfg(loto_tb - ar) (loto_tb.vhd)]", 17, true, false, false, false, true, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Popup Trigger - Node
+selectMenu(PAResourceCommand.PACommandNames_OPEN_FILE_WITH, "Open With"); // am (PAResourceCommand.PACommandNames_OPEN_FILE_WITH, Open With)
+selectMenu(PAResourceCommand.PACommandNames_OPEN_FILE_WITH, "Open With"); // am (PAResourceCommand.PACommandNames_OPEN_FILE_WITH, Open With)
+selectMenu(PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, "Hierarchy Update"); // am (PAResourceCommand.PACommandNames_AUTO_UPDATE_HIER, Hierarchy Update)
+selectMenu(PAResourceQtoS.SrcMenu_IP_HIERARCHY, "IP Hierarchy"); // am (PAResourceQtoS.SrcMenu_IP_HIERARCHY, IP Hierarchy)
+selectMenuItem(PAResourceCommand.PACommandNames_SET_AS_TOP, "Set as Top"); // ap (PAResourceCommand.PACommandNames_SET_AS_TOP, set_as_top_menu)
+// Run Command: PAResourceCommand.PACommandNames_SET_AS_TOP
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: set_property top loto_tb_ar_cfg [get_filesets sim_1]
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// TclEventType: DG_GRAPH_STALE
+// Tcl Message: set_property top_lib xil_defaultlib [get_filesets sim_1]
+// TclEventType: DG_GRAPH_STALE
+// Elapsed Time for: 'L.f': 42m:28s
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 42m:30s
+// Tcl Message: update_compile_order -fileset sim_1
+// Elapsed Time for: 'L.f': 42m:32s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// HMemoryUtils.trashcanNow. Engine heap size: 3,028 MB. GUI used memory: 118 MB. Current time: 2/12/25, 10:42:01 AM CET
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// Tcl Message: INFO: [VRFC 10-163] Analyzing VHDL file "/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd" into library xil_defaultlib INFO: [VRFC 10-3107] analyzing entity 'automate' ERROR: [VRFC 10-4982] syntax error near 'case' [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:42] ERROR: [VRFC 10-9458] unit 'a_automate' is ignored due to previous errors [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:21] INFO: [VRFC 10-8704] VHDL file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd' is ignored due to errors
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log'
+// Tcl Message: ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/xvhdl.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)'
+// 'd' command handler elapsed time: 4 seconds
+selectButton("OptionPane.button", "OK", "Run Simulation"); // JButton (OptionPane.button)
+// Elapsed Time for: 'L.f': 42m:40s
+selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK", "Critical Messages"); // f (PAResourceAtoD.CmdMsgDialog_OK)
+dismissDialog("Critical Messages"); // a (dialog3)
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Syntax Error Files]", 13); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Syntax Error Files, automate.vhd]", 14, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, Syntax Error Files, automate.vhd]", 14, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+// Elapsed time: 18 seconds
+selectCodeEditor("automate.vhd", 232, 225); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 232, 225, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 232, 225); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 43m:04s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// [Engine Memory]: 3,046 MB (+4772kb) [00:43:39]
+// Elapsed Time for: 'L.f': 43m:08s
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: Vivado Simulator v2024.1 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log Using 8 slave threads. Starting static elaboration ERROR: [VRFC 10-3219] choice 'st_end_red' is already covered [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:92] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log'
+// Tcl Message: ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)'
+// 'd' command handler elapsed time: 6 seconds
+selectButton("OptionPane.button", "OK", "Run Simulation"); // JButton (OptionPane.button)
+selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK", "Critical Messages"); // f (PAResourceAtoD.CmdMsgDialog_OK)
+dismissDialog("Critical Messages"); // a (dialog4)
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: Vivado Simulator v2024.1 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log Using 8 slave threads. Starting static elaboration ERROR: [VRFC 10-3219] choice 'st_end_red' is already covered [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:92] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log'
+// Tcl Message: ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+// Tcl Message: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// CommandFailedException: ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+// HOptionPane Error: 'ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. (Run Simulation)'
+// 'd' command handler elapsed time: 5 seconds
+selectButton("OptionPane.button", "OK", "Run Simulation"); // JButton (OptionPane.button)
+selectButton(PAResourceAtoD.CmdMsgDialog_OPEN_MESSAGES_VIEW, "Open Messages View", "Critical Messages"); // a (PAResourceAtoD.CmdMsgDialog_OPEN_MESSAGES_VIEW)
+// Run Command: PAResourceCommand.PACommandNames_MESSAGE_WINDOW
+dismissDialog("Critical Messages"); // a (dialog5)
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 11 seconds
+selectTree(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "[, Simulation, sim_1, [VRFC 10-3219] choice 'st_end_red' is already covered [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd:92]. ]", 6, false); // u.d (PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE)
+messagesViewCrossProbe(PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE, "src;-;/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/automate.vhd;-;;-;16;-;line;-;92;-;;-;16;-;"); // u.d (PAResourceItoN.MsgTreePanel_MESSAGE_VIEW_TREE)
+// Elapsed time: 61 seconds
+selectCodeEditor("automate.vhd", 215, 399); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 45m:00s
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// HMemoryUtils.trashcanNow. Engine heap size: 3,088 MB. GUI used memory: 120 MB. Current time: 2/12/25, 10:44:31 AM CET
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 3,128 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:44:37 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: source loto_tb_ar_cfg.tcl
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 9255.504 ; gain = 57.801 ; free physical = 7613 ; free virtual = 16165
+// 'd' command handler elapsed time: 7 seconds
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// Elapsed Time for: 'L.f': 45m:10s
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 61 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 5", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "s_aff[6:0] ; 40 ; Array", 4, "s_aff[6:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "s_aff[6:0] ; 40 ; Array", 4, "s_aff[6:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// Elapsed time: 21 seconds
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "s_aff[6:0] ; 40 ; Array", 4, "s_aff[6:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "s_aff[6:0] ; 40 ; Array", 4, "s_aff[6:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "an[7:0] ; fd ; Array", 7, "an[7:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+// Elapsed time: 40 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("automate.vhd", 37, 153); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 37, 153, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 43, 143); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 43, 143, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectCodeEditor("automate.vhd", 43, 143); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 193, 176); // ac (automate.vhd)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 5", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, s_aff[6:0]]", 4); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 3,099 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:47:23 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+collapseTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, s_aff[6:0]]", 4); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// Elapsed time: 14 seconds
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// Elapsed time: 10 seconds
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, loto_tb_ar_cfg(loto_tb - ar) (loto_tb.vhd)]", 22, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, loto_tb_ar_cfg(loto_tb - ar) (loto_tb.vhd)]", 22, true, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click - Node
+// HMemoryUtils.trashcanNow. Engine heap size: 3,129 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:48:01 AM CET
+// Elapsed time: 23 seconds
+selectTab((HResource) null, (HResource) null, "Protocol Instances", 1); // aa
+selectTab((HResource) null, (HResource) null, "Objects", 0); // aa
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 5", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// Elapsed time: 23 seconds
+selectTab((HResource) null, (HResource) null, "Scope", 0); // aa
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true, false, false, false, false, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Double Click - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_OPEN_SOURCE
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb(ar)", 1, true, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectMenu("Log to Wave Database"); // am (Log to Wave Database)
+selectMenuItem((HResource) null, "Objects in Scope"); // ap (Objects in Scope)
+// Tcl Command: 'current_wave_config {Untitled 5}'
+// Tcl Message: current_wave_config {Untitled 5}
+// Tcl Message: Untitled 5
+// Tcl Message: log_wave {/loto_tb}
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 5", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb(ar)", 1, true, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectMenuItem((HResource) null, "Add to Wave Window"); // ap (Add to Wave Window)
+// Tcl Command: 'current_wave_config {Untitled 5}'
+// Tcl Message: current_wave_config {Untitled 5}
+// Tcl Message: Untitled 5
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// Tcl Message: add_wave {{/loto_tb}}
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// HMemoryUtils.trashcanNow. Engine heap size: 3,130 MB. GUI used memory: 130 MB. Current time: 2/12/25, 10:49:18 AM CET
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,130 MB. GUI used memory: 130 MB. Current time: 2/12/25, 10:49:20 AM CET
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 14 seconds
+selectButton((HResource) null, "Objects_settings"); // v (Objects_settings): TRUE
+selectCheckBox(PAResourceQtoS.SimulationObjectsView_CHECK_ALL, "Check All", false); // f (PAResourceQtoS.SimulationObjectsView_CHECK_ALL): FALSE
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+selectCheckBox((HResource) null, "Input", false); // f: FALSE
+selectCheckBox((HResource) null, "Output", false); // f: FALSE
+selectCheckBox((HResource) null, "Inout", false); // f: FALSE
+selectCheckBox((HResource) null, "Internal Signal", false); // f: FALSE
+selectCheckBox((HResource) null, "Constant", false); // f: FALSE
+selectCheckBox((HResource) null, "Variable", false); // f: FALSE
+selectCheckBox((HResource) null, "Internal Signal", true); // f: TRUE
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectButton((HResource) null, "Objects_settings"); // v (Objects_settings): TRUE
+// HMemoryUtils.trashcanNow. Engine heap size: 3,150 MB. GUI used memory: 130 MB. Current time: 2/12/25, 10:49:41 AM CET
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+// Elapsed time: 10 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("automate.vhd", 205, 402); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 205, 403, false, false, false, false, true); // ac (automate.vhd) - Double Click
+selectTab((HResource) null, (HResource) null, "Scope", 0); // aa
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// Elapsed time: 12 seconds
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "loto_tb ; loto_tb(ar) ; VHDL Entity", 0, "loto_tb(ar)", 1, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "s_aff[6:0] ; 40 ; Array", 4, "s_aff[6:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "s_aff[6:0] ; 40 ; Array", 4, "s_aff[6:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 22 seconds
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 13 seconds
+collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, compteur_modulo6_tb_arch_cfg(compteur_modulo6_tb - arch) (compteur_modulo6_tb.vhd)]", 25); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Simulation Sources, sim_1, mux6_1_tb_arch_cfg(mux6_1_tb - arch) (mux6_1_tb.vhd)]", 26); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+// Elapsed time: 22 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 5*", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// HMemoryUtils.trashcanNow. Engine heap size: 3,150 MB. GUI used memory: 128 MB. Current time: 2/12/25, 10:51:41 AM CET
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_CLOSE_WCFG
+selectButton("OptionPane.button", "Discard", "Save Waveform Configuration"); // JButton (OptionPane.button)
+closeView(RDIResource.RDIViews_WAVEFORM_VIEWER, "Untitled 5*"); // t (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer)
+selectTab(PAResourceOtoP.PlanAheadTab_TABBED_PANE, (HResource) null, "Behavioral Simulation - Functional - sim_1 - loto_tb_ar_cfg", 2); // z (PAResourceOtoP.PlanAheadTab_TABBED_PANE)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_CLOSE
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+selectButton(RDIResource.BaseDialog_OK, "OK", "Confirm Close"); // a (RDIResource.BaseDialog_OK)
+dismissDialog("Confirm Close"); // t (dialog6)
+// TclEventType: SIMULATION_CLOSE_SIMULATION
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: close_sim
+// Tcl Message: INFO: [Simtcl 6-16] Simulation closed
+dismissDialog("Close"); // bj (Close Progress)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_CLOSE
+selectButton(RDIResource.BaseDialog_OK, "OK", "Confirm Close"); // a (RDIResource.BaseDialog_OK)
+dismissDialog("Confirm Close"); // t (dialog7)
+// TclEventType: SIMULATION_CLOSE_SIMULATION
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: close_sim
+// Tcl Message: INFO: [Simtcl 6-16] Simulation closed
+dismissDialog("Close"); // bj (Close Progress)
+selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // j (PAResourceTtoZ.TaskBanner_CLOSE)
+closeTask("Simulation", "Behavioral Simulation - Functional - sim_1 - compteur_modulo6_tb_arch_cfg", "DesignTask.SIMULATION");
+selectButton(RDIResource.BaseDialog_OK, "OK", "Confirm Close"); // a (RDIResource.BaseDialog_OK)
+dismissDialog("Confirm Close"); // t (dialog8)
+// TclEventType: WAVEFORM_CLOSE_WCFG
+// TclEventType: SIMULATION_CLOSE_SIMULATION
+// Tcl Message: close_sim
+// Tcl Message: INFO: [Simtcl 6-16] Simulation closed
+dismissDialog("Close"); // bj (Close Progress)
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: Vivado Simulator v2024.1 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log Using 8 slave threads. Starting static elaboration Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 3,056 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:52:06 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: source loto_tb_ar_cfg.tcl
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 9275.504 ; gain = 0.000 ; free physical = 7639 ; free virtual = 16194
+// 'd' command handler elapsed time: 6 seconds
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:52:17 AM CET
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, s_aff[6:0]]", 4); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, s_aff[6:0]]", 4, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, s_aff[6:0]]", 4, true, false, false, false, true, false); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Popup Trigger - Node
+selectMenu("Name"); // am (Name)
+selectMenu("Waveform Style"); // am (Waveform Style)
+selectMenu("Signal Color"); // am (Signal Color)
+selectMenu("Radix"); // am (Radix)
+selectMenu("Radix"); // am (Radix)
+selectMenuItem((HResource) null, "Binary"); // ad (Binary)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:52:36 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 39, 182); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+/********** leftMouseClick (1266, 433, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,161 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:52:44 AM CET
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// Elapsed time: 58 seconds
+selectTreeTable(PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE, "an[7:0] ; fd ; Array", 7, "an[7:0]", 0, true); // c (PAResourceQtoS.SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE) - Node
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 14 seconds
+selectCodeEditor("loto_tb.vhd", 143, 465); // ac (loto_tb.vhd)
+selectCodeEditor("loto_tb.vhd", 138, 462); // ac (loto_tb.vhd)
+selectCodeEditor("loto_tb.vhd", 138, 462, false, false, false, false, true); // ac (loto_tb.vhd) - Double Click
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, an[7:0]]", 14); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:54:11 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 106, 582); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1335, 815, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 200, 557); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1429, 790, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 267, 531); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1496, 764, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:54:13 AM CET
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 343, 601); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1572, 834, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 421, 583); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1650, 816, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 494, 562); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1723, 795, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:54:15 AM CET
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 601, 530); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1830, 763, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 673, 599); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** startDrag (1907, 834); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+/********** endDrag (1924, 834); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// HMemoryUtils.trashcanNow. Engine heap size: 4,099 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:54:16 AM CET
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 130 MB. Current time: 2/12/25, 10:54:19 AM CET
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,055 MB. GUI used memory: 129 MB. Current time: 2/12/25, 10:54:20 AM CET
+selectButton(RDIResource.GraphicalView_ZOOM_OUT, "Waveform Viewer_zoom_out"); // B (RDIResource.GraphicalView_ZOOM_OUT, Waveform Viewer_zoom_out)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// Elapsed time: 20 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd)]", 1, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd)]", 1, true, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click - Node
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 13 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 11 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto.vhd", 8); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 251, 157); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1474, 398, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,076 MB. GUI used memory: 130 MB. Current time: 2/12/25, 10:55:39 AM CET
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 251, 157, false, false, false, true, false); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) - Popup Trigger
+/********** leftMouseClick (1474, 398, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectMenu("Waveform Style"); // am (Waveform Style)
+selectMenu("Signal Color"); // am (Signal Color)
+selectMenu("Radix"); // am (Radix)
+selectMenuItem((HResource) null, "Hexadecimal"); // ad (Hexadecimal)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 262, 159, false, false, false, true, false); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) - Popup Trigger
+/********** leftMouseClick (1485, 400, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 228, 159); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+/********** leftMouseClick (1452, 400, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 169, 160, false, false, false, true, false); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) - Popup Trigger
+/********** leftMouseClick (1394, 401, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectMenu("Waveform Style"); // am (Waveform Style)
+selectMenu("Signal Color"); // am (Signal Color)
+selectMenu("Radix"); // am (Radix)
+selectMenu("Radix"); // am (Radix)
+selectMenu("Radix"); // am (Radix)
+selectMenu("Signal Color"); // am (Signal Color)
+selectMenu("Waveform Style"); // am (Waveform Style)
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 19, 318); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+/********** leftMouseClick (1248, 555, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 4,120 MB. GUI used memory: 130 MB. Current time: 2/12/25, 10:56:00 AM CET
+// Elapsed time: 156 seconds
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd)]", 1); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd), tirage_1 : tirage(a_tirage) (tirage.vhd)]", 2, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd), tirage_1 : tirage(a_tirage) (tirage.vhd)]", 2, true, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click - Node
+// Elapsed time: 55 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 128 seconds
+selectTab((HResource) null, (HResource) null, "Scope", 0); // aa
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "tirage_1 ; tirage(a_tirage) ; VHDL Entity", 2, "tirage_1", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "registres_2 ; registres(a_registres) ; VHDL Entity", 4, "registres_2", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "registres_2 ; registres(a_registres) ; VHDL Entity", 4, "registres_2", 0, false, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectMenuItem((HResource) null, "Add to Wave Window"); // ap (Add to Wave Window)
+// Tcl Command: 'current_wave_config {Untitled 6}'
+// Tcl Message: current_wave_config {Untitled 6}
+// Tcl Message: Untitled 6
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// Tcl Message: add_wave {{/loto_tb/DUT/tirage_1/registres_2}}
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 12 seconds
+selectButton(PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH, "simulation_relaunch"); // B (PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH, simulation_relaunch)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH
+// TclEventType: SIMULATION_MODEL_ABOUT_TO_CLOSE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: SIMULATION_MODEL_RELOADED
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: relaunch_sim
+// Tcl Message: Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Tcl Message: Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+// Tcl Message: Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: Vivado Simulator v2024.1 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log Using 8 slave threads. Starting static elaboration Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_MODEL_ABOUT_TO_CLOSE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: SIMULATION_MODEL_RELOADED
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_DELETE_ALL_BREAKPOINTS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// HMemoryUtils.trashcanNow. Engine heap size: 3,133 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:02:13 AM CET
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 9275.504 ; gain = 0.000 ; free physical = 7678 ; free virtual = 16158
+// 'a' command handler elapsed time: 5 seconds
+dismissDialog("Relaunch Simulation"); // b (Relaunch Simulation Progress)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectButton(RDIResource.WaveformView_PREVIOUS_TRANSITION, "Waveform Viewer_waveformPreviousTransition"); // B (RDIResource.WaveformView_PREVIOUS_TRANSITION, Waveform Viewer_waveformPreviousTransition)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,133 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:02:17 AM CET
+selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (RDIResource.WaveformView_GOTO_TIME_0, Waveform Viewer_RunReset)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (RDIResource.WaveformView_GOTO_TIME_0, Waveform Viewer_RunReset)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (RDIResource.WaveformView_GOTO_TIME_0, Waveform Viewer_RunReset)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// Elapsed time: 16 seconds
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "transcod_1 ; transcodeur7s_d_u(transcod_int) ; VHDL Entity", 6, "transcod_1", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "transcod_1 ; transcodeur7s_d_u(transcod_int) ; VHDL Entity", 6, "transcod_1", 0, false, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectMenu("Log to Wave Database"); // am (Log to Wave Database)
+selectMenuItem((HResource) null, "Add to Wave Window"); // ap (Add to Wave Window)
+// Tcl Command: 'current_wave_config {Untitled 6}'
+// Tcl Message: current_wave_config {Untitled 6}
+// Tcl Message: Untitled 6
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// Tcl Message: add_wave {{/loto_tb/DUT/transcod_1}}
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "transcod_1 ; transcodeur7s_d_u(transcod_int) ; VHDL Entity", 6, "transcod_1", 0, false, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectMenu("Log to Wave Database"); // am (Log to Wave Database)
+selectButton(PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH, "simulation_relaunch"); // B (PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH, simulation_relaunch)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH
+// TclEventType: SIMULATION_MODEL_ABOUT_TO_CLOSE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: SIMULATION_MODEL_RELOADED
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: relaunch_sim
+// Tcl Message: Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Tcl Message: Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+// Tcl Message: Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: Vivado Simulator v2024.1 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log Using 8 slave threads. Starting static elaboration Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_MODEL_ABOUT_TO_CLOSE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: SIMULATION_MODEL_RELOADED
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_DELETE_ALL_BREAKPOINTS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:02:48 AM CET
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 9275.504 ; gain = 0.000 ; free physical = 7742 ; free virtual = 16216
+// 'a' command handler elapsed time: 5 seconds
+dismissDialog("Relaunch Simulation"); // b (Relaunch Simulation Progress)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:02:51 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,179 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// [Engine Memory]: 4,179 MB (+1028111kb) [01:04:06]
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,051 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,526 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 14 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 399, 836); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+/********** leftMouseClick (1628, 1070, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:04 AM CET
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, O_reg5[5:0]]", 31, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, O_reg4[5:0]]", 30, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, O_reg3[5:0]]", 29, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,179 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:07 AM CET
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, O_reg2[5:0]]", 28, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, O_reg1[5:0]]", 27, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, O_reg0[5:0]]", 26, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:08 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 229, 724); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1458, 958, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 482, 714); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1711, 948, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 640, 718); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1869, 952, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:13 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:14 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,179 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:14 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,179 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:14 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,399 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:14 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,135 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:15 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,179 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:15 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,136 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:15 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,136 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:15 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,136 MB. GUI used memory: 131 MB. Current time: 2/12/25, 11:03:25 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 18 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 74, 69); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+/********** leftMouseClick (1303, 302, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 75, 69); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,136 MB. GUI used memory: 132 MB. Current time: 2/12/25, 11:03:32 AM CET
+/********** leftMouseClick (1304, 302, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 23 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 21 seconds
+selectCodeEditor("automate.vhd", 138, 582); // ac (automate.vhd)
+// Elapsed time: 32 seconds
+selectCodeEditor("automate.vhd", 316, 596); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 176, 563, false, false, false, true, false); // ac (automate.vhd) - Popup Trigger
+selectMenuItem(RDIResourceCommand.RDICommands_COPY, "Copy"); // ap (RDIResourceCommand.RDICommands_COPY)
+selectCodeEditor("automate.vhd", 141, 478); // ac (automate.vhd)
+typeControlKey((HResource) null, "automate.vhd", 'v'); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 135, 532); // ac (automate.vhd)
+// Elapsed time: 15 seconds
+selectCodeEditor("automate.vhd", 239, 523); // ac (automate.vhd)
+// Elapsed time: 24 seconds
+selectCodeEditor("automate.vhd", 271, 400); // ac (automate.vhd)
+// Elapsed time: 118 seconds
+selectCodeEditor("automate.vhd", 202, 686); // ac (automate.vhd)
+selectCodeEditor("automate.vhd", 225, 684); // ac (automate.vhd)
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Elapsed Time for: 'L.f': 01h:08m:58s
+// Elapsed Time for: 'L.f': 01h:09m:02s
+// Elapsed time: 50 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:08:42 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:08:48 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 21 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, I_data[5:0]]", 26, true); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE) - Node
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:08:53 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 297, 708); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1526, 942, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 115 MB. Current time: 2/12/25, 11:09:01 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:01 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,927 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:01 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,058 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:01 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,405 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:01 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,060 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,405 MB. GUI used memory: 115 MB. Current time: 2/12/25, 11:09:02 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:03 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:03 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:03 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 115 MB. Current time: 2/12/25, 11:09:03 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,060 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:04 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:05 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:05 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 21 seconds
+selectButton(PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, "simulation_live_run_all"); // B (PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL, simulation_live_run_all)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_LIVE_RUN_ALL
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// Tcl Message: run all
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:19 AM CET
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:25 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 16 seconds
+selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (RDIResource.WaveformView_GOTO_TIME_0, Waveform Viewer_RunReset)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 643, 768); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1872, 1002, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:43 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 520, 70); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1750, 302, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 280, 70); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1509, 303, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:48 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 519, 74); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1748, 307, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:09:56 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 543, 788); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1772, 1022, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 523, 71); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1752, 304, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 549, 118); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1778, 351, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:10:11 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 950, 792); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (2180, 1026, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 986, 777); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (2216, 1011, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 983, 787); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:10:16 AM CET
+/********** leftMouseClick (2212, 1022, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 978, 789); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (2208, 1023, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:10:18 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 997, 74); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (2227, 307, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 115 MB. Current time: 2/12/25, 11:10:25 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// WARNING: HEventQueue.dispatchEvent() is taking 5747 ms.
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// WARNING: HTimer (HSTRUtils Dump STR Log Timer) is taking 2894ms to process. Increasing delay to 5000 ms.
+// WARNING: HEventQueue.dispatchEvent() is taking 2899 ms.
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7894 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8297 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7692 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8296 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8298 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8296 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7897 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8297 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8296 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8297 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7897 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8296 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7897 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8439 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7897 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8296 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 7686 ms to process. Increasing delay to 2000 ms.
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 21 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 1015, 127); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (2245, 360, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:10:49 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:11:07 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,144 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:11:07 AM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 26 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 1162, 823); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+/********** leftMouseClick (2371, 1050, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 4,188 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:11:13 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 880, 774); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (2094, 1001, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3393 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 1392 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3393 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 1393 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 1392 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3391 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3393 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 1393 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3392 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3394 ms to process. Increasing delay to 3000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 3393 ms to process. Increasing delay to 3000 ms.
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 16 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto.vhd", 8); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto_tb.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto.vhd", 8); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "tirage.vhd", 9); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectCodeEditor("tirage.vhd", 101, 697); // ac (tirage.vhd)
+selectCodeEditor("tirage.vhd", 101, 697, false, false, false, false, true); // ac (tirage.vhd) - Double Click
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectCodeEditor("tirage.vhd", 101, 697); // ac (tirage.vhd)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectTab((HResource) null, (HResource) null, "Sources", 1); // aa
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 26 seconds
+selectCodeEditor("tirage.vhd", 187, 615); // ac (tirage.vhd)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectCodeEditor("tirage.vhd", 181, 638); // ac (tirage.vhd)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectCodeEditor("tirage.vhd", 183, 628); // ac (tirage.vhd)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// WARNING: HTimer (HSTRUtils Dump STR Log Timer) is taking 4572ms to process. Increasing delay to 6000 ms.
+// WARNING: HEventQueue.dispatchEvent() is taking 4572 ms.
+selectCodeEditor("tirage.vhd", 179, 452); // ac (tirage.vhd)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6479 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6478 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6478 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6477 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6476 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6478 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6475 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6478 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6477 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6476 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6477 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6478 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6476 ms to process. Increasing delay to 4000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 6474 ms to process. Increasing delay to 4000 ms.
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 14 seconds
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd), tirage_1 : tirage(a_tirage) (tirage.vhd)]", 2); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd), tirage_1 : tirage(a_tirage) (tirage.vhd), compteur_1 : compteur1_49(compteur_a) (compteur1_49.vhd)]", 6, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, loto(arch) (loto.vhd), tirage_1 : tirage(a_tirage) (tirage.vhd), compteur_1 : compteur1_49(compteur_a) (compteur1_49.vhd)]", 6, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectCodeEditor("compteur1_49.vhd", 189, 453); // ac (compteur1_49.vhd)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+selectCodeEditor("compteur1_49.vhd", 91, 564); // ac (compteur1_49.vhd)
+selectCodeEditor("compteur1_49.vhd", 73, 164); // ac (compteur1_49.vhd)
+selectCodeEditor("compteur1_49.vhd", 95, 145); // ac (compteur1_49.vhd)
+// WARNING: HTimer (HSTRUtils Dump STR Log Timer) is taking 3103ms to process. Increasing delay to 7000 ms.
+// WARNING: HEventQueue.dispatchEvent() is taking 3103 ms.
+// HMemoryUtils.trashcanNow. Engine heap size: 3,194 MB. GUI used memory: 115 MB. Current time: 2/12/25, 11:13:18 AM CET
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8650 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8345 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8639 ms to process. Increasing delay to 2000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8344 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8345 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8344 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8345 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8346 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8345 ms to process. Increasing delay to 5000 ms.
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 8346 ms to process. Increasing delay to 5000 ms.
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 11 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Untitled 6*", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// HMemoryUtils.trashcanNow. Engine heap size: 3,194 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:13:48 AM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// Elapsed time: 42 seconds
+selectButton("HStatusBar_ProgressStatusItem_Cancel", "Cancel"); // NullButton (HStatusBar_ProgressStatusItem_Cancel)
+// Tcl Message: INFO: [Common 17-41] Interrupt caught. Command should exit soon.
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// WARNING: HEventQueue.dispatchEvent() is taking 6010 ms.
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,194 MB. GUI used memory: 114 MB. Current time: 2/12/25, 11:14:09 AM CET
+// TclEventType: SIMULATION_STOPPED
+// WARNING: HSwingWorker (Monitor File Timestamp Swing Worker) is taking 2689 ms to process. Increasing delay to 3000 ms.
+// WARNING: HEventQueue.dispatchEvent() is taking 1613 ms.
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// CommandFailedException: ERROR: [Common 17-69] Command failed:
+// Tcl Message: run: Time (s): cpu = 00:04:46 ; elapsed = 00:04:57 . Memory (MB): peak = 9301.906 ; gain = 26.402 ; free physical = 866 ; free virtual = 15698
+// Tcl Message: INFO: [Common 17-344] 'run' was cancelled
+// Elapsed time: 27 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 21, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
+selectButton(RDIResource.BaseDialog_YES, "Yes", "No Implementation Results Available"); // a (RDIResource.BaseDialog_YES)
+dismissDialog("No Implementation Results Available"); // t (dialog9)
+dismissDialog("Resetting Runs"); // bj (Resetting Runs Progress)
+// TclEventType: RUN_LAUNCH
+// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 4
+// TclEventType: RUN_MODIFY
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_MODIFY
+// Tcl Message: [Wed Feb 12 11:14:31 2025] Launched synth_1... Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/runme.log [Wed Feb 12 11:14:31 2025] Launched impl_1... Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/runme.log
+dismissDialog("Generate Bitstream"); // bj (Generate Bitstream Progress)
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// Elapsed time: 77 seconds
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints]", 19); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Nexys4DDR-Master.xdc]", 21, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Nexys4DDR-Master.xdc]", 21, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+// TclEventType: RUN_STEP_COMPLETED
+// Elapsed time: 20 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto.vhd", 8); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectCodeEditor("loto.vhd", 72, 151); // ac (loto.vhd)
+selectCodeEditor("loto.vhd", 72, 151, false, false, false, false, true); // ac (loto.vhd) - Double Click
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur1_49.vhd", 10); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Nexys4DDR-Master.xdc", 11); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// Elapsed time: 36 seconds
+selectRadioButton(PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER, "Open Hardware Manager"); // a (PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER)
+selectButton(RDIResource.BaseDialog_OK, "OK", "Bitstream Generation Completed"); // a (RDIResource.BaseDialog_OK)
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes'
+// Tcl (Dont Echo) Command: 'load_features labtools'
+// TclEventType: LOAD_FEATURE
+// TclEventType: HW_SESSION_OPEN
+// Tcl Message: open_hw_manager
+dismissDialog("Open Hardware Manager"); // bj (Open Hardware Manager Progress)
+selectButton(PAResourceOtoP.ProgramDebugTab_OPEN_TARGET, "Open target"); // g (PAResourceOtoP.ProgramDebugTab_OPEN_TARGET)
+selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ap (PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, auto_connect_target_menu)
+// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET
+// Tcl Message: connect_hw_server -allow_non_jtag
+// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server...
+// TclEventType: HW_SERVER_UPDATE
+// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2024.1 **** Build date : May 22 2024 at 19:19:01 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0 INFO: [Labtools 27-3417] Launching cs_server...
+// TclEventType: HW_SERVER_UPDATE
+// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ******** Xilinx cs_server v2024.1.0 ****** Build date : Apr 27 2024-03:40:49 **** Build number : 2024.1.1714182049 ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+// TclEventType: HW_TARGET_CHANGE
+// TclEventType: HW_TARGET_CLOSE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_ADD
+// TclEventType: HW_TARGET_UPDATE
+// Tcl Message: open_hw_target
+// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274675171A
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+// Tcl Message: current_hw_device [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
+// Tcl Message: INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
+dismissDialog("Auto Connect"); // bj (Auto Connect Progress)
+selectButton(PAResourceOtoP.ProgramDebugTab_PROGRAM_DEVICE, "Program device"); // g (PAResourceOtoP.ProgramDebugTab_PROGRAM_DEVICE)
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program", "Program Device"); // a (PAResourceOtoP.ProgramFpgaDialog_PROGRAM, RDIResource.BaseDialog_OK)
+dismissDialog("Program Device"); // aP (dialog11)
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+// Tcl Message: set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+// Tcl Message: program_hw_devices [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+// Tcl Message: INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+// 'D' command handler elapsed time: 4 seconds
+dismissDialog("Program Device"); // bj (Program Device Progress)
+// Elapsed time: 23 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Nexys4DDR-Master.xdc", 10); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 99 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_RTL_DESIGN
+selectButton(RDIResource.BaseDialog_OK, "OK", "Elaborate Design"); // a (RDIResource.BaseDialog_OK)
+dismissDialog("Elaborate Design"); // t (dialog12)
+// Tcl Message: synth_design -rtl -rtl_skip_mlo -name rtl_1
+// Tcl Message: Command: synth_design -rtl -rtl_skip_mlo -name rtl_1 Starting synth_design Using part: xc7a100tcsg324-1 Top: loto
+// TclEventType: ELABORATE_START
+// TclEventType: MSGMGR_REFRESH_MSG
+// HMemoryUtils.trashcanNow. Engine heap size: 4,109 MB. GUI used memory: 120 MB. Current time: 2/12/25, 11:19:36 AM CET
+// TclEventType: ELABORATE_FINISH
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: POWER_CNS_STALE
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: FLOORPLAN_MODIFY
+// TclEventType: DESIGN_NEW
+// HMemoryUtils.trashcanNow. Engine heap size: 4,311 MB. GUI used memory: 119 MB. Current time: 2/12/25, 11:19:40 AM CET
+// TclEventType: DESIGN_NEW
+// WARNING: HEventQueue.dispatchEvent() is taking 2188 ms.
+// Tcl Message: INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 48722
+// TclEventType: CURR_DESIGN_SET
+// Tcl Message: ---------------------------------------------------------------------------------
+// Tcl Message: Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 10184.988 ; gain = 399.773 ; free physical = 1399 ; free virtual = 14895
+// Tcl Message: ---------------------------------------------------------------------------------
+// Tcl Message: Parameter n_fast bound to: 15 - type: integer Parameter n_slow bound to: 25 - type: integer
+// Tcl Message: ---------------------------------------------------------------------------------
+// Tcl Message: Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 10268.832 ; gain = 483.617 ; free physical = 1281 ; free virtual = 14778
+// Tcl Message: ---------------------------------------------------------------------------------
+// Tcl Message: --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
+// Tcl Message: Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 10283.676 ; gain = 498.461 ; free physical = 1279 ; free virtual = 14776
+// Tcl Message: --------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
+// Tcl Message: Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 10283.676 ; gain = 498.461 ; free physical = 1279 ; free virtual = 14776
+// Tcl Message: ---------------------------------------------------------------------------------
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10283.684 ; gain = 0.000 ; free physical = 1287 ; free virtual = 14784
+// Tcl Message: INFO: [Project 1-570] Preparing netlist for logic optimization
+// Tcl Message: Processing XDC Constraints Initializing timing engine Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc] Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc] Completed Processing XDC Constraints
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10402.457 ; gain = 0.000 ; free physical = 1560 ; free virtual = 15059
+// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
+// TclEventType: CURR_DESIGN_SET
+// Xgd.load filename: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/./.Xil/Vivado-13301-fl-tp-br-637/xc7a100t_detail.xgd_5B7F094 elapsed time: 1.5s
+// DeviceModel: Load Xgds SwingWorker Join Forever elapsed time: 3s
+// Tcl Message: RTL Elaboration Complete: : Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 10435.301 ; gain = 650.086 ; free physical = 1480 ; free virtual = 15012
+// Tcl Message: 31 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully
+// Tcl Message: synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 10435.301 ; gain = 1006.000 ; free physical = 1480 ; free virtual = 15012
+// Tcl Message: INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3071.865; main = 3061.524; forked = 10.341 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 10542.855; main = 10435.305; forked = 107.551
+// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
+// 'dQ' command handler elapsed time: 17 seconds
+// Elapsed time: 16 seconds
+dismissDialog("Open Elaborated Design"); // bj (Open Elaborated Design Progress)
+// Elapsed time: 14 seconds
+runTclCommand (PAResourceOtoP.PAViews_SCHEMATIC, "select_objects [get_ports O_green]"); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic)
+runTclCommand (PAResourceOtoP.PAViews_SCHEMATIC, "unselect_objects"); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic)
+// [Engine Memory]: 4,419 MB (+32934kb) [01:21:04]
+selectView(PAResourceOtoP.PAViews_SCHEMATIC, "Schematic", 1633, 302, 1784, 991, false, false, false, true, false); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic) - Popup Trigger
+runTclCommand (PAResourceOtoP.PAViews_SCHEMATIC, "unselect_objects"); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic)
+// HMemoryUtils.trashcanNow. Engine heap size: 4,420 MB. GUI used memory: 153 MB. Current time: 2/12/25, 11:20:01 AM CET
+// Elapsed time: 16 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 28, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+// [GUI Memory]: 225 MB (+9839kb) [01:21:23]
+selectMenuItem((HResource) null, "xc7a100t_0"); // ap (xc7a100t_0)
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes'
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+selectMoreButton(PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE, (String) null, "Program Device"); // r (PAResourceOtoP.ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE)
+setFileChooser("/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit");
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program", "Program Device"); // a (PAResourceOtoP.ProgramFpgaDialog_PROGRAM, RDIResource.BaseDialog_OK)
+dismissDialog("Program Device"); // aP (dialog13)
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+// Tcl Message: set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+// Tcl Message: program_hw_devices [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+// Tcl Message: INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+// 'D' command handler elapsed time: 10 seconds
+dismissDialog("Program Device"); // bj (Program Device Progress)
+// Elapsed time: 60 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Project Manager]", 0, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_PROJECT_MANAGER
+// Elapsed time: 26 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur1_49.vhd", 10); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Nexys4DDR-Master.xdc", 11); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 34 seconds
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1]", 20, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Nexys4DDR-Master.xdc]", 21, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Nexys4DDR-Master.xdc]", 21, false, false, false, false, true, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Popup Trigger
+selectMenu(PAResourceCommand.PACommandNames_OPEN_FILE_WITH, "Open With"); // am (PAResourceCommand.PACommandNames_OPEN_FILE_WITH, Open With)
+selectMenuItem(PAResourceCommand.PACommandNames_SRC_REPLACE_FILE, "Replace File..."); // ap (PAResourceCommand.PACommandNames_SRC_REPLACE_FILE, src_replace_menu)
+// Run Command: PAResourceCommand.PACommandNames_SRC_REPLACE_FILE
+// [GUI Memory]: 240 MB (+4068kb) [01:23:41]
+setFileChooser("/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc");
+// 'dJ' command handler elapsed time: 7 seconds
+// TclEventType: DESIGN_STALE
+// TclEventType: FILE_SET_CHANGE
+// Tcl Message: update_files -from_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc -to_files /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc -filesets [get_filesets *]
+// Tcl Message: INFO: [filemgmt 20-762] Replacing file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4DDR-Master.xdc' with file '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc'.
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 24, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
+selectButton(RDIResource.BaseDialog_YES, "Yes", "Synthesis is Out-of-date"); // a (RDIResource.BaseDialog_YES)
+// TclEventType: RUN_MODIFY
+dismissDialog("Synthesis is Out-of-date"); // t (dialog16)
+// TclEventType: RUN_RESET
+// TclEventType: RUN_STATUS_CHANGE
+// Tcl Message: reset_run synth_1
+// TclEventType: RUN_RESET
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_RESET
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_RESET
+// TclEventType: RUN_MODIFY
+// Tcl Message: INFO: [Project 1-1160] Copying file /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/loto.dcp to /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.srcs/utils_1/imports/synth_1 and adding it to utils fileset
+dismissDialog("Resetting Runs"); // bj (Resetting Runs Progress)
+// TclEventType: RUN_LAUNCH
+// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 4
+// TclEventType: RUN_LAUNCH
+// TclEventType: RUN_MODIFY
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_MODIFY
+// Tcl Message: [Wed Feb 12 11:22:49 2025] Launched synth_1... Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/synth_1/runme.log [Wed Feb 12 11:22:50 2025] Launched impl_1... Run output will be captured here: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/runme.log
+dismissDialog("Generate Bitstream"); // bj (Generate Bitstream Progress)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Nexys4_Master.xdc]", 21, false); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE)
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, Nexys4_Master.xdc]", 21, false, false, false, false, false, true); // E (PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE) - Double Click
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// Elapsed time: 102 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 6); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// Elapsed time: 49 seconds
+selectButton(RDIResource.BaseDialog_OK, "OK", "Bitstream Generation Completed"); // a (RDIResource.BaseDialog_OK)
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl (Dont Echo) Command: 'rdi::info_commands get_hw_probes'
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+dismissDialog("Bitstream Generation Completed"); // Q.a (dialog17)
+selectButton(PAResourceOtoP.ProgramDebugTab_PROGRAM_DEVICE, "Program device"); // g (PAResourceOtoP.ProgramDebugTab_PROGRAM_DEVICE)
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program", "Program Device"); // a (PAResourceOtoP.ProgramFpgaDialog_PROGRAM, RDIResource.BaseDialog_OK)
+dismissDialog("Program Device"); // aP (dialog18)
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+// Tcl Message: set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+// Tcl Message: program_hw_devices [get_hw_devices xc7a100t_0]
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+// Tcl Message: INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+// 'D' command handler elapsed time: 5 seconds
+dismissDialog("Program Device"); // bj (Program Device Progress)
+// Elapsed time: 58 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_RTL_DESIGN
+// Elapsed time: 68 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Nexys4DDR-Master.xdc", 12); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+closeView(PAResourceOtoP.PAViews_CODE, "Code"); // J (PAResourceOtoP.PAViews_CODE, PlanAheadTabCode)
+// Run Command: RDIResourceCommand.RDICommands_FIND
+dismissDialog("Find"); // f (dialog19)
+selectCodeEditor("Nexys4_Master.xdc", 733, 432); // ac (Nexys4_Master.xdc)
+// Elapsed time: 116 seconds
+setText(RDIResource.HCodeEditor_SEARCH_TEXT_COMBO_BOX, "I_blo"); // d.c (RDIResource.HCodeEditor_SEARCH_TEXT_COMBO_BOX)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "tirage.vhd", 10); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur1_49.vhd", 11); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_RTL_DESIGN
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true, false, false, false, false, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Double Click - Node
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+selectButton(PAResourceOtoP.ProjectTab_RELOAD, "Reload"); // g (PAResourceOtoP.ProjectTab_RELOAD)
+// TclEventType: DESIGN_REFRESH
+// HMemoryUtils.trashcanNow. Engine heap size: 4,351 MB. GUI used memory: 172 MB. Current time: 2/12/25, 11:30:00 AM CET
+// Engine heap size: 4,351 MB. GUI used memory: 173 MB. Current time: 2/12/25, 11:30:00 AM CET
+// Tcl Message: refresh_design
+selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background", "Reloading"); // a (RDIResource.ProgressDialog_BACKGROUND)
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: POWER_CNS_STALE
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: FLOORPLAN_MODIFY
+// TclEventType: DESIGN_REFRESH
+// HMemoryUtils.trashcanNow. Engine heap size: 4,351 MB. GUI used memory: 151 MB. Current time: 2/12/25, 11:30:02 AM CET
+// WARNING: HEventQueue.dispatchEvent() is taking 1201 ms.
+// Tcl Message: INFO: [Project 1-570] Preparing netlist for logic optimization
+// Tcl Message: Processing XDC Constraints Initializing timing engine Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc] Finished Parsing XDC File [/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/src/Nexys4_Master.xdc] Completed Processing XDC Constraints
+dismissDialog("Reloading"); // bj (Reloading Progress)
+// Xgd.load filename: /homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/./.Xil/Vivado-13301-fl-tp-br-637/xc7a100t_detail.xgd_39E2B85D elapsed time: 1.2s
+// DeviceModel: Load Xgds SwingWorker Join Forever elapsed time: 2.6s
+// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_RTL_DESIGN
+// [GUI Memory]: 256 MB (+4280kb) [01:31:11]
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_RTL_DESIGN
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true, false, false, false, false, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Double Click - Node
+expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, RTL Analysis, Open Elaborated Design]", 13, true); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree) - Node
+closeView(PAResourceOtoP.PAViews_CODE, "Code"); // J (PAResourceOtoP.PAViews_CODE, PlanAheadTabCode)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "loto.vhd", 9); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "tirage.vhd", 10); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "compteur_modulo6.vhd", 5); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Schematic", 1); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 46 seconds
+runTclCommand (PAResourceOtoP.PAViews_SCHEMATIC, "select_objects [get_nets SC_numTranscode]"); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic)
+// Elapsed time: 73 seconds
+runTclCommand (PAResourceOtoP.PAViews_SCHEMATIC, "select_objects [get_cells mux6_1_1]"); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic)
+runTclCommand (PAResourceOtoP.PAViews_SCHEMATIC, "unselect_objects"); // j (PAResourceOtoP.PAViews_SCHEMATIC, PlanAheadTabSchematic)
+// TclEventType: HW_TARGET_NEEDS_CLOSE
+// TclEventType: HW_TARGET_CLOSE
+// TclEventType: HW_SYSMON_DELETE
+// TclEventType: HW_TARGET_UPDATE
+// TclEventType: DEBUG_PROBE_DELETE
+// Tcl Message: ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210274675171A
+// TclEventType: HW_TARGET_NEEDS_CLOSE
+// TclEventType: HW_SERVER_UPDATE
+// Elapsed time: 63 seconds
+selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK", "Close Hardware Target"); // f (PAResourceAtoD.CmdMsgDialog_OK)
+dismissDialog("Close Hardware Target"); // j.a (dialog20)
+// Elapsed time: 34 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab(PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED, PAResourceOtoP.ProjectSummaryUtilizationPanel_TABLE, "Table", 1); // e (PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED)
+// Elapsed time: 23 seconds
+collapseTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 23); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design]", 23); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Implementation, Open Implemented Design, Report Timing Summary]", 27, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// Tcl Message: open_run impl_1
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: POWER_CNS_STALE
+// TclEventType: FLOORPLAN_MODIFY
+// TclEventType: DESIGN_NEW
+// HMemoryUtils.trashcanNow. Engine heap size: 4,851 MB. GUI used memory: 177 MB. Current time: 2/12/25, 11:34:38 AM CET
+// [Engine Memory]: 4,851 MB (+221195kb) [01:35:43]
+// TclEventType: DESIGN_NEW
+// DeviceView Instantiated
+// TclEventType: CURR_DESIGN_SET
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10459.199 ; gain = 0.000 ; free physical = 2354 ; free virtual = 14805
+// Tcl Message: INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2024.1 INFO: [Project 1-570] Preparing netlist for logic optimization
+// Tcl Message: Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10459.199 ; gain = 0.000 ; free physical = 2428 ; free virtual = 14817
+// Tcl Message: INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. INFO: [Designutils 20-5722] Start Reading Physical Databases.
+// Tcl Message: Reading placement.
+// Tcl Message: Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292
+// Tcl Message: Reading placer database...
+// Tcl Message: Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292 Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292 Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1930 ; free virtual = 14292
+// Tcl Message: Reading routing.
+// Tcl Message: Read RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1928 ; free virtual = 14290 Read Physdb Files: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1928 ; free virtual = 14290
+// Tcl Message: Restored from archive | CPU: 0.030000 secs | Memory: 0.246185 MB |
+// Tcl Message: Finished XDEF File Restore: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1928 ; free virtual = 14290 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 10932.355 ; gain = 0.000 ; free physical = 1926 ; free virtual = 14288
+// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.
+// TclEventType: CURR_DESIGN_SET
+// Device view-level: 0.0
+// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
+// RouteApi::loadEngineXgdAndInitRouteStorage elapsed time: 1.6s
+// RouteApi: Init Delay Mediator Swing Worker Finished
+// TclEventType: DRC_ADDED
+// Device view-level: 0.0
+// Tcl Message: open_run: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 10970.902 ; gain = 511.703 ; free physical = 1894 ; free virtual = 14277
+// TclEventType: DRC_ADDED
+// TclEventType: METHODOLOGY_ADDED
+// TclEventType: POWER_UPDATED
+// TclEventType: TIMING_SUMMARY_UPDATED
+// Run Command: PAResourceCommand.PACommandNames_REPORT_TIMING_SUMMARY
+// Elapsed time: 12 seconds
+selectButton(RDIResource.BaseDialog_OK, "OK", "Report Timing Summary"); // a (RDIResource.BaseDialog_OK)
+dismissDialog("Report Timing Summary"); // ag (dialog21)
+// TclEventType: TIMING_RESULTS_STALE
+// TclEventType: TIMING_SUMMARY_UPDATED
+// Tcl Message: report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
+// Tcl Message: INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+dismissDialog("Report Timing Summary"); // bj (Report Timing Summary Progress)
+selectButton(RDIResource.BaseDialog_OK, "OK", "Methodology Violations"); // a (RDIResource.BaseDialog_OK)
+dismissDialog("Methodology Violations"); // aH (dialog22)
+// [GUI Memory]: 279 MB (+10200kb) [01:35:49]
+// [Engine Memory]: 5,116 MB (+23129kb) [01:35:49]
+// Device view-level: 0.3
+// HMemoryUtils.trashcanNow. Engine heap size: 5,116 MB. GUI used memory: 207 MB. Current time: 2/12/25, 11:34:46 AM CET
+// Device view-level: 0.9
+// Device view-level: 1.2
+// Device view-level: 1.5
+// Device view-level: 1.8
+// Device view-level: 2.1
+// HMemoryUtils.trashcanNow. Engine heap size: 5,117 MB. GUI used memory: 207 MB. Current time: 2/12/25, 11:34:47 AM CET
+// Device view-level: 2.4
+// Device view-level: 2.1
+// Device view-level: 1.8
+// [GUI Memory]: 296 MB (+3472kb) [01:35:52]
+// Device view-level: 2.1
+// Device view-level: 1.8
+// HMemoryUtils.trashcanNow. Engine heap size: 5,109 MB. GUI used memory: 208 MB. Current time: 2/12/25, 11:34:49 AM CET
+// Elapsed time: 13 seconds
+selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Clock Summary]", 3, false); // a (PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE)
+selectTree(PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE, "[Root, Design Timing Summary]", 2, false); // a (PAResourceItoN.NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE)
+selectButton(PAResourceAtoD.DesignTimingSumSectionPanel_WORST_NEGATIVE_SLACK, "6.012 ns"); // g (PAResourceAtoD.DesignTimingSumSectionPanel_WORST_NEGATIVE_SLACK)
+// PAPropertyPanels.initPanels (Path 1) elapsed time: 0.3s
+// Device view-level: 1.5
+// Device view-level: 1.2
+// Device view-level: 0.9
+// Device view-level: 0.6
+// HMemoryUtils.trashcanNow. Engine heap size: 5,110 MB. GUI used memory: 211 MB. Current time: 2/12/25, 11:35:04 AM CET
+// Device view-level: 0.9
+// Device view-level: 1.2
+selectGraphicalView(PAResourceOtoP.PAViews_DEVICE, 365475, 276119); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor)
+// Device view-level: 1.5
+// HMemoryUtils.trashcanNow. Engine heap size: 6,468 MB. GUI used memory: 210 MB. Current time: 2/12/25, 11:35:12 AM CET
+// Device view-level: 2.1
+// [Engine Memory]: 6,468 MB (+1149179kb) [01:36:16]
+// Device view-level: 2.4
+// Device view-level: 2.1
+// Device view-level: 1.5
+// Device view-level: 1.2
+// HMemoryUtils.trashcanNow. Engine heap size: 5,159 MB. GUI used memory: 209 MB. Current time: 2/12/25, 11:35:13 AM CET
+// Device view-level: 0.9
+// Device view-level: 0.6
+// Device view-level: 0.3
+// Device view-level: 0.0
+// Device view-level: 0.6
+// HMemoryUtils.trashcanNow. Engine heap size: 5,159 MB. GUI used memory: 209 MB. Current time: 2/12/25, 11:35:14 AM CET
+// Device view-level: 1.2
+// Device view-level: 1.5
+// Device view-level: 1.8
+// Device view-level: 2.1
+// HMemoryUtils.trashcanNow. Engine heap size: 5,159 MB. GUI used memory: 209 MB. Current time: 2/12/25, 11:35:15 AM CET
+// Device view-level: 2.4
+// Device view-level: 2.7
+// Device view-level: 2.9
+// Device view-level: 3.2
+// [GUI Memory]: 311 MB (+286kb) [01:36:26]
+// HMemoryUtils.trashcanNow. Engine heap size: 6,529 MB. GUI used memory: 215 MB. Current time: 2/12/25, 11:35:21 AM CET
+// Device view-level: 3.5
+// Device view-level: 3.2
+// Device view-level: 2.9
+// Device view-level: 2.7
+// Device view-level: 2.1
+// HMemoryUtils.trashcanNow. Engine heap size: 5,179 MB. GUI used memory: 211 MB. Current time: 2/12/25, 11:35:23 AM CET
+// Device view-level: 1.8
+// Device view-level: 1.5
+// Device view-level: 1.2
+// Device view-level: 0.9
+// Device view-level: 0.6
+// HMemoryUtils.trashcanNow. Engine heap size: 5,165 MB. GUI used memory: 210 MB. Current time: 2/12/25, 11:35:24 AM CET
+// Elapsed time: 15 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 106 seconds
+selectTable(PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_TABLE, "LUT ; 72 ; 63400 ; 0.11356467", 0, "72", 1); // o (PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_TABLE)
+selectTable(PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_TABLE, "FF ; 89 ; 126800 ; 0.070189275", 1, "89", 1); // o (PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_TABLE)
+selectTable(PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_TABLE, "FF ; 89 ; 126800 ; 0.070189275", 1, "89", 1, false, false, false, false, true); // o (PAResourceOtoP.ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_TABLE) - Double Click
+// Elapsed time: 148 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Device", 1); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// HMemoryUtils.trashcanNow. Engine heap size: 5,165 MB. GUI used memory: 211 MB. Current time: 2/12/25, 11:39:45 AM CET
+selectGraphicalView(PAResourceOtoP.PAViews_DEVICE, 231319, 366602); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor)
+/********** leftMouseClick (1662, 717, true); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor) **********/
+// Device select: 'Tile - CLBLM_L_X30Y97'
+selectView(PAResourceOtoP.PAViews_DEVICE, "Device", 948, 1012, 1833, 915); // G (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice)
+// PAPropertyPanels.initPanels (Tile: CLBLM_L_X30Y97) elapsed time: 0.2s
+// HMemoryUtils.trashcanNow. Engine heap size: 5,165 MB. GUI used memory: 212 MB. Current time: 2/12/25, 11:39:47 AM CET
+selectGraphicalView(PAResourceOtoP.PAViews_DEVICE, 237115, 360806); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor)
+/********** leftMouseClick (1678, 437, true); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor) **********/
+// Device select: 'Cell - I_clk_100m_IBUF_BUFG_inst'
+selectView(PAResourceOtoP.PAViews_DEVICE, "Device", 964, 996, 1833, 915); // G (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice)
+// HMemoryUtils.trashcanNow. Engine heap size: 6,533 MB. GUI used memory: 214 MB. Current time: 2/12/25, 11:39:49 AM CET
+selectGraphicalView(PAResourceOtoP.PAViews_DEVICE, 225523, 340882); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor)
+/********** leftMouseClick (1646, 646, true); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor) **********/
+// Device select: 'Tile - CLBLL_R_X29Y105'
+selectView(PAResourceOtoP.PAViews_DEVICE, "Device", 932, 941, 1833, 915); // G (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice)
+// HMemoryUtils.trashcanNow. Engine heap size: 5,173 MB. GUI used memory: 215 MB. Current time: 2/12/25, 11:39:51 AM CET
+// Device view-level: 0.9
+// Device view-level: 1.2
+// HMemoryUtils.trashcanNow. Engine heap size: 5,165 MB. GUI used memory: 214 MB. Current time: 2/12/25, 11:39:55 AM CET
+// Device view-level: 1.5
+// Device view-level: 1.8
+// Device view-level: 2.1
+// Device view-level: 2.4
+// Device view-level: 2.7
+// HMemoryUtils.trashcanNow. Engine heap size: 5,165 MB. GUI used memory: 217 MB. Current time: 2/12/25, 11:39:57 AM CET
+// Device view-level: 2.9
+// [GUI Memory]: 328 MB (+506kb) [01:41:04]
+// HMemoryUtils.trashcanNow. Engine heap size: 6,534 MB. GUI used memory: 216 MB. Current time: 2/12/25, 11:39:59 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,180 MB. GUI used memory: 214 MB. Current time: 2/12/25, 11:40:01 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,165 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:40:01 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,166 MB. GUI used memory: 215 MB. Current time: 2/12/25, 11:40:03 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 6,534 MB. GUI used memory: 214 MB. Current time: 2/12/25, 11:40:04 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:40:04 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,166 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:40:05 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,166 MB. GUI used memory: 212 MB. Current time: 2/12/25, 11:40:05 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 6,534 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:40:06 AM CET
+// Device view-level: 2.7
+// Device view-level: 2.4
+// Device view-level: 2.1
+// Device view-level: 1.8
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:40:06 AM CET
+// Device view-level: 1.5
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 212 MB. Current time: 2/12/25, 11:40:08 AM CET
+// Device view-level: 1.8
+// HMemoryUtils.trashcanNow. Engine heap size: 5,166 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:40:09 AM CET
+// Elapsed time: 28 seconds
+selectTable(PAResourceTtoZ.TimingItemFlatTablePanel_TABLE, "Path 1 ; 6.012 ; 5 ; 2 ; 61 ; diviseur_freq_1/SR_counter_reg[15]/C ; diviseur_freq_1/SR_counter_reg[25]/D ; 3.9909675 ; 1.639 ; 2.351967 ; 10.0 ; sys_clk_pin ; sys_clk_pin ; ; 0.03535534", 0, "6.012", 1); // e.b (PAResourceTtoZ.TimingItemFlatTablePanel_TABLE)
+// Device view-level: 2.1
+// Device view-level: 2.4
+// Device view-level: 2.9
+// HMemoryUtils.trashcanNow. Engine heap size: 6,534 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:41:16 AM CET
+// Device view-level: 3.2
+// Device view-level: 3.5
+// Device view-level: 3.8
+// Device view-level: 4.1
+// Device view-level: 3.8
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 215 MB. Current time: 2/12/25, 11:41:20 AM CET
+// Device view-level: 3.5
+// Device view-level: 3.2
+// Device view-level: 2.9
+// Device view-level: 2.7
+// Device view-level: 2.1
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 214 MB. Current time: 2/12/25, 11:41:21 AM CET
+// Device view-level: 1.8
+// Device view-level: 2.1
+// Device view-level: 2.4
+// Device view-level: 2.7
+// Device view-level: 2.9
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 216 MB. Current time: 2/12/25, 11:41:22 AM CET
+// Device view-level: 3.2
+// Device view-level: 3.5
+// Device view-level: 3.8
+// Elapsed time: 63 seconds
+selectGraphicalView(PAResourceOtoP.PAViews_DEVICE, 235305, 358831); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor)
+// HMemoryUtils.trashcanNow. Engine heap size: 6,538 MB. GUI used memory: 215 MB. Current time: 2/12/25, 11:41:26 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,180 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:41:27 AM CET
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:41:27 AM CET
+// Elapsed time: 20 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Project Summary", 0); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Nexys4_Master.xdc", 11); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "Device", 1); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 213 MB. Current time: 2/12/25, 11:41:47 AM CET
+// Device view-level: 3.5
+// HMemoryUtils.trashcanNow. Engine heap size: 6,538 MB. GUI used memory: 214 MB. Current time: 2/12/25, 11:41:50 AM CET
+// Device view-level: 3.2
+// Device view-level: 2.9
+// Device view-level: 2.7
+// Device view-level: 2.4
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 215 MB. Current time: 2/12/25, 11:42:04 AM CET
+// Device view-level: 2.1
+// Elapsed time: 17 seconds
+selectGraphicalView(PAResourceOtoP.PAViews_DEVICE, 236755, 360691); // t (PAResourceOtoP.PAViews_DEVICE, PlanAheadTabDevice_editor)
+// Elapsed time: 378 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "mux6_1.vhd", 2); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 598 seconds
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "automate.vhd", 7); // o (PlanAheadTabBaseWorkspace_JideTabbedPane)
+// Elapsed time: 667 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Simulation, Run Simulation]", 10, false); // g (PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, Flow Navigator Tree)
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+selectMenuItem(PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, "Run Behavioral Simulation"); // ap (PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL, simulation_run_behavioral_menu)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RUN_BEHAVIORAL
+selectButton("OptionPane.button", "Yes", "Simulation is Already Running"); // JButton (OptionPane.button)
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_CLOSE_WCFG
+selectButton("OptionPane.button", "Discard", "Save Waveform Configuration"); // JButton (OptionPane.button)
+// TclEventType: SIMULATION_CLOSE_SIMULATION
+// Tcl Message: close_sim
+// Tcl Message: INFO: xsimkernel Simulation Memory Usage: 110128 KB (Peak: 159460 KB), Simulation CPU Usage: 165610 ms
+// Tcl Message: INFO: [Simtcl 6-16] Simulation closed
+dismissDialog("Close"); // bj (Close Progress)
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: launch_simulation
+// Tcl Message: Command: launch_simulation
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0' INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM_LOG
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: LAUNCH_SIM
+// Tcl Message: Built simulation snapshot loto_tb_ar_cfg_behav
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [USF-XSim-98] *** Running xsim
+// Tcl Message: with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+// Tcl Message: INFO: [USF-XSim-8] Loading simulator feature
+// TclEventType: SIMULATION_CREATE_SIMULATION_OBJECT
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// Tcl Message: Time resolution is 1 ps
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // u (PAResourceOtoP.PAViews_PROJECT_SUMMARY, PlanAheadTabProject Summary)
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_PROTOCOL_INSTANCE_TREE
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 5,186 MB. GUI used memory: 228 MB. Current time: 2/12/25, 12:09:45 PM CET
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// Tcl Message: source loto_tb_ar_cfg.tcl
+// Tcl Message: # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # }
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: # run 1000ns
+// Tcl Message: INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+// Tcl Message: launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 11096.234 ; gain = 0.000 ; free physical = 4684 ; free virtual = 13201
+// 'd' command handler elapsed time: 13 seconds
+dismissDialog("Run Simulation"); // e (Run Simulation Progress)
+selectButton(RDIResource.GraphicalView_ZOOM_FIT, "Waveform Viewer_zoom_fit"); // B (RDIResource.GraphicalView_ZOOM_FIT, Waveform Viewer_zoom_fit)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "DUT ; loto(arch) ; VHDL Entity", 1, "DUT", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "transcod_1 ; transcodeur7s_d_u(transcod_int) ; VHDL Entity", 6, "transcod_1", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "diviseur_freq_1 ; diviseur_freq(Behavioral) ; VHDL Entity", 4, "diviseur_freq_1", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "modulo6_1 ; compteur_modulo6(modulo6_a) ; VHDL Entity", 3, "modulo6_1", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "tirage_1 ; tirage(a_tirage) ; VHDL Entity", 2, "tirage_1", 0, true); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Node
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "automate_1 ; automate(a_automate) ; VHDL Entity", 3, "automate_1", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "automate_1 ; automate(a_automate) ; VHDL Entity", 3, "automate_1", 0, false, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectMenu("Log to Wave Database"); // am (Log to Wave Database)
+selectMenuItem((HResource) null, "Add to Wave Window"); // ap (Add to Wave Window)
+// Tcl Command: 'current_wave_config {Untitled 7}'
+// Tcl Message: current_wave_config {Untitled 7}
+// Tcl Message: Untitled 7
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 5,166 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:00 PM CET
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// Tcl Message: add_wave {{/loto_tb/DUT/tirage_1/automate_1}}
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "registres_2 ; registres(a_registres) ; VHDL Entity", 4, "registres_2", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, SR_STATE]", 20, false); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "automate_1 ; automate(a_automate) ; VHDL Entity", 3, "automate_1", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "registres_2 ; registres(a_registres) ; VHDL Entity", 4, "registres_2", 0, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE)
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectTreeTable(PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE, "registres_2 ; registres(a_registres) ; VHDL Entity", 4, "registres_2", 0, false, false, false, false, true, false); // c (PAResourceQtoS.SimulationScopesPanel_SIMULATE_SCOPE_TABLE) - Popup Trigger
+// TclEventType: SIMULATION_REQUEST_SELECT_SCOPES
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+selectMenu("Log to Wave Database"); // am (Log to Wave Database)
+selectMenuItem((HResource) null, "Add to Wave Window"); // ap (Add to Wave Window)
+// Tcl Command: 'current_wave_config {Untitled 7}'
+// Tcl Message: current_wave_config {Untitled 7}
+// Tcl Message: Untitled 7
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// Tcl Message: add_wave {{/loto_tb/DUT/tirage_1/registres_2}}
+selectButton(PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH, "simulation_relaunch"); // B (PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH, simulation_relaunch)
+// Run Command: PAResourceCommand.PACommandNames_SIMULATION_RELAUNCH
+// TclEventType: SIMULATION_MODEL_ABOUT_TO_CLOSE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: SIMULATION_MODEL_RELOADED
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Tcl Message: relaunch_sim
+// Tcl Message: Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+// TclEventType: LAUNCH_SIM
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// Tcl Message: Waiting for jobs to finish... No pending jobs, compilation finished.
+// Tcl Message: INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
+// Tcl Message: Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+// Tcl Message: INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg' INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim' INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/m22kling/MEDCON/tp-loto-etudiant-m22kling/loto/loto.sim/sim_1/behav/xsim'
+// Tcl Message: xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: Vivado Simulator v2024.1 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log Using 8 slave threads. Starting static elaboration Completed static elaboration INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+// Tcl Message: INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_MODEL_ABOUT_TO_CLOSE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: SIMULATION_MODEL_RELOADED
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_DELETE_ALL_BREAKPOINTS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:28 PM CET
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// TclEventType: SIMULATION_CLEAR_CURRENT_LINE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: SIMULATION_OBJECT_TREE_RESTORED
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: SIMULATION_UPDATE_LATEST_TIME
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: SIMULATION_CURRENT_SCOPE_CHANGED
+// TclEventType: SIMULATION_CURRENT_STACK_CHANGED
+// TclEventType: SIMULATION_UPDATE_STACK_FRAMES
+// TclEventType: SIMULATION_CURRENT_STACK_FRAME_CHANGED
+// TclEventType: SIMULATION_UPDATE_LOCALS
+// TclEventType: SIMULATION_UPDATE_SCOPE_TREE
+// TclEventType: SIMULATION_UPDATE_STACKS
+// TclEventType: SIMULATION_UPDATE_OBJECT_TREE
+// TclEventType: SIMULATION_UPDATE_SIMULATION_STATE
+// Tcl Message: Time resolution is 1 ps relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 11096.234 ; gain = 0.000 ; free physical = 4728 ; free virtual = 13171
+// 'a' command handler elapsed time: 5 seconds
+dismissDialog("Relaunch Simulation"); // b (Relaunch Simulation Progress)
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectButton(RDIResource.WaveformView_GOTO_TIME_0, "Waveform Viewer_RunReset"); // B (RDIResource.WaveformView_GOTO_TIME_0, Waveform Viewer_RunReset)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 5,174 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:38 PM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 5,311 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:39 PM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 5,207 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:39 PM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 5,207 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:40 PM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 6,558 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:40 PM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 6,167 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:40 PM CET
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 23 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 670, 553); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+/********** startDrag (1896, 786); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+/********** endDrag (1892, 784); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// HMemoryUtils.trashcanNow. Engine heap size: 5,215 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:10:55 PM CET
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 791, 551); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+/********** leftMouseClick (1972, 779, true); // b (RDIResource.RDIViews_WAVEFORM_VIEWER, PlanAheadTabWaveform Viewer_viewer) **********/
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+selectButton(RDIResource.GraphicalView_ZOOM_IN, "Waveform Viewer_zoom_in"); // B (RDIResource.GraphicalView_ZOOM_IN, Waveform Viewer_zoom_in)
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MOVE_CURSOR
+// HMemoryUtils.trashcanNow. Engine heap size: 5,215 MB. GUI used memory: 226 MB. Current time: 2/12/25, 12:11:00 PM CET
+// Elapsed time: 11 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, I_clk]", 21, false); // k (RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE)
+// TclEventType: WAVEFORM_SELECTED_WAVE_OBJECT_NAMES
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
--
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