From b0447ca07bbcf90afc6d1ef55641c14b64078846 Mon Sep 17 00:00:00 2001
From: unknown <mathieu.bossart@imt-atlantique.net>
Date: Wed, 26 Mar 2025 12:23:15 +0100
Subject: [PATCH] Rendu v1
---
docs/compte-rendu.md | 48 +
docs/img/FSM.drawio | 879 ++-
docs/img/OperativeUnit.drawio | 1540 +++--
tp_vivado/proj/ECG.cache/sim/ssm.db | 11 +
tp_vivado/proj/ECG.cache/wt/project.wpc | 3 +
tp_vivado/proj/ECG.cache/wt/xsim.wdf | 4 +
tp_vivado/proj/ECG.hw/ECG.lpr | 7 +
tp_vivado/proj/ECG.ip_user_files/README.txt | 1 +
.../ip/clk_wiz_0/clk_wiz_0.vho | 103 +
.../proj/ECG.sim/sim_1/behav/xsim/compile.bat | 27 +
.../ECG.sim/sim_1/behav/xsim/elaborate.bat | 26 +
.../ECG.sim/sim_1/behav/xsim/elaborate.log | 19 +
.../ECG.sim/sim_1/behav/xsim/simulate.bat | 26 +
.../ECG.sim/sim_1/behav/xsim/simulate.log | 1 +
.../ECG.sim/sim_1/behav/xsim/tb_firUnit.tcl | 11 +
.../sim_1/behav/xsim/tb_firUnit_behav.wdb | Bin 0 -> 36768 bytes
.../sim_1/behav/xsim/tb_firUnit_vhdl.prj | 9 +
.../proj/ECG.sim/sim_1/behav/xsim/xelab.pb | Bin 0 -> 1963 bytes
.../tb_firUnit_behav/Compile_Options.txt | 1 +
.../tb_firUnit_behav/TempBreakPointFile.txt | 1 +
.../tb_firUnit_behav/obj/xsim_0.win64.obj | Bin 0 -> 23363 bytes
.../xsim.dir/tb_firUnit_behav/obj/xsim_1.c | 143 +
.../tb_firUnit_behav/obj/xsim_1.win64.obj | Bin 0 -> 4199 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.dbg | Bin 0 -> 17640 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.mem | Bin 0 -> 4746 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.reloc | Bin 0 -> 1963 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rlx | 12 +
.../xsim/xsim.dir/tb_firUnit_behav/xsim.rtti | Bin 0 -> 903 bytes
.../xsim.dir/tb_firUnit_behav/xsim.svtype | Bin 0 -> 12 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.type | Bin 0 -> 7424 bytes
.../xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg | Bin 0 -> 84288 bytes
.../tb_firUnit_behav/xsimSettings.ini | 50 +
.../xsim.dir/tb_firUnit_behav/xsimcrash.log | 0
.../xsim/xsim.dir/tb_firUnit_behav/xsimk.exe | Bin 0 -> 83293 bytes
.../xsim.dir/tb_firUnit_behav/xsimkernel.log | 7 +
.../xsim.dir/xil_defaultlib/controlunit.vdb | Bin 0 -> 14548 bytes
.../xsim/xsim.dir/xil_defaultlib/firunit.vdb | Bin 0 -> 15686 bytes
.../xsim.dir/xil_defaultlib/operativeunit.vdb | Bin 0 -> 34694 bytes
.../xsim.dir/xil_defaultlib/tb_firunit.vdb | Bin 0 -> 6154 bytes
.../xil_defaultlib/xil_defaultlib.rlx | 8 +
.../proj/ECG.sim/sim_1/behav/xsim/xsim.ini | 489 ++
.../ECG.sim/sim_1/behav/xsim/xsim.ini.bak | 489 ++
.../proj/ECG.sim/sim_1/behav/xsim/xvhdl.log | 0
.../proj/ECG.sim/sim_1/behav/xsim/xvhdl.pb | 4 +
tp_vivado/proj/ECG.xpr | 302 +
tp_vivado/proj/cleanup.cmd | 21 +
tp_vivado/proj/cleanup.sh | 15 +
tp_vivado/proj/create_project.tcl | 111 +
.../src/constraints/NexysVideo_Master.xdc | 365 ++
tp_vivado/src/hdl/TWICtl.vhd | 571 ++
tp_vivado/src/hdl/audioProc.v | 231 +
tp_vivado/src/hdl/audio_init.v | 246 +
tp_vivado/src/hdl/controlUnit.vhd | 183 +
tp_vivado/src/hdl/debounce.v | 108 +
tp_vivado/src/hdl/fir.vhd | 93 +
tp_vivado/src/hdl/firUnit.vhd | 162 +
tp_vivado/src/hdl/i2s_ctl.vhd | 296 +
tp_vivado/src/hdl/operativeUnit.vhd | 374 ++
tp_vivado/src/hdl/processingUnitIP.v | 3270 +++++++++++
tp_vivado/src/hdl/tb_firUnit.vhd | 87 +
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.dcp | Bin 0 -> 12528 bytes
.../src/ip/clk_wiz_0/clk_wiz_0.upgrade_log | 332 ++
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.v | 100 +
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.vho | 103 +
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xci | 525 ++
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xdc | 59 +
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xml | 4933 +++++++++++++++++
.../src/ip/clk_wiz_0/clk_wiz_0_board.xdc | 2 +
.../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 215 +
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc | 56 +
.../src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v | 278 +
.../ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl | 218 +
tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.v | 24 +
.../src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 33 +
.../clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt | 115 +
75 files changed, 16451 insertions(+), 896 deletions(-)
create mode 100644 tp_vivado/proj/ECG.cache/sim/ssm.db
create mode 100644 tp_vivado/proj/ECG.cache/wt/project.wpc
create mode 100644 tp_vivado/proj/ECG.cache/wt/xsim.wdf
create mode 100644 tp_vivado/proj/ECG.hw/ECG.lpr
create mode 100644 tp_vivado/proj/ECG.ip_user_files/README.txt
create mode 100644 tp_vivado/proj/ECG.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/compile.bat
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.bat
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.log
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.bat
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.log
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit.tcl
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xelab.pb
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.win64.obj
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.dbg
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.mem
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.reloc
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.xdbg
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_firunit.vdb
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini.bak
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.log
create mode 100644 tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.pb
create mode 100644 tp_vivado/proj/ECG.xpr
create mode 100644 tp_vivado/proj/cleanup.cmd
create mode 100644 tp_vivado/proj/cleanup.sh
create mode 100644 tp_vivado/proj/create_project.tcl
create mode 100644 tp_vivado/src/constraints/NexysVideo_Master.xdc
create mode 100644 tp_vivado/src/hdl/TWICtl.vhd
create mode 100644 tp_vivado/src/hdl/audioProc.v
create mode 100644 tp_vivado/src/hdl/audio_init.v
create mode 100644 tp_vivado/src/hdl/controlUnit.vhd
create mode 100644 tp_vivado/src/hdl/debounce.v
create mode 100644 tp_vivado/src/hdl/fir.vhd
create mode 100644 tp_vivado/src/hdl/firUnit.vhd
create mode 100644 tp_vivado/src/hdl/i2s_ctl.vhd
create mode 100644 tp_vivado/src/hdl/operativeUnit.vhd
create mode 100644 tp_vivado/src/hdl/processingUnitIP.v
create mode 100644 tp_vivado/src/hdl/tb_firUnit.vhd
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.dcp
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.v
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.vho
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xci
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xdc
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xml
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.v
create mode 100644 tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
create mode 100644 tp_vivado/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 30ffa40..c7ed9b3 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -19,3 +19,51 @@ mainfont: sans-serif
## Remarques
(Notez toute information qui vous semble pertinente)
+
+Succession de 3 filtres : FIR -> IIR -> FIR
+
+Pour notre filtre on calcule $x_k \rightarrow y_k \rightarrow z_k \rightarrow r_k$ avec $x_k$ l'entrée
+
+$$y_k = \sum_{i=0}^{94}x_{k-i} \times h_i$$
+
+$$z_k = \sum_{i=0}^2 y_{k-i}\times b_i - \sum_{i=1}^2 z_{k-i}\times a_i$$
+
+$$r_k = \sum_{i=0}^{10} z_{k-i} \times g_i$$
+
+## Code de chaque filtre
+
+### Baseline
+
+```
+Fs=500
+Fn=Fs/2
+fBaseLine=fir1(128, 5/Fn, 'high');
+```
+
+### Coupe-bande basique
+
+```
+Fs=500
+Fn=Fs/2
+f50Hz=fir1(100, [45 55]/Fn, 'stop');
+```
+
+### Pei Tseng Notch
+
+```
+Fs=500
+Fn=Fs/2
+[b, a]=pei_tseng_notch(50/Fn, 10/Fn);
+```
+
+### Parks McClellan
+
+```
+Fs=500
+Fn=Fs/2
+Fpass=50;
+Fstop=60;
+F =[0 Fpass Fstop Fn]/(Fn)
+A =[1 1 0 0]
+fLP =remez(10, F, A)
+```
\ No newline at end of file
diff --git a/docs/img/FSM.drawio b/docs/img/FSM.drawio
index 2451a53..3f98edd 100644
--- a/docs/img/FSM.drawio
+++ b/docs/img/FSM.drawio
@@ -1,470 +1,409 @@
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+ <mxCell id="342" style="edgeStyle=none;html=1;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" source="336" target="141" edge="1">
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+ </mxCell>
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+ <mxCell id="345" style="edgeStyle=none;html=1;entryX=0;entryY=0.5;entryDx=0;entryDy=0;" parent="1" source="337" target="uwrRxOYGmB2LabIKb8In-14" edge="1">
+ <mxGeometry relative="1" as="geometry"/>
+ </mxCell>
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+ </mxCell>
+ <mxCell id="337" value="" style="html=1;shadow=0;dashed=0;align=center;verticalAlign=middle;shape=mxgraph.arrows2.arrow;dy=0;dx=10;notch=10;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
+ <mxGeometry x="372.5" y="-650" width="67.5" height="30" as="geometry"/>
+ </mxCell>
+ <mxCell id="339" style="edgeStyle=none;html=1;entryX=1;entryY=0.5;entryDx=0;entryDy=0;rounded=0;curved=0;" parent="1" target="230" edge="1">
+ <mxGeometry relative="1" as="geometry">
+ <mxPoint x="656.0000000000009" y="260" as="targetPoint"/>
+ <mxPoint x="410" y="-320" as="sourcePoint"/>
+ <Array as="points">
+ <mxPoint x="410.0000000000009" y="-300"/>
+ <mxPoint x="566.0000000000009" y="-190"/>
+ <mxPoint x="566" y="390"/>
+ </Array>
+ </mxGeometry>
+ </mxCell>
+ <mxCell id="348" value="1:10" style="text;html=1;align=center;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;fontSize=19;" vertex="1" parent="1">
+ <mxGeometry x="810" y="-160" width="60" height="40" as="geometry"/>
+ </mxCell>
+ <mxCell id="349" value="2:9" style="text;html=1;align=center;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;fontSize=19;" vertex="1" parent="1">
+ <mxGeometry x="815" y="100" width="50" height="40" as="geometry"/>
+ </mxCell>
+ <mxCell id="350" value="2:9" style="text;html=1;align=center;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;fontSize=19;" vertex="1" parent="1">
+ <mxGeometry x="815" y="300" width="50" height="40" as="geometry"/>
+ </mxCell>
+ <mxCell id="351" value="1:10" style="text;html=1;align=center;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;fontSize=19;" vertex="1" parent="1">
+ <mxGeometry x="810" y="560" width="60" height="40" as="geometry"/>
+ </mxCell>
+ </root>
+ </mxGraphModel>
+ </diagram>
+</mxfile>
\ No newline at end of file
diff --git a/tp_vivado/proj/ECG.cache/sim/ssm.db b/tp_vivado/proj/ECG.cache/sim/ssm.db
new file mode 100644
index 0000000..8724fa8
--- /dev/null
+++ b/tp_vivado/proj/ECG.cache/sim/ssm.db
@@ -0,0 +1,11 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Mar 26 11:21:43 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,
diff --git a/tp_vivado/proj/ECG.cache/wt/project.wpc b/tp_vivado/proj/ECG.cache/wt/project.wpc
new file mode 100644
index 0000000..0161c5d
--- /dev/null
+++ b/tp_vivado/proj/ECG.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:6
+eof:
diff --git a/tp_vivado/proj/ECG.cache/wt/xsim.wdf b/tp_vivado/proj/ECG.cache/wt/xsim.wdf
new file mode 100644
index 0000000..51d5206
--- /dev/null
+++ b/tp_vivado/proj/ECG.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
+eof:2427094519
diff --git a/tp_vivado/proj/ECG.hw/ECG.lpr b/tp_vivado/proj/ECG.hw/ECG.lpr
new file mode 100644
index 0000000..9f2f4bc
--- /dev/null
+++ b/tp_vivado/proj/ECG.hw/ECG.lpr
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0"/>
diff --git a/tp_vivado/proj/ECG.ip_user_files/README.txt b/tp_vivado/proj/ECG.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/tp_vivado/proj/ECG.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/tp_vivado/proj/ECG.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/tp_vivado/proj/ECG.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100644
index 0000000..c6b126b
--- /dev/null
+++ b/tp_vivado/proj/ECG.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,103 @@
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+
+ -- Clock in ports
+ clk_in1 => clk_in1,
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/compile.bat b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/compile.bat
new file mode 100644
index 0000000..76ef341
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/compile.bat
@@ -0,0 +1,27 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename : compile.bat
+REM Simulator : AMD Vivado Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Generated by Vivado on Wed Mar 26 12:19:40 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: compile.bat
+REM
+REM ****************************************************************************
+REM compile VHDL design sources
+echo "xvhdl --incr --relax -prj tb_firUnit_vhdl.prj"
+call xvhdl --incr --relax -prj tb_firUnit_vhdl.prj -log xvhdl.log
+call type xvhdl.log > compile.log
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.bat b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.bat
new file mode 100644
index 0000000..17aad06
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename : elaborate.bat
+REM Simulator : AMD Vivado Simulator
+REM Description : Script for elaborating the compiled design
+REM
+REM Generated by Vivado on Wed Mar 26 12:19:42 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: elaborate.bat
+REM
+REM ****************************************************************************
+REM elaborate design
+echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log"
+call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.log b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000..515bcc8
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,19 @@
+Vivado Simulator v2024.2.0
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: C:/Xilinx/Vivado/2024.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit -log elaborate.log
+Using 2 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.bat b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.bat
new file mode 100644
index 0000000..2cdac6a
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.bat
@@ -0,0 +1,26 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2024.2 (64-bit)
+REM
+REM Filename : simulate.bat
+REM Simulator : AMD Vivado Simulator
+REM Description : Script for simulating the design by launching the simulator
+REM
+REM Generated by Vivado on Wed Mar 26 11:45:26 +0100 2025
+REM SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+REM
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+REM usage: simulate.bat
+REM
+REM ****************************************************************************
+REM simulate design
+echo "xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log"
+call xsim tb_firUnit_behav -key {Behavioral:sim_1:Functional:tb_firUnit} -tclbatch tb_firUnit.tcl -log simulate.log
+if "%errorlevel%"=="0" goto SUCCESS
+if "%errorlevel%"=="1" goto END
+:END
+exit 1
+:SUCCESS
+exit 0
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.log b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000..3a14ee6
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit.tcl b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit.tcl
new file mode 100644
index 0000000..1094e45
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..240b87084ebcaadb40beb13f3f474994f3ffdcc7
GIT binary patch
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
new file mode 100644
index 0000000..0107b4e
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/tb_firUnit_vhdl.prj
@@ -0,0 +1,9 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/hdl/controlUnit.vhd" \
+"../../../../../src/hdl/operativeUnit.vhd" \
+"../../../../../src/hdl/firUnit.vhd" \
+"../../../../../src/hdl/tb_firUnit.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xelab.pb b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..cb33821cb848f406541364fbad7d42619dbd4469
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
new file mode 100644
index 0000000..693a583
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" -L "xpm" --snapshot "tb_firUnit_behav" "xil_defaultlib.tb_firUnit" -log "elaborate.log"
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000..fdbc612
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj
new file mode 100644
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literal 0
HcmV?d00001
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
new file mode 100644
index 0000000..9d9d7cc
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/obj/xsim_1.c
@@ -0,0 +1,143 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_25(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_31(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_35(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_49(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_52(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_56(char*, char *);
+IKI_DLLESPEC extern void execute_57(char*, char *);
+IKI_DLLESPEC extern void execute_58(char*, char *);
+IKI_DLLESPEC extern void execute_59(char*, char *);
+IKI_DLLESPEC extern void execute_60(char*, char *);
+IKI_DLLESPEC extern void execute_61(char*, char *);
+IKI_DLLESPEC extern void execute_62(char*, char *);
+IKI_DLLESPEC extern void execute_63(char*, char *);
+IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+funcp funcTab[37] = {(funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
+const int NumRelocateId= 37;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc", (void **)funcTab, 37);
+ iki_vhdl_file_variable_register(dp + 16080);
+ iki_vhdl_file_variable_register(dp + 16136);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_firUnit_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/tb_firUnit_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/tb_firUnit_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/tb_firUnit_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
new file mode 100644
index 0000000..b4d92e1
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 3343777929024806533 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" ,
+ buildDate : "Nov 8 2024" ,
+ buildTime : "22:36:57" ,
+ linkCmd : "C:\\Xilinx\\Vivado\\2024.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/tb_firUnit_behav/xsimk.exe\" \"xsim.dir/tb_firUnit_behav/obj/xsim_0.win64.obj\" \"xsim.dir/tb_firUnit_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2024.2\\lib\\win64.o\" -lxv_simulator_kernel -lxv_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..658a3b63e8814748be2f346d2049650cc20084aa
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.svtype
new file mode 100644
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GIT binary patch
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.type
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
new file mode 100644
index 0000000..359171a
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
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+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
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+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=140
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=193
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+OBJECT_VALUE_COLUMN_WIDTH=59
+OBJECT_DATA_TYPE_COLUMN_WIDTH=90
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
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+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
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+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
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+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimcrash.log
new file mode 100644
index 0000000..e69de29
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimk.exe
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
new file mode 100644
index 0000000..2eae4ff
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/tb_firUnit_behav/xsimk.exe -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 49669
+Design successfully loaded
+Design Loading Memory Usage: 28544 KB (Peak: 28544 KB)
+Design Loading CPU Usage: 764 ms
+Simulation completed
+Simulation Memory Usage: 29308 KB (Peak: 29308 KB)
+Simulation CPU Usage: 827 ms
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/controlunit.vdb
new file mode 100644
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/firunit.vdb
new file mode 100644
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GIT binary patch
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diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/operativeunit.vdb
new file mode 100644
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GIT binary patch
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new file mode 100644
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literal 0
HcmV?d00001
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000..54e8b15
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,8 @@
+0.7
+2020.2
+Nov 8 2024
+22:36:57
+C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/controlUnit.vhd,1742987636,vhdl,C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/firUnit.vhd,1742984448,vhdl,C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
+C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/operativeUnit.vhd,1742987971,vhdl,C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
+C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/src/hdl/tb_firUnit.vhd,1742984692,vhdl,,,,tb_firunit,,,,,,,,
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000..e2f5709
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,489 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+cpri_v8_12_0=$RDI_DATADIR/xsim/ip/cpri_v8_12_0
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+an_lt_v1_0_14=$RDI_DATADIR/xsim/ip/an_lt_v1_0_14
+axi_chip2chip_v5_0_24=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_24
+g709_fec_v2_4_11=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_11
+audio_formatter_v1_0_15=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_15
+ats_switch_v1_0_12=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_12
+xbip_pipe_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_10
+v_gamma_lut_v1_1_13=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_13
+vrf_fft_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_fft_v1_0_0
+v_hdmi_tx1_v1_0_10=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_10
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+axi_mm2s_mapper_v1_1_32=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_32
+axis_data_fifo_v1_1_34=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_34
+mailbox_v2_1_18=$RDI_DATADIR/xsim/ip/mailbox_v2_1_18
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+sdfec_ld_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/sdfec_ld_wrapper_v1_0_0
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+tcc_encoder_3gpplte_v4_0_20=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_20
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+vitis_net_p4_v2_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_2_0
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+v_frmbuf_rd_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v3_0_0
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+dfx_bitstream_monitor_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_6
+rs_toolbox_v9_0_14=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_14
+perf_axi_tg_v1_0_15=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_15
+xbip_utils_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_14
+dptx_v1_0_5=$RDI_DATADIR/xsim/ip/dptx_v1_0_5
+rs_decoder_v9_0_23=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_23
+dsp_macro_v1_0_7=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_7
+axi_vdma_v6_3_21=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_21
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+qdriv_pl_v1_0_14=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_14
+axis_data_fifo_v2_0_15=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_15
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_i3c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_2
+axi_sg_v4_1_19=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_19
+mipi_csi2_rx_ctrl_v1_0_11=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_11
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+xxv_ethernet_v4_1_13=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_13
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+ernic_v4_2_0=$RDI_DATADIR/xsim/ip/ernic_v4_2_0
+rama_v1_1_19_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_19_lib
+rfdace5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfdace5_wrapper_v1_0_0
+tsn_temac_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_12
+tri_mode_ethernet_mac_v9_0_35=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_35
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+ieee802d3_200g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_12
+fast_adapter_v1_0_10=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_10
+hdmi_gt_controller_v2_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v2_0_0
+xdfe_ofdm_v2_2_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_2_0
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+vfb_v1_0_27=$RDI_DATADIR/xsim/ip/vfb_v1_0_27
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+vcu2_v1_0_0=$RDI_DATADIR/xsim/ip/vcu2_v1_0_0
+shell_utils_addr_remap_v1_0_12=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_12
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+sim_trig_v1_0_13=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_13
+v_hdmi_phy1_v1_0_13=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_13
+displayport_v7_0_25=$RDI_DATADIR/xsim/ip/displayport_v7_0_25
+cordic_v6_0_23=$RDI_DATADIR/xsim/ip/cordic_v6_0_23
+axi_crossbar_v2_1_34=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_34
+proc_sys_reset_v5_0_16=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_16
+polar_v1_1_5=$RDI_DATADIR/xsim/ip/polar_v1_1_5
+xscl=$RDI_DATADIR/xsim/ip/xscl
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+ldpc_v2_0_16=$RDI_DATADIR/xsim/ip/ldpc_v2_0_16
+switch_core_top_v1_0_17=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_17
+v_frmbuf_wr_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_3
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+audio_clock_recovery_unit_v1_0_5=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_5
+xdfe_resampler_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_10
+sd_fec_v1_1_15=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_15
+fifo_generator_v13_2_11=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_11
+axi_timebase_wdt_v3_0_25=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_25
+psx_vip_v1_0_6=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_6
+axi_memory_init_v1_0_14=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_14
+emc_common_v3_0_8=$RDI_DATADIR/xsim/ip/emc_common_v3_0_8
+ieee802d3_rs_fec_v2_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_24
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+v_vcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_13
+v_csc_v1_1_13=$RDI_DATADIR/xsim/ip/v_csc_v1_1_13
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+zynq_ultra_ps_e_vip_v1_0_19=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_19
+axi_cdma_v4_1_33=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_33
+v_dp_axi4s_vid_out_v1_0_9=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_9
+i2s_receiver_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_9
+rld3_pl_v1_0_15=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_15
+axi_firewall_v1_2_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_8
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+cpm5n_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_9
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+axis_switch_v1_1_33=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_33
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+mipi_dphy_v4_3_13=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_13
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+iomodule_v3_1_11=$RDI_DATADIR/xsim/ip/iomodule_v3_1_11
+fc32_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_28
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+axi_hwicap_v3_0_37=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_37
+g709_rs_decoder_v2_2_15=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_15
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+tmr_voter_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_7
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mdm_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_3
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+amm_axi_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_19
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+axis_accelerator_adapter_v2_1_19=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_19
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+vrf_channelizer_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_channelizer_v1_0_0
+uhdsdi_gt_v2_1_5=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_5
+v_deinterlacer_v5_1_6=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_6
+noc_hbm_v1_0_1=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_1
+in_system_ibert_v1_0_23=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_23
+axi_pcie_v2_9_12=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_12
+axi_epu_v1_0_6=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_6
+floating_point_v7_0_24=$RDI_DATADIR/xsim/ip/floating_point_v7_0_24
+v_axi4s_vid_out_v4_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_19
+v_multi_scaler_v1_2_7=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_7
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+can_v5_1_5=$RDI_DATADIR/xsim/ip/can_v5_1_5
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+xdfe_cc_filter_v1_1_5=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_5
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+v_smpte_uhdsdi_tx_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_5
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+noc2_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_sim_v1_0_0
+tmr_sem_v1_0_27=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_27
+axi_ahblite_bridge_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_30
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+axi_uart16550_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_35
+ecc_v2_0_17=$RDI_DATADIR/xsim/ip/ecc_v2_0_17
+v_frmbuf_rd_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_12
+axi_data_fifo_v2_1_32=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_32
+xdfe_equalizer_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_10
+axi_mcdma_v1_2_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_2_0
+versal_cips_ps_vip_v1_0_11=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_11
+emb_mem_gen_v1_0_10=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_10
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+displayport_v8_1_10=$RDI_DATADIR/xsim/ip/displayport_v8_1_10
+tcc_encoder_3gpp_v5_0_23=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_23
+pcie_qdma_mailbox_v1_0_8=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_8
+v_frmbuf_rd_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_dwidth_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_32
+axi4svideo_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_19
+util_ff_v1_0_4=$RDI_DATADIR/xsim/ip/util_ff_v1_0_4
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+microblaze_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_3
+cpri_v8_11_22=$RDI_DATADIR/xsim/ip/cpri_v8_11_22
+v_vid_in_axi4s_v5_0_5=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_5
+dprx_v1_0_5=$RDI_DATADIR/xsim/ip/dprx_v1_0_5
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+axi_pcie3_v3_0_32=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_32
+v_smpte_uhdsdi_rx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_4
+axi_datamover_v5_1_35=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_35
+interlaken_v2_4_19=$RDI_DATADIR/xsim/ip/interlaken_v2_4_19
+nvmeha_v1_0_14=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_14
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+bfr_ft_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/bfr_ft_wrapper_v1_0_0
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+zynq_ultra_ps_e_v3_3_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_14
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+v_hdmi_rx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_5
+ethernet_1_10_25g_v2_7_18=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_18
+v_tpg_v8_2_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_6
+qdma_v5_0_12=$RDI_DATADIR/xsim/ip/qdma_v5_0_12
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+jesd204c_v4_3_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_3_0
+axi_timer_v2_0_35=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_35
+c_compare_v12_0_10=$RDI_DATADIR/xsim/ip/c_compare_v12_0_10
+axi_clock_converter_v2_1_32=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_32
+axi_protocol_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_33
+axi_dma_v7_1_34=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_34
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+dfx_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_11
+axi_sideband_util_v1_0_17=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_17
+tmr_manager_v1_0_13=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_13
+fec_5g_common_v1_1_5=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_5
+axi_ethernetlite_v3_0_32=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_32
+lib_bmg_v1_0_18=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_18
+high_speed_selectio_wiz_v3_6_10=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_10
+c_shift_ram_v12_0_18=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_18
+axi_pmon_v1_0_2=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_2
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+uhdsdi_gt_v2_2_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_2_0
+v_tpg_v8_1_12=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_12
+noc2_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_sim_v1_0_0
+axi_gpio_v2_0_35=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_35
+axis_interconnect_v1_1_24=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_24
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+c_addsub_v12_0_19=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_19
+sem_ultra_v3_1_27=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_27
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+v_warp_init_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+roe_framer_v3_0_9=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_9
+axi_remapper_tx_v1_0_3=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_3
+axi_traffic_gen_v3_0_19=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_19
+dfx_controller_v1_0_8=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_8
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+tmr_comparator_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_8
+rfadce5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfadce5_wrapper_v1_0_0
+axi_mmu_v2_1_31=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_31
+axi_dwidth_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_33
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+picxo_fracxo_v2_0_3=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_3
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+v_frmbuf_wr_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_12
+sd_fec_beta_v1_0_0=$RDI_DATADIR/xsim/ip/sd_fec_beta_v1_0_0
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+lmb_bram_if_cntlr_v4_0_25=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_25
+mrmac_v3_0_0=$RDI_DATADIR/xsim/ip/mrmac_v3_0_0
+tsn_endpoint_ethernet_mac_block_v1_0_18=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_18
+axis_vio_v1_0_12=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_12
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+floating_point_v7_1_19=$RDI_DATADIR/xsim/ip/floating_point_v7_1_19
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+pc_cfr_v8_0_3=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_3
+axi_amm_bridge_v1_0_23=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_23
+c_counter_binary_v12_0_20=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_20
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+axi_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_19
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+axi_msg_v1_0_12=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_12
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+xpm=$RDI_DATADIR/xsim/ip/xpm
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+gtwizard_ultrascale_v1_7_19=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_19
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mipi_rx_phy_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_1
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+dds_compiler_v6_0_26=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_26
+xdma_v4_1_31=$RDI_DATADIR/xsim/ip/xdma_v4_1_31
+axi_fifo_mm_s_v4_3_5=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_5
+l_ethernet_v3_3_13=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_13
+xdfe_nlf_v1_1_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_2
+axi_mcdma_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_14
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+xdfe_common_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_4
+axi_intc_v4_1_20=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_20
+axi_uartlite_v2_0_37=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_37
+gmii_to_rgmii_v4_1_17=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_17
+cdcam_v1_2_0=$RDI_DATADIR/xsim/ip/cdcam_v1_2_0
+blk_mem_gen_v8_4_9=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_9
+system_cache_v5_0_12=$RDI_DATADIR/xsim/ip/system_cache_v5_0_12
+cmac_usplus_v3_1_19=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_19
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_interconnect_v1_7_24=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_24
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+v_hdmi_tx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_5
+dft_v4_2_9=$RDI_DATADIR/xsim/ip/dft_v4_2_9
+ieee802d3_400g_rs_fec_v3_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_3
+srio_gen2_v4_1_20=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_20
+mipi_tx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_tx_phy_v1_0_0
+axi_epc_v2_0_36=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_36
+i2s_transmitter_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_9
+flexo_100g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_30
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+axi_emc_v3_0_33=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_33
+multi_channel_25g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_28
+axi_protocol_checker_v2_0_19=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_19
+axi_register_slice_v2_1_33=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_33
+v_letterbox_v1_1_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_13
+gtwizard_ultrascale_v1_6_17=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_17
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+axis_broadcaster_v1_1_32=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_32
+axis_clock_converter_v1_1_34=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_34
+ahblite_axi_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_28
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+sid_v8_0_22=$RDI_DATADIR/xsim/ip/sid_v8_0_22
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+ten_gig_eth_pcs_pma_v6_0_28=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_28
+axis_register_slice_v1_1_33=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_33
+clk_vip_v1_0_5=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_5
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+v_vid_sdi_tx_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_3
+processing_system7_vip_v1_0_21=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_21
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+cmac_v2_6_17=$RDI_DATADIR/xsim/ip/cmac_v2_6_17
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+mpram_v1_0_5=$RDI_DATADIR/xsim/ip/mpram_v1_0_5
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+v_hscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_13
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+axis_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_17
+xbip_multadd_v3_0_21=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_21
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+axi_vfifo_ctrl_v2_0_36=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_36
+v_warp_filter_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_5
+xfft_v9_1_13=$RDI_DATADIR/xsim/ip/xfft_v9_1_13
+axi_bram_ctrl_v4_1_11=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_11
+v_hcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_13
+v_demosaic_v1_1_13=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_13
+lte_fft_v2_1_11=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_11
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+mrmac_v2_3_2=$RDI_DATADIR/xsim/ip/mrmac_v2_3_2
+v_tc_v6_2_9=$RDI_DATADIR/xsim/ip/v_tc_v6_2_9
+div_gen_v5_1_23=$RDI_DATADIR/xsim/ip/div_gen_v5_1_23
+rs_encoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_22
+axi_utils_v2_0_10=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_10
+v_axi4s_remap_v1_1_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_12
+v_mix_v5_2_11=$RDI_DATADIR/xsim/ip/v_mix_v5_2_11
+xdfe_fft_v1_0_8=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_8
+cic_compiler_v4_0_20=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_20
+sim_clk_gen_v1_0_5=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_5
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+usxgmii_v1_2_20=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_20
+v_smpte_sdi_v3_0_12=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_12
+mipi_dsi2_rx_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_1
+mdm_v3_2_27=$RDI_DATADIR/xsim/ip/mdm_v3_2_27
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+g975_efec_i7_v2_0_24=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_24
+axis_combiner_v1_1_31=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_31
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+dcmac_v2_5_0=$RDI_DATADIR/xsim/ip/dcmac_v2_5_0
+convolution_v9_0_21=$RDI_DATADIR/xsim/ip/convolution_v9_0_21
+microblaze_v11_0_14=$RDI_DATADIR/xsim/ip/microblaze_v11_0_14
+cpm4_v1_0_17=$RDI_DATADIR/xsim/ip/cpm4_v1_0_17
+cmpy_v6_0_25=$RDI_DATADIR/xsim/ip/cmpy_v6_0_25
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+spdif_v2_0_30=$RDI_DATADIR/xsim/ip/spdif_v2_0_30
+oran_radio_if_v3_2_1=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_1
+v_hdmi_rx1_v1_0_11=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_11
+cam_v3_1_0=$RDI_DATADIR/xsim/ip/cam_v3_1_0
+emb_fifo_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_6
+axi_iic_v2_1_9=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_9
+axi_perf_mon_v5_0_35=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_35
+v_tpg_v8_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_16
+mutex_v2_1_14=$RDI_DATADIR/xsim/ip/mutex_v2_1_14
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+lib_fifo_v1_0_20=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_20
+advanced_io_wizard_v1_0_15=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_15
+c_reg_fd_v12_0_10=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_10
+axi4stream_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_19
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+ieee802d3_50g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_25
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+vid_edid_v1_0_3=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_3
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+mult_gen_v12_0_22=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_22
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+dfe_channelizer_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/dfe_channelizer_wrapper_v1_0_0
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+v_frmbuf_wr_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v3_0_0
+xdfe_cc_mixer_v2_0_5=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_5
+mipi_dsi_tx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_10
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+ieee802d3_clause74_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_19
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_tft_v2_0_29=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_29
+viterbi_v9_1_18=$RDI_DATADIR/xsim/ip/viterbi_v9_1_18
+ieee802d3_50g_rs_fec_v2_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_18
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+ilknf_v1_3_5=$RDI_DATADIR/xsim/ip/ilknf_v1_3_5
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+g975_efec_i4_v1_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_23
+c_accum_v12_0_19=$RDI_DATADIR/xsim/ip/c_accum_v12_0_19
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+ieee802d3_25g_rs_fec_v1_0_31=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_31
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+xdfe_nr_prach_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_4
+gig_ethernet_pcs_pma_v16_2_21=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_21
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+v_sdi_rx_vid_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_3
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+ldpc_5gnr_v1_0_4=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_4
+soft_ecc_proxy_v1_1_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_2
+axi_c2c_v1_0_11=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_11
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+v_smpte_uhdsdi_v1_0_12=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_12
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+fir_compiler_v7_2_23=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_23
+axi_hbicap_v1_0_8=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_8
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+canfd_v3_0_12=$RDI_DATADIR/xsim/ip/canfd_v3_0_12
+nvme_tc_v3_0_8=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_8
+axi_usb2_device_v5_0_34=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_34
+ldpc_5gnr_lite_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_3
+tmr_inject_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_7
+v_uhdsdi_audio_v2_0_9=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_9
+xsdbm_v3_0_3=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_3
+v_vscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_13
+vid_phy_controller_v2_2_19=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_19
+mem_tg_v1_0_15=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_15
+dfx_axi_shutdown_manager_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_4
+ibert_lib_v1_0_12=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_12
+ta_dma_v1_0_17=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_17
+cam_blk_lib_v1_2_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_2_0
+noc2_nps6x_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps6x_v1_0_0
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+tcc_decoder_3gppmm_v2_0_28=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_28
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+ddr4_pl_v1_0_15=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_15
+advanced_io_wizard_phy_v1_0_4=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_4
+ft_prach_v1_2_3=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_3
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+x5io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_6
+axis_subset_converter_v1_1_33=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_33
+axi_quad_spi_v3_2_32=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_32
+g709_rs_encoder_v2_2_13=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_13
+hdcp_v1_0_6=$RDI_DATADIR/xsim/ip/hdcp_v1_0_6
+v_frmbuf_rd_v2_4_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_4
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+quadsgmii_v3_5_21=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_21
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+rst_vip_v1_0_7=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_7
+ethernet_offload_v1_0_0=$RDI_DATADIR/xsim/ip/ethernet_offload_v1_0_0
+cpm5_v1_0_17=$RDI_DATADIR/xsim/ip/cpm5_v1_0_17
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+displayport_v9_0_10=$RDI_DATADIR/xsim/ip/displayport_v9_0_10
+visp_v1_0_0=$RDI_DATADIR/xsim/ip/visp_v1_0_0
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini.bak b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini.bak
new file mode 100644
index 0000000..e2f5709
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -0,0 +1,489 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+cpri_v8_12_0=$RDI_DATADIR/xsim/ip/cpri_v8_12_0
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+an_lt_v1_0_14=$RDI_DATADIR/xsim/ip/an_lt_v1_0_14
+axi_chip2chip_v5_0_24=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_24
+g709_fec_v2_4_11=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_11
+audio_formatter_v1_0_15=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_15
+ats_switch_v1_0_12=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_12
+xbip_pipe_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_10
+v_gamma_lut_v1_1_13=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_13
+vrf_fft_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_fft_v1_0_0
+v_hdmi_tx1_v1_0_10=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_10
+pci32_v5_0_13=$RDI_DATADIR/xsim/ip/pci32_v5_0_13
+axi_mm2s_mapper_v1_1_32=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_32
+axis_data_fifo_v1_1_34=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_34
+mailbox_v2_1_18=$RDI_DATADIR/xsim/ip/mailbox_v2_1_18
+lib_cdc_v1_0_3=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_3
+sdfec_ld_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/sdfec_ld_wrapper_v1_0_0
+v_tc_v6_1_14=$RDI_DATADIR/xsim/ip/v_tc_v6_1_14
+tcc_encoder_3gpplte_v4_0_20=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_20
+axis_ila_intf_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_2
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+vitis_net_p4_v2_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v2_2_0
+generic_baseblocks_v2_1_2=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_2
+ten_gig_eth_mac_v15_1_12=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_12
+hdmi_gt_controller_v1_0_13=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_13
+v_frmbuf_rd_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v3_0_0
+fifo_generator_v13_1_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_5
+dfx_bitstream_monitor_v1_0_6=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_6
+rs_toolbox_v9_0_14=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_14
+perf_axi_tg_v1_0_15=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_15
+xbip_utils_v3_0_14=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_14
+dptx_v1_0_5=$RDI_DATADIR/xsim/ip/dptx_v1_0_5
+rs_decoder_v9_0_23=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_23
+dsp_macro_v1_0_7=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_7
+axi_vdma_v6_3_21=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_21
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+qdriv_pl_v1_0_14=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_14
+axis_data_fifo_v2_0_15=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_15
+audio_tpg_v1_0_2=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_2
+noc_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_sim_v1_0_0
+axi_i3c_v1_0_2=$RDI_DATADIR/xsim/ip/axi_i3c_v1_0_2
+axi_sg_v4_1_19=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_19
+mipi_csi2_rx_ctrl_v1_0_11=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_11
+hdmi_acr_ctrl_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_3
+xxv_ethernet_v4_1_13=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_13
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+ernic_v4_2_0=$RDI_DATADIR/xsim/ip/ernic_v4_2_0
+rama_v1_1_19_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_19_lib
+rfdace5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfdace5_wrapper_v1_0_0
+tsn_temac_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_12
+tri_mode_ethernet_mac_v9_0_35=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_35
+axi_jtag_v1_0_2=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_2
+ieee802d3_200g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_12
+fast_adapter_v1_0_10=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_10
+hdmi_gt_controller_v2_0_0=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v2_0_0
+xdfe_ofdm_v2_2_0=$RDI_DATADIR/xsim/ip/xdfe_ofdm_v2_2_0
+ptp_1588_timer_syncer_v2_0_6=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_6
+vfb_v1_0_27=$RDI_DATADIR/xsim/ip/vfb_v1_0_27
+blk_mem_gen_v8_3_7=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_7
+vcu2_v1_0_0=$RDI_DATADIR/xsim/ip/vcu2_v1_0_0
+shell_utils_addr_remap_v1_0_12=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_12
+oddr_v1_0_4=$RDI_DATADIR/xsim/ip/oddr_v1_0_4
+sim_trig_v1_0_13=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_13
+v_hdmi_phy1_v1_0_13=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_13
+displayport_v7_0_25=$RDI_DATADIR/xsim/ip/displayport_v7_0_25
+cordic_v6_0_23=$RDI_DATADIR/xsim/ip/cordic_v6_0_23
+axi_crossbar_v2_1_34=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_34
+proc_sys_reset_v5_0_16=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_16
+polar_v1_1_5=$RDI_DATADIR/xsim/ip/polar_v1_1_5
+xscl=$RDI_DATADIR/xsim/ip/xscl
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+v_scenechange_v1_1_6=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_6
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+ldpc_v2_0_16=$RDI_DATADIR/xsim/ip/ldpc_v2_0_16
+switch_core_top_v1_0_17=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_17
+v_frmbuf_wr_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_5_3
+bs_switch_v1_0_4=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_4
+audio_clock_recovery_unit_v1_0_5=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_5
+xdfe_resampler_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_10
+sd_fec_v1_1_15=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_15
+fifo_generator_v13_2_11=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_11
+axi_timebase_wdt_v3_0_25=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_25
+psx_vip_v1_0_6=$RDI_DATADIR/xsim/ip/psx_vip_v1_0_6
+axi_memory_init_v1_0_14=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_14
+emc_common_v3_0_8=$RDI_DATADIR/xsim/ip/emc_common_v3_0_8
+ieee802d3_rs_fec_v2_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_24
+axi_bram_ctrl_v4_0_15=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_15
+v_vcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_13
+v_csc_v1_1_13=$RDI_DATADIR/xsim/ip/v_csc_v1_1_13
+axi_lmb_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_3
+zynq_ultra_ps_e_vip_v1_0_19=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_19
+axi_cdma_v4_1_33=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_33
+v_dp_axi4s_vid_out_v1_0_9=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_9
+i2s_receiver_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_9
+rld3_pl_v1_0_15=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_15
+axi_firewall_v1_2_8=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_8
+axis_ila_ct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_1
+cpm5n_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_9
+hdcp22_cipher_dp_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_2
+lut_buffer_v2_0_1=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_1
+axis_switch_v1_1_33=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_33
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+mipi_dphy_v4_3_13=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_13
+msm_adapters=$RDI_DATADIR/xsim/ip/msm_adapters
+msm_cpp=$RDI_DATADIR/xsim/ip/msm_cpp
+iomodule_v3_1_11=$RDI_DATADIR/xsim/ip/iomodule_v3_1_11
+fc32_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_28
+mammoth_transcode_v1_0_2=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_2
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+axi_hwicap_v3_0_37=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_37
+g709_rs_decoder_v2_2_15=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_15
+axi_stream_monitor_v1_1_1=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_1
+axis_itct_v1_0_1=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_1
+tmr_voter_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_7
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+mdm_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/mdm_riscv_v1_0_3
+axis_mem_v1_0_2=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_2
+amm_axi_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_19
+videoaxi4s_bridge_v1_0_7=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_7
+axis_accelerator_adapter_v2_1_19=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_19
+axi_master_burst_v2_0_9=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_9
+vrf_channelizer_v1_0_0=$RDI_DATADIR/xsim/ip/vrf_channelizer_v1_0_0
+uhdsdi_gt_v2_1_5=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_5
+v_deinterlacer_v5_1_6=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_6
+noc_hbm_v1_0_1=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_1
+in_system_ibert_v1_0_23=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_23
+axi_pcie_v2_9_12=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_12
+axi_epu_v1_0_6=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_6
+floating_point_v7_0_24=$RDI_DATADIR/xsim/ip/floating_point_v7_0_24
+v_axi4s_vid_out_v4_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_19
+v_multi_scaler_v1_2_7=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_7
+axis_dbg_sync_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_1
+can_v5_1_5=$RDI_DATADIR/xsim/ip/can_v5_1_5
+axis_cap_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_1
+xdfe_cc_filter_v1_1_5=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_5
+anlt_subcore_ip_v1_0_2=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_2
+v_smpte_uhdsdi_tx_v1_0_5=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_5
+xlslice_v1_0_4=$RDI_DATADIR/xsim/ip/xlslice_v1_0_4
+noc2_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_sim_v1_0_0
+tmr_sem_v1_0_27=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_27
+axi_ahblite_bridge_v3_0_30=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_30
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+hdcp_keymngmt_blk_v1_0_2=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_2
+util_idelay_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_4
+axi_uart16550_v2_0_35=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_35
+ecc_v2_0_17=$RDI_DATADIR/xsim/ip/ecc_v2_0_17
+v_frmbuf_rd_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_12
+axi_data_fifo_v2_1_32=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_32
+xdfe_equalizer_v1_0_10=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_10
+axi_mcdma_v1_2_0=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_2_0
+versal_cips_ps_vip_v1_0_11=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_11
+emb_mem_gen_v1_0_10=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_10
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+displayport_v8_1_10=$RDI_DATADIR/xsim/ip/displayport_v8_1_10
+tcc_encoder_3gpp_v5_0_23=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_23
+pcie_qdma_mailbox_v1_0_8=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_8
+v_frmbuf_rd_v2_5_3=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_5_3
+util_vector_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_4
+axis_dwidth_converter_v1_1_32=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_32
+axi4svideo_bridge_v1_0_19=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_19
+util_ff_v1_0_4=$RDI_DATADIR/xsim/ip/util_ff_v1_0_4
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+microblaze_riscv_v1_0_3=$RDI_DATADIR/xsim/ip/microblaze_riscv_v1_0_3
+cpri_v8_11_22=$RDI_DATADIR/xsim/ip/cpri_v8_11_22
+v_vid_in_axi4s_v5_0_5=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_5
+dprx_v1_0_5=$RDI_DATADIR/xsim/ip/dprx_v1_0_5
+shell_utils_build_info_v2_0_0=$RDI_DATADIR/xsim/ip/shell_utils_build_info_v2_0_0
+util_reduced_logic_v2_0_6=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_6
+axi_pcie3_v3_0_32=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_32
+v_smpte_uhdsdi_rx_v1_0_4=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_4
+axi_datamover_v5_1_35=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_35
+interlaken_v2_4_19=$RDI_DATADIR/xsim/ip/interlaken_v2_4_19
+nvmeha_v1_0_14=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_14
+av_pat_gen_v2_0_2=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_2
+bfr_ft_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/bfr_ft_wrapper_v1_0_0
+axis_mu_v1_0_1=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_1
+zynq_ultra_ps_e_v3_3_14=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_14
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+v_hdmi_rx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_5
+ethernet_1_10_25g_v2_7_18=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_18
+v_tpg_v8_2_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_6
+qdma_v5_0_12=$RDI_DATADIR/xsim/ip/qdma_v5_0_12
+pci64_v5_0_12=$RDI_DATADIR/xsim/ip/pci64_v5_0_12
+v_uhdsdi_vidgen_v1_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_3
+jesd204c_v4_3_0=$RDI_DATADIR/xsim/ip/jesd204c_v4_3_0
+axi_timer_v2_0_35=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_35
+c_compare_v12_0_10=$RDI_DATADIR/xsim/ip/c_compare_v12_0_10
+axi_clock_converter_v2_1_32=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_32
+axi_protocol_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_33
+axi_dma_v7_1_34=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_34
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+dfx_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_11
+axi_sideband_util_v1_0_17=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_17
+tmr_manager_v1_0_13=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_13
+fec_5g_common_v1_1_5=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_5
+axi_ethernetlite_v3_0_32=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_32
+lib_bmg_v1_0_18=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_18
+high_speed_selectio_wiz_v3_6_10=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_10
+c_shift_ram_v12_0_18=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_18
+axi_pmon_v1_0_2=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_2
+v_vid_in_axi4s_v4_0_11=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_11
+uhdsdi_gt_v2_2_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_2_0
+v_tpg_v8_1_12=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_12
+noc2_nsu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_sim_v1_0_0
+axi_gpio_v2_0_35=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_35
+axis_interconnect_v1_1_24=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_24
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+c_addsub_v12_0_19=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_19
+sem_ultra_v3_1_27=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_27
+v_dual_splitter_v1_0_11=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_11
+v_warp_init_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_5
+mipi_csi2_tx_ctrl_v1_0_6=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_6
+roe_framer_v3_0_9=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_9
+axi_remapper_tx_v1_0_3=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_3
+axi_traffic_gen_v3_0_19=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_19
+dfx_controller_v1_0_8=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_8
+pr_decoupler_v1_0_11=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_11
+tmr_comparator_v1_0_8=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_8
+rfadce5_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/rfadce5_wrapper_v1_0_0
+axi_mmu_v2_1_31=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_31
+axi_dwidth_converter_v2_1_33=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_33
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+axis_ila_adv_trig_v1_0_1=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_1
+picxo_fracxo_v2_0_3=$RDI_DATADIR/xsim/ip/picxo_fracxo_v2_0_3
+dp_videoaxi4s_bridge_v1_0_3=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_3
+v_frmbuf_wr_v2_2_12=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_12
+sd_fec_beta_v1_0_0=$RDI_DATADIR/xsim/ip/sd_fec_beta_v1_0_0
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+lmb_bram_if_cntlr_v4_0_25=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_25
+mrmac_v3_0_0=$RDI_DATADIR/xsim/ip/mrmac_v3_0_0
+tsn_endpoint_ethernet_mac_block_v1_0_18=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_18
+axis_vio_v1_0_12=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_12
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+bscan_jtag=$RDI_DATADIR/xsim/ip/bscan_jtag
+floating_point_v7_1_19=$RDI_DATADIR/xsim/ip/floating_point_v7_1_19
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+pc_cfr_v8_0_3=$RDI_DATADIR/xsim/ip/pc_cfr_v8_0_3
+axi_amm_bridge_v1_0_23=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_23
+c_counter_binary_v12_0_20=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_20
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+axi_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_19
+xlconcat_v2_1_6=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_6
+axi_msg_v1_0_12=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_12
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+xpm=$RDI_DATADIR/xsim/ip/xpm
+bsip_v1_1_1=$RDI_DATADIR/xsim/ip/bsip_v1_1_1
+interrupt_control_v3_1_5=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_5
+gtwizard_ultrascale_v1_7_19=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_19
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+rld3_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_2
+mipi_rx_phy_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_rx_phy_v1_0_1
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+dds_compiler_v6_0_26=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_26
+xdma_v4_1_31=$RDI_DATADIR/xsim/ip/xdma_v4_1_31
+axi_fifo_mm_s_v4_3_5=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_3_5
+l_ethernet_v3_3_13=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_13
+xdfe_nlf_v1_1_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_1_2
+axi_mcdma_v1_1_14=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_14
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+ltlib_v1_0_2=$RDI_DATADIR/xsim/ip/ltlib_v1_0_2
+xdfe_common_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_4
+axi_intc_v4_1_20=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_20
+axi_uartlite_v2_0_37=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_37
+gmii_to_rgmii_v4_1_17=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_17
+cdcam_v1_2_0=$RDI_DATADIR/xsim/ip/cdcam_v1_2_0
+blk_mem_gen_v8_4_9=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_9
+system_cache_v5_0_12=$RDI_DATADIR/xsim/ip/system_cache_v5_0_12
+cmac_usplus_v3_1_19=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_19
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+axi_interconnect_v1_7_24=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_24
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+uram_rd_back_v1_0_4=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_4
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+sem_v4_1_15=$RDI_DATADIR/xsim/ip/sem_v4_1_15
+v_hdmi_tx_v3_0_5=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_5
+dft_v4_2_9=$RDI_DATADIR/xsim/ip/dft_v4_2_9
+ieee802d3_400g_rs_fec_v3_0_3=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v3_0_3
+srio_gen2_v4_1_20=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_20
+mipi_tx_phy_v1_0_0=$RDI_DATADIR/xsim/ip/mipi_tx_phy_v1_0_0
+axi_epc_v2_0_36=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_36
+i2s_transmitter_v1_0_9=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_9
+flexo_100g_rs_fec_v1_0_30=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_30
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axis_infrastructure_v1_1_1=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_1
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+axi_emc_v3_0_33=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_33
+multi_channel_25g_rs_fec_v1_0_28=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_28
+axi_protocol_checker_v2_0_19=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_19
+axi_register_slice_v2_1_33=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_33
+v_letterbox_v1_1_13=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_13
+gtwizard_ultrascale_v1_6_17=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_17
+dprx_fec_8b10b_v1_0_3=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_3
+axis_broadcaster_v1_1_32=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_32
+axis_clock_converter_v1_1_34=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_34
+ahblite_axi_bridge_v3_0_28=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_28
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+sid_v8_0_22=$RDI_DATADIR/xsim/ip/sid_v8_0_22
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+v_vid_gt_bridge_v2_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_5
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+axis_ila_pp_v1_0_2=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_2
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+ten_gig_eth_pcs_pma_v6_0_28=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_28
+axis_register_slice_v1_1_33=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_33
+clk_vip_v1_0_5=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_5
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+v_vid_sdi_tx_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_3
+processing_system7_vip_v1_0_21=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_21
+microblaze_v9_5_5=$RDI_DATADIR/xsim/ip/microblaze_v9_5_5
+cmac_v2_6_17=$RDI_DATADIR/xsim/ip/cmac_v2_6_17
+pcie_jtag_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_1
+mem_pl_v1_0_2=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_2
+mpram_v1_0_5=$RDI_DATADIR/xsim/ip/mpram_v1_0_5
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+v_hscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_13
+ddr4_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_2
+axis_protocol_checker_v2_0_17=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_17
+xbip_multadd_v3_0_21=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_21
+axi_remapper_rx_v1_0_2=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_2
+axi_vfifo_ctrl_v2_0_36=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_36
+v_warp_filter_v1_1_5=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_5
+xfft_v9_1_13=$RDI_DATADIR/xsim/ip/xfft_v9_1_13
+axi_bram_ctrl_v4_1_11=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_11
+v_hcresampler_v1_1_13=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_13
+v_demosaic_v1_1_13=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_13
+lte_fft_v2_1_11=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_11
+xsdbs_v1_0_4=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_4
+mrmac_v2_3_2=$RDI_DATADIR/xsim/ip/mrmac_v2_3_2
+v_tc_v6_2_9=$RDI_DATADIR/xsim/ip/v_tc_v6_2_9
+div_gen_v5_1_23=$RDI_DATADIR/xsim/ip/div_gen_v5_1_23
+rs_encoder_v9_0_22=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_22
+axi_utils_v2_0_10=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_10
+v_axi4s_remap_v1_1_12=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_12
+v_mix_v5_2_11=$RDI_DATADIR/xsim/ip/v_mix_v5_2_11
+xdfe_fft_v1_0_8=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_8
+cic_compiler_v4_0_20=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_20
+sim_clk_gen_v1_0_5=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_5
+qdriv_pl_phy_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_2
+lib_srl_fifo_v1_0_4=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_4
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+hdcp22_cipher_v1_0_5=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_5
+usxgmii_v1_2_20=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_20
+v_smpte_sdi_v3_0_12=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_12
+mipi_dsi2_rx_ctrl_v1_0_1=$RDI_DATADIR/xsim/ip/mipi_dsi2_rx_ctrl_v1_0_1
+mdm_v3_2_27=$RDI_DATADIR/xsim/ip/mdm_v3_2_27
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+g975_efec_i7_v2_0_24=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_24
+axis_combiner_v1_1_31=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_31
+xpm_cdc_gen_v1_0_4=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_4
+dcmac_v2_5_0=$RDI_DATADIR/xsim/ip/dcmac_v2_5_0
+convolution_v9_0_21=$RDI_DATADIR/xsim/ip/convolution_v9_0_21
+microblaze_v11_0_14=$RDI_DATADIR/xsim/ip/microblaze_v11_0_14
+cpm4_v1_0_17=$RDI_DATADIR/xsim/ip/cpm4_v1_0_17
+cmpy_v6_0_25=$RDI_DATADIR/xsim/ip/cmpy_v6_0_25
+xlconstant_v1_1_9=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_9
+noc_mc_ddr5_phy_v1_0_1=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_1
+spdif_v2_0_30=$RDI_DATADIR/xsim/ip/spdif_v2_0_30
+oran_radio_if_v3_2_1=$RDI_DATADIR/xsim/ip/oran_radio_if_v3_2_1
+v_hdmi_rx1_v1_0_11=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_11
+cam_v3_1_0=$RDI_DATADIR/xsim/ip/cam_v3_1_0
+emb_fifo_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_6
+axi_iic_v2_1_9=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_9
+axi_perf_mon_v5_0_35=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_35
+v_tpg_v8_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_16
+mutex_v2_1_14=$RDI_DATADIR/xsim/ip/mutex_v2_1_14
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+lib_fifo_v1_0_20=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_20
+advanced_io_wizard_v1_0_15=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_15
+c_reg_fd_v12_0_10=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_10
+axi4stream_vip_v1_1_19=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_19
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+lmb_v10_v3_0_14=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_14
+ieee802d3_50g_rs_fec_v1_0_25=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_25
+icap_arb_v1_0_2=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_2
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+vid_edid_v1_0_3=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_3
+shell_utils_msp432_bsl_crc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_2
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+mult_gen_v12_0_22=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_22
+timer_sync_1588_v1_2_5=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_5
+dfe_channelizer_wrapper_v1_0_0=$RDI_DATADIR/xsim/ip/dfe_channelizer_wrapper_v1_0_0
+clk_gen_sim_v1_0_4=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_4
+hsdp_trace_v2_0_2=$RDI_DATADIR/xsim/ip/hsdp_trace_v2_0_2
+noc_sc_v1_0_0_legacy=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0_legacy
+v_frmbuf_wr_v3_0_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v3_0_0
+xdfe_cc_mixer_v2_0_5=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_5
+mipi_dsi_tx_ctrl_v1_0_10=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_10
+axi_apb_bridge_v3_0_20=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_20
+ieee802d3_clause74_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_19
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+axi_tft_v2_0_29=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_29
+viterbi_v9_1_18=$RDI_DATADIR/xsim/ip/viterbi_v9_1_18
+ieee802d3_50g_rs_fec_v2_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_18
+microblaze_mcs_v2_3_7=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_7
+fifo_generator_v13_0_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_7
+video_frame_crc_v1_0_6=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_6
+dist_mem_gen_v8_0_15=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_15
+ilknf_v1_3_5=$RDI_DATADIR/xsim/ip/ilknf_v1_3_5
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+axi_ethernet_buffer_v2_0_25=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_25
+g975_efec_i4_v1_0_23=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_23
+c_accum_v12_0_19=$RDI_DATADIR/xsim/ip/c_accum_v12_0_19
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+ieee802d3_25g_rs_fec_v1_0_31=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_31
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+noc_hbm_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_nmu_sim_v1_0_0
+xdfe_nr_prach_v2_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v2_0_4
+gig_ethernet_pcs_pma_v16_2_21=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_21
+trace_s2mm_v2_0_1=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_1
+v_sdi_rx_vid_bridge_v2_0_3=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_3
+fit_timer_v2_0_12=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_12
+ldpc_5gnr_v1_0_4=$RDI_DATADIR/xsim/ip/ldpc_5gnr_v1_0_4
+soft_ecc_proxy_v1_1_2=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_1_2
+axi_c2c_v1_0_11=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_11
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+hdcp22_rng_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_3
+v_smpte_uhdsdi_v1_0_12=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_12
+bs_mux_v1_0_1=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_1
+noc_nmu_sim_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_sim_v1_0_0
+fir_compiler_v7_2_23=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_23
+axi_hbicap_v1_0_8=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_8
+x5io_wizard_phy_v1_0_1=$RDI_DATADIR/xsim/ip/x5io_wizard_phy_v1_0_1
+canfd_v3_0_12=$RDI_DATADIR/xsim/ip/canfd_v3_0_12
+nvme_tc_v3_0_8=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_8
+axi_usb2_device_v5_0_34=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_34
+ldpc_5gnr_lite_v1_0_3=$RDI_DATADIR/xsim/ip/ldpc_5gnr_lite_v1_0_3
+tmr_inject_v1_0_7=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_7
+v_uhdsdi_audio_v2_0_9=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_9
+xsdbm_v3_0_3=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_3
+v_vscaler_v1_1_13=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_13
+vid_phy_controller_v2_2_19=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_19
+mem_tg_v1_0_15=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_15
+dfx_axi_shutdown_manager_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_4
+ibert_lib_v1_0_12=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_12
+ta_dma_v1_0_17=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_17
+cam_blk_lib_v1_2_0=$RDI_DATADIR/xsim/ip/cam_blk_lib_v1_2_0
+noc2_nps6x_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps6x_v1_0_0
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+tcc_decoder_3gppmm_v2_0_28=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_28
+noc_nps_v1_0_1=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_1
+ddr4_pl_v1_0_15=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_15
+advanced_io_wizard_phy_v1_0_4=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_4
+ft_prach_v1_2_3=$RDI_DATADIR/xsim/ip/ft_prach_v1_2_3
+lib_pkg_v1_0_4=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_4
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+x5io_wizard_v1_0_6=$RDI_DATADIR/xsim/ip/x5io_wizard_v1_0_6
+axis_subset_converter_v1_1_33=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_33
+axi_quad_spi_v3_2_32=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_32
+g709_rs_encoder_v2_2_13=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_13
+hdcp_v1_0_6=$RDI_DATADIR/xsim/ip/hdcp_v1_0_6
+v_frmbuf_rd_v2_4_4=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_4
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+quadsgmii_v3_5_21=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_21
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+rst_vip_v1_0_7=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_7
+ethernet_offload_v1_0_0=$RDI_DATADIR/xsim/ip/ethernet_offload_v1_0_0
+cpm5_v1_0_17=$RDI_DATADIR/xsim/ip/cpm5_v1_0_17
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+xbip_dsp48_wrapper_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_6
+vitis_deadlock_detector_v1_0_2=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_2
+axis_dbg_stub_v1_0_1=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_1
+displayport_v9_0_10=$RDI_DATADIR/xsim/ip/displayport_v9_0_10
+visp_v1_0_0=$RDI_DATADIR/xsim/ip/visp_v1_0_0
+bscan_axi_v1_0_2=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_2
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.log b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000..e69de29
diff --git a/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.pb b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000..b155e40
--- /dev/null
+++ b/tp_vivado/proj/ECG.sim/sim_1/behav/xsim/xvhdl.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/tp_vivado/proj/ECG.xpr b/tp_vivado/proj/ECG.xpr
new file mode 100644
index 0000000..6489ec6
--- /dev/null
+++ b/tp_vivado/proj/ECG.xpr
@@ -0,0 +1,302 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/Mouthieu.MB-TUF/Documents/cours-et-projets/imt/medcon/tp-ecg-etudiant-m23bossa/tp_vivado/proj/ECG.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="cab960dde7154154b2e2b77e2633c827"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.2"/>
+ <Option Name="SimulatorVersionModelSim" Val="2024.1"/>
+ <Option Name="SimulatorVersionQuesta" Val="2024.1"/>
+ <Option Name="SimulatorVersionXcelium" Val="24.03.003"/>
+ <Option Name="SimulatorVersionVCS" Val="V-2023.12-SP1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2024.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../repo"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="30"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="UseInlineHdlIP" Val="TRUE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audio_init.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/debounce.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/TWICtl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/controlUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/operativeUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/firUnit.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
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+ </File>
+ <File Path="$PPRDIR/../src/hdl/fir.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/i2s_ctl.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/audioProc.v">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/hdl/processingUnitIP.v">
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+ <Attr Name="UsedIn" Val="synthesis"/>
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+ </File>
+ <File Path="$PPRDIR/../src/hdl/tb_firUnit.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
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+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="audioProc"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/constraints/NexysVideo_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="tb_firUnit"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ <Option Name="CosimPdi" Val=""/>
+ <Option Name="CosimPlatform" Val=""/>
+ <Option Name="CosimElf" Val=""/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ <Simulator Name="ActiveHDL">
+ <Option Name="Description" Val="Active-HDL Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Higher performance designs, resource sharing is turned off, the global fanout guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with a larger threshold" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Flow_PerfOptimized_High" Flow="Vivado Synthesis 2014"/>
+ <Step Id="synth_design">
+ <Option Id="FsmExtraction">1</Option>
+ <Option Id="KeepEquivalentRegisters">1</Option>
+ <Option Id="NoCombineLuts">1</Option>
+ <Option Id="RepFanoutThreshold">400</Option>
+ <Option Id="ResourceSharing">2</Option>
+ <Option Id="ShregMinSize">5</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream">
+ <Option Id="BinFile">1</Option>
+ </Step>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/tp_vivado/proj/cleanup.cmd b/tp_vivado/proj/cleanup.cmd
new file mode 100644
index 0000000..ab966b0
--- /dev/null
+++ b/tp_vivado/proj/cleanup.cmd
@@ -0,0 +1,21 @@
+@echo off
+rem delete all files from subfolders
+for /d /r %%i in (*) do del /f /q %%i\*
+rem delete all subfolders
+for /d %%i in (*) do rd /S /Q %%i
+
+rem unmark read only from all files
+attrib -R .\* /S
+
+rem mark read only those we wish to keep
+attrib +R .\create_project.tcl
+attrib +R .\cleanup.sh
+attrib +R .\cleanup.cmd
+attrib +R .\.gitignore
+attrib +R .\_READ_ME_.txt
+
+rem delete all non read-only
+del /Q /A:-R .\*
+
+rem unmark read-only
+attrib -R .\*
diff --git a/tp_vivado/proj/cleanup.sh b/tp_vivado/proj/cleanup.sh
new file mode 100644
index 0000000..ea903c2
--- /dev/null
+++ b/tp_vivado/proj/cleanup.sh
@@ -0,0 +1,15 @@
+# This script is useful for cleaning up the 'project'
+# directory of a Digilent Vivado-project git repository
+###
+# Run the following command to change permissions of
+# this 'cleanup' file if needed:
+# chmod u+x cleanup.sh
+###
+# Remove directories/subdirectories
+find . -mindepth 1 -type d -exec rm -rf {} +
+# Remove any other files than:
+find . -type f ! -name 'cleanup.sh' \
+ ! -name 'cleanup.cmd' \
+ ! -name 'create_project.tcl' \
+ ! -name '.gitignore' \
+ -exec rm -rf {} +
diff --git a/tp_vivado/proj/create_project.tcl b/tp_vivado/proj/create_project.tcl
new file mode 100644
index 0000000..b5ecfce
--- /dev/null
+++ b/tp_vivado/proj/create_project.tcl
@@ -0,0 +1,111 @@
+# Run this script to create the Vivado project files in the WORKING DIRECTORY
+# If ::create_path global variable is set, the project is created under that path instead of the working dir
+
+if {[info exists ::create_path]} {
+ set dest_dir $::create_path
+} else {
+ set dest_dir [pwd]
+}
+puts "INFO: Creating new project in $dest_dir"
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set proj_name "ECG"
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir ".."
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/proj"]"
+
+set src_dir $origin_dir/src
+set repo_dir $origin_dir/repo
+
+# Set the board part number
+set part_num "xc7a200tsbg484-1"
+
+# Create project
+create_project $proj_name $dest_dir
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [get_projects $proj_name]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "part" "$part_num" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+ create_fileset -srcset sources_1
+}
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+ create_fileset -constrset constrs_1
+}
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
+
+# Add conventional sources
+add_files -quiet $src_dir/hdl
+
+# Add IPs
+add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
+
+# Add constraints
+add_files -fileset constrs_1 -quiet $src_dir/constraints
+
+# Refresh IP Repositories
+#update_ip_catalog
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+ create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
+} else {
+ set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
+ set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property "part" "$part_num" $obj
+set_property "steps.synth_design.args.fanout_limit" "400" $obj
+set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
+set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
+set_property "steps.synth_design.args.resource_sharing" "off" $obj
+set_property "steps.synth_design.args.no_lc" "1" $obj
+set_property "steps.synth_design.args.shreg_min_size" "5" $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+ create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+} else {
+ set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+ set_property flow "Vivado Implementation 2014" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property "part" "$part_num" $obj
+set_property "steps.write_bitstream.args.bin_file" "1" $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+#puts "INFO: Project created:$proj_name"
+
+# Comment the following section, if there is no block design
+# Create block design
+#source $origin_dir/src/bd/bt_gpio.tcl
+
+# Generate the wrapper
+#set design_name [get_bd_designs]
+#make_wrapper -files [get_files $design_name.bd] -top -import
+
+#set obj [get_filesets sources_1]
+#set_property "top" "bt_gpio_top" $obj
+
+#puts "INFO: Block design created: $design_name.bd"
diff --git a/tp_vivado/src/constraints/NexysVideo_Master.xdc b/tp_vivado/src/constraints/NexysVideo_Master.xdc
new file mode 100644
index 0000000..b256a38
--- /dev/null
+++ b/tp_vivado/src/constraints/NexysVideo_Master.xdc
@@ -0,0 +1,365 @@
+### This file is a general .xdc for the Nexys Video Rev. A
+### To use it in a project:
+### - uncomment the lines corresponding to used pins
+### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+
+##Clock Signal
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
+
+
+##LEDs
+#set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports {LED[0]}]
+#set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports {LED[1]}]
+#set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports {LED[2]}]
+set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports { led3 }];#[get_ports {LED[3]}]
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports { led4 }];#[get_ports {LED[4]}]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports { led5 }];#[get_ports {LED[5]}]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports { led6 }];#[get_ports {LED[6]}]
+set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports { led7 }];#[get_ports {LED[7]}]
+
+
+## Buttons
+set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports BTNC]
+set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports BTND]
+set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports BTNL]
+set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports BTNR]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports BTNU]
+set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports rstn]
+
+
+##Switches
+set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports sw]
+#set_property -dict { PACKAGE_PIN F21 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN G21 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
+set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports { sw3 }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports { sw4 }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports { sw5 }]; #IO_0_15 Sch=sw[5]
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { sw6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { sw7 }]; #IO_25_15 Sch=sw[7]
+
+
+##OLED Display
+#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { oled_dc }]; #IO_L7N_T1_D10_14 Sch=oled_dc
+#set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { oled_res }]; #IO_L4N_T0_D05_14 Sch=oled_res
+#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { oled_sclk }]; #IO_L7P_T1_D09_14 Sch=oled_sclk
+#set_property -dict { PACKAGE_PIN Y22 IOSTANDARD LVCMOS33 } [get_ports { oled_sdin }]; #IO_L9N_T1_DQS_D13_14 Sch=oled_sdin
+#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_0_14 Sch=oled_vbat
+#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { oled_vdd }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=oled_vdd
+
+
+##HDMI in
+#set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
+#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
+#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
+#set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
+#set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
+#set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
+#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
+#set_property -dict { PACKAGE_PIN AA3 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
+#set_property -dict { PACKAGE_PIN Y3 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
+#set_property -dict { PACKAGE_PIN Y2 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
+#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
+#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
+#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
+
+
+##HDMI out
+#set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
+#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
+#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
+#set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
+#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
+#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
+#set_property -dict { PACKAGE_PIN Y1 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
+#set_property -dict { PACKAGE_PIN W1 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
+#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
+#set_property -dict { PACKAGE_PIN AA1 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
+#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
+#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
+
+
+##Display Port
+#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVDS } [get_ports { dp_tx_aux_n }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
+#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVDS } [get_ports { dp_tx_aux_n }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
+#set_property -dict { PACKAGE_PIN AA9 IOSTANDARD LVDS } [get_ports { dp_tx_aux_p }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
+#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVDS } [get_ports { dp_tx_aux_p }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
+#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { dp_tx_hpd }]; #IO_25_14 Sch=dp_tx_hpd
+
+
+##Audio Codec
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ac_adc_sdata]
+set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ac_bclk]
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ac_dac_sdata]
+set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ac_lrclk]
+set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ac_mclk]
+
+
+##Pmod header JA
+#set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports JA1]
+#set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { JA2 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { JA3 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { JA4 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { JA5 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { JA6 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
+
+
+##Pmod header JB
+#set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports LED17_B]
+#set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports LED17_G]
+#set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports LED16_R]
+#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L19P_T3_34 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L24N_T3_34 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L24P_T3_34 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L23N_T3_34 Sch=jb_n[4]
+#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L23P_T3_34 Sch=jb_p[4]
+
+
+##Pmod header JC
+#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18N_T2_34 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18P_T2_34 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22P_T3_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L17N_T2_34 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L17P_T2_34 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L20N_T3_34 Sch=jc_n[4]
+#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_34 Sch=jc_p[4]
+
+
+##XADC Header
+#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
+
+
+##UART
+#set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
+#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
+
+
+##Ethernet
+#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
+#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
+#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_25_34 Sch=eth_rst_b
+#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
+#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
+#set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN AB11 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
+#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
+#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
+
+
+##Fan PWM
+#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
+
+
+##DPTI/DSPI
+#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
+#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { prog_d[0]}]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
+#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
+#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[3]}]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
+#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
+#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
+#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
+#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
+#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
+#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
+#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
+#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { prog_siwun }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=prog_siwun
+#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { prog_spien }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=prog_spien
+#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { prog_txen }]; #IO_L13N_T2_MRCC_14 Sch=prog_txen
+#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { prog_wrn }]; #IO_L5N_T0_D07_14 Sch=prog_wrn
+
+
+##HID port
+#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data
+
+
+##QSPI
+#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports scl]
+set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports sda]
+
+##SD card
+#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cclk }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
+#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
+#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
+#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
+#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
+#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
+
+
+
+
+##Voltage Adjust
+#set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
+#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]
+#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
+
+
+##DDR3
+#set_property -dict {PACKAGE_PIN M2} [get_ports {ddr3_addr[0]}]
+#set_property -dict {PACKAGE_PIN M5} [get_ports {ddr3_addr[1]}]
+#set_property -dict {PACKAGE_PIN M3} [get_ports {ddr3_addr[2]}]
+#set_property -dict {PACKAGE_PIN M1} [get_ports {ddr3_addr[3]}]
+#set_property -dict {PACKAGE_PIN L6} [get_ports {ddr3_addr[4]}]
+#set_property -dict {PACKAGE_PIN P1} [get_ports {ddr3_addr[5]}]
+#set_property -dict {PACKAGE_PIN N3} [get_ports {ddr3_addr[6]}]
+#set_property -dict {PACKAGE_PIN N2} [get_ports {ddr3_addr[7]}]
+#set_property -dict {PACKAGE_PIN M6} [get_ports {ddr3_addr[8]}]
+#set_property -dict {PACKAGE_PIN R1} [get_ports {ddr3_addr[9]}]
+#set_property -dict {PACKAGE_PIN L5} [get_ports {ddr3_addr[10]}]
+#set_property -dict {PACKAGE_PIN N5} [get_ports {ddr3_addr[11]}]
+#set_property -dict {PACKAGE_PIN N4} [get_ports {ddr3_addr[12]}]
+#set_property -dict {PACKAGE_PIN P2} [get_ports {ddr3_addr[13]}]
+#set_property -dict {PACKAGE_PIN P6} [get_ports {ddr3_addr[14]}]
+#set_property -dict {PACKAGE_PIN L3} [get_ports {ddr3_ba[0]}]
+#set_property -dict {PACKAGE_PIN K6} [get_ports {ddr3_ba[1]}]
+#set_property -dict {PACKAGE_PIN L4} [get_ports {ddr3_ba[2]}]
+#set_property -dict {PACKAGE_PIN K3} [get_ports ddr3_cas_n]
+#set_property -dict {PACKAGE_PIN J6} [get_ports ddr3_cke]
+#set_property -dict {PACKAGE_PIN P4} [get_ports ddr3_ck_n]
+#set_property -dict {PACKAGE_PIN P5} [get_ports ddr3_ck_p]
+#set_property -dict {PACKAGE_PIN G3} [get_ports {ddr3_dm[0]}]
+#set_property -dict {PACKAGE_PIN F1} [get_ports {ddr3_dm[1]}]
+#set_property -dict {PACKAGE_PIN G2} [get_ports {ddr3_dq[0]}]
+#set_property -dict {PACKAGE_PIN H4} [get_ports {ddr3_dq[1]}]
+#set_property -dict {PACKAGE_PIN H5} [get_ports {ddr3_dq[2]}]
+#set_property -dict {PACKAGE_PIN J1} [get_ports {ddr3_dq[3]}]
+#set_property -dict {PACKAGE_PIN K1} [get_ports {ddr3_dq[4]}]
+#set_property -dict {PACKAGE_PIN H3} [get_ports {ddr3_dq[5]}]
+#set_property -dict {PACKAGE_PIN H2} [get_ports {ddr3_dq[6]}]
+#set_property -dict {PACKAGE_PIN J5} [get_ports {ddr3_dq[7]}]
+#set_property -dict {PACKAGE_PIN E3} [get_ports {ddr3_dq[8]}]
+#set_property -dict {PACKAGE_PIN B2} [get_ports {ddr3_dq[9]}]
+#set_property -dict {PACKAGE_PIN F3} [get_ports {ddr3_dq[10]}]
+#set_property -dict {PACKAGE_PIN D2} [get_ports {ddr3_dq[11]}]
+#set_property -dict {PACKAGE_PIN C2} [get_ports {ddr3_dq[12]}]
+#set_property -dict {PACKAGE_PIN A1} [get_ports {ddr3_dq[13]}]
+#set_property -dict {PACKAGE_PIN E2} [get_ports {ddr3_dq[14]}]
+#set_property -dict {PACKAGE_PIN B1} [get_ports {ddr3_dq[15]}]
+#set_property -dict {PACKAGE_PIN J2} [get_ports {ddr3_dqs_n[0]}]
+#set_property -dict {PACKAGE_PIN K2} [get_ports {ddr3_dqs_p[0]}]
+#set_property -dict {PACKAGE_PIN D1} [get_ports {ddr3_dqs_n[1]}]
+#set_property -dict {PACKAGE_PIN E1} [get_ports {ddr3_dqs_p[1]}]
+#set_property -dict {PACKAGE_PIN K4} [get_ports ddr3_odt]
+#set_property -dict {PACKAGE_PIN J4} [get_ports ddr3_ras_n]
+#set_property -dict { PACKAGE_PIN G1 } [get_ports { ddr3_reset_n }]; #IO_L5P_T0_AD13P_35 Sch=ddr3_reset
+#set_property -dict {PACKAGE_PIN L1} [get_ports ddr3_we_n]
+
+
+##FMC
+#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
+#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
+#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk1_m2c_n }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
+#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { fmc_clk1_m2c_p }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
+#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
+#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la01_cc_n }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
+#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la01_cc_p }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
+#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
+#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
+#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
+#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
+#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
+#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
+#set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
+#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
+#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
+#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
+#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
+#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
+#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
+#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
+#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
+#set_property -dict { PACKAGE_PIN K22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
+#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
+#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
+#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
+#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
+#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
+#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
+#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
+#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
+#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
+#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la17_cc_n }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
+#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la17_cc_p }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
+#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la18_cc_n }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
+#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la18_cc_p }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
+#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
+#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
+#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
+#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
+#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
+#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
+#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
+#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
+#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
+#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
+#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
+#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
+#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
+#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
+#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
+#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
+#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
+#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
+#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
+#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
+#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
+#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
+#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
+#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
+#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
+#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_n[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
+#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { fmc_la_p[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
+
+#set_property -dict { PACKAGE_PIN D15 } [get_ports { vrefa_m2c }]; #IO_L6N_T0_VREF_16 Sch=vrefa_m2c
+#set_property -dict { PACKAGE_PIN K14 } [get_ports { vrefa_m2c }]; #IO_L19N_T3_A21_VREF_15 Sch=vrefa_m2c
+#set_property -dict { PACKAGE_PIN H18 } [get_ports { vrefa_m2c }]; #IO_L6N_T0_VREF_15 Sch=vrefa_m2c
+#set_property -dict { PACKAGE_PIN C20 } [get_ports { vrefa_m2c }]; #IO_L19N_T3_VREF_16 Sch=vrefa_m2c
+
+#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { prsnt_m2c }]; #IO_L22N_T3_A04_D20_14 Sch=prsnt_m2c
+
+
+##???????????
+##set_property PACKAGE_PIN D16 [get_ports {netic20_d16}]; #IO_L5N_T0_16
+##set_property PACKAGE_PIN D20 [get_ports {netic20_d20}]; #IO_L19P_T3_16
+##set_property PACKAGE_PIN E16 [get_ports {netic20_e16}]; #IO_L5P_T0_16
+##set_property PACKAGE_PIN F4 [get_ports {netic20_f4}]; #IO_0_35
+##set_property PACKAGE_PIN T3 [get_ports {netic20_t3}]; #IO_0_34
+##set_property PACKAGE_PIN Y17 [get_ports {netic20_y17}]; #IO_0_13
+
+#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { pic_ss_b }]; #IO_L3N_T0_DQS_34 Sch=pic_ss_b
diff --git a/tp_vivado/src/hdl/TWICtl.vhd b/tp_vivado/src/hdl/TWICtl.vhd
new file mode 100644
index 0000000..e0dad08
--- /dev/null
+++ b/tp_vivado/src/hdl/TWICtl.vhd
@@ -0,0 +1,571 @@
+----------------------------------------------------------------------------------
+-- Company: Digilent Ro
+-- Engineer: Elod Gyorgy
+--
+-- Create Date: 14:55:31 04/07/2011
+-- Design Name:
+-- Module Name: TWIUtils - Package
+-- Project Name: TWI Master Controller Reference Design
+-- Target Devices:
+-- Tool versions:
+-- Description: This package provides enumeration types for TWI (Two-Wire
+-- Interface) bus status and error conditions.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+package TWIUtils is
+ type busState_type is (busUnknown, busBusy, busFree);
+ type error_type is (errArb, errNAck);
+end TWIUtils;
+
+package body TWIUtils is
+end TWIUtils;
+
+----------------------------------------------------------------------------------
+-- Company: Digilent Ro
+-- Engineer: Elod Gyorgy
+--
+-- Create Date: 14:55:31 04/07/2011
+-- Design Name:
+-- Module Name: TWICtl - Behavioral
+-- Project Name: TWI Master Controller Reference Design
+-- Target Devices:
+-- Tool versions:
+-- Description: TWICtl is a reusabled Master Controller implementation of the
+-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
+-- FAST mode should also be theoretically possible, although it has not been
+-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
+-- buses. Slave-wait is also supported.
+--
+--
+-- Dependencies: digilent.TWIUtils package - TWICtl.vhd
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.math_real.all;
+
+library digilent;
+--use digilent.TWIUtils.ALL;
+
+entity TWICtl is
+----------------------------------------------------------------------------------
+-- Title : Mode of operation
+-- Description: The controller can be instructed to initiate/continue/stop a
+-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
+-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
+-- signals are synchronous to CLK and input signals must also be synchronous to
+-- CLK. Signals are active-high.
+-- Fast-track instructions (single byte transfer):
+-- -put the TWI address on A_I
+-- -if data is written put it on D_I
+-- -assert STB_I
+-- -when DONE_O pulse arrives, read data is present on D_O, if any
+-- -repeat, or deassert STB_I
+-- Detailed data transfer flow:
+-- -when DONE_O is low, the controller is ready to accept commands
+-- -data transfer can be initiated by putting a TWI slave address on the A_I
+-- bus and providing a strobe (STB_I)
+-- -the direction of data transfer (read/write) is determined by the LSB of the
+-- address (0-write, 1-read)
+-- -in case of a 'write' the data byte should also be present on the D_I bus
+-- prior to the arrival of the strobe (STB_I)
+-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
+-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
+-- together with DONE_I high indicates success
+-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
+-- strobe can be sent; this is useful, when multiple bytes are sent/received
+-- in a single transfer packet; for ex. for write transfers, a new byte can
+-- be put on the D_I and STB_I provided;
+-- -if no new strobe is provided, the transfer will end
+-- -if a new strobe is provided, but the address changed, the current transfer
+-- will end and a new will begin
+-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
+-- a strobe, the data byte will be written/read in a new packet; the advantage
+-- of this is relevant only in multi-master buses: rather than waiting for the
+-- current transfer to end and the bus to be released, a new transfer can be
+-- initiated without giving up the control over the bus
+----------------------------------------------------------------------------------
+ generic (CLOCKFREQ : natural := 50); -- input CLK frequency in MHz
+ port (
+ MSG_I : in STD_LOGIC; --new message
+ STB_I : in STD_LOGIC; --strobe
+ A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
+ D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
+ D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
+ DONE_O : out STD_LOGIC; --done status signal
+ ERR_O : out STD_LOGIC; --error status
+ CLK : in std_logic;
+ SRST : in std_logic;
+----------------------------------------------------------------------------------
+-- TWI bus signals
+----------------------------------------------------------------------------------
+ SDA : inout std_logic; --TWI SDA
+ SCL : inout std_logic --TWI SCL
+ );
+end TWICtl;
+
+architecture Behavioral of TWICtl is
+ attribute fsm_encoding: string;
+
+ constant FSCL : natural := 400_000; --in Hz SCL clock frequency
+ constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
+ constant TSCL_CYCLES : natural :=
+ natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
+ constant TIMEOUT_CYCLES : natural :=
+ natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
+
+ type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
+ stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
+ type busState_type is (busUnknown, busFree, busBusy);
+ type error_type is (errNAck, errArb);
+ signal state, nstate : state_type;
+ attribute fsm_encoding of state: signal is "gray";
+
+ signal dSda, ddSda, dScl, ddScl : std_logic;
+ signal fStart, fStop : std_logic;
+ signal busState : busState_type := busUnknown;
+ signal errTypeR, errType : error_type;
+ signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
+ signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
+ signal slaveWait, arbLost : std_logic;
+ signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
+ signal rSda, rScl : std_logic := '1';
+ signal subState : std_logic_vector(1 downto 0) := "00";
+ signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
+ signal bitCount : natural range 0 to 7 := 7;
+ signal int_Rst : std_logic := '0';
+begin
+
+----------------------------------------------------------------------------------
+--Bus State detection
+----------------------------------------------------------------------------------
+SYNC_FFS: process(CLK)
+ begin
+ if Rising_Edge(CLK) then
+ dSda <= SDA;
+ ddSda <= dSda;
+ dScl <= SCL;
+ end if;
+ end process;
+
+ fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
+ fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
+
+TWISTATE: process(CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (int_Rst = '1') then
+ busState <= busUnknown;
+ elsif (fStart = '1') then --If START condition detected, bus is busy
+ busState <= busBusy;
+ elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
+ busState <= busFree;
+ end if;
+ end if;
+ end process;
+
+TBUF_CNT: process(CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
+ busFreeCnt <= TSCL_CYCLES;
+ elsif (dSCL = '1' and dSDA = '1') then
+ busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+--Slave devices can insert wait states by keeping SCL low
+----------------------------------------------------------------------------------
+ slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
+ '0';
+----------------------------------------------------------------------------------
+--If the SDA line does not correspond to the transmitted data while the SCL line
+--is at the HIGH level the master lost an arbitration to another master.
+----------------------------------------------------------------------------------
+ arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
+ '0';
+
+----------------------------------------------------------------------------------
+-- Internal reset signal
+----------------------------------------------------------------------------------
+ RST_PROC: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (state = stIdle and SRST = '0') then
+ int_Rst <= '0';
+ elsif (SRST = '1') then
+ int_Rst <= '1';
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+-- SCL period counter
+----------------------------------------------------------------------------------
+SCL_CNT: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (sclCnt = 0 or state = stIdle) then
+ sclCnt <= TSCL_CYCLES/4;
+ elsif (slaveWait = '0') then -- clock synchronization with other masters
+ sclCnt <= sclCnt - 1;
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+-- SCL period counter
+----------------------------------------------------------------------------------
+TIMEOUT_CNT: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (timeOutCnt = 0 or slaveWait = '0') then
+ timeOutCnt <= TIMEOUT_CYCLES;
+ elsif (slaveWait = '1') then -- count timeout on wait period inserted by slave
+ timeOutCnt <= timeOutCnt - 1;
+ end if;
+ end if;
+ end process;
+
+----------------------------------------------------------------------------------
+-- Title: Data byte shift register
+-- Description: Stores the byte to be written or the byte read depending on the
+-- transfer direction.
+----------------------------------------------------------------------------------
+DATABYTE_SHREG: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
+ dataByte <= loadByte; --latch address/data
+ bitCount <= 7;
+ --set flag so that we now what is the byte we are sending
+ if (latchData = '1') then
+ addrNData <= '0';
+ else
+ addrNData <= '1';
+ end if;
+ elsif (shiftBit = '1' and sclCnt = 0) then
+ dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
+ bitCount <= bitCount - 1;
+ end if;
+ end if;
+ end process;
+
+ loadByte <= A_I when latchAddr = '1' else
+ D_I;
+ dataBitOut <= dataByte(dataByte'high);
+
+ D_O <= dataByte;
+
+----------------------------------------------------------------------------------
+-- Title: Current address register
+-- Description: Stores the TWI slave address
+----------------------------------------------------------------------------------
+CURRADDR_REG: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (latchAddr = '1') then
+ currAddr <= A_I; --latch address/data
+ end if;
+ end if;
+ end process;
+
+ rwBit <= currAddr(0);
+----------------------------------------------------------------------------------
+-- Title: Substate counter
+-- Description: Divides each state into 4, to respect the setup and hold times of
+-- the TWI bus.
+----------------------------------------------------------------------------------
+SUBSTATE_CNT: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ if (state = stIdle) then
+ subState <= "00";
+ elsif (sclCnt = 0) then
+ subState <= subState + 1;
+ end if;
+ end if;
+ end process;
+
+SYNC_PROC: process (CLK)
+ begin
+ if Rising_Edge(CLK) then
+ state <= nstate;
+
+ rSda <= iSda;
+ rScl <= iScl;
+ DONE_O <= iDone;
+ ERR_O <= iErr;
+ errTypeR <= errType;
+ end if;
+ end process;
+
+OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
+ sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
+ begin
+ iSda <= rSda; --no change by default
+ iScl <= rScl;
+ iDone <= '0';
+ iErr <= '0';
+ errType <= errTypeR; --keep error type
+ shiftBit <= '0';
+ latchAddr <= '0';
+ latchData <= '0';
+
+ if (state = stStart) then
+ case (subState) is
+ when "00" =>
+ iSda <= '1';
+ --keep SCL
+ when "01" =>
+ iSda <= '1';
+ iScl <= '1';
+ when "10" =>
+ iSda <= '0';
+ iScl <= '1';
+ when "11" =>
+ iSda <= '0';
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stStop or state = stStopError) then
+ case (subState) is
+ when "00" =>
+ iSda <= '0';
+ --keep SCL
+ when "01" =>
+ iSda <= '0';
+ iScl <= '1';
+ when "10" =>
+ iSda <= '1';
+ iScl <= '1';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stRead or state = stSAck) then
+ case (subState) is
+ when "00" =>
+ iSda <= '1'; --this will be 'Z' on SDA
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stWrite) then
+ case (subState) is
+ when "00" =>
+ iSda <= dataBitOut;
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stMAck) then
+ case (subState) is
+ when "00" =>
+ iSda <= '0'; -- acknowledge by writing 0
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stMNAckStop or state = stMNAckStart) then
+ case (subState) is
+ when "00" =>
+ iSda <= '1'; -- not acknowledge by writing 1
+ --keep SCL
+ when "01" =>
+ --keep SDA
+ iScl <= '1';
+ when "10" =>
+ --keep SDA
+ iScl <= '1';
+ when "11" =>
+ --keep SDA
+ iScl <= '0';
+ when others =>
+ end case;
+ end if;
+
+ if (state = stSAck and sclCnt = 0 and subState = "01") then
+ if (dSda = '1') then
+ iDone <= '1';
+ iErr <= '1'; --not acknowledged
+ errType <= errNAck;
+ elsif (addrNData = '0') then
+ --we are done only when the data is sent too after the address
+ iDone <= '1';
+ end if;
+ end if;
+
+ if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
+ iDone <= '1'; --read done
+ end if;
+
+ if (state = stWrite and arbLost = '1') then
+ iDone <= '1'; --write done
+ iErr <= '1'; --we lost the arbitration
+ errType <= errArb;
+ end if;
+
+ if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
+ ((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
+ shiftBit <= '1';
+ end if;
+
+ if (state = stStart) then
+ latchAddr <= '1';
+ end if;
+
+ if (state = stSAck and subState = "11") then --get the data byte for the next write
+ latchData <= '1';
+ end if;
+
+ end process;
+
+NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I,
+SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
+ begin
+
+ nstate <= state; --default is to stay in current state
+
+ case (state) is
+ when stIdle =>
+ if (STB_I = '1' and busState = busFree and SRST = '0') then
+ nstate <= stStart;
+ end if;
+
+ when stStart =>
+ if (subState = "11" and sclCnt = 0) then
+ nstate <= stWrite;
+ end if;
+
+ when stWrite =>
+ if (arbLost = '1') then
+ nstate <= stIdle;
+ elsif (subState = "11" and sclCnt = 0 and bitCount = 0) then
+ nstate <= stSAck;
+ end if;
+
+ when stSAck =>
+ if (subState = "11" and sclCnt = 0) then
+ if (int_Rst = '1' or dataByte(0) = '1') then
+ nstate <= stStop;
+ else
+ if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
+ if (rwBit = '1') then
+ nstate <= stRead;
+ else
+ nstate <= stWrite;
+ end if;
+ elsif (STB_I = '1') then
+ if (MSG_I = '1' or currAddr /= A_I) then
+ nstate <= stStart;
+ else
+ if (rwBit = '1') then
+ nstate <= stRead;
+ else
+ nstate <= stWrite;
+ end if;
+ end if;
+ else
+ nstate <= stStop;
+ end if;
+ end if;
+ end if;
+
+ when stStop =>
+ if (subState = "10" and sclCnt = 0) then
+ nstate <= stIdle;
+ end if;
+
+ when stRead =>
+ if (subState = "11" and sclCnt = 0 and bitCount = 7) then --bitCount will underflow
+ if (int_Rst = '0' and STB_I = '1') then
+ if (MSG_I = '1' or currAddr /= A_I) then
+ nstate <= stMNAckStart;
+ else
+ nstate <= stMAck;
+ end if;
+ else
+ nstate <= stMNAckStop;
+ end if;
+ end if;
+
+ when stMAck =>
+ if (subState = "11" and sclCnt = 0) then
+ nstate <= stRead;
+ end if;
+
+ when stMNAckStart =>
+ if (arbLost = '1') then
+ nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
+ elsif (subState = "11" and sclCnt = 0) then
+ nstate <= stStart;
+ end if;
+
+ when stMNAckStop =>
+ if (arbLost = '1') then
+ nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
+ elsif (subState = "11" and sclCnt = 0) then
+ nstate <= stStop;
+ end if;
+
+ when others =>
+ nstate <= stIdle;
+ end case;
+ end process;
+
+----------------------------------------------------------------------------------
+-- Open-drain outputs for bi-directional SDA and SCL
+----------------------------------------------------------------------------------
+ SDA <= 'Z' when rSDA = '1' else
+ '0';
+ SCL <= 'Z' when rSCL = '1' else
+ '0';
+
+end Behavioral;
\ No newline at end of file
diff --git a/tp_vivado/src/hdl/audioProc.v b/tp_vivado/src/hdl/audioProc.v
new file mode 100644
index 0000000..cae83df
--- /dev/null
+++ b/tp_vivado/src/hdl/audioProc.v
@@ -0,0 +1,231 @@
+// -*- Mode: Verilog -*-
+// Filename : audioProc.v
+// Description : Audio processing project for IMTA A1S2 Labs in digital electronics, based on looper project by Digilent Inc.
+// Author : Matthieu Arzel
+// Created On : Fri Feb 8 11:16:35 2019
+// Last Modified By: Matthieu Arzel
+// Last Modified On: Fri Feb 8 11:16:35 2019
+// Update Count : 0
+// Status : Unknown, Use with caution!
+
+`timescale 1ns / 1ps
+
+module audioProc(
+
+
+ input BTNL,
+ input BTNR,
+ input BTND,
+ input BTNC,
+ input BTNU,
+ // input JA1,
+ // input JA2,
+ // input JA3,
+ // input JA4,
+
+ input CLK100MHZ,
+ input rstn,
+ input sw,
+ //input [3:0]sw,
+ input sw3,
+ input sw4,
+ input sw5,
+ input sw6,
+ input sw7,
+ output led3,
+ output led4,
+ output led5,
+ output led6,
+ output led7,
+
+ inout scl,
+ inout sda,
+
+ output ac_mclk,
+ input ac_adc_sdata,
+ output ac_dac_sdata,
+ output ac_bclk,
+ output ac_lrclk
+
+ );
+
+ wire rst;
+ assign rst = ~rstn;
+ wire clk50;
+ parameter tenhz = 10000000;
+
+
+
+ wire [4:0] buttons_i;
+ assign buttons_i = {BTNU, BTNR, BTNC, BTND, BTNL};
+
+ reg [21:0] max_block=0;
+
+ wire set_max;
+ wire reset_max;
+
+
+ wire [4:0] buttons_db;//Debounced buttons
+
+ wire data_flag;
+ reg [23:0] sound_dataL;
+ reg [23:0] sound_dataR;
+ wire data_ready;
+
+ wire mix_data;
+ wire [21:0] block48KHz;
+
+ wire clk_out_100MHZ;
+ wire clk_out_200MHZ;
+
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+ //// clk_wiz instantiation and wiring
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+ clk_wiz_0 clk_1
+ (
+ // Clock in ports
+ .clk_in1(CLK100MHZ),
+ // Clock out ports
+ .clk_out1(clk_out_100MHZ),
+ .clk_out2(clk_out_200MHZ),
+ .clk_out3(ac_mclk),
+ .clk_out4(clk50),
+ // Status and control signals
+ .locked()
+ );
+
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+ //// Audio Initialization via TWI
+ //////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ audio_init initialize_audio
+ (
+ .clk(clk50),
+ .rst(rst),
+ .sda(sda),
+ .scl(scl)
+ );
+
+
+ wire [23:0] mixL;
+ wire [23:0] mixR;
+
+
+ debounce dbuttons(
+ .clock(clk_out_100MHZ),
+ .reset(rst),
+ .button(buttons_i),
+ .out(buttons_db)
+ );
+
+
+
+
+
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // Audio input and output
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ wire [23:0] in_audioL;
+ wire [23:0] in_audioR;
+ wire [23:0] out_audioL;
+ wire [23:0] out_audioR;
+
+ i2s_ctl audio_inout(
+ .CLK_I(clk_out_100MHZ), //Sys clk
+ .RST_I(rst), //Sys rst
+ .EN_TX_I(1), // Transmit Enable (push sound data into chip)
+ .EN_RX_I(1), //Receive enable (pull sound data out of chip)
+ .FS_I(4'b0101), //Sampling rate selector
+ .MM_I(0), //Audio controller Master mode select
+ .D_L_I(mixL), //Left channel data input from mix (mixed audio output)
+ .D_R_I(mixR), //Right channel data input from mix
+ .D_L_O(in_audioL), // Left channel data (input from mic input)
+ .D_R_O(in_audioR), // Right channel data (input from mic input)
+ .BCLK_O(ac_bclk), // serial CLK
+ .LRCLK_O(ac_lrclk), // channel CLK
+ .SDATA_O(ac_dac_sdata), // Output serial data
+ .SDATA_I(ac_adc_sdata) // Input serial data
+ );
+
+ reg lrclkD1=0;
+ reg lrclkD2=0;
+
+ always@(posedge(clk_out_100MHZ))begin
+ lrclkD1<=ac_lrclk;
+ lrclkD2<=lrclkD1;
+ end
+
+ reg pulse48kHz;
+ wire lrclkrise;
+ assign lrclkrise = lrclkD1 & ~lrclkD2;
+ reg[3:0] lrclkcnt=0;
+
+ always@(posedge(clk_out_100MHZ))begin
+ if (lrclkcnt==15)begin
+ pulse48kHz<=1;
+ lrclkcnt<=0;
+ end
+ else
+ pulse48kHz<=0;
+ if (lrclkrise)lrclkcnt<=lrclkcnt+1;
+ end
+ //////////////////////////////
+ //FIR filter
+ // Marz
+ /////////////////////////////
+ wire [23:0] inputLeftSample, inputRightSample,outputLeftSample,outputRightSample;
+ wire [4:0] configSw;
+
+ assign inputLeftSample = in_audioL;
+ assign inputRightSample = in_audioR;
+ assign configSw[0]=sw3;
+ assign configSw[1]=sw4;
+ assign configSw[2]=sw5;
+ assign configSw[3]=sw6;
+ assign configSw[4]=sw7;
+ assign led3=sw3;
+ assign led4=sw4;
+ assign led5=sw5;
+ assign led6=sw6;
+ assign led7=sw7;
+
+ fir #(24,16) leftFir
+ (
+ inputLeftSample,
+ outputLeftSample,
+ configSw,//config_sw, // : in std_logic_vector(3 downto 0); --inutilise dans le TP majeure
+ clk_out_100MHZ, // : in std_logic;
+ rst,// : in std_logic;
+ pulse48kHz// : in std_logic; -- signal de validation de din a la frequence des echantillons audio
+ );
+ fir #(24,16) rightFir
+ (
+ inputRightSample,
+ outputRightSample,
+ configSw,//config_sw, // : in std_logic_vector(3 downto 0); --inutilise dans le TP majeure
+ clk_out_100MHZ, // : in std_logic;
+ rst,// : in std_logic;
+ pulse48kHz// : in std_logic; -- signal de validation de din a la frequence des echantillons audio
+ );
+
+ assign mixL = buttons_db[2] ? in_audioL : outputLeftSample;
+ assign mixR = buttons_db[2] ? in_audioR : outputRightSample;
+
+
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+ //// Data in latch
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ //Latch audio data input when data_flag goes high
+ always@(posedge(clk_out_100MHZ))begin
+ if (data_flag==1)begin
+ sound_dataL<=in_audioL;
+ sound_dataR<=in_audioR;
+ end
+ end
+
+
+endmodule
diff --git a/tp_vivado/src/hdl/audio_init.v b/tp_vivado/src/hdl/audio_init.v
new file mode 100644
index 0000000..0f33184
--- /dev/null
+++ b/tp_vivado/src/hdl/audio_init.v
@@ -0,0 +1,246 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 07/08/2015 06:07:53 PM
+// Design Name:
+// Module Name: audio_init
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+
+module audio_init(
+ input clk,
+ input rst,
+ inout sda,
+ inout scl
+ );
+ parameter stRegAddr1 = 4'b0000;
+ parameter stRegAddr2 = 4'b0001;
+ parameter stData1 = 4'b0010;
+ parameter stData2 = 4'b0011;
+ parameter stError = 4'b0100;
+ parameter stDone = 4'b0101;
+ parameter stIdle = 4'b0110;
+ parameter stDelay = 4'b0111;
+ parameter stPLLsecond = 4'b1111;
+
+ parameter INIT_VECTORS = 35;
+ parameter IRD = 1'b1;//init read
+ parameter IWR = 1'b0;//init write
+ parameter delay = 1000*24;
+
+ reg [3:0] state=stIdle;//State machine
+ reg [32:0] initWord;
+ reg initFbWe;
+ reg initEn;
+ reg [6:0]initA=0;
+ always @(posedge(clk))begin
+ case (initA)
+ 0: initWord <= {IWR,31'h40150100};
+ 1: initWord <= {IWR,31'h40160000};
+ 2: initWord <= {IWR,31'h40170000};
+ 3: initWord <= {IWR,31'h40F80000};
+ 4: initWord <= {IWR,31'h40191300};
+ 5: initWord <= {IWR,31'h402A0300};
+ 6: initWord <= {IWR,31'h40290300};
+ 7: initWord <= {IWR,31'h40F20100};
+ 8: initWord <= {IWR,31'h40F97F00};
+ 9: initWord <= {IWR,31'h40FA0300};
+
+ 10: initWord <= {IWR,31'h40200300};
+ 11: initWord <= {IWR,31'h40220100};
+ 12: initWord <= {IWR,31'h40210900};
+ 13: initWord <= {IWR,31'h4025E600};
+ 14: initWord <= {IWR,31'h4026E600};
+ 15: initWord <= {IWR,31'h40270300};
+ 16: initWord <= {IWR,31'h40100100};
+ 17: initWord <= {IWR,31'h40280000};
+ 18: initWord <= {IWR,31'h4023E600};
+ 19: initWord <= {IWR,31'h4024E600};
+
+ 20: initWord <= {IWR,31'h400A0100};
+ 21: initWord <= {IWR,31'h400B0500};
+ 22: initWord <= {IWR,31'h400C0100};
+ 23: initWord <= {IWR,31'h400D0500};
+ 24: initWord <= {IWR,31'h400E0300};
+ 25: initWord <= {IWR,31'h400F0300};
+ 26: initWord <= {IWR,31'h401C2100};
+ 27: initWord <= {IWR,31'h401D0000};
+ 28: initWord <= {IWR,31'h401E4100};
+ 29: initWord <= {IWR,31'h401F0000};
+ 30: initWord <= {IWR,31'h40F30100};
+ 31: initWord <= {IWR,31'h40F40000};
+ 32: initWord <= {IWR,31'h40000F00};
+ 33: initWord <= {IWR,31'h4002007D};//This sends the address of the PLL reg and the first config bits
+ 34: initWord <= {IWR,31'h000C2101}; //These are the config bytes for the PLL reg
+ endcase
+ end
+ reg msg;//New message signal
+ reg stb;//Strobe signal
+ reg [7:0] data_i;//Data into TWI controller
+ wire [7:0] data_o;//Data out of TWI controller
+ wire done;
+ wire error;
+ wire errortype;
+ wire [7:0] twiAddr;//Address of device on TWI
+ reg [7:0] regData1;
+
+ reg delayEn=0;
+ integer delaycnt;
+
+
+ assign twiAddr[7:1] = 7'b0111011;
+
+ assign twiAddr[0] = 0;
+
+ TWICtl twi_controller(
+ .MSG_I(msg),
+ .STB_I(stb),
+ .A_I(twiAddr),
+ .D_I(data_i),
+ .D_O(data_o),
+ .DONE_O(done),
+ .ERR_O(error),
+ .CLK(clk),
+ .SRST(rst),
+ .SDA(sda),
+ .SCL(scl)
+ );
+
+
+
+always @(posedge(clk))begin
+ if (delayEn==1)
+ delaycnt<=delaycnt-1;
+ else
+ delaycnt<=delay;
+end
+
+
+always @(posedge(clk))begin
+ if (state == stData1 && done == 1 && error != 1)
+ regData1 <= data_o;
+end
+
+
+always @(posedge(clk))begin
+ if (rst==1)begin
+ state<= stIdle;
+ delayEn <= 0;
+ initA <=0;
+ end
+ else begin
+ data_i <= "--------";
+ stb <= 0;
+ msg <= 0;
+
+ initFbWe <= 0;
+ case (state)
+ stRegAddr1: begin// Sends x40
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else
+ state <= stRegAddr2;
+ end
+ data_i <= initWord[31:24];
+ stb <= 1;
+ msg <= 1;
+ end
+ stRegAddr2: begin //Sends register address x40(XX)
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else
+ state <= stData1;
+ end
+ data_i <= initWord[23:16];
+ stb <= 1;
+ end
+ stData1: begin
+ if (done == 1) begin
+ if (error == 1)
+ state <= stError;
+ else begin
+ if (initWord[7:0]!=0)//If there is another byte, send it
+ state <= stData2;
+ else begin//no more bytes to send
+ initEn <= 1;
+
+ if (initA == INIT_VECTORS-1)//Done with all instructions
+ state <= stDone;
+ else //Only 3 bytes to send
+ state <= stDelay;
+ end
+ end
+ end
+ if (initWord[32] == 1) msg <= 1;
+ data_i <= initWord[15:8];
+ stb <= 1;
+ end
+ stData2: begin
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else begin
+ initEn<=1;
+ if (initWord[32] == 1) initFbWe <= 1;
+ if (initWord[23:16]== 8'h02)begin//If its the PLL register
+ initA<=initA+1;//Move initWord to the remaining PLL config bits
+ state <= stPLLsecond;//And send them
+ end
+ else if (initA == INIT_VECTORS-1)
+ state <= stDone;
+ else
+ state <= stDelay;
+ end
+ end
+ data_i <= initWord[7:0];
+ stb <= 1;
+ end
+ stPLLsecond:begin
+ if (done == 1)begin
+ if (error == 1)
+ state <= stError;
+ else
+ state <= stRegAddr2;
+ end
+ data_i <= initWord[31:24];
+ stb <= 1;
+ end
+ stError: begin
+ state <= stRegAddr1;
+ end
+ stDone: begin
+ end
+ stIdle:begin
+ state <= stRegAddr1;
+ end
+ stDelay:begin
+ delayEn <= 1;
+ if (delaycnt==0)begin
+ delayEn<=0;
+ if (initEn)begin
+ initA<=initA+1;
+ initEn <= 0;
+ end
+ state<=stRegAddr1;
+ end
+ end
+ endcase
+ end
+end
+endmodule
diff --git a/tp_vivado/src/hdl/controlUnit.vhd b/tp_vivado/src/hdl/controlUnit.vhd
new file mode 100644
index 0000000..954bf21
--- /dev/null
+++ b/tp_vivado/src/hdl/controlUnit.vhd
@@ -0,0 +1,183 @@
+-------------------------------------------------------------------------------
+-- Title : controlUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Control unit of a sequential FIR filter.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity controlUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSampleValid : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_processingDone_y : in std_logic;
+ I_processingDone_z_a : in std_logic;
+ I_processingDone_z_b : in std_logic;
+ I_processingDone_r : in std_logic;
+ O_loadShift_X : out std_logic; --
+ O_loadShift_Y : out std_logic; --
+ O_loadShift_Z : out std_logic; --
+ O_initAddress_x : out std_logic; -- Control signal to initialize register read address
+ O_initAddress_y : out std_logic;
+ O_initAddress_z : out std_logic;
+ O_incrAddress_x : out std_logic; -- Control signal to increment register read address
+ O_incrAddress_y : out std_logic; -- Control signal to increment register read address
+ O_incrAddress_z : out std_logic; -- Control signal to increment register read address
+ O_filtre : out std_logic_vector(1 downto 0);
+ O_filtreCoef : out std_logic_vector(1 downto 0);
+ O_initSum : out std_logic; -- Control signal to initialize the MAC register
+ O_loadSum : out std_logic; -- Control signal to load the MAC register;
+ O_loadY : out std_logic; -- Control signal to load Y register
+ O_FilteredSampleValid : out std_logic -- Data valid signal for filtered sample
+ );
+
+end entity controlUnit;
+architecture archi_operativeUnit of controlUnit is
+
+
+ type T_state is (WAIT_SAMPLE, STORE_X, PROCESSING_LOOP_Y, STORE_Y, PROCESSING_LOOP_Z_A, INITADRESS, PROCESSING_LOOP_Z_B, STORE_Z, PROCESSING_LOOP_R, OUTPUT, WAIT_END_SAMPLE); -- state list
+ signal SR_presentState : T_state;
+ signal SR_futurState : T_state;
+
+begin
+
+ process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_presentState <= WAIT_SAMPLE;
+ elsif rising_edge(I_clock) then -- rising clock edge
+ SR_presentState <= SR_futurState;
+ end if;
+ end process;
+
+ process (I_clock, SR_presentState) is
+ begin
+ case SR_presentState is
+ when WAIT_SAMPLE =>
+ if I_inputSampleValid = '0' then
+ SR_futurState <= WAIT_SAMPLE;
+ else
+ SR_futurState <= STORE_X;
+ end if;
+
+ when STORE_X =>
+ SR_futurState <= PROCESSING_LOOP_Y;
+
+ when PROCESSING_LOOP_Y =>
+ if I_processingDone_Y = '1' then
+ SR_futurState <= STORE_Y;
+ else
+ SR_futurSTATE <= PROCESSING_LOOP_Y;
+ end if;
+
+ when STORE_Y =>
+ SR_futurState <= PROCESSING_LOOP_Z_A;
+
+ when PROCESSING_LOOP_Z_A =>
+ if I_processingDone_z_a = '1' then
+ SR_futurState <= INITADRESS;
+ else
+ SR_futurState <= PROCESSING_LOOP_Z_A;
+ end if;
+
+ when INITADRESS =>
+ SR_futurState <= PROCESSING_LOOP_Z_B;
+
+ when PROCESSING_LOOP_Z_B =>
+ if I_processingDone_z_b = '1' then
+ SR_futurState <= STORE_Z;
+ else
+ SR_futurState <= PROCESSING_LOOP_Z_B;
+ end if;
+
+ when STORE_Z =>
+ SR_futurState <= PROCESSING_LOOP_R;
+
+ when PROCESSING_LOOP_R =>
+ if I_processingDone_R = '1' then
+ SR_futurState <= OUTPUT;
+ else
+ SR_futurState <= PROCESSING_LOOP_R;
+ end if;
+
+ when OUTPUT =>
+ SR_futurState <= WAIT_END_SAMPLE;
+
+ when WAIT_END_SAMPLE =>
+ if I_inputSampleValid = '1' then
+ SR_futurState <= WAIT_END_SAMPLE;
+ else
+ SR_futurState <= WAIT_SAMPLE;
+ end if;
+
+ when others => null;
+ end case;
+ end process;
+
+ handle_filters: process (I_clock, I_reset, SR_presentState) is
+ begin
+ if I_reset = '1' then
+ O_Filtre <= "00";
+ O_FiltreCoef <= "00";
+ else
+ if SR_presentState = STORE_X or SR_presentState = PROCESSING_LOOP_Y then
+ O_Filtre <= "00";
+ O_FiltreCoef <= "00";
+ end if;
+
+ if SR_presentState = PROCESSING_LOOP_Z_B then
+ O_Filtre <= "01";
+ O_FiltreCoef <= "01";
+ end if;
+
+ if SR_presentState = PROCESSING_LOOP_Z_A then
+ O_filtre <= "10";
+ end if;
+
+ if SR_presentState = PROCESSING_LOOP_R then
+ O_Filtre <= "10";
+ O_FiltreCoef <= "11";
+ end if;
+ end if;
+ end process handle_filters;
+
+ O_loadShift_X <= '1' when SR_presentState = STORE_X else '0';
+ O_loadShift_Y <= '1' when SR_presentState = STORE_Y else '0';
+ O_loadShift_Z <= '1' when SR_presentState = STORE_Z else '0';
+ O_initAddress_x <= '1' when SR_presentState = STORE_X else '0';
+ O_initAddress_y <= '1' when SR_presentState = STORE_Y or SR_presentState = INITADRESS else '0';
+ O_initAddress_z <= '1' when SR_presentState = STORE_Z else '0';
+ O_incrAddress_x <= '1' when SR_presentState = PROCESSING_LOOP_Y else '0';
+ O_incrAddress_y <= '1' when SR_presentState = PROCESSING_LOOP_Z_A or SR_presentState = PROCESSING_LOOP_Z_B else '0';
+ O_incrAddress_z <= '1' when SR_presentState = PROCESSING_LOOP_R else '0';
+ O_initSum <= '1' when SR_presentState = STORE_X
+ or SR_presentState = STORE_Y
+ or SR_presentState = STORE_Z else '0';
+ O_loadSum <= '1' when SR_presentState = PROCESSING_LOOP_Y
+ or SR_presentState = PROCESSING_LOOP_Z_A
+ or SR_presentState = PROCESSING_LOOP_Z_B
+ or SR_presentState = PROCESSING_LOOP_R else '0';
+
+ O_loadY <= '1' when SR_presentState = OUTPUT else '0';
+-- O_FilteredSampleValid <= '1' when _BLANK_ ;
+
+end architecture archi_operativeUnit;
diff --git a/tp_vivado/src/hdl/debounce.v b/tp_vivado/src/hdl/debounce.v
new file mode 100644
index 0000000..033a4fb
--- /dev/null
+++ b/tp_vivado/src/hdl/debounce.v
@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 05/13/2015 09:14:14 PM
+// Design Name:
+// Module Name: debounce
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module debounce(
+ input clock,//100MHz clock
+ input reset,
+ input [4:0] button,//Buttons to debounce
+ output reg [4:0]out
+);
+
+reg [12:0] cnt0=0, cnt1=0, cnt2=0, cnt3=0, cnt4;
+reg [4:0] IV = 0;
+
+//parameter dbTime = 19;
+parameter dbTime = 4000;
+
+always @ (posedge(clock))begin
+ if(reset==1)begin
+ cnt0<=0;
+ cnt1<=0;
+ cnt2<=0;
+ cnt3<=0;
+ cnt4<=0;
+ out<=0;
+ end
+ else begin
+ if(button[0]==IV[0]) begin
+ if (cnt0==dbTime) begin
+ out[0]<=IV[0];
+ end
+ else begin
+ cnt0<=cnt0+1;
+ end
+ end
+ else begin
+ cnt0<=0;
+ IV[0]<=button[0];
+ end
+ if(button[1]==IV[1]) begin
+ if (cnt1==dbTime) begin
+ out[1]<=IV[1];
+ end
+ else begin
+ cnt1<=cnt1+1;
+ end
+ end
+ else begin
+ cnt1<=0;
+ IV[1]<=button[1];
+ end
+ if(button[2]==IV[2]) begin
+ if (cnt2==dbTime) begin
+ out[2]<=IV[2];
+ end
+ else begin
+ cnt2<=cnt2+1;
+ end
+ end
+ else begin
+ cnt2<=0;
+ IV[2]<=button[2];
+ end
+ if(button[3]==IV[3]) begin
+ if (cnt3==dbTime) begin
+ out[3]<=IV[3];
+ end
+ else begin
+ cnt3<=cnt3+1;
+ end
+ end
+ else begin
+ cnt3<=0;
+ IV[3]<=button[3];
+ end
+ if(button[4]==IV[4]) begin
+ if (cnt4==dbTime) begin
+ out[4]<=IV[4];
+ end
+ else begin
+ cnt4<=cnt4+1;
+ end
+ end
+ else begin
+ cnt4<=0;
+ IV[4]<=button[4];
+ end
+ end
+end
+endmodule
\ No newline at end of file
diff --git a/tp_vivado/src/hdl/fir.vhd b/tp_vivado/src/hdl/fir.vhd
new file mode 100644
index 0000000..785d6e4
--- /dev/null
+++ b/tp_vivado/src/hdl/fir.vhd
@@ -0,0 +1,93 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity fir is
+
+ generic (
+ dwidth : natural := 18;
+ ntaps : natural := 15);
+
+ port (
+ din : in std_logic_vector(dwidth-1 downto 0);
+ dout : out std_logic_vector(dwidth-1 downto 0);
+ config_sw : in std_logic_vector(4 downto 0); --inutilise dans le TP majeure
+ clk : in std_logic;
+ rst : in std_logic;
+ ce : in std_logic; -- signal de validation de din a la frequence des echantillons audio
+ dbg_output_0 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
+ dbg_output_1 : out std_logic_vector(7 downto 0); --inutilise dans le TP majeure
+ dbg_output_2 : out std_logic; --inutilise dans le TP majeure
+ dbg_output_3 : out std_logic; --inutilise dans le TP majeure
+ dbg_output_4 : out std_logic --inutilise dans le TP majeure
+-- dout_valid : out std_logic
+ );
+
+end fir;
+
+architecture myarch of fir is
+
+ component firUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSample : in std_logic_vector(7 downto 0);
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(7 downto 0);
+ O_filteredSampleValid : out std_logic);
+ end component firUnit;
+
+
+ signal D_in, D_out : std_logic_vector(7 downto 0);
+
+begin -- myarch
+
+-- Quantization on 8 bits or less
+
+-- When config_sw(3)='1', rounding is made by finding the nearest value else rounding is made by truncating.
+ prc : process (config_sw(3 downto 0), din) is
+ begin -- process prc
+ case to_integer(unsigned(config_sw(3 downto 0))) is
+ when 0 => D_in <= din(dwidth-1 downto dwidth -8);
+ when 1 => D_in <= din(dwidth-1 downto dwidth -7)&'0';
+ when 2 => D_in <= din(dwidth-1 downto dwidth -6)&"00";
+ when 3 => D_in <= din(dwidth-1 downto dwidth -5)&"000";
+ when 4 => D_in <= din(dwidth-1 downto dwidth -4)&"0000";
+ when 5 => D_in <= din(dwidth-1 downto dwidth -3)&"00000";
+ when 6 => D_in <= din(dwidth-1 downto dwidth -2)&"000000";
+ when 7 => D_in <= din(dwidth-1)&"0000000";
+ when 8 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -8);else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -8))+1); end if;
+ when 9 => if din(dwidth-8) = '0' then D_in <= din(dwidth-1 downto dwidth -7)&'0'; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -7))+1)&'0'; end if;
+ when 10 => if din(dwidth-7) = '0' then D_in <= din(dwidth-1 downto dwidth -6)&"00"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -6))+1)&"00"; end if;
+ when 11 => if din(dwidth-6) = '0' then D_in <= din(dwidth-1 downto dwidth -5)&"000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -5))+1)&"000"; end if;
+ when 12 => if din(dwidth-5) = '0' then D_in <= din(dwidth-1 downto dwidth -4)&"0000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -4))+1)&"0000"; end if;
+ when 13 => if din(dwidth-4) = '0' then D_in <= din(dwidth-1 downto dwidth -3)&"00000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -3))+1)&"00000"; end if;
+ when 14 => if din(dwidth-3) = '0' then D_in <= din(dwidth-1 downto dwidth -2)&"000000"; else D_in <=std_logic_vector(signed(din(dwidth-1 downto dwidth -2))+1)&"000000"; end if;
+ when 15 => D_in <= din(dwidth-1)&"0000000";
+ when others => D_in <= (others => '0');
+ end case;
+ end process prc;
+
+--FIR over 8 bits
+
+ firUnit_1 : entity work.firUnit
+ port map (
+ I_clock => clk,
+ I_reset => rst,
+ I_inputSample => D_in,
+ I_inputSampleValid => ce,
+ O_filteredSample => D_out,
+ O_filteredSampleValid => open);
+
+
+-- End of FIR
+
+
+ dout(dwidth-1 downto dwidth -8) <= D_out when config_sw(4) = '1' else D_in;
+ dout(dwidth-9 downto 0) <= (others => '0');
+
+
+
+
+
+end myarch;
diff --git a/tp_vivado/src/hdl/firUnit.vhd b/tp_vivado/src/hdl/firUnit.vhd
new file mode 100644
index 0000000..e0d34f4
--- /dev/null
+++ b/tp_vivado/src/hdl/firUnit.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+-- Title : firUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2018-04-11
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity firUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(10 downto 0); -- filtered sample
+ O_filteredSampleValid : out std_logic
+ );
+
+end entity firUnit;
+
+architecture archi_firUnit of firUnit is
+
+ component controlUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSampleValid : in std_logic;
+ I_processingDone_Y : in std_logic;
+ I_processingDone_Za : in std_logic;
+ I_processingDone_Zb : in std_logic;
+ I_processingDone_R : in std_logic;
+ O_loadShift_X : out std_logic; --
+ O_loadShift_Y : out std_logic; --
+ O_loadShift_Z : out std_logic; --
+ O_initAddress_x : in std_logic; -- Control signal to initialize register read address
+ O_initAddress_y : in std_logic; -- Control signal to initialize register read address
+ O_initAddress_z : in std_logic; -- Control signal to initialize register read address
+ O_incrAddress_Y : out std_logic; -- Control signal to increment register read address
+ O_incrAddress_Za : out std_logic; -- Control signal to increment register read address
+ O_incrAddress_Zb : out std_logic; -- Control signal to increment register read address
+ O_filtre : out std_logic_vector(1 downto 0);
+ O_filtreCoef : out std_logic_vector(1 downto 0);
+ O_initSum : out std_logic;
+ O_loadSum : out std_logic;
+ O_loadY : out std_logic;
+ O_FilteredSampleValid : out std_logic);
+ end component controlUnit;
+
+ component operativeUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSample : in std_logic_vector(10 downto 0);
+ I_loadShift_x : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShift_y : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShift_z : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_initAddress_x : in std_logic; -- Control signal to initialize register read address
+ I_initAddress_y : in std_logic; -- Control signal to initialize register read address
+ I_initAddress_z : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress_x : in std_logic; -- Control signal to increment register read address
+ I_incrAddress_y : in std_logic; -- Control signal to increment register read address
+ I_incrAddress_z : in std_logic; -- Control signal to increment register read address
+ I_initSum : in std_logic;
+ I_loadSum : in std_logic;
+ I_loadY : in std_logic;
+ I_filtre : in std_logic_vector(1 downto 0);
+ I_filtreCoef : in std_logic_vector(1 downto 0);
+ O_processingDone_y : out std_logic; -- Indicate that processing is done
+ O_processingDone_z_a : out std_logic; -- Indicate that processing is done
+ O_processingDone_z_b : out std_logic; -- Indicate that processing is done
+ O_processingDone_r : out std_logic; -- Indicate that processing is done
+ O_Y : out std_logic_vector(10 downto 0));
+ end component operativeUnit;
+
+ signal SC_processingDone_y : std_logic;
+ signal SC_processingDone_z_a : std_logic;
+ signal SC_processingDone_z_b : std_logic;
+ signal SC_processingDone_r : std_logic;
+ signal SC_loadShift_x : std_logic;
+ signal SC_loadShift_y : std_logic;
+ signal SC_loadShift_Z : std_logic;
+ signal SC_initAddress_x : std_logic;
+ signal SC_initAddress_y : std_logic;
+ signal SC_initAddress_z : std_logic;
+ signal SC_incrAddress_x : std_logic;
+ signal SC_incrAddress_y : std_logic;
+ signal SC_incrAddress_z : std_logic;
+ signal SC_initSum : std_logic;
+ signal SC_Filtre : std_logic_vector(1 downto 0);
+ signal SC_FiltreCoef : std_logic_vector(1 downto 0);
+ signal SC_loadSum : std_logic;
+ signal SC_loadY : std_logic;
+
+begin
+
+ controlUnit_1 : entity work.controlUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSampleValid => I_inputSampleValid,
+ I_processingDone_y => SC_processingDone_y,
+ I_processingDone_z_a => SC_processingDone_z_a,
+ I_processingDone_z_b => SC_processingDone_z_b,
+ I_processingDone_r => SC_processingDone_r,
+ O_loadShift_x => SC_loadShift_x,
+ O_initAddress_x => SC_initAddress_x,
+ O_initAddress_y => SC_initAddress_y,
+ O_initAddress_z => SC_initAddress_z,
+ O_incrAddress_x => SC_incrAddress_x,
+ O_incrAddress_y => SC_incrAddress_y,
+ O_incrAddress_z => SC_incrAddress_z,
+ O_filtre => SC_Filtre,
+ O_filtreCoef => SC_FiltreCoef,
+ O_initSum => SC_initSum,
+ O_loadSum => SC_loadSum,
+ O_loadY => SC_loadY,
+ O_FilteredSampleValid => O_FilteredSampleValid);
+
+ operativeUnit_1 : entity work.operativeUnit
+ port map (
+ I_clock => I_clock,
+ I_reset => I_reset,
+ I_inputSample => I_inputSample,
+ I_loadShift_x => SC_loadShift_x,
+ I_loadShift_y => SC_loadShift_y,
+ I_loadShift_z => SC_loadShift_z,
+ I_initAddress_x => SC_initAddress_x,
+ I_initAddress_y => SC_initAddress_y,
+ I_initAddress_z => SC_initAddress_z,
+ I_incrAddress_x => SC_incrAddress_x,
+ I_incrAddress_y => SC_incrAddress_y,
+ I_incrAddress_z => SC_incrAddress_z,
+ I_initSum => SC_initSum,
+ I_loadSum => SC_loadSum,
+ I_loadY => SC_loadY,
+ I_Filtre => SC_Filtre,
+ I_FiltreCoef => SC_FiltreCoef,
+ O_processingDone_y => SC_processingDone_y,
+ O_processingDone_z_a => SC_processingDone_z_a,
+ O_processingDone_z_b => SC_processingDone_z_b,
+ O_processingDone_r => SC_processingDone_r,
+ O_Y => O_filteredSample);
+
+end architecture archi_firUnit;
diff --git a/tp_vivado/src/hdl/i2s_ctl.vhd b/tp_vivado/src/hdl/i2s_ctl.vhd
new file mode 100644
index 0000000..1b608ad
--- /dev/null
+++ b/tp_vivado/src/hdl/i2s_ctl.vhd
@@ -0,0 +1,296 @@
+-------------------------------------------------------------------------------
+--
+-- COPYRIGHT (C) 2012, Digilent RO. All rights reserved
+--
+-------------------------------------------------------------------------------
+-- FILE NAME : i2s_ctl.vhd
+-- MODULE NAME : I2S Control
+-- AUTHOR : Mihaita Nagy
+-- AUTHOR'S EMAIL : mihaita.nagy@digilent.ro
+-------------------------------------------------------------------------------
+-- REVISION HISTORY
+-- VERSION DATE AUTHOR DESCRIPTION
+-- 1.0 2012-25-01 Mihaita Nagy Created
+-- 2.0 2012-02-04 Mihaita Nagy Remade the i2s_transmitter.vhd and
+-- i2s_receiver.vhd into one new module.
+-- 3.0 2014-12-02 HegbeliC Implemented edge detection for the
+-- master mode and the division rate
+-- for the different sampling rates
+-------------------------------------------------------------------------------
+-- KEYWORDS : I2S
+-------------------------------------------------------------------------------
+-- DESCRIPTION : This module implements the I2S transmitter and receiver
+-- interface, with a 32-bit Stereo data transmission. Parameter
+-- C_DATA_WIDTH sets the width of the data to be transmitted,
+-- with a maximum value of 32 bits. If a smaller width size is
+-- used (i.e. 24) than the remaining bits that needs to be
+-- transmitted to complete the 32-bit length, are automaticaly
+-- set to 0.
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+------------------------------------------------------------------------
+-- Module Declaration
+------------------------------------------------------------------------
+entity i2s_ctl is
+ generic (
+ -- Width of one Slot (24/20/18/16-bit wide)
+ C_DATA_WIDTH: integer := 24
+ );
+ port (
+ CLK_I : in std_logic; -- System clock (100 MHz)
+ RST_I : in std_logic; -- System reset
+ EN_TX_I : in std_logic; -- Transmit enable
+ EN_RX_I : in std_logic; -- Receive enable
+ FS_I : in std_logic_vector(3 downto 0); -- Sampling rate slector
+ MM_I : in std_logic; -- Audio controler Master Mode delcetor
+ D_L_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
+ D_R_I : in std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
+-- OE_L_O : out std_logic; -- Left channel data output enable pulse
+-- OE_R_O : out std_logic; -- Right channel data output enable pulse
+-- WE_L_O : out std_logic; -- Left channel data write enable pulse
+-- WE_R_O : out std_logic; -- Right channel data write enable pulse
+ D_L_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Left channel data
+ D_R_O : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Right channel data
+ BCLK_O : out std_logic; -- serial CLK
+ LRCLK_O : out std_logic; -- channel CLK
+ SDATA_O : out std_logic; -- Output serial data
+ SDATA_I : in std_logic -- Input serial data
+ );
+end i2s_ctl;
+
+architecture Behavioral of i2s_ctl is
+
+------------------------------------------------------------------------
+-- Signal Declarations
+------------------------------------------------------------------------
+-- Counter for the clock divider
+signal Cnt_Bclk : integer range 0 to 31;
+
+-- Counter for the L/R clock divider
+signal Cnt_Lrclk : integer range 0 to 31;
+
+-- Rising and Falling edge impulses of the serial clock
+signal BCLK_Fall, BCLK_Rise : std_logic;
+signal BCLK_Fall_int, BCLK_Rise_int : std_logic;
+--signal BCLK_Fall_shot, BCLK_Rise_shot : std_logic;
+
+-- Synchronisation signals for Rising and Falling edge
+signal Q1R, Q2R, Q3R : std_logic;
+signal Q1F, Q2F, Q3F : std_logic;
+
+-- Internal synchronous BCLK signal
+signal BCLK_int : std_logic;
+
+-- Internal synchronous LRCLK signal
+signal LRCLK_int : std_logic;
+signal LRCLK : std_logic;
+
+--
+signal Data_Out_int : std_logic_vector(31 downto 0);
+
+--
+signal Data_In_int : std_logic_vector(31 downto 0);
+
+--
+signal D_L_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
+
+--
+signal D_R_O_int : std_logic_vector(C_DATA_WIDTH-1 downto 0);
+
+--Internal synchronous OE signals
+signal OE_R_int, OE_L_int : std_logic;
+
+--Internal synchronous WE signals
+signal WE_R_int, WE_L_int : std_logic;
+
+-- Division rate for the BCLK and LRCLK
+signal DIV_RATE : natural := 4;
+
+------------------------------------------------------------------------
+-- Module Implementation
+------------------------------------------------------------------------
+
+begin
+
+------------------------------------------------------------------------
+-- Sampling frequency and data width decoder (DIV_RATE, C_DATA_WIDTH)
+------------------------------------------------------------------------
+
+ BIT_FS: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ case (FS_I) is
+ when x"0" => DIV_RATE <= 24;
+ when x"1" => DIV_RATE <= 16;
+ when x"2" => DIV_RATE <= 12;
+ when x"3" => DIV_RATE <= 8;
+ when x"4" => DIV_RATE <= 6;
+ when x"5" => DIV_RATE <= 4;
+ when x"6" => DIV_RATE <= 2;
+ when others => DIV_RATE <= 4;
+ end case;
+ end if;
+ end process;
+
+------------------------------------------------------------------------
+-- Serial clock generator (BCLK_O, BCLK_Fall, BCLK_Rise)
+------------------------------------------------------------------------
+ SER_CLK: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Cnt_Bclk <= 0;
+ BCLK_int <= '0';
+ elsif Cnt_Bclk = ((DIV_RATE/2)-1) then
+ Cnt_Bclk <= 0;
+ BCLK_int <= not BCLK_int;
+ else
+ Cnt_Bclk <= Cnt_Bclk + 1;
+ end if;
+ end if;
+ end process SER_CLK;
+
+ -- Rising and Falling edges when in Slave mode
+ BCLK_Fall_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '1' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
+ BCLK_Rise_int <= '1' when Cnt_Bclk = ((DIV_RATE/2)-1) and BCLK_int = '0' and (EN_RX_I = '1' or EN_TX_I = '1') else '0';
+
+
+
+ -- Falling edge selection with respect to Master Mode bit
+ BCLK_Fall <= BCLK_Fall_int;
+
+ -- Risesing edge selection with respect to Master Mode bit
+ BCLK_Rise <= BCLK_Rise_int;
+
+ -- Serial clock output
+ BCLK_O <= BCLK_int when EN_RX_I = '1' or EN_TX_I = '1' else '1';
+
+------------------------------------------------------------------------
+-- Left/Right clock generator (LRCLK_O, LRCLK_Pls)
+------------------------------------------------------------------------
+ LRCLK_GEN: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Cnt_Lrclk <= 0;
+ LRCLK <= '0'; -- Left channel active by default
+ elsif BCLK_Fall = '1' then
+ if Cnt_Lrclk = 31 then -- half of frame (64 bits)
+ Cnt_Lrclk <= 0;
+ LRCLK <= not LRCLK;
+ else
+ Cnt_Lrclk <= Cnt_Lrclk + 1;
+ end if;
+ end if;
+ end if;
+ end process LRCLK_GEN;
+
+ -- L/R clock output
+ LRCLK_O <= LRCLK when EN_TX_I = '1' or EN_RX_I = '1' else '0';
+ LRCLK_int <= LRCLK;
+
+
+------------------------------------------------------------------------
+-- Load in paralled data, shift out serial data (SDATA_O)
+------------------------------------------------------------------------
+ SER_DATA_O: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Data_Out_int(31) <= '0';
+ Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I; -- Left channel data by default
+ Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
+ elsif Cnt_Lrclk = 0 and BCLK_Rise = '1' then -- load par. data
+ if LRCLK_int = '1' then
+ Data_Out_int(31) <= '0';
+ Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_R_I;
+ Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
+ else
+ Data_Out_int(31) <= '0';
+ Data_Out_int(30 downto 31-C_DATA_WIDTH) <= D_L_I;
+ Data_Out_int(30-C_DATA_WIDTH downto 0) <= (others => '0');
+ end if;
+ elsif BCLK_Fall = '1' then -- shift out ser. data
+ Data_Out_int <= Data_Out_int(30 downto 0) & '0';
+ end if;
+ end if;
+ end process SER_DATA_O;
+
+ -- Serial data output
+ SDATA_O <= Data_Out_int(31) when EN_TX_I = '1' else '0';
+
+------------------------------------------------------------------------
+-- Shift in serial data, load out parallel data (SDATA_I)
+------------------------------------------------------------------------
+ SER_DATA_I: process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ Data_In_int <= (others => '0');
+ D_L_O_int <= (others => '0');
+ D_R_O_int <= (others => '0');
+ elsif Cnt_Lrclk = 0 and BCLK_Fall = '1' then -- load par. data
+ if LRCLK_int = '1' then
+ D_L_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
+ Data_In_int <= (others => '0');
+ else
+ D_R_O_int <= Data_In_int(31 downto 32-C_DATA_WIDTH);
+ Data_In_int <= (others => '0');
+ end if;
+ elsif BCLK_Rise = '1' then -- shift in ser. data
+ Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
+ end if;
+ end if;
+ end process SER_DATA_I;
+
+ D_L_O <= D_L_O_int;
+ D_R_O <= D_R_O_int;
+
+--------------------------------------------------------------------------
+---- Output Enable signals (for FIFO)
+--------------------------------------------------------------------------
+-- OE_GEN: process(CLK_I)
+-- begin
+-- if rising_edge(CLK_I) then
+-- if Cnt_Lrclk = 31 and BCLK_Fall = '1' then
+-- if LRCLK_int = '1' then -- Right channel
+-- OE_R_int <= '1';
+-- else -- Left channel
+-- OE_L_int <= '1';
+-- end if;
+-- else
+-- OE_R_int <= '0';
+-- OE_L_int <= '0';
+-- end if;
+-- end if;
+-- end process OE_GEN;
+
+-- OE_R_O <= OE_R_int when EN_TX_I = '1' else '0';
+-- OE_L_O <= OE_L_int when EN_TX_I = '1' else '0';
+
+--------------------------------------------------------------------------
+---- Write Enable signals (for FIFO)
+--------------------------------------------------------------------------
+-- WE_GEN: process(CLK_I)
+-- begin
+-- if rising_edge(CLK_I) then
+-- if Cnt_Lrclk = 1 and BCLK_Rise = '1' then
+-- if LRCLK_int = '1' then -- Right channel
+-- WE_R_int <= '1';
+-- else -- Left channel
+-- WE_L_int <= '1';
+-- end if;
+-- else
+-- WE_R_int <= '0';
+-- WE_L_int <= '0';
+-- end if;
+-- end if;
+-- end process WE_GEN;
+
+-- WE_R_O <= WE_R_int when EN_RX_I = '1' else '0';
+-- WE_L_O <= WE_L_int when EN_RX_I = '1' else '0';
+
+end Behavioral;
+
diff --git a/tp_vivado/src/hdl/operativeUnit.vhd b/tp_vivado/src/hdl/operativeUnit.vhd
new file mode 100644
index 0000000..68bcc70
--- /dev/null
+++ b/tp_vivado/src/hdl/operativeUnit.vhd
@@ -0,0 +1,374 @@
+-------------------------------------------------------------------------------
+-- Title : operativeUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-13
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Operative unit of a sequential FIR filter. Including shift
+-- register for samples, registers for coefficients, a MAC and a register to
+-- store the result
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2019-02-13 1.1 marzel Update to provide a 16-tap filter and improve
+-- the user experience ;)
+-- 2018-04-11 1.0 jnbazin Created
+-- 2018-04-18 1.0 marzel Modification of SR_Y assignment to a round
+-- instead of a trunc
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity operativeUnit is
+
+ port (
+ I_clock : in std_logic; -- global clock
+ I_reset : in std_logic; -- asynchronous global reset
+ I_inputSample : in std_logic_vector(10 downto 0); -- 8 bit input sample
+ I_loadShift_x : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShift_y : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_loadShift_z : in std_logic; -- Control signal to load the input sample in the sample shift register and shift the register
+ I_initAddress_x : in std_logic; -- Control signal to initialize register read address
+ I_initAddress_y : in std_logic; -- Control signal to initialize register read address
+ I_initAddress_z : in std_logic; -- Control signal to initialize register read address
+ I_incrAddress_x : in std_logic; -- Control signal to increment register read address
+ I_incrAddress_y : in std_logic; -- Control signal to increment register read address
+ I_incrAddress_z : in std_logic; -- Control signal to increment register read address
+ I_initSum : in std_logic; -- Control signal to initialize the MAC register
+ I_loadSum : in std_logic; -- Control signal to load the MAC register;
+ I_loadY : in std_logic; -- Control signal to load Y register
+ I_filtre : in std_logic_vector(1 downto 0);
+ I_filtreCoef : in std_logic_vector(1 downto 0);
+ O_processingDone_y : out std_logic := '0'; -- Indicate that processing is done
+ O_processingDone_z_a : out std_logic := '0'; -- Indicate that processing is done
+ O_processingDone_z_b : out std_logic := '0'; -- Indicate that processing is done
+ O_processingDone_r : out std_logic := '0'; -- Indicate that processing is done
+ O_Y : out std_logic_vector(10 downto 0) -- filtered sample
+ );
+
+end entity operativeUnit;
+
+architecture arch_operativeUnit of operativeUnit is
+ type registerFile_x is array(0 to 94) of signed(10 downto 0);
+ type registerFile_y is array(0 to 2) of signed(10 downto 0);
+ type registerFile_z is array(0 to 10) of signed(10 downto 0);
+
+ -- COEFFICIENTS
+ signal SR_coefRegister_h : registerFile_x;
+ signal SR_coefRegister_b : registerFile_y;
+ signal SR_coefRegister_a : registerFile_y;
+ signal SR_coefRegister_g : registerFile_z;
+
+ signal SR_shiftRegister_x : registerFile_x; -- shift register file used to store and shift input samples
+ signal SR_shiftRegister_y : registerFile_y;
+ signal SR_shiftRegister_z : registerFile_z;
+
+ signal SC_multOperand1 : signed(10 downto 0);
+ signal SC_multOperand2 : signed(10 downto 0);
+ signal SC_MultResult : signed(21 downto 0); -- Result of the multiplication Xi*Hi
+ signal SC_addResult : signed(28 downto 0); -- result of the accumulation addition
+ signal SR_sum : signed(28 downto 0); -- Accumulation register
+ signal SR_Y : signed(10 downto 0); -- filtered sample storage register
+
+ -- ADDRESS GENERATORS
+ signal SR_readAddress_1 : integer range 0 to 94; -- register files read address
+ signal SR_readAddress_2 : integer range 0 to 2;
+ signal SR_readAddress_3 : integer range 0 to 2;
+ signal SR_readAddress_4 : integer range 0 to 10;
+
+begin
+
+-- BaseLine filter provided with octave (or Matlab ;)) command
+-- fir1(128, 1/100, 'high')*2^10
+ SR_coefRegister_h <= (to_signed(-1, 11), -- ROM register used file to store FIR coefficients
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-4, 11),
+ to_signed(-4, 11),
+ to_signed(-5, 11),
+ to_signed(-5, 11),
+ to_signed(-6, 11),
+ to_signed(-6, 11),
+ to_signed(-7, 11),
+ to_signed(-7, 11),
+ to_signed(-8, 11),
+ to_signed(-8, 11),
+ to_signed(-9, 11),
+ to_signed(-10, 11),
+ to_signed(-10, 11),
+ to_signed(-11, 11),
+ to_signed(-11, 11),
+ to_signed(-12, 11),
+ to_signed(-13, 11),
+ to_signed(-13, 11),
+ to_signed(-14, 11),
+ to_signed(-14, 11),
+ to_signed(-15, 11),
+ to_signed(-15, 11),
+ to_signed(-16, 11),
+ to_signed(-16, 11),
+ to_signed(-17, 11),
+ to_signed(-17, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(1004, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-19, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-18, 11),
+ to_signed(-17, 11),
+ to_signed(-17, 11),
+ to_signed(-16, 11),
+ to_signed(-16, 11),
+ to_signed(-15, 11),
+ to_signed(-15, 11),
+ to_signed(-14, 11),
+ to_signed(-14, 11),
+ to_signed(-13, 11),
+ to_signed(-13, 11),
+ to_signed(-12, 11),
+ to_signed(-11, 11),
+ to_signed(-11, 11),
+ to_signed(-10, 11),
+ to_signed(-10, 11),
+ to_signed(-9, 11),
+ to_signed(-8, 11),
+ to_signed(-8, 11),
+ to_signed(-7, 11),
+ to_signed(-7, 11),
+ to_signed(-6, 11),
+ to_signed(-6, 11),
+ to_signed(-5, 11),
+ to_signed(-5, 11),
+ to_signed(-4, 11),
+ to_signed(-4, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-3, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-2, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11),
+ to_signed(-1, 11)
+ );
+
+-- Pei Tseng Notch filter provided by octave
+-- [b, a] = pei_tseng_notch(1/5, 1/25)*2^9
+SR_coefRegister_b <= (
+ to_signed(480, 11),
+ to_signed(-777, 11),
+ to_signed(480, 11)
+ );
+
+SR_coefRegister_a <= (
+ to_signed(512, 11),
+ to_signed(-777, 11),
+ to_signed(449, 11)
+ );
+
+-- Parks McClellan filter provided by octave
+-- fLP = remez(10, [0 50 60 250]/250, [1 1 0 0])*2^10
+SR_coefRegister_g <= (
+ to_signed(-119, 11),
+ to_signed(122, 11),
+ to_signed(149, 11),
+ to_signed(191, 11),
+ to_signed(226, 11),
+ to_signed(239, 11),
+ to_signed(226, 11),
+ to_signed(191, 11),
+ to_signed(149, 11),
+ to_signed(122, 11),
+ to_signed(-119, 11)
+ );
+
+ shift : process (I_clock, I_reset) is
+ begin -- process shift
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_shiftRegister_x <= (others => (others => '0'));
+ SR_shiftRegister_y <= (others => (others => '0'));
+ SR_shiftRegister_z <= (others => (others => '0'));
+ elsif rising_edge(I_clock) then
+ if I_loadShift_x = '1' then
+ for i in 94 downto 1 loop
+ SR_shiftRegister_x(i) <= SR_shiftRegister_x(i-1);
+ end loop;
+ SR_shiftRegister_x(0) <= signed(I_inputSample);
+ end if;
+
+ if I_loadShift_y = '1' then
+ for i in 2 downto 1 loop
+ SR_shiftRegister_y(i) <= SR_shiftRegister_y(i-1);
+ end loop;
+ SR_shiftRegister_y(0) <= SR_sum(21 downto 11);
+ end if;
+
+ if I_loadShift_z = '1' then
+ for i in 10 downto 1 loop
+ SR_shiftRegister_z(i) <= SR_shiftRegister_z(i-1);
+ end loop;
+ SR_shiftRegister_z(0) <= SR_sum(21 downto 11);
+ end if;
+ end if;
+ end process shift;
+
+ incr_address : process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ -- REINITIALISATION DES ADRESSES
+ SR_readAddress_1 <= 0;
+ SR_readAddress_2 <= 0;
+ SR_readAddress_3 <= 0;
+ SR_readAddress_4 <= 0;
+ elsif rising_edge(I_clock) then
+ -- PREMIER FILTRE Y
+ if I_initAddress_x = '1' then
+ SR_readAddress_1 <= 0;
+ elsif I_incrAddress_x = '1' then
+ if SR_readAddress_1 < 94 then
+ SR_readAddress_1 <= SR_readAddress_1 + 1;
+ else
+ SR_readAddress_1 <= 0;
+ end if;
+ end if;
+
+ -- SECOND FILTRE (AVEC DEUX COEFFICIENTS)
+ if I_initAddress_y = '1' then
+ SR_readAddress_2 <= 0;
+ SR_readAddress_3 <= 0;
+ elsif I_incrAddress_y = '1' then
+ if SR_readAddress_2 < 2 then
+ SR_readAddress_2 <= SR_readAddress_2 + 1;
+ else
+ SR_readAddress_2 <= 0;
+ end if;
+
+ if SR_readAddress_3 < 2 then
+ SR_readAddress_3 <= SR_readAddress_3 + 1;
+ else
+ SR_readAddress_3 <= 0;
+ end if;
+ end if;
+
+ -- TROISIEME FILTRE
+ if I_initAddress_z = '1' then
+ SR_readAddress_4 <= 0;
+ elsif I_incrAddress_z = '1' then
+ if SR_readAddress_4 < 10 then
+ SR_readAddress_4 <= SR_readAddress_4 + 1;
+ else
+ SR_readAddress_4 <= 0;
+ end if;
+ end if;
+ end if;
+ end process incr_address;
+
+ O_processingDone_y <= '1' when SR_readAddress_1 = 94 else '0'; -- CALCUL DE Y TERMINÉ
+ O_processingDone_z_a <= '1' when SR_readAddress_2 = 2 else '0'; -- CALCUL DE Z_A TERMINÉ
+ O_processingDone_z_b <= '1' when SR_readAddress_3 = 2 else '0'; -- CALCUL DE Z_B TERMINÉ
+ O_processingDone_r <= '1' when SR_readAddress_4 = 10 else '0'; -- CALCUL DE R TERMINÉ
+
+-- A VERIFIER
+mult_choose: process (I_clock, I_reset) is
+begin
+ if I_reset = '1' then
+ SC_multOperand1 <= (others => '0');
+ SC_multOperand1(0) <= '1';
+
+ SC_multOperand2 <= (others => '0');
+ SC_multOperand2(0) <= '1';
+ else
+ case I_filtre is
+ when "00" =>
+ SC_multOperand1 <= SR_shiftRegister_x(SR_readAddress_1);
+ when "01" =>
+ SC_multOperand1 <= SR_shiftRegister_y(SR_readAddress_2);
+ when "10" =>
+ SC_multOperand1 <= SR_shiftRegister_z(SR_readAddress_4);
+ when others =>
+ SC_multOperand1 <= (others => '0');
+ SC_multOperand1(0) <= '1';
+ end case;
+
+ case I_filtreCoef is
+ when "00" =>
+ SC_multOperand2 <= SR_coefRegister_h(SR_readAddress_1);
+ when "01" =>
+ SC_multOperand2 <= SR_coefRegister_b(SR_readAddress_2);
+ when "10" =>
+ SC_multOperand2 <= SR_coefRegister_a(SR_readAddress_3);
+ when "11" =>
+ SC_multOperand2 <= SR_coefRegister_g(SR_readAddress_4);
+ when others =>
+ SC_multOperand2 <= (others => '0');
+ SC_multOperand2(0) <= '1';
+ end case;
+ end if;
+end process mult_choose;
+
+ SC_MultResult <= SC_multOperand1 * SC_multOperand2 ; -- 22 bits
+ SC_addResult <= resize(SC_MultResult, SC_addResult'length) + SR_sum;
+
+ sum_acc : process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then -- asynchronous reset (active high)
+ SR_sum <= (others => '0');
+ elsif rising_edge(I_clock) then
+ if I_initSum = '1' then
+ SR_sum <= (others => '0');
+ elsif I_loadSum = '1' then
+ SR_sum <= SC_addResult;
+ end if;
+ end if;
+ end process sum_acc;
+
+ store_result : process (I_clock, I_reset) is
+ begin
+ if I_reset = '1' then
+ SR_Y <= (others => '0');
+ elsif rising_edge(I_clock) then
+ if I_loadY = '1' then
+ SR_Y <= SC_addResult(20 downto 10);
+ end if;
+ end if;
+
+ end process store_result;
+
+ O_Y <= std_logic_vector(SR_Y);
+
+end architecture arch_operativeUnit;
diff --git a/tp_vivado/src/hdl/processingUnitIP.v b/tp_vivado/src/hdl/processingUnitIP.v
new file mode 100644
index 0000000..8ca1850
--- /dev/null
+++ b/tp_vivado/src/hdl/processingUnitIP.v
@@ -0,0 +1,3270 @@
+// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
+// Date : Mon Feb 25 17:59:18 2019
+// Host : marzel-XPS-13-9350 running 64-bit Ubuntu 18.04.2 LTS
+// Command : write_verilog
+// /home/marzel/Documents/enseignements/IMTA_ELEC_A1S2_TAF/UV_ELEC_A1S2/TP_loto_ProcSon/ProcSon/NexysVideo/src/hdl/processingUnitIP.v
+// Design : operativeUnit
+// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
+// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
+// design files.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* STRUCTURAL_NETLIST = "yes" *)
+module operativeUnit
+ (I_clock,
+ I_reset,
+ I_inputSample,
+ I_loadShift,
+ I_initAddress,
+ I_incrAddress,
+ I_initSum,
+ I_loadSum,
+ I_loadY,
+ O_processingDone,
+ O_Y);
+ input I_clock;
+ input I_reset;
+ input [7:0]I_inputSample;
+ input I_loadShift;
+ input I_initAddress;
+ input I_incrAddress;
+ input I_initSum;
+ input I_loadSum;
+ input I_loadY;
+ output O_processingDone;
+ output [7:0]O_Y;
+
+ wire \<const0> ;
+ wire \<const1> ;
+ wire I_clock;
+ wire I_clock_IBUF;
+ wire I_clock_IBUF_BUFG;
+ wire I_incrAddress;
+ wire I_incrAddress_IBUF;
+ wire I_initAddress;
+ wire I_initAddress_IBUF;
+ wire I_initSum;
+ wire I_initSum_IBUF;
+ wire [7:0]I_inputSample;
+ wire [7:0]I_inputSample_IBUF;
+ wire I_loadShift;
+ wire I_loadShift_IBUF;
+ wire I_loadSum;
+ wire I_loadSum_IBUF;
+ wire I_loadY;
+ wire I_loadY_IBUF;
+ wire I_reset;
+ wire I_reset_IBUF;
+ wire [14:7]L;
+ wire [7:0]O_Y;
+ wire [7:0]O_Y_OBUF;
+ wire O_processingDone;
+ wire O_processingDone_OBUF;
+ wire [14:0]SC_MultResult;
+ wire [4:0]SC_multOperand2;
+ wire \SR_Y[4]_i_11_n_0 ;
+ wire \SR_Y[4]_i_12_n_0 ;
+ wire \SR_Y[4]_i_13_n_0 ;
+ wire \SR_Y[4]_i_14_n_0 ;
+ wire \SR_Y[4]_i_15_n_0 ;
+ wire \SR_Y[4]_i_16_n_0 ;
+ wire \SR_Y[4]_i_17_n_0 ;
+ wire \SR_Y[4]_i_18_n_0 ;
+ wire \SR_Y[4]_i_19_n_0 ;
+ wire \SR_Y[4]_i_20_n_0 ;
+ wire \SR_Y[4]_i_21_n_0 ;
+ wire \SR_Y[4]_i_22_n_0 ;
+ wire \SR_Y[4]_i_23_n_0 ;
+ wire \SR_Y[4]_i_24_n_0 ;
+ wire \SR_Y[4]_i_25_n_0 ;
+ wire \SR_Y[4]_i_26_n_0 ;
+ wire \SR_Y[4]_i_28_n_0 ;
+ wire \SR_Y[4]_i_29_n_0 ;
+ wire \SR_Y[4]_i_30_n_0 ;
+ wire \SR_Y[4]_i_32_n_0 ;
+ wire \SR_Y[4]_i_33_n_0 ;
+ wire \SR_Y[4]_i_34_n_0 ;
+ wire \SR_Y[4]_i_35_n_0 ;
+ wire \SR_Y[4]_i_36_n_0 ;
+ wire \SR_Y[4]_i_37_n_0 ;
+ wire \SR_Y[4]_i_38_n_0 ;
+ wire \SR_Y[4]_i_39_n_0 ;
+ wire \SR_Y[4]_i_40_n_0 ;
+ wire \SR_Y[4]_i_41_n_0 ;
+ wire \SR_Y[4]_i_42_n_0 ;
+ wire \SR_Y[4]_i_43_n_0 ;
+ wire \SR_Y[4]_i_44_n_0 ;
+ wire \SR_Y[4]_i_45_n_0 ;
+ wire \SR_Y[4]_i_46_n_0 ;
+ wire \SR_Y[4]_i_47_n_0 ;
+ wire \SR_Y[4]_i_48_n_0 ;
+ wire \SR_Y[4]_i_49_n_0 ;
+ wire \SR_Y[4]_i_50_n_0 ;
+ wire \SR_Y[4]_i_51_n_0 ;
+ wire \SR_Y[4]_i_5_n_0 ;
+ wire \SR_Y[4]_i_6_n_0 ;
+ wire \SR_Y[4]_i_7_n_0 ;
+ wire \SR_Y[4]_i_8_n_0 ;
+ wire \SR_Y[7]_i_11_n_0 ;
+ wire \SR_Y[7]_i_12_n_0 ;
+ wire \SR_Y[7]_i_13_n_0 ;
+ wire \SR_Y[7]_i_15_n_0 ;
+ wire \SR_Y[7]_i_16_n_0 ;
+ wire \SR_Y[7]_i_17_n_0 ;
+ wire \SR_Y[7]_i_18_n_0 ;
+ wire \SR_Y[7]_i_19_n_0 ;
+ wire \SR_Y[7]_i_20_n_0 ;
+ wire \SR_Y[7]_i_21_n_0 ;
+ wire \SR_Y[7]_i_22_n_0 ;
+ wire \SR_Y[7]_i_25_n_0 ;
+ wire \SR_Y[7]_i_26_n_0 ;
+ wire \SR_Y[7]_i_27_n_0 ;
+ wire \SR_Y[7]_i_28_n_0 ;
+ wire \SR_Y[7]_i_3_n_0 ;
+ wire \SR_Y[7]_i_42_n_0 ;
+ wire \SR_Y[7]_i_43_n_0 ;
+ wire \SR_Y[7]_i_44_n_0 ;
+ wire \SR_Y[7]_i_45_n_0 ;
+ wire \SR_Y[7]_i_46_n_0 ;
+ wire \SR_Y[7]_i_47_n_0 ;
+ wire \SR_Y[7]_i_48_n_0 ;
+ wire \SR_Y[7]_i_49_n_0 ;
+ wire \SR_Y[7]_i_50_n_0 ;
+ wire \SR_Y[7]_i_51_n_0 ;
+ wire \SR_Y[7]_i_52_n_0 ;
+ wire \SR_Y[7]_i_53_n_0 ;
+ wire \SR_Y[7]_i_54_n_0 ;
+ wire \SR_Y[7]_i_55_n_0 ;
+ wire \SR_Y[7]_i_56_n_0 ;
+ wire \SR_Y[7]_i_57_n_0 ;
+ wire \SR_Y[7]_i_5_n_0 ;
+ wire \SR_Y[7]_i_6_n_0 ;
+ wire \SR_Y[7]_i_7_n_0 ;
+ wire \SR_Y[7]_i_9_n_0 ;
+ wire \SR_Y_reg[4]_i_10_n_0 ;
+ wire \SR_Y_reg[4]_i_10_n_1 ;
+ wire \SR_Y_reg[4]_i_10_n_2 ;
+ wire \SR_Y_reg[4]_i_10_n_3 ;
+ wire \SR_Y_reg[4]_i_27_n_0 ;
+ wire \SR_Y_reg[4]_i_27_n_1 ;
+ wire \SR_Y_reg[4]_i_27_n_2 ;
+ wire \SR_Y_reg[4]_i_27_n_3 ;
+ wire \SR_Y_reg[4]_i_27_n_4 ;
+ wire \SR_Y_reg[4]_i_27_n_5 ;
+ wire \SR_Y_reg[4]_i_27_n_6 ;
+ wire \SR_Y_reg[4]_i_27_n_7 ;
+ wire \SR_Y_reg[4]_i_2_n_0 ;
+ wire \SR_Y_reg[4]_i_2_n_1 ;
+ wire \SR_Y_reg[4]_i_2_n_2 ;
+ wire \SR_Y_reg[4]_i_2_n_3 ;
+ wire \SR_Y_reg[4]_i_3_n_0 ;
+ wire \SR_Y_reg[4]_i_3_n_1 ;
+ wire \SR_Y_reg[4]_i_3_n_2 ;
+ wire \SR_Y_reg[4]_i_3_n_3 ;
+ wire \SR_Y_reg[4]_i_3_n_5 ;
+ wire \SR_Y_reg[4]_i_4_n_0 ;
+ wire \SR_Y_reg[4]_i_4_n_1 ;
+ wire \SR_Y_reg[4]_i_4_n_2 ;
+ wire \SR_Y_reg[4]_i_4_n_3 ;
+ wire \SR_Y_reg[4]_i_9_n_0 ;
+ wire \SR_Y_reg[4]_i_9_n_1 ;
+ wire \SR_Y_reg[4]_i_9_n_2 ;
+ wire \SR_Y_reg[4]_i_9_n_3 ;
+ wire \SR_Y_reg[7]_i_10_n_0 ;
+ wire \SR_Y_reg[7]_i_10_n_1 ;
+ wire \SR_Y_reg[7]_i_10_n_2 ;
+ wire \SR_Y_reg[7]_i_10_n_3 ;
+ wire \SR_Y_reg[7]_i_10_n_4 ;
+ wire \SR_Y_reg[7]_i_10_n_5 ;
+ wire \SR_Y_reg[7]_i_10_n_6 ;
+ wire \SR_Y_reg[7]_i_10_n_7 ;
+ wire \SR_Y_reg[7]_i_14_n_1 ;
+ wire \SR_Y_reg[7]_i_14_n_3 ;
+ wire \SR_Y_reg[7]_i_14_n_6 ;
+ wire \SR_Y_reg[7]_i_14_n_7 ;
+ wire \SR_Y_reg[7]_i_2_n_2 ;
+ wire \SR_Y_reg[7]_i_2_n_3 ;
+ wire \SR_Y_reg[7]_i_33_n_0 ;
+ wire \SR_Y_reg[7]_i_34_n_0 ;
+ wire \SR_Y_reg[7]_i_35_n_0 ;
+ wire \SR_Y_reg[7]_i_36_n_0 ;
+ wire \SR_Y_reg[7]_i_38_n_0 ;
+ wire \SR_Y_reg[7]_i_39_n_0 ;
+ wire \SR_Y_reg[7]_i_40_n_0 ;
+ wire \SR_Y_reg[7]_i_41_n_0 ;
+ wire \SR_Y_reg[7]_i_4_n_1 ;
+ wire \SR_Y_reg[7]_i_4_n_2 ;
+ wire \SR_Y_reg[7]_i_4_n_3 ;
+ wire \SR_Y_reg[7]_i_8_n_2 ;
+ wire \SR_Y_reg[7]_i_8_n_3 ;
+ wire \SR_Y_reg[7]_i_8_n_5 ;
+ wire \SR_Y_reg[7]_i_8_n_6 ;
+ wire \SR_Y_reg[7]_i_8_n_7 ;
+ wire \SR_readAddress[0]_i_1_n_0 ;
+ wire \SR_readAddress[1]_i_1_n_0 ;
+ wire \SR_readAddress[2]_i_1_n_0 ;
+ wire \SR_readAddress[3]_i_1_n_0 ;
+ wire \SR_readAddress[3]_i_2_n_0 ;
+ wire [3:0]SR_readAddress_reg__0;
+ wire [7:0]\SR_shiftRegister[0] ;
+ wire [7:0]\SR_shiftRegister_reg[0]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[10]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[11]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[12]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[13]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[14]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[15]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[1]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[2]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[3]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[4]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[5]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[6]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[7]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[8]__0 ;
+ wire [7:0]\SR_shiftRegister_reg[9]__0 ;
+ wire \SR_sum[0]_i_10_n_0 ;
+ wire \SR_sum[0]_i_13_n_0 ;
+ wire \SR_sum[0]_i_14_n_0 ;
+ wire \SR_sum[0]_i_15_n_0 ;
+ wire \SR_sum[0]_i_16_n_0 ;
+ wire \SR_sum[0]_i_17_n_0 ;
+ wire \SR_sum[0]_i_18_n_0 ;
+ wire \SR_sum[0]_i_19_n_0 ;
+ wire \SR_sum[0]_i_1_n_0 ;
+ wire \SR_sum[0]_i_20_n_0 ;
+ wire \SR_sum[0]_i_21_n_0 ;
+ wire \SR_sum[0]_i_22_n_0 ;
+ wire \SR_sum[0]_i_23_n_0 ;
+ wire \SR_sum[0]_i_24_n_0 ;
+ wire \SR_sum[0]_i_25_n_0 ;
+ wire \SR_sum[0]_i_26_n_0 ;
+ wire \SR_sum[0]_i_27_n_0 ;
+ wire \SR_sum[0]_i_31_n_0 ;
+ wire \SR_sum[0]_i_32_n_0 ;
+ wire \SR_sum[0]_i_33_n_0 ;
+ wire \SR_sum[0]_i_3_n_0 ;
+ wire \SR_sum[0]_i_45_n_0 ;
+ wire \SR_sum[0]_i_46_n_0 ;
+ wire \SR_sum[0]_i_47_n_0 ;
+ wire \SR_sum[0]_i_48_n_0 ;
+ wire \SR_sum[0]_i_49_n_0 ;
+ wire \SR_sum[0]_i_4_n_0 ;
+ wire \SR_sum[0]_i_50_n_0 ;
+ wire \SR_sum[0]_i_51_n_0 ;
+ wire \SR_sum[0]_i_52_n_0 ;
+ wire \SR_sum[0]_i_53_n_0 ;
+ wire \SR_sum[0]_i_54_n_0 ;
+ wire \SR_sum[0]_i_55_n_0 ;
+ wire \SR_sum[0]_i_56_n_0 ;
+ wire \SR_sum[0]_i_57_n_0 ;
+ wire \SR_sum[0]_i_58_n_0 ;
+ wire \SR_sum[0]_i_59_n_0 ;
+ wire \SR_sum[0]_i_5_n_0 ;
+ wire \SR_sum[0]_i_60_n_0 ;
+ wire \SR_sum[0]_i_6_n_0 ;
+ wire \SR_sum[0]_i_7_n_0 ;
+ wire \SR_sum[0]_i_8_n_0 ;
+ wire \SR_sum[0]_i_9_n_0 ;
+ wire \SR_sum[12]_i_2_n_0 ;
+ wire \SR_sum[12]_i_3_n_0 ;
+ wire \SR_sum[12]_i_4_n_0 ;
+ wire \SR_sum[12]_i_5_n_0 ;
+ wire \SR_sum[12]_i_6_n_0 ;
+ wire \SR_sum[4]_i_2_n_0 ;
+ wire \SR_sum[4]_i_3_n_0 ;
+ wire \SR_sum[4]_i_4_n_0 ;
+ wire \SR_sum[4]_i_5_n_0 ;
+ wire \SR_sum[4]_i_6_n_0 ;
+ wire \SR_sum[4]_i_7_n_0 ;
+ wire \SR_sum[4]_i_8_n_0 ;
+ wire \SR_sum[4]_i_9_n_0 ;
+ wire \SR_sum[8]_i_2_n_0 ;
+ wire \SR_sum[8]_i_3_n_0 ;
+ wire \SR_sum[8]_i_4_n_0 ;
+ wire \SR_sum[8]_i_5_n_0 ;
+ wire \SR_sum[8]_i_6_n_0 ;
+ wire \SR_sum[8]_i_7_n_0 ;
+ wire \SR_sum[8]_i_8_n_0 ;
+ wire \SR_sum[8]_i_9_n_0 ;
+ wire [14:0]SR_sum_reg;
+ wire \SR_sum_reg[0]_i_11_n_0 ;
+ wire \SR_sum_reg[0]_i_11_n_1 ;
+ wire \SR_sum_reg[0]_i_11_n_2 ;
+ wire \SR_sum_reg[0]_i_11_n_3 ;
+ wire \SR_sum_reg[0]_i_11_n_4 ;
+ wire \SR_sum_reg[0]_i_11_n_5 ;
+ wire \SR_sum_reg[0]_i_11_n_6 ;
+ wire \SR_sum_reg[0]_i_11_n_7 ;
+ wire \SR_sum_reg[0]_i_12_n_0 ;
+ wire \SR_sum_reg[0]_i_12_n_1 ;
+ wire \SR_sum_reg[0]_i_12_n_2 ;
+ wire \SR_sum_reg[0]_i_12_n_3 ;
+ wire \SR_sum_reg[0]_i_12_n_4 ;
+ wire \SR_sum_reg[0]_i_2_n_0 ;
+ wire \SR_sum_reg[0]_i_2_n_1 ;
+ wire \SR_sum_reg[0]_i_2_n_2 ;
+ wire \SR_sum_reg[0]_i_2_n_3 ;
+ wire \SR_sum_reg[0]_i_2_n_4 ;
+ wire \SR_sum_reg[0]_i_2_n_5 ;
+ wire \SR_sum_reg[0]_i_2_n_6 ;
+ wire \SR_sum_reg[0]_i_2_n_7 ;
+ wire \SR_sum_reg[0]_i_37_n_0 ;
+ wire \SR_sum_reg[0]_i_38_n_0 ;
+ wire \SR_sum_reg[0]_i_39_n_0 ;
+ wire \SR_sum_reg[0]_i_40_n_0 ;
+ wire \SR_sum_reg[0]_i_41_n_0 ;
+ wire \SR_sum_reg[0]_i_42_n_0 ;
+ wire \SR_sum_reg[0]_i_43_n_0 ;
+ wire \SR_sum_reg[0]_i_44_n_0 ;
+ wire \SR_sum_reg[12]_i_1_n_2 ;
+ wire \SR_sum_reg[12]_i_1_n_3 ;
+ wire \SR_sum_reg[12]_i_1_n_5 ;
+ wire \SR_sum_reg[12]_i_1_n_6 ;
+ wire \SR_sum_reg[12]_i_1_n_7 ;
+ wire \SR_sum_reg[4]_i_1_n_0 ;
+ wire \SR_sum_reg[4]_i_1_n_1 ;
+ wire \SR_sum_reg[4]_i_1_n_2 ;
+ wire \SR_sum_reg[4]_i_1_n_3 ;
+ wire \SR_sum_reg[4]_i_1_n_4 ;
+ wire \SR_sum_reg[4]_i_1_n_5 ;
+ wire \SR_sum_reg[4]_i_1_n_6 ;
+ wire \SR_sum_reg[4]_i_1_n_7 ;
+ wire \SR_sum_reg[8]_i_1_n_0 ;
+ wire \SR_sum_reg[8]_i_1_n_1 ;
+ wire \SR_sum_reg[8]_i_1_n_2 ;
+ wire \SR_sum_reg[8]_i_1_n_3 ;
+ wire \SR_sum_reg[8]_i_1_n_4 ;
+ wire \SR_sum_reg[8]_i_1_n_5 ;
+ wire \SR_sum_reg[8]_i_1_n_6 ;
+ wire \SR_sum_reg[8]_i_1_n_7 ;
+ wire [7:0]p_0_in;
+ wire [3:0]\NLW_SR_Y_reg[4]_i_10_O_UNCONNECTED ;
+ wire [3:0]\NLW_SR_Y_reg[4]_i_3_O_UNCONNECTED ;
+ wire [3:0]\NLW_SR_Y_reg[7]_i_14_CO_UNCONNECTED ;
+
+ GND GND
+ (.G(\<const0> ));
+ BUFG I_clock_IBUF_BUFG_inst
+ (.I(I_clock_IBUF),
+ .O(I_clock_IBUF_BUFG));
+ IBUF I_clock_IBUF_inst
+ (.I(I_clock),
+ .O(I_clock_IBUF));
+ IBUF I_incrAddress_IBUF_inst
+ (.I(I_incrAddress),
+ .O(I_incrAddress_IBUF));
+ IBUF I_initAddress_IBUF_inst
+ (.I(I_initAddress),
+ .O(I_initAddress_IBUF));
+ IBUF I_initSum_IBUF_inst
+ (.I(I_initSum),
+ .O(I_initSum_IBUF));
+ IBUF \I_inputSample_IBUF[0]_inst
+ (.I(I_inputSample[0]),
+ .O(I_inputSample_IBUF[0]));
+ IBUF \I_inputSample_IBUF[1]_inst
+ (.I(I_inputSample[1]),
+ .O(I_inputSample_IBUF[1]));
+ IBUF \I_inputSample_IBUF[2]_inst
+ (.I(I_inputSample[2]),
+ .O(I_inputSample_IBUF[2]));
+ IBUF \I_inputSample_IBUF[3]_inst
+ (.I(I_inputSample[3]),
+ .O(I_inputSample_IBUF[3]));
+ IBUF \I_inputSample_IBUF[4]_inst
+ (.I(I_inputSample[4]),
+ .O(I_inputSample_IBUF[4]));
+ IBUF \I_inputSample_IBUF[5]_inst
+ (.I(I_inputSample[5]),
+ .O(I_inputSample_IBUF[5]));
+ IBUF \I_inputSample_IBUF[6]_inst
+ (.I(I_inputSample[6]),
+ .O(I_inputSample_IBUF[6]));
+ IBUF \I_inputSample_IBUF[7]_inst
+ (.I(I_inputSample[7]),
+ .O(I_inputSample_IBUF[7]));
+ IBUF I_loadShift_IBUF_inst
+ (.I(I_loadShift),
+ .O(I_loadShift_IBUF));
+ IBUF I_loadSum_IBUF_inst
+ (.I(I_loadSum),
+ .O(I_loadSum_IBUF));
+ IBUF I_loadY_IBUF_inst
+ (.I(I_loadY),
+ .O(I_loadY_IBUF));
+ IBUF I_reset_IBUF_inst
+ (.I(I_reset),
+ .O(I_reset_IBUF));
+ OBUF \O_Y_OBUF[0]_inst
+ (.I(O_Y_OBUF[0]),
+ .O(O_Y[0]));
+ OBUF \O_Y_OBUF[1]_inst
+ (.I(O_Y_OBUF[1]),
+ .O(O_Y[1]));
+ OBUF \O_Y_OBUF[2]_inst
+ (.I(O_Y_OBUF[2]),
+ .O(O_Y[2]));
+ OBUF \O_Y_OBUF[3]_inst
+ (.I(O_Y_OBUF[3]),
+ .O(O_Y[3]));
+ OBUF \O_Y_OBUF[4]_inst
+ (.I(O_Y_OBUF[4]),
+ .O(O_Y[4]));
+ OBUF \O_Y_OBUF[5]_inst
+ (.I(O_Y_OBUF[5]),
+ .O(O_Y[5]));
+ OBUF \O_Y_OBUF[6]_inst
+ (.I(O_Y_OBUF[6]),
+ .O(O_Y[6]));
+ OBUF \O_Y_OBUF[7]_inst
+ (.I(O_Y_OBUF[7]),
+ .O(O_Y[7]));
+ OBUF O_processingDone_OBUF_inst
+ (.I(O_processingDone_OBUF),
+ .O(O_processingDone));
+ LUT3 #(
+ .INIT(8'h80))
+ O_processingDone_OBUF_inst_i_1
+ (.I0(SR_readAddress_reg__0[1]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[2]),
+ .O(O_processingDone_OBUF));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[0]_i_1
+ (.I0(\SR_Y_reg[4]_i_3_n_5 ),
+ .I1(L[7]),
+ .O(p_0_in[0]));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'h78))
+ \SR_Y[1]_i_1
+ (.I0(\SR_Y_reg[4]_i_3_n_5 ),
+ .I1(L[7]),
+ .I2(L[8]),
+ .O(p_0_in[1]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT4 #(
+ .INIT(16'h7F80))
+ \SR_Y[2]_i_1
+ (.I0(L[7]),
+ .I1(\SR_Y_reg[4]_i_3_n_5 ),
+ .I2(L[8]),
+ .I3(L[9]),
+ .O(p_0_in[2]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT5 #(
+ .INIT(32'h7FFF8000))
+ \SR_Y[3]_i_1
+ (.I0(L[8]),
+ .I1(\SR_Y_reg[4]_i_3_n_5 ),
+ .I2(L[7]),
+ .I3(L[9]),
+ .I4(L[10]),
+ .O(p_0_in[3]));
+ LUT6 #(
+ .INIT(64'h7FFFFFFF80000000))
+ \SR_Y[4]_i_1
+ (.I0(L[9]),
+ .I1(L[7]),
+ .I2(\SR_Y_reg[4]_i_3_n_5 ),
+ .I3(L[8]),
+ .I4(L[10]),
+ .I5(L[11]),
+ .O(p_0_in[4]));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_11
+ (.I0(SC_MultResult[7]),
+ .I1(SR_sum_reg[7]),
+ .O(\SR_Y[4]_i_11_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_12
+ (.I0(SC_MultResult[6]),
+ .I1(SR_sum_reg[6]),
+ .O(\SR_Y[4]_i_12_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_13
+ (.I0(SC_MultResult[5]),
+ .I1(SR_sum_reg[5]),
+ .O(\SR_Y[4]_i_13_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_14
+ (.I0(SC_MultResult[4]),
+ .I1(SR_sum_reg[4]),
+ .O(\SR_Y[4]_i_14_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \SR_Y[4]_i_15
+ (.I0(\SR_Y_reg[7]_i_10_n_5 ),
+ .I1(\SR_Y_reg[7]_i_14_n_6 ),
+ .O(\SR_Y[4]_i_15_n_0 ));
+ LUT2 #(
+ .INIT(4'h8))
+ \SR_Y[4]_i_16
+ (.I0(\SR_Y_reg[7]_i_10_n_6 ),
+ .I1(\SR_Y_reg[7]_i_14_n_7 ),
+ .O(\SR_Y[4]_i_16_n_0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \SR_Y[4]_i_17
+ (.I0(\SR_Y_reg[4]_i_27_n_4 ),
+ .I1(\SR_Y_reg[7]_i_10_n_7 ),
+ .O(\SR_Y[4]_i_17_n_0 ));
+ LUT2 #(
+ .INIT(4'h9))
+ \SR_Y[4]_i_18
+ (.I0(\SR_Y_reg[7]_i_10_n_7 ),
+ .I1(\SR_Y_reg[4]_i_27_n_4 ),
+ .O(\SR_Y[4]_i_18_n_0 ));
+ LUT4 #(
+ .INIT(16'h8778))
+ \SR_Y[4]_i_19
+ (.I0(\SR_Y_reg[7]_i_14_n_6 ),
+ .I1(\SR_Y_reg[7]_i_10_n_5 ),
+ .I2(\SR_Y_reg[7]_i_10_n_4 ),
+ .I3(\SR_Y_reg[7]_i_14_n_1 ),
+ .O(\SR_Y[4]_i_19_n_0 ));
+ LUT4 #(
+ .INIT(16'h8778))
+ \SR_Y[4]_i_20
+ (.I0(\SR_Y_reg[7]_i_14_n_7 ),
+ .I1(\SR_Y_reg[7]_i_10_n_6 ),
+ .I2(\SR_Y_reg[7]_i_10_n_5 ),
+ .I3(\SR_Y_reg[7]_i_14_n_6 ),
+ .O(\SR_Y[4]_i_20_n_0 ));
+ LUT4 #(
+ .INIT(16'hE11E))
+ \SR_Y[4]_i_21
+ (.I0(\SR_Y_reg[7]_i_10_n_7 ),
+ .I1(\SR_Y_reg[4]_i_27_n_4 ),
+ .I2(\SR_Y_reg[7]_i_10_n_6 ),
+ .I3(\SR_Y_reg[7]_i_14_n_7 ),
+ .O(\SR_Y[4]_i_21_n_0 ));
+ LUT4 #(
+ .INIT(16'h6999))
+ \SR_Y[4]_i_22
+ (.I0(\SR_Y_reg[7]_i_10_n_7 ),
+ .I1(\SR_Y_reg[4]_i_27_n_4 ),
+ .I2(\SR_Y_reg[4]_i_27_n_5 ),
+ .I3(\SR_sum_reg[0]_i_11_n_4 ),
+ .O(\SR_Y[4]_i_22_n_0 ));
+ LUT3 #(
+ .INIT(8'h96))
+ \SR_Y[4]_i_23
+ (.I0(\SR_sum_reg[0]_i_11_n_7 ),
+ .I1(\SR_sum_reg[0]_i_12_n_4 ),
+ .I2(SR_sum_reg[3]),
+ .O(\SR_Y[4]_i_23_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_24
+ (.I0(SC_MultResult[2]),
+ .I1(SR_sum_reg[2]),
+ .O(\SR_Y[4]_i_24_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_25
+ (.I0(SC_MultResult[1]),
+ .I1(SR_sum_reg[1]),
+ .O(\SR_Y[4]_i_25_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_26
+ (.I0(SC_MultResult[0]),
+ .I1(SR_sum_reg[0]),
+ .O(\SR_Y[4]_i_26_n_0 ));
+ LUT3 #(
+ .INIT(8'h96))
+ \SR_Y[4]_i_28
+ (.I0(\SR_sum_reg[0]_i_11_n_5 ),
+ .I1(\SR_sum_reg[0]_i_11_n_4 ),
+ .I2(\SR_Y_reg[4]_i_27_n_5 ),
+ .O(\SR_Y[4]_i_28_n_0 ));
+ LUT2 #(
+ .INIT(4'h9))
+ \SR_Y[4]_i_29
+ (.I0(\SR_sum_reg[0]_i_11_n_5 ),
+ .I1(\SR_Y_reg[4]_i_27_n_6 ),
+ .O(\SR_Y[4]_i_29_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_30
+ (.I0(\SR_Y_reg[4]_i_27_n_7 ),
+ .I1(\SR_sum_reg[0]_i_11_n_6 ),
+ .O(\SR_Y[4]_i_30_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_31
+ (.I0(\SR_sum_reg[0]_i_12_n_4 ),
+ .I1(\SR_sum_reg[0]_i_11_n_7 ),
+ .O(SC_MultResult[3]));
+ LUT3 #(
+ .INIT(8'h17))
+ \SR_Y[4]_i_32
+ (.I0(\SR_Y[4]_i_40_n_0 ),
+ .I1(\SR_Y[4]_i_41_n_0 ),
+ .I2(\SR_Y[4]_i_42_n_0 ),
+ .O(\SR_Y[4]_i_32_n_0 ));
+ LUT3 #(
+ .INIT(8'h17))
+ \SR_Y[4]_i_33
+ (.I0(\SR_Y[4]_i_43_n_0 ),
+ .I1(\SR_Y[4]_i_44_n_0 ),
+ .I2(\SR_Y[4]_i_45_n_0 ),
+ .O(\SR_Y[4]_i_33_n_0 ));
+ LUT3 #(
+ .INIT(8'h17))
+ \SR_Y[4]_i_34
+ (.I0(\SR_Y[4]_i_46_n_0 ),
+ .I1(\SR_Y[4]_i_47_n_0 ),
+ .I2(\SR_Y[4]_i_48_n_0 ),
+ .O(\SR_Y[4]_i_34_n_0 ));
+ LUT3 #(
+ .INIT(8'h17))
+ \SR_Y[4]_i_35
+ (.I0(\SR_sum[0]_i_32_n_0 ),
+ .I1(\SR_sum[0]_i_31_n_0 ),
+ .I2(\SR_sum[0]_i_33_n_0 ),
+ .O(\SR_Y[4]_i_35_n_0 ));
+ LUT4 #(
+ .INIT(16'h6996))
+ \SR_Y[4]_i_36
+ (.I0(\SR_Y[4]_i_32_n_0 ),
+ .I1(\SR_Y[4]_i_49_n_0 ),
+ .I2(\SR_Y[4]_i_50_n_0 ),
+ .I3(\SR_Y[4]_i_51_n_0 ),
+ .O(\SR_Y[4]_i_36_n_0 ));
+ LUT6 #(
+ .INIT(64'h17E8E817E81717E8))
+ \SR_Y[4]_i_37
+ (.I0(\SR_Y[4]_i_45_n_0 ),
+ .I1(\SR_Y[4]_i_44_n_0 ),
+ .I2(\SR_Y[4]_i_43_n_0 ),
+ .I3(\SR_Y[4]_i_41_n_0 ),
+ .I4(\SR_Y[4]_i_40_n_0 ),
+ .I5(\SR_Y[4]_i_42_n_0 ),
+ .O(\SR_Y[4]_i_37_n_0 ));
+ LUT6 #(
+ .INIT(64'h17E8E817E81717E8))
+ \SR_Y[4]_i_38
+ (.I0(\SR_Y[4]_i_48_n_0 ),
+ .I1(\SR_Y[4]_i_47_n_0 ),
+ .I2(\SR_Y[4]_i_46_n_0 ),
+ .I3(\SR_Y[4]_i_44_n_0 ),
+ .I4(\SR_Y[4]_i_43_n_0 ),
+ .I5(\SR_Y[4]_i_45_n_0 ),
+ .O(\SR_Y[4]_i_38_n_0 ));
+ LUT6 #(
+ .INIT(64'h17E8E817E81717E8))
+ \SR_Y[4]_i_39
+ (.I0(\SR_sum[0]_i_33_n_0 ),
+ .I1(\SR_sum[0]_i_31_n_0 ),
+ .I2(\SR_sum[0]_i_32_n_0 ),
+ .I3(\SR_Y[4]_i_47_n_0 ),
+ .I4(\SR_Y[4]_i_46_n_0 ),
+ .I5(\SR_Y[4]_i_48_n_0 ),
+ .O(\SR_Y[4]_i_39_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT5 #(
+ .INIT(32'hF5FD7F5F))
+ \SR_Y[4]_i_40
+ (.I0(\SR_shiftRegister[0] [4]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_40_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'h557D7D55))
+ \SR_Y[4]_i_41
+ (.I0(\SR_shiftRegister[0] [5]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_Y[4]_i_41_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'hFF7D7DFF))
+ \SR_Y[4]_i_42
+ (.I0(\SR_shiftRegister[0] [6]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_42_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT5 #(
+ .INIT(32'hF5FD7F5F))
+ \SR_Y[4]_i_43
+ (.I0(\SR_shiftRegister[0] [3]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_43_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT5 #(
+ .INIT(32'h557D7D55))
+ \SR_Y[4]_i_44
+ (.I0(\SR_shiftRegister[0] [4]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_Y[4]_i_44_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'hFF7D7DFF))
+ \SR_Y[4]_i_45
+ (.I0(\SR_shiftRegister[0] [5]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_45_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'hF5FD7F5F))
+ \SR_Y[4]_i_46
+ (.I0(\SR_shiftRegister[0] [2]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_46_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT5 #(
+ .INIT(32'h557D7D55))
+ \SR_Y[4]_i_47
+ (.I0(\SR_shiftRegister[0] [3]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_Y[4]_i_47_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT5 #(
+ .INIT(32'hFF7D7DFF))
+ \SR_Y[4]_i_48
+ (.I0(\SR_shiftRegister[0] [4]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_48_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h557D7D55))
+ \SR_Y[4]_i_49
+ (.I0(\SR_shiftRegister[0] [6]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_Y[4]_i_49_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_5
+ (.I0(SC_MultResult[11]),
+ .I1(SR_sum_reg[11]),
+ .O(\SR_Y[4]_i_5_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT5 #(
+ .INIT(32'hF5FD7F5F))
+ \SR_Y[4]_i_50
+ (.I0(\SR_shiftRegister[0] [5]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_50_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT5 #(
+ .INIT(32'hFF7D7DFF))
+ \SR_Y[4]_i_51
+ (.I0(\SR_shiftRegister[0] [7]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_Y[4]_i_51_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_6
+ (.I0(SC_MultResult[10]),
+ .I1(SR_sum_reg[10]),
+ .O(\SR_Y[4]_i_6_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_7
+ (.I0(SC_MultResult[9]),
+ .I1(SR_sum_reg[9]),
+ .O(\SR_Y[4]_i_7_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[4]_i_8
+ (.I0(SC_MultResult[8]),
+ .I1(SR_sum_reg[8]),
+ .O(\SR_Y[4]_i_8_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[5]_i_1
+ (.I0(\SR_Y[7]_i_3_n_0 ),
+ .I1(L[12]),
+ .O(p_0_in[5]));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'h78))
+ \SR_Y[6]_i_1
+ (.I0(\SR_Y[7]_i_3_n_0 ),
+ .I1(L[12]),
+ .I2(L[13]),
+ .O(p_0_in[6]));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'h7F80))
+ \SR_Y[7]_i_1
+ (.I0(L[12]),
+ .I1(\SR_Y[7]_i_3_n_0 ),
+ .I2(L[13]),
+ .I3(L[14]),
+ .O(p_0_in[7]));
+ LUT6 #(
+ .INIT(64'hFFF55FFFDDF55F77))
+ \SR_Y[7]_i_11
+ (.I0(\SR_shiftRegister[0] [7]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [6]),
+ .O(\SR_Y[7]_i_11_n_0 ));
+ LUT5 #(
+ .INIT(32'hFDDD777F))
+ \SR_Y[7]_i_12
+ (.I0(\SR_shiftRegister[0] [7]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_Y[7]_i_12_n_0 ));
+ LUT6 #(
+ .INIT(64'hDDC00377FFFFFFFF))
+ \SR_Y[7]_i_13
+ (.I0(\SR_shiftRegister[0] [6]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [7]),
+ .O(\SR_Y[7]_i_13_n_0 ));
+ LUT6 #(
+ .INIT(64'h333AACCC220AA088))
+ \SR_Y[7]_i_15
+ (.I0(\SR_shiftRegister[0] [6]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [5]),
+ .O(\SR_Y[7]_i_15_n_0 ));
+ LUT6 #(
+ .INIT(64'h333AACCC220AA088))
+ \SR_Y[7]_i_16
+ (.I0(\SR_shiftRegister[0] [5]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [4]),
+ .O(\SR_Y[7]_i_16_n_0 ));
+ LUT6 #(
+ .INIT(64'h333AACCC220AA088))
+ \SR_Y[7]_i_17
+ (.I0(\SR_shiftRegister[0] [4]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [3]),
+ .O(\SR_Y[7]_i_17_n_0 ));
+ LUT6 #(
+ .INIT(64'h333AACCC220AA088))
+ \SR_Y[7]_i_18
+ (.I0(\SR_shiftRegister[0] [3]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [2]),
+ .O(\SR_Y[7]_i_18_n_0 ));
+ LUT5 #(
+ .INIT(32'hD32C6060))
+ \SR_Y[7]_i_19
+ (.I0(\SR_shiftRegister[0] [5]),
+ .I1(\SR_shiftRegister[0] [6]),
+ .I2(SC_multOperand2[4]),
+ .I3(\SR_shiftRegister[0] [7]),
+ .I4(SC_multOperand2[3]),
+ .O(\SR_Y[7]_i_19_n_0 ));
+ LUT5 #(
+ .INIT(32'h2CD39F9F))
+ \SR_Y[7]_i_20
+ (.I0(\SR_shiftRegister[0] [4]),
+ .I1(\SR_shiftRegister[0] [5]),
+ .I2(SC_multOperand2[4]),
+ .I3(\SR_shiftRegister[0] [6]),
+ .I4(SC_multOperand2[3]),
+ .O(\SR_Y[7]_i_20_n_0 ));
+ LUT5 #(
+ .INIT(32'h2CD39F9F))
+ \SR_Y[7]_i_21
+ (.I0(\SR_shiftRegister[0] [3]),
+ .I1(\SR_shiftRegister[0] [4]),
+ .I2(SC_multOperand2[4]),
+ .I3(\SR_shiftRegister[0] [5]),
+ .I4(SC_multOperand2[3]),
+ .O(\SR_Y[7]_i_21_n_0 ));
+ LUT5 #(
+ .INIT(32'h2CD39F9F))
+ \SR_Y[7]_i_22
+ (.I0(\SR_shiftRegister[0] [2]),
+ .I1(\SR_shiftRegister[0] [3]),
+ .I2(SC_multOperand2[4]),
+ .I3(\SR_shiftRegister[0] [4]),
+ .I4(SC_multOperand2[3]),
+ .O(\SR_Y[7]_i_22_n_0 ));
+ LUT6 #(
+ .INIT(64'h134001C400000000))
+ \SR_Y[7]_i_25
+ (.I0(\SR_shiftRegister[0] [7]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[3]),
+ .I5(\SR_shiftRegister[0] [6]),
+ .O(\SR_Y[7]_i_25_n_0 ));
+ LUT3 #(
+ .INIT(8'h71))
+ \SR_Y[7]_i_26
+ (.I0(\SR_Y[4]_i_50_n_0 ),
+ .I1(\SR_Y[4]_i_49_n_0 ),
+ .I2(\SR_Y[4]_i_51_n_0 ),
+ .O(\SR_Y[7]_i_26_n_0 ));
+ LUT6 #(
+ .INIT(64'hCE3FFCB3DD7FFD77))
+ \SR_Y[7]_i_27
+ (.I0(\SR_shiftRegister[0] [6]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[3]),
+ .I5(\SR_shiftRegister[0] [7]),
+ .O(\SR_Y[7]_i_27_n_0 ));
+ LUT6 #(
+ .INIT(64'h8171FC0C1EEE3CCC))
+ \SR_Y[7]_i_28
+ (.I0(SC_multOperand2[0]),
+ .I1(\SR_Y[4]_i_50_n_0 ),
+ .I2(\SR_shiftRegister[0] [6]),
+ .I3(SC_multOperand2[2]),
+ .I4(\SR_shiftRegister[0] [7]),
+ .I5(SC_multOperand2[1]),
+ .O(\SR_Y[7]_i_28_n_0 ));
+ LUT6 #(
+ .INIT(64'h8000000000000000))
+ \SR_Y[7]_i_3
+ (.I0(L[11]),
+ .I1(L[9]),
+ .I2(L[7]),
+ .I3(\SR_Y_reg[4]_i_3_n_5 ),
+ .I4(L[8]),
+ .I5(L[10]),
+ .O(\SR_Y[7]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h542A))
+ \SR_Y[7]_i_31
+ (.I0(SR_readAddress_reg__0[3]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .O(SC_multOperand2[4]));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT4 #(
+ .INIT(16'h724E))
+ \SR_Y[7]_i_32
+ (.I0(SR_readAddress_reg__0[3]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .O(SC_multOperand2[3]));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT4 #(
+ .INIT(16'h6006))
+ \SR_Y[7]_i_37
+ (.I0(SR_readAddress_reg__0[2]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[1]),
+ .O(SC_multOperand2[0]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_42
+ (.I0(\SR_shiftRegister_reg[3]__0 [7]),
+ .I1(\SR_shiftRegister_reg[2]__0 [7]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [7]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [7]),
+ .O(\SR_Y[7]_i_42_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_43
+ (.I0(\SR_shiftRegister_reg[7]__0 [7]),
+ .I1(\SR_shiftRegister_reg[6]__0 [7]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [7]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [7]),
+ .O(\SR_Y[7]_i_43_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_44
+ (.I0(\SR_shiftRegister_reg[11]__0 [7]),
+ .I1(\SR_shiftRegister_reg[10]__0 [7]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [7]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [7]),
+ .O(\SR_Y[7]_i_44_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_45
+ (.I0(\SR_shiftRegister_reg[15]__0 [7]),
+ .I1(\SR_shiftRegister_reg[14]__0 [7]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [7]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [7]),
+ .O(\SR_Y[7]_i_45_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_46
+ (.I0(\SR_shiftRegister_reg[3]__0 [6]),
+ .I1(\SR_shiftRegister_reg[2]__0 [6]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [6]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [6]),
+ .O(\SR_Y[7]_i_46_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_47
+ (.I0(\SR_shiftRegister_reg[7]__0 [6]),
+ .I1(\SR_shiftRegister_reg[6]__0 [6]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [6]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [6]),
+ .O(\SR_Y[7]_i_47_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_48
+ (.I0(\SR_shiftRegister_reg[11]__0 [6]),
+ .I1(\SR_shiftRegister_reg[10]__0 [6]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [6]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [6]),
+ .O(\SR_Y[7]_i_48_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_49
+ (.I0(\SR_shiftRegister_reg[15]__0 [6]),
+ .I1(\SR_shiftRegister_reg[14]__0 [6]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [6]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [6]),
+ .O(\SR_Y[7]_i_49_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[7]_i_5
+ (.I0(SR_sum_reg[14]),
+ .I1(SC_MultResult[14]),
+ .O(\SR_Y[7]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_50
+ (.I0(\SR_shiftRegister_reg[3]__0 [5]),
+ .I1(\SR_shiftRegister_reg[2]__0 [5]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [5]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [5]),
+ .O(\SR_Y[7]_i_50_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_51
+ (.I0(\SR_shiftRegister_reg[7]__0 [5]),
+ .I1(\SR_shiftRegister_reg[6]__0 [5]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [5]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [5]),
+ .O(\SR_Y[7]_i_51_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_52
+ (.I0(\SR_shiftRegister_reg[11]__0 [5]),
+ .I1(\SR_shiftRegister_reg[10]__0 [5]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [5]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [5]),
+ .O(\SR_Y[7]_i_52_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_53
+ (.I0(\SR_shiftRegister_reg[15]__0 [5]),
+ .I1(\SR_shiftRegister_reg[14]__0 [5]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [5]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [5]),
+ .O(\SR_Y[7]_i_53_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_54
+ (.I0(\SR_shiftRegister_reg[3]__0 [4]),
+ .I1(\SR_shiftRegister_reg[2]__0 [4]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [4]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [4]),
+ .O(\SR_Y[7]_i_54_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_55
+ (.I0(\SR_shiftRegister_reg[7]__0 [4]),
+ .I1(\SR_shiftRegister_reg[6]__0 [4]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [4]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [4]),
+ .O(\SR_Y[7]_i_55_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_56
+ (.I0(\SR_shiftRegister_reg[11]__0 [4]),
+ .I1(\SR_shiftRegister_reg[10]__0 [4]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [4]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [4]),
+ .O(\SR_Y[7]_i_56_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_Y[7]_i_57
+ (.I0(\SR_shiftRegister_reg[15]__0 [4]),
+ .I1(\SR_shiftRegister_reg[14]__0 [4]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [4]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [4]),
+ .O(\SR_Y[7]_i_57_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[7]_i_6
+ (.I0(SC_MultResult[13]),
+ .I1(SR_sum_reg[13]),
+ .O(\SR_Y[7]_i_6_n_0 ));
+ LUT2 #(
+ .INIT(4'h6))
+ \SR_Y[7]_i_7
+ (.I0(SC_MultResult[12]),
+ .I1(SR_sum_reg[12]),
+ .O(\SR_Y[7]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'h78))
+ \SR_Y[7]_i_9
+ (.I0(\SR_Y_reg[7]_i_14_n_1 ),
+ .I1(\SR_Y_reg[7]_i_10_n_4 ),
+ .I2(\SR_Y_reg[7]_i_8_n_7 ),
+ .O(\SR_Y[7]_i_9_n_0 ));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[0]),
+ .Q(O_Y_OBUF[0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[1]),
+ .Q(O_Y_OBUF[1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[2]),
+ .Q(O_Y_OBUF[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[3]),
+ .Q(O_Y_OBUF[3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[4]),
+ .Q(O_Y_OBUF[4]));
+ CARRY4 \SR_Y_reg[4]_i_10
+ (.CI(\<const0> ),
+ .CO({\SR_Y_reg[4]_i_10_n_0 ,\SR_Y_reg[4]_i_10_n_1 ,\SR_Y_reg[4]_i_10_n_2 ,\SR_Y_reg[4]_i_10_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_sum_reg[0]_i_11_n_5 ,\SR_Y_reg[4]_i_27_n_6 ,\SR_Y_reg[4]_i_27_n_7 ,\SR_sum_reg[0]_i_12_n_4 }),
+ .O({SC_MultResult[6:4],\NLW_SR_Y_reg[4]_i_10_O_UNCONNECTED [0]}),
+ .S({\SR_Y[4]_i_28_n_0 ,\SR_Y[4]_i_29_n_0 ,\SR_Y[4]_i_30_n_0 ,SC_MultResult[3]}));
+ CARRY4 \SR_Y_reg[4]_i_2
+ (.CI(\SR_Y_reg[4]_i_3_n_0 ),
+ .CO({\SR_Y_reg[4]_i_2_n_0 ,\SR_Y_reg[4]_i_2_n_1 ,\SR_Y_reg[4]_i_2_n_2 ,\SR_Y_reg[4]_i_2_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI(SC_MultResult[11:8]),
+ .O(L[11:8]),
+ .S({\SR_Y[4]_i_5_n_0 ,\SR_Y[4]_i_6_n_0 ,\SR_Y[4]_i_7_n_0 ,\SR_Y[4]_i_8_n_0 }));
+ CARRY4 \SR_Y_reg[4]_i_27
+ (.CI(\SR_sum_reg[0]_i_12_n_0 ),
+ .CO({\SR_Y_reg[4]_i_27_n_0 ,\SR_Y_reg[4]_i_27_n_1 ,\SR_Y_reg[4]_i_27_n_2 ,\SR_Y_reg[4]_i_27_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_Y[4]_i_32_n_0 ,\SR_Y[4]_i_33_n_0 ,\SR_Y[4]_i_34_n_0 ,\SR_Y[4]_i_35_n_0 }),
+ .O({\SR_Y_reg[4]_i_27_n_4 ,\SR_Y_reg[4]_i_27_n_5 ,\SR_Y_reg[4]_i_27_n_6 ,\SR_Y_reg[4]_i_27_n_7 }),
+ .S({\SR_Y[4]_i_36_n_0 ,\SR_Y[4]_i_37_n_0 ,\SR_Y[4]_i_38_n_0 ,\SR_Y[4]_i_39_n_0 }));
+ CARRY4 \SR_Y_reg[4]_i_3
+ (.CI(\SR_Y_reg[4]_i_9_n_0 ),
+ .CO({\SR_Y_reg[4]_i_3_n_0 ,\SR_Y_reg[4]_i_3_n_1 ,\SR_Y_reg[4]_i_3_n_2 ,\SR_Y_reg[4]_i_3_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI(SC_MultResult[7:4]),
+ .O({L[7],\SR_Y_reg[4]_i_3_n_5 ,\NLW_SR_Y_reg[4]_i_3_O_UNCONNECTED [1:0]}),
+ .S({\SR_Y[4]_i_11_n_0 ,\SR_Y[4]_i_12_n_0 ,\SR_Y[4]_i_13_n_0 ,\SR_Y[4]_i_14_n_0 }));
+ CARRY4 \SR_Y_reg[4]_i_4
+ (.CI(\SR_Y_reg[4]_i_10_n_0 ),
+ .CO({\SR_Y_reg[4]_i_4_n_0 ,\SR_Y_reg[4]_i_4_n_1 ,\SR_Y_reg[4]_i_4_n_2 ,\SR_Y_reg[4]_i_4_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_Y[4]_i_15_n_0 ,\SR_Y[4]_i_16_n_0 ,\SR_Y[4]_i_17_n_0 ,\SR_Y[4]_i_18_n_0 }),
+ .O(SC_MultResult[10:7]),
+ .S({\SR_Y[4]_i_19_n_0 ,\SR_Y[4]_i_20_n_0 ,\SR_Y[4]_i_21_n_0 ,\SR_Y[4]_i_22_n_0 }));
+ CARRY4 \SR_Y_reg[4]_i_9
+ (.CI(\<const0> ),
+ .CO({\SR_Y_reg[4]_i_9_n_0 ,\SR_Y_reg[4]_i_9_n_1 ,\SR_Y_reg[4]_i_9_n_2 ,\SR_Y_reg[4]_i_9_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({SR_sum_reg[3],SC_MultResult[2:0]}),
+ .S({\SR_Y[4]_i_23_n_0 ,\SR_Y[4]_i_24_n_0 ,\SR_Y[4]_i_25_n_0 ,\SR_Y[4]_i_26_n_0 }));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[5]),
+ .Q(O_Y_OBUF[5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[6]),
+ .Q(O_Y_OBUF[6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_Y_reg[7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadY_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(p_0_in[7]),
+ .Q(O_Y_OBUF[7]));
+ CARRY4 \SR_Y_reg[7]_i_10
+ (.CI(\SR_sum_reg[0]_i_11_n_0 ),
+ .CO({\SR_Y_reg[7]_i_10_n_0 ,\SR_Y_reg[7]_i_10_n_1 ,\SR_Y_reg[7]_i_10_n_2 ,\SR_Y_reg[7]_i_10_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_Y[7]_i_15_n_0 ,\SR_Y[7]_i_16_n_0 ,\SR_Y[7]_i_17_n_0 ,\SR_Y[7]_i_18_n_0 }),
+ .O({\SR_Y_reg[7]_i_10_n_4 ,\SR_Y_reg[7]_i_10_n_5 ,\SR_Y_reg[7]_i_10_n_6 ,\SR_Y_reg[7]_i_10_n_7 }),
+ .S({\SR_Y[7]_i_19_n_0 ,\SR_Y[7]_i_20_n_0 ,\SR_Y[7]_i_21_n_0 ,\SR_Y[7]_i_22_n_0 }));
+ CARRY4 \SR_Y_reg[7]_i_14
+ (.CI(\SR_Y_reg[4]_i_27_n_0 ),
+ .CO({\SR_Y_reg[7]_i_14_n_1 ,\NLW_SR_Y_reg[7]_i_14_CO_UNCONNECTED [1],\SR_Y_reg[7]_i_14_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\SR_Y[7]_i_25_n_0 ,\SR_Y[7]_i_26_n_0 }),
+ .O({\SR_Y_reg[7]_i_14_n_6 ,\SR_Y_reg[7]_i_14_n_7 }),
+ .S({\<const0> ,\<const1> ,\SR_Y[7]_i_27_n_0 ,\SR_Y[7]_i_28_n_0 }));
+ CARRY4 \SR_Y_reg[7]_i_2
+ (.CI(\SR_Y_reg[4]_i_2_n_0 ),
+ .CO({\SR_Y_reg[7]_i_2_n_2 ,\SR_Y_reg[7]_i_2_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,SC_MultResult[13:12]}),
+ .O(L[14:12]),
+ .S({\<const0> ,\SR_Y[7]_i_5_n_0 ,\SR_Y[7]_i_6_n_0 ,\SR_Y[7]_i_7_n_0 }));
+ MUXF8 \SR_Y_reg[7]_i_23
+ (.I0(\SR_Y_reg[7]_i_33_n_0 ),
+ .I1(\SR_Y_reg[7]_i_34_n_0 ),
+ .O(\SR_shiftRegister[0] [7]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF8 \SR_Y_reg[7]_i_24
+ (.I0(\SR_Y_reg[7]_i_35_n_0 ),
+ .I1(\SR_Y_reg[7]_i_36_n_0 ),
+ .O(\SR_shiftRegister[0] [6]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF8 \SR_Y_reg[7]_i_29
+ (.I0(\SR_Y_reg[7]_i_38_n_0 ),
+ .I1(\SR_Y_reg[7]_i_39_n_0 ),
+ .O(\SR_shiftRegister[0] [5]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF8 \SR_Y_reg[7]_i_30
+ (.I0(\SR_Y_reg[7]_i_40_n_0 ),
+ .I1(\SR_Y_reg[7]_i_41_n_0 ),
+ .O(\SR_shiftRegister[0] [4]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF7 \SR_Y_reg[7]_i_33
+ (.I0(\SR_Y[7]_i_42_n_0 ),
+ .I1(\SR_Y[7]_i_43_n_0 ),
+ .O(\SR_Y_reg[7]_i_33_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_Y_reg[7]_i_34
+ (.I0(\SR_Y[7]_i_44_n_0 ),
+ .I1(\SR_Y[7]_i_45_n_0 ),
+ .O(\SR_Y_reg[7]_i_34_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_Y_reg[7]_i_35
+ (.I0(\SR_Y[7]_i_46_n_0 ),
+ .I1(\SR_Y[7]_i_47_n_0 ),
+ .O(\SR_Y_reg[7]_i_35_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_Y_reg[7]_i_36
+ (.I0(\SR_Y[7]_i_48_n_0 ),
+ .I1(\SR_Y[7]_i_49_n_0 ),
+ .O(\SR_Y_reg[7]_i_36_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_Y_reg[7]_i_38
+ (.I0(\SR_Y[7]_i_50_n_0 ),
+ .I1(\SR_Y[7]_i_51_n_0 ),
+ .O(\SR_Y_reg[7]_i_38_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_Y_reg[7]_i_39
+ (.I0(\SR_Y[7]_i_52_n_0 ),
+ .I1(\SR_Y[7]_i_53_n_0 ),
+ .O(\SR_Y_reg[7]_i_39_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ CARRY4 \SR_Y_reg[7]_i_4
+ (.CI(\SR_Y_reg[4]_i_4_n_0 ),
+ .CO({\SR_Y_reg[7]_i_4_n_1 ,\SR_Y_reg[7]_i_4_n_2 ,\SR_Y_reg[7]_i_4_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\SR_Y_reg[7]_i_8_n_5 ,\<const0> ,\SR_Y_reg[7]_i_8_n_7 }),
+ .O(SC_MultResult[14:11]),
+ .S({\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_6 ,\SR_Y[7]_i_9_n_0 }));
+ MUXF7 \SR_Y_reg[7]_i_40
+ (.I0(\SR_Y[7]_i_54_n_0 ),
+ .I1(\SR_Y[7]_i_55_n_0 ),
+ .O(\SR_Y_reg[7]_i_40_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_Y_reg[7]_i_41
+ (.I0(\SR_Y[7]_i_56_n_0 ),
+ .I1(\SR_Y[7]_i_57_n_0 ),
+ .O(\SR_Y_reg[7]_i_41_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ CARRY4 \SR_Y_reg[7]_i_8
+ (.CI(\SR_Y_reg[7]_i_10_n_0 ),
+ .CO({\SR_Y_reg[7]_i_8_n_2 ,\SR_Y_reg[7]_i_8_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\<const0> ,\SR_Y[7]_i_11_n_0 }),
+ .O({\SR_Y_reg[7]_i_8_n_5 ,\SR_Y_reg[7]_i_8_n_6 ,\SR_Y_reg[7]_i_8_n_7 }),
+ .S({\<const0> ,\<const1> ,\SR_Y[7]_i_12_n_0 ,\SR_Y[7]_i_13_n_0 }));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT2 #(
+ .INIT(4'h1))
+ \SR_readAddress[0]_i_1
+ (.I0(SR_readAddress_reg__0[0]),
+ .I1(I_initAddress_IBUF),
+ .O(\SR_readAddress[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT3 #(
+ .INIT(8'h06))
+ \SR_readAddress[1]_i_1
+ (.I0(SR_readAddress_reg__0[1]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(I_initAddress_IBUF),
+ .O(\SR_readAddress[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT4 #(
+ .INIT(16'h006A))
+ \SR_readAddress[2]_i_1
+ (.I0(SR_readAddress_reg__0[2]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(I_initAddress_IBUF),
+ .O(\SR_readAddress[2]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \SR_readAddress[3]_i_1
+ (.I0(I_incrAddress_IBUF),
+ .I1(I_initAddress_IBUF),
+ .O(\SR_readAddress[3]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT5 #(
+ .INIT(32'h00006AAA))
+ \SR_readAddress[3]_i_2
+ (.I0(SR_readAddress_reg__0[3]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(I_initAddress_IBUF),
+ .O(\SR_readAddress[3]_i_2_n_0 ));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[0]_i_1_n_0 ),
+ .Q(SR_readAddress_reg__0[0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[1]_i_1_n_0 ),
+ .Q(SR_readAddress_reg__0[1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[2]_i_1_n_0 ),
+ .Q(SR_readAddress_reg__0[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_readAddress_reg[3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_readAddress[3]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_readAddress[3]_i_2_n_0 ),
+ .Q(SR_readAddress_reg__0[3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[0]),
+ .Q(\SR_shiftRegister_reg[0]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[1]),
+ .Q(\SR_shiftRegister_reg[0]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[2]),
+ .Q(\SR_shiftRegister_reg[0]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[3]),
+ .Q(\SR_shiftRegister_reg[0]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[4]),
+ .Q(\SR_shiftRegister_reg[0]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[5]),
+ .Q(\SR_shiftRegister_reg[0]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[6]),
+ .Q(\SR_shiftRegister_reg[0]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[0][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(I_inputSample_IBUF[7]),
+ .Q(\SR_shiftRegister_reg[0]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [0]),
+ .Q(\SR_shiftRegister_reg[10]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [1]),
+ .Q(\SR_shiftRegister_reg[10]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [2]),
+ .Q(\SR_shiftRegister_reg[10]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [3]),
+ .Q(\SR_shiftRegister_reg[10]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [4]),
+ .Q(\SR_shiftRegister_reg[10]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [5]),
+ .Q(\SR_shiftRegister_reg[10]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [6]),
+ .Q(\SR_shiftRegister_reg[10]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[10][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[9]__0 [7]),
+ .Q(\SR_shiftRegister_reg[10]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [0]),
+ .Q(\SR_shiftRegister_reg[11]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [1]),
+ .Q(\SR_shiftRegister_reg[11]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [2]),
+ .Q(\SR_shiftRegister_reg[11]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [3]),
+ .Q(\SR_shiftRegister_reg[11]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [4]),
+ .Q(\SR_shiftRegister_reg[11]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [5]),
+ .Q(\SR_shiftRegister_reg[11]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [6]),
+ .Q(\SR_shiftRegister_reg[11]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[11][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[10]__0 [7]),
+ .Q(\SR_shiftRegister_reg[11]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [0]),
+ .Q(\SR_shiftRegister_reg[12]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [1]),
+ .Q(\SR_shiftRegister_reg[12]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [2]),
+ .Q(\SR_shiftRegister_reg[12]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [3]),
+ .Q(\SR_shiftRegister_reg[12]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [4]),
+ .Q(\SR_shiftRegister_reg[12]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [5]),
+ .Q(\SR_shiftRegister_reg[12]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [6]),
+ .Q(\SR_shiftRegister_reg[12]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[12][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[11]__0 [7]),
+ .Q(\SR_shiftRegister_reg[12]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [0]),
+ .Q(\SR_shiftRegister_reg[13]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [1]),
+ .Q(\SR_shiftRegister_reg[13]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [2]),
+ .Q(\SR_shiftRegister_reg[13]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [3]),
+ .Q(\SR_shiftRegister_reg[13]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [4]),
+ .Q(\SR_shiftRegister_reg[13]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [5]),
+ .Q(\SR_shiftRegister_reg[13]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [6]),
+ .Q(\SR_shiftRegister_reg[13]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[13][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[12]__0 [7]),
+ .Q(\SR_shiftRegister_reg[13]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [0]),
+ .Q(\SR_shiftRegister_reg[14]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [1]),
+ .Q(\SR_shiftRegister_reg[14]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [2]),
+ .Q(\SR_shiftRegister_reg[14]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [3]),
+ .Q(\SR_shiftRegister_reg[14]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [4]),
+ .Q(\SR_shiftRegister_reg[14]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [5]),
+ .Q(\SR_shiftRegister_reg[14]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [6]),
+ .Q(\SR_shiftRegister_reg[14]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[14][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[13]__0 [7]),
+ .Q(\SR_shiftRegister_reg[14]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [0]),
+ .Q(\SR_shiftRegister_reg[15]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [1]),
+ .Q(\SR_shiftRegister_reg[15]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [2]),
+ .Q(\SR_shiftRegister_reg[15]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [3]),
+ .Q(\SR_shiftRegister_reg[15]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [4]),
+ .Q(\SR_shiftRegister_reg[15]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [5]),
+ .Q(\SR_shiftRegister_reg[15]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [6]),
+ .Q(\SR_shiftRegister_reg[15]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[15][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[14]__0 [7]),
+ .Q(\SR_shiftRegister_reg[15]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [0]),
+ .Q(\SR_shiftRegister_reg[1]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [1]),
+ .Q(\SR_shiftRegister_reg[1]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [2]),
+ .Q(\SR_shiftRegister_reg[1]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [3]),
+ .Q(\SR_shiftRegister_reg[1]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [4]),
+ .Q(\SR_shiftRegister_reg[1]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [5]),
+ .Q(\SR_shiftRegister_reg[1]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [6]),
+ .Q(\SR_shiftRegister_reg[1]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[1][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[0]__0 [7]),
+ .Q(\SR_shiftRegister_reg[1]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [0]),
+ .Q(\SR_shiftRegister_reg[2]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [1]),
+ .Q(\SR_shiftRegister_reg[2]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [2]),
+ .Q(\SR_shiftRegister_reg[2]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [3]),
+ .Q(\SR_shiftRegister_reg[2]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [4]),
+ .Q(\SR_shiftRegister_reg[2]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [5]),
+ .Q(\SR_shiftRegister_reg[2]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [6]),
+ .Q(\SR_shiftRegister_reg[2]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[2][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[1]__0 [7]),
+ .Q(\SR_shiftRegister_reg[2]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [0]),
+ .Q(\SR_shiftRegister_reg[3]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [1]),
+ .Q(\SR_shiftRegister_reg[3]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [2]),
+ .Q(\SR_shiftRegister_reg[3]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [3]),
+ .Q(\SR_shiftRegister_reg[3]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [4]),
+ .Q(\SR_shiftRegister_reg[3]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [5]),
+ .Q(\SR_shiftRegister_reg[3]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [6]),
+ .Q(\SR_shiftRegister_reg[3]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[3][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[2]__0 [7]),
+ .Q(\SR_shiftRegister_reg[3]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [0]),
+ .Q(\SR_shiftRegister_reg[4]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [1]),
+ .Q(\SR_shiftRegister_reg[4]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [2]),
+ .Q(\SR_shiftRegister_reg[4]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [3]),
+ .Q(\SR_shiftRegister_reg[4]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [4]),
+ .Q(\SR_shiftRegister_reg[4]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [5]),
+ .Q(\SR_shiftRegister_reg[4]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [6]),
+ .Q(\SR_shiftRegister_reg[4]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[4][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[3]__0 [7]),
+ .Q(\SR_shiftRegister_reg[4]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [0]),
+ .Q(\SR_shiftRegister_reg[5]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [1]),
+ .Q(\SR_shiftRegister_reg[5]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [2]),
+ .Q(\SR_shiftRegister_reg[5]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [3]),
+ .Q(\SR_shiftRegister_reg[5]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [4]),
+ .Q(\SR_shiftRegister_reg[5]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [5]),
+ .Q(\SR_shiftRegister_reg[5]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [6]),
+ .Q(\SR_shiftRegister_reg[5]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[5][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[4]__0 [7]),
+ .Q(\SR_shiftRegister_reg[5]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [0]),
+ .Q(\SR_shiftRegister_reg[6]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [1]),
+ .Q(\SR_shiftRegister_reg[6]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [2]),
+ .Q(\SR_shiftRegister_reg[6]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [3]),
+ .Q(\SR_shiftRegister_reg[6]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [4]),
+ .Q(\SR_shiftRegister_reg[6]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [5]),
+ .Q(\SR_shiftRegister_reg[6]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [6]),
+ .Q(\SR_shiftRegister_reg[6]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[6][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[5]__0 [7]),
+ .Q(\SR_shiftRegister_reg[6]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [0]),
+ .Q(\SR_shiftRegister_reg[7]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [1]),
+ .Q(\SR_shiftRegister_reg[7]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [2]),
+ .Q(\SR_shiftRegister_reg[7]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [3]),
+ .Q(\SR_shiftRegister_reg[7]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [4]),
+ .Q(\SR_shiftRegister_reg[7]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [5]),
+ .Q(\SR_shiftRegister_reg[7]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [6]),
+ .Q(\SR_shiftRegister_reg[7]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[7][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[6]__0 [7]),
+ .Q(\SR_shiftRegister_reg[7]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [0]),
+ .Q(\SR_shiftRegister_reg[8]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [1]),
+ .Q(\SR_shiftRegister_reg[8]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [2]),
+ .Q(\SR_shiftRegister_reg[8]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [3]),
+ .Q(\SR_shiftRegister_reg[8]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [4]),
+ .Q(\SR_shiftRegister_reg[8]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [5]),
+ .Q(\SR_shiftRegister_reg[8]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [6]),
+ .Q(\SR_shiftRegister_reg[8]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[8][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[7]__0 [7]),
+ .Q(\SR_shiftRegister_reg[8]__0 [7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [0]),
+ .Q(\SR_shiftRegister_reg[9]__0 [0]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [1]),
+ .Q(\SR_shiftRegister_reg[9]__0 [1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [2]),
+ .Q(\SR_shiftRegister_reg[9]__0 [2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [3]),
+ .Q(\SR_shiftRegister_reg[9]__0 [3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [4]),
+ .Q(\SR_shiftRegister_reg[9]__0 [4]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [5]),
+ .Q(\SR_shiftRegister_reg[9]__0 [5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [6]),
+ .Q(\SR_shiftRegister_reg[9]__0 [6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_shiftRegister_reg[9][7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(I_loadShift_IBUF),
+ .CLR(I_reset_IBUF),
+ .D(\SR_shiftRegister_reg[8]__0 [7]),
+ .Q(\SR_shiftRegister_reg[9]__0 [7]));
+ LUT2 #(
+ .INIT(4'hE))
+ \SR_sum[0]_i_1
+ (.I0(I_loadSum_IBUF),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[0]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[0]_i_10
+ (.I0(SC_MultResult[0]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[0]),
+ .O(\SR_sum[0]_i_10_n_0 ));
+ LUT1 #(
+ .INIT(2'h1))
+ \SR_sum[0]_i_13
+ (.I0(\SR_sum[0]_i_27_n_0 ),
+ .O(\SR_sum[0]_i_13_n_0 ));
+ LUT5 #(
+ .INIT(32'hFDDD777F))
+ \SR_sum[0]_i_14
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_sum[0]_i_14_n_0 ));
+ LUT5 #(
+ .INIT(32'h724E0000))
+ \SR_sum[0]_i_15
+ (.I0(SR_readAddress_reg__0[3]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(\SR_shiftRegister[0] [1]),
+ .O(\SR_sum[0]_i_15_n_0 ));
+ LUT6 #(
+ .INIT(64'h02228880FDDD777F))
+ \SR_sum[0]_i_16
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[3]),
+ .I5(\SR_sum[0]_i_27_n_0 ),
+ .O(\SR_sum[0]_i_16_n_0 ));
+ LUT6 #(
+ .INIT(64'hCED287B3FDDD777F))
+ \SR_sum[0]_i_17
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[3]),
+ .I5(\SR_shiftRegister[0] [2]),
+ .O(\SR_sum[0]_i_17_n_0 ));
+ LUT6 #(
+ .INIT(64'h113AAC44220AA088))
+ \SR_sum[0]_i_18
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [0]),
+ .O(\SR_sum[0]_i_18_n_0 ));
+ LUT5 #(
+ .INIT(32'h028AA280))
+ \SR_sum[0]_i_19
+ (.I0(\SR_shiftRegister[0] [0]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_sum[0]_i_19_n_0 ));
+ LUT3 #(
+ .INIT(8'h69))
+ \SR_sum[0]_i_20
+ (.I0(\SR_sum[0]_i_31_n_0 ),
+ .I1(\SR_sum[0]_i_32_n_0 ),
+ .I2(\SR_sum[0]_i_33_n_0 ),
+ .O(\SR_sum[0]_i_20_n_0 ));
+ LUT6 #(
+ .INIT(64'h9B4AA1E6A88AA22A))
+ \SR_sum[0]_i_21
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[3]),
+ .I5(\SR_shiftRegister[0] [0]),
+ .O(\SR_sum[0]_i_21_n_0 ));
+ LUT5 #(
+ .INIT(32'h60060000))
+ \SR_sum[0]_i_22
+ (.I0(SR_readAddress_reg__0[2]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(\SR_shiftRegister[0] [1]),
+ .O(\SR_sum[0]_i_22_n_0 ));
+ LUT6 #(
+ .INIT(64'h6696969666666666))
+ \SR_sum[0]_i_23
+ (.I0(\SR_sum[0]_i_31_n_0 ),
+ .I1(\SR_sum[0]_i_33_n_0 ),
+ .I2(\SR_shiftRegister[0] [1]),
+ .I3(SC_multOperand2[1]),
+ .I4(\SR_shiftRegister[0] [0]),
+ .I5(SC_multOperand2[2]),
+ .O(\SR_sum[0]_i_23_n_0 ));
+ LUT6 #(
+ .INIT(64'h96AAAA96AAAAAAAA))
+ \SR_sum[0]_i_24
+ (.I0(\SR_sum[0]_i_21_n_0 ),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[3]),
+ .I4(SR_readAddress_reg__0[1]),
+ .I5(\SR_shiftRegister[0] [2]),
+ .O(\SR_sum[0]_i_24_n_0 ));
+ LUT6 #(
+ .INIT(64'hF7C143DF08028020))
+ \SR_sum[0]_i_25
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[2]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister[0] [0]),
+ .O(\SR_sum[0]_i_25_n_0 ));
+ LUT5 #(
+ .INIT(32'h00828200))
+ \SR_sum[0]_i_26
+ (.I0(\SR_shiftRegister[0] [0]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_sum[0]_i_26_n_0 ));
+ LUT6 #(
+ .INIT(64'h113AAC44220AA088))
+ \SR_sum[0]_i_27
+ (.I0(\SR_shiftRegister[0] [3]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[0]),
+ .I3(SR_readAddress_reg__0[1]),
+ .I4(SR_readAddress_reg__0[2]),
+ .I5(\SR_shiftRegister[0] [2]),
+ .O(\SR_sum[0]_i_27_n_0 ));
+ LUT3 #(
+ .INIT(8'h06))
+ \SR_sum[0]_i_3
+ (.I0(\SR_sum_reg[0]_i_11_n_7 ),
+ .I1(\SR_sum_reg[0]_i_12_n_4 ),
+ .I2(I_initSum_IBUF),
+ .O(\SR_sum[0]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'h557D7D55))
+ \SR_sum[0]_i_31
+ (.I0(\SR_shiftRegister[0] [2]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[2]),
+ .I4(SR_readAddress_reg__0[3]),
+ .O(\SR_sum[0]_i_31_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT5 #(
+ .INIT(32'hF5FD7F5F))
+ \SR_sum[0]_i_32
+ (.I0(\SR_shiftRegister[0] [1]),
+ .I1(SR_readAddress_reg__0[3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_sum[0]_i_32_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT5 #(
+ .INIT(32'hFF7D7DFF))
+ \SR_sum[0]_i_33
+ (.I0(\SR_shiftRegister[0] [3]),
+ .I1(SR_readAddress_reg__0[1]),
+ .I2(SR_readAddress_reg__0[3]),
+ .I3(SR_readAddress_reg__0[0]),
+ .I4(SR_readAddress_reg__0[2]),
+ .O(\SR_sum[0]_i_33_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT4 #(
+ .INIT(16'hF99F))
+ \SR_sum[0]_i_34
+ (.I0(SR_readAddress_reg__0[3]),
+ .I1(SR_readAddress_reg__0[2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[0]),
+ .O(SC_multOperand2[1]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT4 #(
+ .INIT(16'h581A))
+ \SR_sum[0]_i_35
+ (.I0(SR_readAddress_reg__0[2]),
+ .I1(SR_readAddress_reg__0[0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(SR_readAddress_reg__0[3]),
+ .O(SC_multOperand2[2]));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[0]_i_4
+ (.I0(SC_MultResult[2]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[0]_i_4_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_45
+ (.I0(\SR_shiftRegister_reg[3]__0 [1]),
+ .I1(\SR_shiftRegister_reg[2]__0 [1]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [1]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [1]),
+ .O(\SR_sum[0]_i_45_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_46
+ (.I0(\SR_shiftRegister_reg[7]__0 [1]),
+ .I1(\SR_shiftRegister_reg[6]__0 [1]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [1]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [1]),
+ .O(\SR_sum[0]_i_46_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_47
+ (.I0(\SR_shiftRegister_reg[11]__0 [1]),
+ .I1(\SR_shiftRegister_reg[10]__0 [1]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [1]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [1]),
+ .O(\SR_sum[0]_i_47_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_48
+ (.I0(\SR_shiftRegister_reg[15]__0 [1]),
+ .I1(\SR_shiftRegister_reg[14]__0 [1]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [1]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [1]),
+ .O(\SR_sum[0]_i_48_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_49
+ (.I0(\SR_shiftRegister_reg[3]__0 [2]),
+ .I1(\SR_shiftRegister_reg[2]__0 [2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [2]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [2]),
+ .O(\SR_sum[0]_i_49_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[0]_i_5
+ (.I0(SC_MultResult[1]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[0]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_50
+ (.I0(\SR_shiftRegister_reg[7]__0 [2]),
+ .I1(\SR_shiftRegister_reg[6]__0 [2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [2]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [2]),
+ .O(\SR_sum[0]_i_50_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_51
+ (.I0(\SR_shiftRegister_reg[11]__0 [2]),
+ .I1(\SR_shiftRegister_reg[10]__0 [2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [2]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [2]),
+ .O(\SR_sum[0]_i_51_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_52
+ (.I0(\SR_shiftRegister_reg[15]__0 [2]),
+ .I1(\SR_shiftRegister_reg[14]__0 [2]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [2]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [2]),
+ .O(\SR_sum[0]_i_52_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_53
+ (.I0(\SR_shiftRegister_reg[3]__0 [0]),
+ .I1(\SR_shiftRegister_reg[2]__0 [0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [0]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [0]),
+ .O(\SR_sum[0]_i_53_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_54
+ (.I0(\SR_shiftRegister_reg[7]__0 [0]),
+ .I1(\SR_shiftRegister_reg[6]__0 [0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [0]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [0]),
+ .O(\SR_sum[0]_i_54_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_55
+ (.I0(\SR_shiftRegister_reg[11]__0 [0]),
+ .I1(\SR_shiftRegister_reg[10]__0 [0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [0]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [0]),
+ .O(\SR_sum[0]_i_55_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_56
+ (.I0(\SR_shiftRegister_reg[15]__0 [0]),
+ .I1(\SR_shiftRegister_reg[14]__0 [0]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [0]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [0]),
+ .O(\SR_sum[0]_i_56_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_57
+ (.I0(\SR_shiftRegister_reg[3]__0 [3]),
+ .I1(\SR_shiftRegister_reg[2]__0 [3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[1]__0 [3]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[0]__0 [3]),
+ .O(\SR_sum[0]_i_57_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_58
+ (.I0(\SR_shiftRegister_reg[7]__0 [3]),
+ .I1(\SR_shiftRegister_reg[6]__0 [3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[5]__0 [3]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[4]__0 [3]),
+ .O(\SR_sum[0]_i_58_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_59
+ (.I0(\SR_shiftRegister_reg[11]__0 [3]),
+ .I1(\SR_shiftRegister_reg[10]__0 [3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[9]__0 [3]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[8]__0 [3]),
+ .O(\SR_sum[0]_i_59_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[0]_i_6
+ (.I0(SC_MultResult[0]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[0]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \SR_sum[0]_i_60
+ (.I0(\SR_shiftRegister_reg[15]__0 [3]),
+ .I1(\SR_shiftRegister_reg[14]__0 [3]),
+ .I2(SR_readAddress_reg__0[1]),
+ .I3(\SR_shiftRegister_reg[13]__0 [3]),
+ .I4(SR_readAddress_reg__0[0]),
+ .I5(\SR_shiftRegister_reg[12]__0 [3]),
+ .O(\SR_sum[0]_i_60_n_0 ));
+ LUT4 #(
+ .INIT(16'h0906))
+ \SR_sum[0]_i_7
+ (.I0(\SR_sum_reg[0]_i_12_n_4 ),
+ .I1(\SR_sum_reg[0]_i_11_n_7 ),
+ .I2(I_initSum_IBUF),
+ .I3(SR_sum_reg[3]),
+ .O(\SR_sum[0]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[0]_i_8
+ (.I0(SC_MultResult[2]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[2]),
+ .O(\SR_sum[0]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[0]_i_9
+ (.I0(SC_MultResult[1]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[1]),
+ .O(\SR_sum[0]_i_9_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[12]_i_2
+ (.I0(SC_MultResult[13]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[12]_i_2_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[12]_i_3
+ (.I0(SC_MultResult[12]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[12]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[12]_i_4
+ (.I0(SC_MultResult[14]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[14]),
+ .O(\SR_sum[12]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[12]_i_5
+ (.I0(SC_MultResult[13]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[13]),
+ .O(\SR_sum[12]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[12]_i_6
+ (.I0(SC_MultResult[12]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[12]),
+ .O(\SR_sum[12]_i_6_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[4]_i_2
+ (.I0(SC_MultResult[7]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[4]_i_2_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[4]_i_3
+ (.I0(SC_MultResult[6]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[4]_i_3_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[4]_i_4
+ (.I0(SC_MultResult[5]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[4]_i_4_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[4]_i_5
+ (.I0(SC_MultResult[4]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[4]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[4]_i_6
+ (.I0(SC_MultResult[7]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[7]),
+ .O(\SR_sum[4]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[4]_i_7
+ (.I0(SC_MultResult[6]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[6]),
+ .O(\SR_sum[4]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[4]_i_8
+ (.I0(SC_MultResult[5]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[5]),
+ .O(\SR_sum[4]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[4]_i_9
+ (.I0(SC_MultResult[4]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[4]),
+ .O(\SR_sum[4]_i_9_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[8]_i_2
+ (.I0(SC_MultResult[11]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[8]_i_2_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[8]_i_3
+ (.I0(SC_MultResult[10]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[8]_i_3_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[8]_i_4
+ (.I0(SC_MultResult[9]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[8]_i_4_n_0 ));
+ LUT2 #(
+ .INIT(4'h2))
+ \SR_sum[8]_i_5
+ (.I0(SC_MultResult[8]),
+ .I1(I_initSum_IBUF),
+ .O(\SR_sum[8]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[8]_i_6
+ (.I0(SC_MultResult[11]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[11]),
+ .O(\SR_sum[8]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[8]_i_7
+ (.I0(SC_MultResult[10]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[10]),
+ .O(\SR_sum[8]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[8]_i_8
+ (.I0(SC_MultResult[9]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[9]),
+ .O(\SR_sum[8]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'h12))
+ \SR_sum[8]_i_9
+ (.I0(SC_MultResult[8]),
+ .I1(I_initSum_IBUF),
+ .I2(SR_sum_reg[8]),
+ .O(\SR_sum[8]_i_9_n_0 ));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[0]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[0]_i_2_n_7 ),
+ .Q(SR_sum_reg[0]));
+ CARRY4 \SR_sum_reg[0]_i_11
+ (.CI(\<const0> ),
+ .CO({\SR_sum_reg[0]_i_11_n_0 ,\SR_sum_reg[0]_i_11_n_1 ,\SR_sum_reg[0]_i_11_n_2 ,\SR_sum_reg[0]_i_11_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_sum[0]_i_13_n_0 ,\SR_sum[0]_i_14_n_0 ,\SR_sum[0]_i_15_n_0 ,\<const0> }),
+ .O({\SR_sum_reg[0]_i_11_n_4 ,\SR_sum_reg[0]_i_11_n_5 ,\SR_sum_reg[0]_i_11_n_6 ,\SR_sum_reg[0]_i_11_n_7 }),
+ .S({\SR_sum[0]_i_16_n_0 ,\SR_sum[0]_i_17_n_0 ,\SR_sum[0]_i_18_n_0 ,\SR_sum[0]_i_19_n_0 }));
+ CARRY4 \SR_sum_reg[0]_i_12
+ (.CI(\<const0> ),
+ .CO({\SR_sum_reg[0]_i_12_n_0 ,\SR_sum_reg[0]_i_12_n_1 ,\SR_sum_reg[0]_i_12_n_2 ,\SR_sum_reg[0]_i_12_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_sum[0]_i_20_n_0 ,\SR_sum[0]_i_21_n_0 ,\SR_sum[0]_i_22_n_0 ,\<const0> }),
+ .O({\SR_sum_reg[0]_i_12_n_4 ,SC_MultResult[2:0]}),
+ .S({\SR_sum[0]_i_23_n_0 ,\SR_sum[0]_i_24_n_0 ,\SR_sum[0]_i_25_n_0 ,\SR_sum[0]_i_26_n_0 }));
+ CARRY4 \SR_sum_reg[0]_i_2
+ (.CI(\<const0> ),
+ .CO({\SR_sum_reg[0]_i_2_n_0 ,\SR_sum_reg[0]_i_2_n_1 ,\SR_sum_reg[0]_i_2_n_2 ,\SR_sum_reg[0]_i_2_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_sum[0]_i_3_n_0 ,\SR_sum[0]_i_4_n_0 ,\SR_sum[0]_i_5_n_0 ,\SR_sum[0]_i_6_n_0 }),
+ .O({\SR_sum_reg[0]_i_2_n_4 ,\SR_sum_reg[0]_i_2_n_5 ,\SR_sum_reg[0]_i_2_n_6 ,\SR_sum_reg[0]_i_2_n_7 }),
+ .S({\SR_sum[0]_i_7_n_0 ,\SR_sum[0]_i_8_n_0 ,\SR_sum[0]_i_9_n_0 ,\SR_sum[0]_i_10_n_0 }));
+ MUXF8 \SR_sum_reg[0]_i_28
+ (.I0(\SR_sum_reg[0]_i_37_n_0 ),
+ .I1(\SR_sum_reg[0]_i_38_n_0 ),
+ .O(\SR_shiftRegister[0] [1]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF8 \SR_sum_reg[0]_i_29
+ (.I0(\SR_sum_reg[0]_i_39_n_0 ),
+ .I1(\SR_sum_reg[0]_i_40_n_0 ),
+ .O(\SR_shiftRegister[0] [2]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF8 \SR_sum_reg[0]_i_30
+ (.I0(\SR_sum_reg[0]_i_41_n_0 ),
+ .I1(\SR_sum_reg[0]_i_42_n_0 ),
+ .O(\SR_shiftRegister[0] [0]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF8 \SR_sum_reg[0]_i_36
+ (.I0(\SR_sum_reg[0]_i_43_n_0 ),
+ .I1(\SR_sum_reg[0]_i_44_n_0 ),
+ .O(\SR_shiftRegister[0] [3]),
+ .S(SR_readAddress_reg__0[3]));
+ MUXF7 \SR_sum_reg[0]_i_37
+ (.I0(\SR_sum[0]_i_45_n_0 ),
+ .I1(\SR_sum[0]_i_46_n_0 ),
+ .O(\SR_sum_reg[0]_i_37_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_38
+ (.I0(\SR_sum[0]_i_47_n_0 ),
+ .I1(\SR_sum[0]_i_48_n_0 ),
+ .O(\SR_sum_reg[0]_i_38_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_39
+ (.I0(\SR_sum[0]_i_49_n_0 ),
+ .I1(\SR_sum[0]_i_50_n_0 ),
+ .O(\SR_sum_reg[0]_i_39_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_40
+ (.I0(\SR_sum[0]_i_51_n_0 ),
+ .I1(\SR_sum[0]_i_52_n_0 ),
+ .O(\SR_sum_reg[0]_i_40_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_41
+ (.I0(\SR_sum[0]_i_53_n_0 ),
+ .I1(\SR_sum[0]_i_54_n_0 ),
+ .O(\SR_sum_reg[0]_i_41_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_42
+ (.I0(\SR_sum[0]_i_55_n_0 ),
+ .I1(\SR_sum[0]_i_56_n_0 ),
+ .O(\SR_sum_reg[0]_i_42_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_43
+ (.I0(\SR_sum[0]_i_57_n_0 ),
+ .I1(\SR_sum[0]_i_58_n_0 ),
+ .O(\SR_sum_reg[0]_i_43_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ MUXF7 \SR_sum_reg[0]_i_44
+ (.I0(\SR_sum[0]_i_59_n_0 ),
+ .I1(\SR_sum[0]_i_60_n_0 ),
+ .O(\SR_sum_reg[0]_i_44_n_0 ),
+ .S(SR_readAddress_reg__0[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[10]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[8]_i_1_n_5 ),
+ .Q(SR_sum_reg[10]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[11]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[8]_i_1_n_4 ),
+ .Q(SR_sum_reg[11]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[12]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[12]_i_1_n_7 ),
+ .Q(SR_sum_reg[12]));
+ CARRY4 \SR_sum_reg[12]_i_1
+ (.CI(\SR_sum_reg[8]_i_1_n_0 ),
+ .CO({\SR_sum_reg[12]_i_1_n_2 ,\SR_sum_reg[12]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\<const0> ,\<const0> ,\SR_sum[12]_i_2_n_0 ,\SR_sum[12]_i_3_n_0 }),
+ .O({\SR_sum_reg[12]_i_1_n_5 ,\SR_sum_reg[12]_i_1_n_6 ,\SR_sum_reg[12]_i_1_n_7 }),
+ .S({\<const0> ,\SR_sum[12]_i_4_n_0 ,\SR_sum[12]_i_5_n_0 ,\SR_sum[12]_i_6_n_0 }));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[13]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[12]_i_1_n_6 ),
+ .Q(SR_sum_reg[13]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[14]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[12]_i_1_n_5 ),
+ .Q(SR_sum_reg[14]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[1]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[0]_i_2_n_6 ),
+ .Q(SR_sum_reg[1]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[2]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[0]_i_2_n_5 ),
+ .Q(SR_sum_reg[2]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[3]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[0]_i_2_n_4 ),
+ .Q(SR_sum_reg[3]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[4]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[4]_i_1_n_7 ),
+ .Q(SR_sum_reg[4]));
+ CARRY4 \SR_sum_reg[4]_i_1
+ (.CI(\SR_sum_reg[0]_i_2_n_0 ),
+ .CO({\SR_sum_reg[4]_i_1_n_0 ,\SR_sum_reg[4]_i_1_n_1 ,\SR_sum_reg[4]_i_1_n_2 ,\SR_sum_reg[4]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_sum[4]_i_2_n_0 ,\SR_sum[4]_i_3_n_0 ,\SR_sum[4]_i_4_n_0 ,\SR_sum[4]_i_5_n_0 }),
+ .O({\SR_sum_reg[4]_i_1_n_4 ,\SR_sum_reg[4]_i_1_n_5 ,\SR_sum_reg[4]_i_1_n_6 ,\SR_sum_reg[4]_i_1_n_7 }),
+ .S({\SR_sum[4]_i_6_n_0 ,\SR_sum[4]_i_7_n_0 ,\SR_sum[4]_i_8_n_0 ,\SR_sum[4]_i_9_n_0 }));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[5]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[4]_i_1_n_6 ),
+ .Q(SR_sum_reg[5]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[6]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[4]_i_1_n_5 ),
+ .Q(SR_sum_reg[6]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[7]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[4]_i_1_n_4 ),
+ .Q(SR_sum_reg[7]));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[8]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[8]_i_1_n_7 ),
+ .Q(SR_sum_reg[8]));
+ CARRY4 \SR_sum_reg[8]_i_1
+ (.CI(\SR_sum_reg[4]_i_1_n_0 ),
+ .CO({\SR_sum_reg[8]_i_1_n_0 ,\SR_sum_reg[8]_i_1_n_1 ,\SR_sum_reg[8]_i_1_n_2 ,\SR_sum_reg[8]_i_1_n_3 }),
+ .CYINIT(\<const0> ),
+ .DI({\SR_sum[8]_i_2_n_0 ,\SR_sum[8]_i_3_n_0 ,\SR_sum[8]_i_4_n_0 ,\SR_sum[8]_i_5_n_0 }),
+ .O({\SR_sum_reg[8]_i_1_n_4 ,\SR_sum_reg[8]_i_1_n_5 ,\SR_sum_reg[8]_i_1_n_6 ,\SR_sum_reg[8]_i_1_n_7 }),
+ .S({\SR_sum[8]_i_6_n_0 ,\SR_sum[8]_i_7_n_0 ,\SR_sum[8]_i_8_n_0 ,\SR_sum[8]_i_9_n_0 }));
+ FDCE #(
+ .INIT(1'b0))
+ \SR_sum_reg[9]
+ (.C(I_clock_IBUF_BUFG),
+ .CE(\SR_sum[0]_i_1_n_0 ),
+ .CLR(I_reset_IBUF),
+ .D(\SR_sum_reg[8]_i_1_n_6 ),
+ .Q(SR_sum_reg[9]));
+ VCC VCC
+ (.P(\<const1> ));
+endmodule
diff --git a/tp_vivado/src/hdl/tb_firUnit.vhd b/tp_vivado/src/hdl/tb_firUnit.vhd
new file mode 100644
index 0000000..76f7d19
--- /dev/null
+++ b/tp_vivado/src/hdl/tb_firUnit.vhd
@@ -0,0 +1,87 @@
+-------------------------------------------------------------------------------
+-- Title : FirUnit
+-- Project :
+-------------------------------------------------------------------------------
+-- File : operativeUnit.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2018-04-11
+-- Last update: 2019-02-26
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: 8 bit FIR
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-04-11 1.0 jnbazin Created
+-- 2018-04-18 1.1 marzel Modified to add more test inputs
+-- 2019-02-26 1.1 marzel Adapted to 16-tap filtering
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_firUnit is
+end entity tb_firUnit;
+
+architecture archi_tb_firUnit of tb_firUnit is
+ component firUnit is
+ port (
+ I_clock : in std_logic;
+ I_reset : in std_logic;
+ I_inputSample : in std_logic_vector(10 downto 0);
+ I_inputSampleValid : in std_logic;
+ O_filteredSample : out std_logic_vector(10 downto 0);
+ O_filteredSampleValid : out std_logic);
+ end component firUnit;
+
+ signal SC_clock : std_logic := '0';
+ signal SC_reset : std_logic;
+ signal SC_inputSample : std_logic_vector(10 downto 0);
+ signal SC_inputSampleValid : std_logic:='0';
+ signal SC_filteredSample : std_logic_vector(10 downto 0);
+ signal SC_filteredSampleValid : std_logic;
+
+begin
+
+ SC_clock <= not SC_clock after 5 ns;
+ SC_reset <= '0', '1' after 19 ns, '0' after 57 ns;
+
+ -- Sample period = 20 clk period
+ SC_inputSampleValid <= not SC_inputSampleValid after 100 ns;
+
+ -- Null signal followed by a Dirac and then an arbitrary sequence
+ SC_inputSample <= "00000000000",
+ "00001111111" after 401 ns,
+ "00000000000" after 601 ns,
+ "00000100100" after 4201 ns,
+ "00001100100" after 4401 ns,
+ "00010100010" after 4601 ns,
+ "00011011011" after 4801 ns,
+ "00000001011" after 5001 ns,
+ "00010000000" after 5201 ns,
+ "00001111111" after 5401 ns,
+ "00010111010" after 5601 ns;
+
+
+-- the filter output on 8 bits is a sequence of signed numbers (with the assumption
+-- of rounding the output, so the accuracy can be slightly different depending
+-- on your final stage):
+ -- 0 2 3 6 10 15 20 24 26 26 24 20 15 10 6 3 2 0 0 0 1 2 3 5 7 7 8 4 -1 -8
+ -- -17 -27 -38 -49 -61 -71 -82 -93 -101 -107 -112 -113 -116
+
+
+ firUnit_1 : entity work.firUnit
+ port map (
+ I_clock => SC_clock,
+ I_reset => SC_reset,
+ I_inputSample => SC_inputSample,
+ I_inputSampleValid => SC_inputSampleValid,
+ O_filteredSample => SC_filteredSample,
+ O_filteredSampleValid => SC_filteredSampleValid);
+
+end architecture archi_tb_firUnit;
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.dcp b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.dcp
new file mode 100644
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diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log
new file mode 100644
index 0000000..6bd8d52
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.upgrade_log
@@ -0,0 +1,332 @@
+Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+| Date : Thu Jan 21 16:58:14 2016
+| Host : WK86 running 64-bit Service Pack 1 (build 7601)
+| Command : upgrade_ip
+| Device : xc7a200tsbg484-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'clk_wiz_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the update of clk_wiz_0 (xilinx.com:ip:clk_wiz:5.2) to current project options.
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Warnings
+-----------
+
+WARNING: The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. When checking the upgrade script, note that parameter names are case sensitive.
+
+
+3. Interface Information
+------------------------
+
+Detected external interface differences while upgrading IP 'clk_wiz_0'.
+
+
+-upgrade has removed interface 'clock_CLK_OUT2'
+-upgrade has removed interface 'clock_CLK_OUT3'
+-upgrade has removed interface 'clock_CLK_OUT4'
+-upgrade has added interface 'reset'
+
+4. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading IP 'clk_wiz_0'. These changes may impact your design.
+
+
+-upgrade has removed port 'clk_out2'
+-upgrade has removed port 'clk_out3'
+-upgrade has removed port 'clk_out4'
+-upgrade has added port 'reset'
+
+5. Customization warnings
+-------------------------
+
+WARNING: Value 'sys_clock' is out of the range for parameter 'CLK IN1 BOARD INTERFACE(CLK_IN1_BOARD_INTERFACE)' for IP 'clk_wiz_0' . Valid values are - Custom, sys_diff_clock
+
+WARNING: Customization errors found on 'clk_wiz_0'. Restoring to previous valid configuration.
+
+WARNING: An attempt to modify the value of disabled parameter 'CLKOUT2_REQUESTED_OUT_FREQ' from '200.000' to '100.000' has been ignored for IP 'clk_wiz_0'
+
+WARNING: An attempt to modify the value of disabled parameter 'CLKOUT3_REQUESTED_OUT_FREQ' from '12.000' to '100.000' has been ignored for IP 'clk_wiz_0'
+
+WARNING: An attempt to modify the value of disabled parameter 'CLKOUT4_REQUESTED_OUT_FREQ' from '50.000' to '100.000' has been ignored for IP 'clk_wiz_0'
+
+
+6. Debug Commands
+-----------------
+
+ The following debug information can be passed to Vivado as Tcl commands,
+in order to validate or debug the output of the upgrade flow.
+ Please consult the warnings from the previous sections, and alter or remove
+the configuration parameter(s) which caused the warning; then execute the Tcl
+commands, and use the IP Customization GUI to verify the IP configuration.
+
+create_ip -vlnv xilinx.com:ip:clk_wiz:5.2 -user_name clk_wiz_0
+set_property -dict "\
+ CONFIG.CALC_DONE empty \
+ CONFIG.CDDCDONE_PORT cddcdone \
+ CONFIG.CDDCREQ_PORT cddcreq \
+ CONFIG.CLKFB_IN_N_PORT clkfb_in_n \
+ CONFIG.CLKFB_IN_PORT clkfb_in \
+ CONFIG.CLKFB_IN_P_PORT clkfb_in_p \
+ CONFIG.CLKFB_IN_SIGNALING SINGLE \
+ CONFIG.CLKFB_OUT_N_PORT clkfb_out_n \
+ CONFIG.CLKFB_OUT_PORT clkfb_out \
+ CONFIG.CLKFB_OUT_P_PORT clkfb_out_p \
+ CONFIG.CLKFB_STOPPED_PORT clkfb_stopped \
+ CONFIG.CLKIN1_JITTER_PS 100.0 \
+ CONFIG.CLKIN1_UI_JITTER 0.010 \
+ CONFIG.CLKIN2_JITTER_PS 100.0 \
+ CONFIG.CLKIN2_UI_JITTER 0.010 \
+ CONFIG.CLKOUT1_DRIVES BUFG \
+ CONFIG.CLKOUT1_JITTER 151.366 \
+ CONFIG.CLKOUT1_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT1_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT1_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT1_USED true \
+ CONFIG.CLKOUT2_DRIVES BUFG \
+ CONFIG.CLKOUT2_JITTER 132.221 \
+ CONFIG.CLKOUT2_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT2_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 200.000 \
+ CONFIG.CLKOUT2_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT2_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT2_USED true \
+ CONFIG.CLKOUT3_DRIVES BUFG \
+ CONFIG.CLKOUT3_JITTER 231.952 \
+ CONFIG.CLKOUT3_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT3_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ 12.000 \
+ CONFIG.CLKOUT3_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT3_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT3_USED true \
+ CONFIG.CLKOUT4_DRIVES BUFG \
+ CONFIG.CLKOUT4_JITTER 174.353 \
+ CONFIG.CLKOUT4_PHASE_ERROR 132.063 \
+ CONFIG.CLKOUT4_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ 50.000 \
+ CONFIG.CLKOUT4_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT4_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT4_USED true \
+ CONFIG.CLKOUT5_DRIVES BUFG \
+ CONFIG.CLKOUT5_JITTER 0.0 \
+ CONFIG.CLKOUT5_PHASE_ERROR 0.0 \
+ CONFIG.CLKOUT5_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT5_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT5_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT5_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT5_USED false \
+ CONFIG.CLKOUT6_DRIVES BUFG \
+ CONFIG.CLKOUT6_JITTER 0.0 \
+ CONFIG.CLKOUT6_PHASE_ERROR 0.0 \
+ CONFIG.CLKOUT6_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT6_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT6_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT6_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT6_USED false \
+ CONFIG.CLKOUT7_DRIVES BUFG \
+ CONFIG.CLKOUT7_JITTER 0.0 \
+ CONFIG.CLKOUT7_PHASE_ERROR 0.0 \
+ CONFIG.CLKOUT7_REQUESTED_DUTY_CYCLE 50.000 \
+ CONFIG.CLKOUT7_REQUESTED_OUT_FREQ 100.000 \
+ CONFIG.CLKOUT7_REQUESTED_PHASE 0.000 \
+ CONFIG.CLKOUT7_SEQUENCE_NUMBER 1 \
+ CONFIG.CLKOUT7_USED false \
+ CONFIG.CLKOUTPHY_REQUESTED_FREQ 600.000 \
+ CONFIG.CLK_IN1_BOARD_INTERFACE sys_clock \
+ CONFIG.CLK_IN2_BOARD_INTERFACE Custom \
+ CONFIG.CLK_IN_SEL_PORT clk_in_sel \
+ CONFIG.CLK_OUT1_PORT clk_out1 \
+ CONFIG.CLK_OUT1_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT2_PORT clk_out2 \
+ CONFIG.CLK_OUT2_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT3_PORT clk_out3 \
+ CONFIG.CLK_OUT3_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT4_PORT clk_out4 \
+ CONFIG.CLK_OUT4_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT5_PORT clk_out5 \
+ CONFIG.CLK_OUT5_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT6_PORT clk_out6 \
+ CONFIG.CLK_OUT6_USE_FINE_PS_GUI false \
+ CONFIG.CLK_OUT7_PORT clk_out7 \
+ CONFIG.CLK_OUT7_USE_FINE_PS_GUI false \
+ CONFIG.CLK_VALID_PORT CLK_VALID \
+ CONFIG.CLOCK_MGR_TYPE auto \
+ CONFIG.Component_Name clk_wiz_0 \
+ CONFIG.DADDR_PORT daddr \
+ CONFIG.DCLK_PORT dclk \
+ CONFIG.DEN_PORT den \
+ CONFIG.DIFF_CLK_IN1_BOARD_INTERFACE Custom \
+ CONFIG.DIFF_CLK_IN2_BOARD_INTERFACE Custom \
+ CONFIG.DIN_PORT din \
+ CONFIG.DOUT_PORT dout \
+ CONFIG.DRDY_PORT drdy \
+ CONFIG.DWE_PORT dwe \
+ CONFIG.ENABLE_CDDC false \
+ CONFIG.ENABLE_CLKOUTPHY false \
+ CONFIG.FEEDBACK_SOURCE FDBK_AUTO \
+ CONFIG.INPUT_CLK_STOPPED_PORT input_clk_stopped \
+ CONFIG.INPUT_MODE frequency \
+ CONFIG.INTERFACE_SELECTION Enable_AXI \
+ CONFIG.IN_FREQ_UNITS Units_MHz \
+ CONFIG.IN_JITTER_UNITS Units_UI \
+ CONFIG.JITTER_OPTIONS UI \
+ CONFIG.JITTER_SEL No_Jitter \
+ CONFIG.LOCKED_PORT locked \
+ CONFIG.MMCM_BANDWIDTH OPTIMIZED \
+ CONFIG.MMCM_CLKFBOUT_MULT_F 6.000 \
+ CONFIG.MMCM_CLKFBOUT_PHASE 0.000 \
+ CONFIG.MMCM_CLKFBOUT_USE_FINE_PS false \
+ CONFIG.MMCM_CLKIN1_PERIOD 10.0 \
+ CONFIG.MMCM_CLKIN2_PERIOD 10.0 \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F 6.000 \
+ CONFIG.MMCM_CLKOUT0_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT0_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT0_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT1_DIVIDE 3 \
+ CONFIG.MMCM_CLKOUT1_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT1_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT1_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT2_DIVIDE 50 \
+ CONFIG.MMCM_CLKOUT2_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT2_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT2_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT3_DIVIDE 12 \
+ CONFIG.MMCM_CLKOUT3_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT3_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT3_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT4_CASCADE false \
+ CONFIG.MMCM_CLKOUT4_DIVIDE 1 \
+ CONFIG.MMCM_CLKOUT4_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT4_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT4_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT5_DIVIDE 1 \
+ CONFIG.MMCM_CLKOUT5_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT5_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT5_USE_FINE_PS false \
+ CONFIG.MMCM_CLKOUT6_DIVIDE 1 \
+ CONFIG.MMCM_CLKOUT6_DUTY_CYCLE 0.500 \
+ CONFIG.MMCM_CLKOUT6_PHASE 0.000 \
+ CONFIG.MMCM_CLKOUT6_USE_FINE_PS false \
+ CONFIG.MMCM_CLOCK_HOLD false \
+ CONFIG.MMCM_COMPENSATION ZHOLD \
+ CONFIG.MMCM_DIVCLK_DIVIDE 1 \
+ CONFIG.MMCM_NOTES None \
+ CONFIG.MMCM_REF_JITTER1 0.010 \
+ CONFIG.MMCM_REF_JITTER2 0.010 \
+ CONFIG.MMCM_STARTUP_WAIT false \
+ CONFIG.NUM_OUT_CLKS 4 \
+ CONFIG.OVERRIDE_MMCM false \
+ CONFIG.OVERRIDE_PLL false \
+ CONFIG.PHASE_DUTY_CONFIG false \
+ CONFIG.PLATFORM UNKNOWN \
+ CONFIG.PLL_BANDWIDTH OPTIMIZED \
+ CONFIG.PLL_CLKFBOUT_MULT 4 \
+ CONFIG.PLL_CLKFBOUT_PHASE 0.000 \
+ CONFIG.PLL_CLKIN_PERIOD 10.000 \
+ CONFIG.PLL_CLKOUT0_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT0_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT0_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT1_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT1_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT1_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT2_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT2_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT2_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT3_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT3_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT3_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT4_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT4_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT4_PHASE 0.000 \
+ CONFIG.PLL_CLKOUT5_DIVIDE 1 \
+ CONFIG.PLL_CLKOUT5_DUTY_CYCLE 0.500 \
+ CONFIG.PLL_CLKOUT5_PHASE 0.000 \
+ CONFIG.PLL_CLK_FEEDBACK CLKFBOUT \
+ CONFIG.PLL_COMPENSATION SYSTEM_SYNCHRONOUS \
+ CONFIG.PLL_DIVCLK_DIVIDE 1 \
+ CONFIG.PLL_NOTES None \
+ CONFIG.PLL_REF_JITTER 0.010 \
+ CONFIG.POWER_DOWN_PORT power_down \
+ CONFIG.PRIMARY_PORT clk_in1 \
+ CONFIG.PRIMITIVE MMCM \
+ CONFIG.PRIMTYPE_SEL mmcm_adv \
+ CONFIG.PRIM_IN_FREQ 100.000 \
+ CONFIG.PRIM_IN_JITTER 0.010 \
+ CONFIG.PRIM_IN_TIMEPERIOD 10.000 \
+ CONFIG.PRIM_SOURCE Single_ended_clock_capable_pin \
+ CONFIG.PSCLK_PORT psclk \
+ CONFIG.PSDONE_PORT psdone \
+ CONFIG.PSEN_PORT psen \
+ CONFIG.PSINCDEC_PORT psincdec \
+ CONFIG.RELATIVE_INCLK REL_PRIMARY \
+ CONFIG.RESET_BOARD_INTERFACE Custom \
+ CONFIG.RESET_PORT reset \
+ CONFIG.RESET_TYPE ACTIVE_HIGH \
+ CONFIG.SECONDARY_IN_FREQ 100.000 \
+ CONFIG.SECONDARY_IN_JITTER 0.010 \
+ CONFIG.SECONDARY_IN_TIMEPERIOD 10.000 \
+ CONFIG.SECONDARY_PORT clk_in2 \
+ CONFIG.SECONDARY_SOURCE Single_ended_clock_capable_pin \
+ CONFIG.SS_MODE CENTER_HIGH \
+ CONFIG.SS_MOD_FREQ 250 \
+ CONFIG.SS_MOD_TIME 0.004 \
+ CONFIG.STATUS_PORT STATUS \
+ CONFIG.SUMMARY_STRINGS empty \
+ CONFIG.USE_BOARD_FLOW false \
+ CONFIG.USE_CLKFB_STOPPED false \
+ CONFIG.USE_CLK_VALID false \
+ CONFIG.USE_CLOCK_SEQUENCING false \
+ CONFIG.USE_DYN_PHASE_SHIFT false \
+ CONFIG.USE_DYN_RECONFIG false \
+ CONFIG.USE_FREEZE false \
+ CONFIG.USE_FREQ_SYNTH true \
+ CONFIG.USE_INCLK_STOPPED false \
+ CONFIG.USE_INCLK_SWITCHOVER false \
+ CONFIG.USE_LOCKED true \
+ CONFIG.USE_MAX_I_JITTER false \
+ CONFIG.USE_MIN_O_JITTER false \
+ CONFIG.USE_MIN_POWER false \
+ CONFIG.USE_PHASE_ALIGNMENT true \
+ CONFIG.USE_POWER_DOWN false \
+ CONFIG.USE_RESET false \
+ CONFIG.USE_SAFE_CLOCK_STARTUP false \
+ CONFIG.USE_SPREAD_SPECTRUM false \
+ CONFIG.USE_STATUS false " [get_ips clk_wiz_0]
+
+
+
+
+
+
+
+Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+| Date : Thu Jan 21 15:55:32 2016
+| Host : WK86 running 64-bit Service Pack 1 (build 7601)
+| Command : upgrade_ip
+| Device : xc7a200tsbg484-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'clk_wiz_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of clk_wiz_0 from xilinx.com:ip:clk_wiz:5.1 (Rev. 7) to xilinx.com:ip:clk_wiz:5.2
+
+2. Upgrade messages
+-------------------
+
+Removed parameter PRIM_IN_FREQ
+Added parameter PRIM_IN_FREQ with value 100.000 (source 'default')
+
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.v b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.v
new file mode 100644
index 0000000..2e3a203
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.v
@@ -0,0 +1,100 @@
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+// CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+// CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+// CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module clk_wiz_0
+ (
+ // Clock in ports
+ input clk_in1,
+ // Clock out ports
+ output clk_out1,
+ output clk_out2,
+ output clk_out3,
+ output clk_out4,
+ // Status and control signals
+ input reset,
+ output locked
+ );
+
+ clk_wiz_0_clk_wiz inst
+ (
+ // Clock in ports
+ .clk_in1(clk_in1),
+ // Clock out ports
+ .clk_out1(clk_out1),
+ .clk_out2(clk_out2),
+ .clk_out3(clk_out3),
+ .clk_out4(clk_out4),
+ // Status and control signals
+ .reset(reset),
+ .locked(locked)
+ );
+
+endmodule
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.vho b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100644
index 0000000..c6b126b
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,103 @@
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+-- CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+-- CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+-- CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ clk_in1 : in std_logic;
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ clk_out2 : out std_logic;
+ clk_out3 : out std_logic;
+ clk_out4 : out std_logic;
+ -- Status and control signals
+ reset : in std_logic;
+ locked : out std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+
+ -- Clock in ports
+ clk_in1 => clk_in1,
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ -- Status and control signals
+ reset => reset,
+ locked => locked
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xci b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xci
new file mode 100644
index 0000000..79f1c0a
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xci
@@ -0,0 +1,525 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>clk_wiz_0</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______151.366____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______132.221____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____12.000______0.000______50.0______231.952____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4____50.000______0.000______50.0______174.353____132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">151.366</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">132.221</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">231.952</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">12.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">174.353</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">132.063</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">6.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">6.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">50</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">sbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xdc b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xdc
new file mode 100644
index 0000000..420a6de
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xdc
@@ -0,0 +1,59 @@
+# file: clk_wiz_0.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 10.0 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.10000000000000001
+
+
+
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xml b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xml
new file mode 100644
index 0000000..66fd124
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0.xml
@@ -0,0 +1,4933 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
+ <spirit:name>clk_wiz_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>s_axi_lite</spirit:name>
+ <spirit:displayName>S_AXI_LITE</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
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+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_RESET" spirit:order="227">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_RESET_LOW</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_LOW" spirit:order="408">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_LOCKED" spirit:order="228">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_STOPPED" spirit:order="229">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED" spirit:order="230">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_POWER_DOWN" spirit:order="231">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_STATUS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STATUS" spirit:order="232">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREEZE" spirit:order="233">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OUT_CLKS" spirit:order="234">4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DRIVES" spirit:order="235">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DRIVES" spirit:order="236">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DRIVES" spirit:order="237">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DRIVES" spirit:order="238">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DRIVES" spirit:order="239">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DRIVES" spirit:order="240">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DRIVES" spirit:order="241">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW0</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW0" spirit:order="242">Input Clock Freq (MHz) Input Jitter (UI)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW1" spirit:order="243">__primary_________100.000____________0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW2" spirit:order="244">no_secondary_input_clock </spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0A</spirit:name>
+ <spirit:displayName>C Outclk Sum Row0a</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A" spirit:order="245"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0B</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B" spirit:order="246"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">CLK_OUT1___100.000______0.000______50.0______151.366____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">CLK_OUT2___200.000______0.000______50.0______132.221____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">CLK_OUT3____12.000______0.000______50.0______231.952____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">CLK_OUT4____50.000______0.000______50.0______174.353____132.063</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5" spirit:order="251">no_CLK_OUT5_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6" spirit:order="252">no_CLK_OUT6_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7" spirit:order="253">no_CLK_OUT7_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="254">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">200.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="256">12.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="257">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="258">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="259">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="260">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE" spirit:order="261">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE" spirit:order="262">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE" spirit:order="263">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE" spirit:order="264">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE" spirit:order="265">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE" spirit:order="266">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE" spirit:order="267">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="268">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="269">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="270">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="271">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="272">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="273">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="274">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">200.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">12.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ" spirit:order="279">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ" spirit:order="280">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ" spirit:order="281">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_PHASE" spirit:order="282">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_PHASE" spirit:order="283">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_PHASE" spirit:order="284">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_PHASE" spirit:order="285">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_PHASE" spirit:order="286">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_PHASE" spirit:order="287">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_PHASE" spirit:order="288">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE" spirit:order="289">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE" spirit:order="290">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE" spirit:order="291">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE" spirit:order="292">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE" spirit:order="293">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE" spirit:order="294">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE" spirit:order="295">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP" spirit:order="500">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING" spirit:order="501">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER" spirit:order="502">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER" spirit:order="503">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER" spirit:order="504">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER" spirit:order="505">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER" spirit:order="506">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER" spirit:order="507">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER" spirit:order="508">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_NOTES" spirit:order="296">None</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_BANDWIDTH" spirit:order="297">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F" spirit:order="298">6.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD" spirit:order="299">10.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD" spirit:order="300">10.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE" spirit:order="301">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD" spirit:order="302">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_COMPENSATION" spirit:order="303">ZHOLD</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE" spirit:order="304">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER1" spirit:order="305">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER2" spirit:order="306">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">6.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">50</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">12</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="315">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="316">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="317">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="318">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="319">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="320">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="321">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE" spirit:order="322">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE" spirit:order="323">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE" spirit:order="324">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE" spirit:order="325">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE" spirit:order="326">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE" spirit:order="327">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE" spirit:order="328">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE" spirit:order="329">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="330">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS" spirit:order="331">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS" spirit:order="332">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS" spirit:order="333">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS" spirit:order="334">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS" spirit:order="335">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS" spirit:order="336">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS" spirit:order="337">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_NOTES" spirit:order="338">No notes</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_BANDWIDTH" spirit:order="339">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK" spirit:order="340">CLKFBOUT</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT" spirit:order="341">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD" spirit:order="342">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_COMPENSATION" spirit:order="343">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE" spirit:order="344">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_REF_JITTER" spirit:order="345">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE" spirit:order="346">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE" spirit:order="347">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE" spirit:order="348">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE" spirit:order="349">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE" spirit:order="350">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE" spirit:order="351">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE" spirit:order="352">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE" spirit:order="353">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE" spirit:order="354">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE" spirit:order="355">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE" spirit:order="356">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE" spirit:order="357">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE" spirit:order="358">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE" spirit:order="359">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE" spirit:order="360">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE" spirit:order="361">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE" spirit:order="362">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE" spirit:order="363">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE" spirit:order="364">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLOCK_MGR_TYPE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE" spirit:order="365">NA</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_MMCM" spirit:order="366">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_PLL" spirit:order="367">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">reset</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_HAS_CDDC</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_876bfc32</spirit:name>
+ <spirit:enumeration>UI</spirit:enumeration>
+ <spirit:enumeration>PS</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_a9bdfce0</spirit:name>
+ <spirit:enumeration>LOW</spirit:enumeration>
+ <spirit:enumeration>HIGH</spirit:enumeration>
+ <spirit:enumeration>OPTIMIZED</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_ac75ef1e</spirit:name>
+ <spirit:enumeration>Custom</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_b9d38208</spirit:name>
+ <spirit:enumeration>CLKFBOUT</spirit:enumeration>
+ <spirit:enumeration>CLKOUT0</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_e099fe6c</spirit:name>
+ <spirit:enumeration>MMCM</spirit:enumeration>
+ <spirit:enumeration>PLL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_035ca1c3</spirit:name>
+ <spirit:enumeration spirit:text="SYSTEM SYNCHRONOUS">SYSTEM_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="SOURCE SYNCHRONOUS">SOURCE_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_0920eb1b</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_11d71346</spirit:name>
+ <spirit:enumeration spirit:text="Single ended clock capable pin">Single_ended_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential clock capable pin">Differential_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Global buffer">Global_buffer</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_15c806d5</spirit:name>
+ <spirit:enumeration spirit:text="Automatic Control On-Chip">FDBK_AUTO</spirit:enumeration>
+ <spirit:enumeration spirit:text="Automatic Control Off-Chip">FDBK_AUTO_OFFCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_3c2d3ec7</spirit:name>
+ <spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential">DIFF</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_502d9f23</spirit:name>
+ <spirit:enumeration spirit:text="ZHOLD">ZHOLD</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUF IN">BUF_IN</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_66e4c81f</spirit:name>
+ <spirit:enumeration spirit:text="BUFG">BUFG</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFH">BUFH</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE">BUFGCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFHCE">BUFHCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8b28f1f7</spirit:name>
+ <spirit:enumeration spirit:text="AXI4Lite">Enable_AXI</spirit:enumeration>
+ <spirit:enumeration spirit:text="DRP">Enable_DRP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8eea9b32</spirit:name>
+ <spirit:enumeration spirit:text="Units MHz">Units_MHz</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ns">Units_ns</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a4fbc00c</spirit:name>
+ <spirit:enumeration spirit:text="Active High">ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="Active Low">ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a8642b4c</spirit:name>
+ <spirit:enumeration spirit:text="Balanced">No_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Minimize Output Jitter">Min_O_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Maximize Input Jitter filtering">Max_I_Jitter</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_c5ef7212</spirit:name>
+ <spirit:enumeration spirit:text="Units UI">Units_UI</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ps">Units_ps</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_e1c87518</spirit:name>
+ <spirit:enumeration spirit:text="Primary Clock">REL_PRIMARY</spirit:enumeration>
+ <spirit:enumeration spirit:text="Secondary Clock">REL_SECONDARY</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f4e10086</spirit:name>
+ <spirit:enumeration spirit:text="CENTER HIGH">CENTER_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="CENTER LOW">CENTER_LOW</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN HIGH">DOWN_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN LOW">DOWN_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f669c2f5</spirit:name>
+ <spirit:enumeration spirit:text="Frequency">frequency</spirit:enumeration>
+ <spirit:enumeration spirit:text="Time">Time</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.vho</spirit:name>
+ <spirit:userFileType>vhdlTemplate</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:define>
+ <spirit:name>processing_order</spirit:name>
+ <spirit:value>early</spirit:value>
+ </spirit:define>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_board.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_board</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>doc/clk_wiz_v5_2_changelog.txt</spirit:name>
+ <spirit:userFileType>text</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clk_wiz_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMITIVE</spirit:name>
+ <spirit:displayName>Primitive</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMITIVE" spirit:choiceRef="choice_list_e099fe6c" spirit:order="2">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMTYPE_SEL</spirit:name>
+ <spirit:displayName>Primtype Sel</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMTYPE_SEL" spirit:order="3">mmcm_adv</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLOCK_MGR_TYPE</spirit:name>
+ <spirit:displayName>Clock Mgr Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_MGR_TYPE" spirit:order="410">auto</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREQ_SYNTH" spirit:order="6" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SPREAD_SPECTRUM" spirit:order="7" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PHASE_ALIGNMENT" spirit:order="8" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_POWER" spirit:order="9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_PHASE_SHIFT" spirit:order="10" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_RECONFIG" spirit:order="11" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_SEL" spirit:choiceRef="choice_pairs_a8642b4c" spirit:order="13" spirit:configGroups="0 NoDisplay">No_Jitter</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_FREQ" spirit:order="14.401" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_TIMEPERIOD" spirit:order="14.9" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_JITTER_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RELATIVE_INCLK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RELATIVE_INCLK" spirit:choiceRef="choice_pairs_e1c87518" spirit:order="17" spirit:configGroups="0 NoDisplay">REL_PRIMARY</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_SWITCHOVER" spirit:order="13.9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_FREQ" spirit:order="21.3" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD" spirit:order="21.299" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_PORT" spirit:order="20" spirit:configGroups="0 NoDisplay">clk_in2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="21" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_OPTIONS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_OPTIONS" spirit:choiceRef="choice_list_876bfc32" spirit:order="22" spirit:configGroups="0 NoDisplay">UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_UI_JITTER" spirit:order="23" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_UI_JITTER" spirit:order="24" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_JITTER" spirit:order="25" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_JITTER" spirit:order="26" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_JITTER_PS" spirit:order="27" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_JITTER_PS" spirit:order="28" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_USED" spirit:order="4" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_USED" spirit:order="29" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_USED" spirit:order="30" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_USED" spirit:order="31" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_USED" spirit:order="32" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_USED" spirit:order="33" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_USED" spirit:order="34" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OUT_CLKS" spirit:order="407" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI" spirit:order="36" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI" spirit:order="37" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI" spirit:order="38" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI" spirit:order="39" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI" spirit:order="40" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI" spirit:order="41" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI" spirit:order="42" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMARY_PORT" spirit:order="43" spirit:configGroups="0 NoDisplay">clk_in1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_PORT" spirit:order="44" spirit:configGroups="0 NoDisplay">clk_out1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_PORT" spirit:order="45" spirit:configGroups="0 NoDisplay">clk_out2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_PORT" spirit:order="46" spirit:configGroups="0 NoDisplay">clk_out3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_PORT" spirit:order="47" spirit:configGroups="0 NoDisplay">clk_out4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_PORT" spirit:order="48" spirit:configGroups="0 NoDisplay">clk_out5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_PORT" spirit:order="49" spirit:configGroups="0 NoDisplay">clk_out6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_PORT" spirit:order="50" spirit:configGroups="0 NoDisplay">clk_out7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DADDR_PORT" spirit:order="51" spirit:configGroups="0 NoDisplay">daddr</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DCLK_PORT" spirit:order="52" spirit:configGroups="0 NoDisplay">dclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DRDY_PORT" spirit:order="53" spirit:configGroups="0 NoDisplay">drdy</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DWE_PORT" spirit:order="54" spirit:configGroups="0 NoDisplay">dwe</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_PORT" spirit:order="55" spirit:configGroups="0 NoDisplay">din</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_PORT" spirit:order="56" spirit:configGroups="0 NoDisplay">dout</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DEN_PORT" spirit:order="57" spirit:configGroups="0 NoDisplay">den</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSCLK_PORT" spirit:order="58" spirit:configGroups="0 NoDisplay">psclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSEN_PORT" spirit:order="59" spirit:configGroups="0 NoDisplay">psen</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSINCDEC_PORT" spirit:order="60" spirit:configGroups="0 NoDisplay">psincdec</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSDONE_PORT" spirit:order="61" spirit:configGroups="0 NoDisplay">psdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="62" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" spirit:order="63" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="64" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">200.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE" spirit:order="66" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="67" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="68" spirit:configGroups="0 NoDisplay">12.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE" spirit:order="69" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="70" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="71" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" spirit:order="72" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="73" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="74" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE" spirit:order="75" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="76" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="77" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE" spirit:order="78" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="79" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="80" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE" spirit:order="81" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="82" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MAX_I_JITTER" spirit:order="83" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="86" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="87" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="88" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="89" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="90" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="91" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="92" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FEEDBACK_SOURCE" spirit:choiceRef="choice_pairs_15c806d5" spirit:order="93" spirit:configGroups="0 NoDisplay">FDBK_AUTO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_SIGNALING" spirit:choiceRef="choice_pairs_3c2d3ec7" spirit:order="94" spirit:configGroups="0 NoDisplay">SINGLE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_PORT" spirit:order="95" spirit:configGroups="0 NoDisplay">clkfb_in</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_P_PORT" spirit:order="96" spirit:configGroups="0 NoDisplay">clkfb_in_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_N_PORT" spirit:order="97" spirit:configGroups="0 NoDisplay">clkfb_in_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_PORT" spirit:order="98" spirit:configGroups="0 NoDisplay">clkfb_out</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_P_PORT" spirit:order="99" spirit:configGroups="0 NoDisplay">clkfb_out_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_N_PORT" spirit:order="100" spirit:configGroups="0 NoDisplay">clkfb_out_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLATFORM" spirit:order="101" spirit:configGroups="0 NoDisplay">UNKNOWN</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUMMARY_STRINGS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SUMMARY_STRINGS" spirit:order="102" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_LOCKED" spirit:order="103" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CALC_DONE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CALC_DONE" spirit:order="104" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_RESET</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_RESET" spirit:order="105" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_POWER_DOWN" spirit:order="106" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_STATUS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_STATUS" spirit:order="107" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREEZE" spirit:order="108" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLK_VALID" spirit:order="109" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_STOPPED" spirit:order="110" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLKFB_STOPPED" spirit:order="111" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_PORT" spirit:order="409" spirit:configGroups="0 NoDisplay">reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCKED_PORT" spirit:order="113" spirit:configGroups="0 NoDisplay">locked</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POWER_DOWN_PORT" spirit:order="114" spirit:configGroups="0 NoDisplay">power_down</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_VALID_PORT" spirit:order="115" spirit:configGroups="0 NoDisplay">CLK_VALID</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STATUS_PORT" spirit:order="116" spirit:configGroups="0 NoDisplay">STATUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN_SEL_PORT" spirit:order="117" spirit:configGroups="0 NoDisplay">clk_in_sel</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" spirit:order="118" spirit:configGroups="0 NoDisplay">input_clk_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_STOPPED_PORT" spirit:order="119" spirit:configGroups="0 NoDisplay">clkfb_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MODE" spirit:choiceRef="choice_pairs_f4e10086" spirit:order="120" spirit:configGroups="0 NoDisplay">CENTER_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_FREQ" spirit:order="121" spirit:configGroups="0 NoDisplay">250</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_TIME" spirit:order="121.001" spirit:configGroups="0 NoDisplay">0.004</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_MMCM" spirit:order="122" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_NOTES" spirit:order="123" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="106" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="125" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" spirit:order="126" spirit:configGroups="0 NoDisplay">6.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_PHASE" spirit:order="127" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="128" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN1_PERIOD" spirit:order="129" spirit:configGroups="0 NoDisplay">10.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN2_PERIOD" spirit:order="130" spirit:configGroups="0 NoDisplay">10.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_CASCADE" spirit:order="131" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLOCK_HOLD" spirit:order="132" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_COMPENSATION" spirit:choiceRef="choice_pairs_502d9f23" spirit:order="133" spirit:configGroups="0 NoDisplay">ZHOLD</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER1" spirit:order="134" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER2" spirit:order="135" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_STARTUP_WAIT" spirit:order="136" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" spirit:order="137" spirit:configGroups="0 NoDisplay">6.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="138" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_PHASE" spirit:order="139" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS" spirit:order="140" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="142" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_PHASE" spirit:order="143" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS" spirit:order="144" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="146" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_PHASE" spirit:order="147" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS" spirit:order="148" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">12</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="150" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_PHASE" spirit:order="151" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS" spirit:order="152" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="154" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_PHASE" spirit:order="155" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS" spirit:order="156" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="158" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_PHASE" spirit:order="159" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS" spirit:order="160" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="162" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_PHASE" spirit:order="163" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS" spirit:order="164" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_PLL" spirit:order="165" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_NOTES" spirit:order="166" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="167" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_MULT" spirit:order="168" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_PHASE" spirit:order="169" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLK_FEEDBACK" spirit:choiceRef="choice_list_b9d38208" spirit:order="170" spirit:configGroups="0 NoDisplay">CLKFBOUT</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_DIVCLK_DIVIDE" spirit:order="171" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="52" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKIN_PERIOD" spirit:order="172" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_COMPENSATION" spirit:choiceRef="choice_pairs_035ca1c3" spirit:order="173" spirit:configGroups="0 NoDisplay">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_REF_JITTER" spirit:order="174" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DIVIDE" spirit:order="175" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE" spirit:order="176" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_PHASE" spirit:order="177" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DIVIDE" spirit:order="178" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE" spirit:order="179" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_PHASE" spirit:order="180" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DIVIDE" spirit:order="181" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE" spirit:order="182" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_PHASE" spirit:order="183" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DIVIDE" spirit:order="184" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE" spirit:order="185" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_PHASE" spirit:order="186" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DIVIDE" spirit:order="187" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE" spirit:order="188" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_PHASE" spirit:order="189" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DIVIDE" spirit:order="190" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE" spirit:order="191" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_PHASE" spirit:order="192" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_TYPE</spirit:name>
+ <spirit:displayName>Reset Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_TYPE" spirit:choiceRef="choice_pairs_a4fbc00c" spirit:order="408" spirit:configGroups="0 NoDisplay">ACTIVE_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" spirit:order="85.5" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLOCK_SEQUENCING" spirit:order="501" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER" spirit:order="502" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER" spirit:order="503" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER" spirit:order="504" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER" spirit:order="505" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER" spirit:order="506" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER" spirit:order="507" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER" spirit:order="508" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_BOARD_FLOW</spirit:name>
+ <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.8">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.9">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.1">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CDDC</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CDDC" spirit:order="509">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCDONE_PORT" spirit:order="510" spirit:configGroups="0 NoDisplay">cddcdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCREQ_PORT" spirit:order="511" spirit:configGroups="0 NoDisplay">cddcreq</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLKOUTPHY" spirit:order="123.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUTPHY_REQUESTED_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ" spirit:order="123.2" spirit:configGroups="0 NoDisplay">600.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_JITTER</spirit:name>
+ <spirit:displayName>Clkout1 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_JITTER" spirit:order="1000">151.366</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout1 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_PHASE_ERROR" spirit:order="1001">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_JITTER</spirit:name>
+ <spirit:displayName>Clkout2 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">132.221</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout2 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_PHASE_ERROR" spirit:order="1003">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_JITTER</spirit:name>
+ <spirit:displayName>Clkout3 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_JITTER" spirit:order="1004">231.952</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout3 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_PHASE_ERROR" spirit:order="1005">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_JITTER</spirit:name>
+ <spirit:displayName>Clkout4 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_JITTER" spirit:order="1006">174.353</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout4 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_PHASE_ERROR" spirit:order="1007">132.063</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_JITTER</spirit:name>
+ <spirit:displayName>Clkout5 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_JITTER" spirit:order="1008">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout5 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_PHASE_ERROR" spirit:order="1009">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_JITTER</spirit:name>
+ <spirit:displayName>Clkout6 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_JITTER" spirit:order="1010">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout6 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_PHASE_ERROR" spirit:order="1011">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_JITTER</spirit:name>
+ <spirit:displayName>Clkout7 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_JITTER" spirit:order="1012">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout7 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_PHASE_ERROR" spirit:order="1013">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="14.4">frequency</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE_DUTY_CONFIG</spirit:name>
+ <spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PHASE_DUTY_CONFIG">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>Clocking Wizard</xilinx:displayName>
+ <xilinx:coreRevision>0</xilinx:coreRevision>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2015.3</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="69bff2c8"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3a523104"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="a5d35bf6"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="18e8d175"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="09870f83"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_board.xdc b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
new file mode 100644
index 0000000..3422a8e
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_board.xdc
@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
new file mode 100644
index 0000000..e47643a
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
@@ -0,0 +1,215 @@
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1___100.000______0.000______50.0______151.366____132.063
+// CLK_OUT2___200.000______0.000______50.0______132.221____132.063
+// CLK_OUT3____12.000______0.000______50.0______231.952____132.063
+// CLK_OUT4____50.000______0.000______50.0______174.353____132.063
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+module clk_wiz_0_clk_wiz
+ (// Clock in ports
+ input clk_in1,
+ // Clock out ports
+ output clk_out1,
+ output clk_out2,
+ output clk_out3,
+ output clk_out4,
+ // Status and control signals
+ input reset,
+ output locked
+ );
+
+ // Input buffering
+ //------------------------------------
+ IBUF clkin1_ibufg
+ (.O (clk_in1_clk_wiz_0),
+ .I (clk_in1));
+
+
+
+ // Clocking PRIMITIVE
+ //------------------------------------
+
+ // Instantiation of the MMCM PRIMITIVE
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire [15:0] do_unused;
+ wire drdy_unused;
+ wire psdone_unused;
+ wire locked_int;
+ wire clkfbout_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfboutb_unused;
+ wire clkout0b_unused;
+ wire clkout1b_unused;
+ wire clkout2b_unused;
+ wire clkout3b_unused;
+ wire clkout4_unused;
+ wire clkout5_unused;
+ wire clkout6_unused;
+ wire clkfbstopped_unused;
+ wire clkinstopped_unused;
+ wire reset_high;
+
+ MMCME2_ADV
+ #(.BANDWIDTH ("OPTIMIZED"),
+ .CLKOUT4_CASCADE ("FALSE"),
+ .COMPENSATION ("ZHOLD"),
+ .STARTUP_WAIT ("FALSE"),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT_F (6.000),
+ .CLKFBOUT_PHASE (0.000),
+ .CLKFBOUT_USE_FINE_PS ("FALSE"),
+ .CLKOUT0_DIVIDE_F (6.000),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT0_USE_FINE_PS ("FALSE"),
+ .CLKOUT1_DIVIDE (3),
+ .CLKOUT1_PHASE (0.000),
+ .CLKOUT1_DUTY_CYCLE (0.500),
+ .CLKOUT1_USE_FINE_PS ("FALSE"),
+ .CLKOUT2_DIVIDE (50),
+ .CLKOUT2_PHASE (0.000),
+ .CLKOUT2_DUTY_CYCLE (0.500),
+ .CLKOUT2_USE_FINE_PS ("FALSE"),
+ .CLKOUT3_DIVIDE (12),
+ .CLKOUT3_PHASE (0.000),
+ .CLKOUT3_DUTY_CYCLE (0.500),
+ .CLKOUT3_USE_FINE_PS ("FALSE"),
+ .CLKIN1_PERIOD (10.0))
+ mmcm_adv_inst
+ // Output clocks
+ (
+ .CLKFBOUT (clkfbout_clk_wiz_0),
+ .CLKFBOUTB (clkfboutb_unused),
+ .CLKOUT0 (clk_out1_clk_wiz_0),
+ .CLKOUT0B (clkout0b_unused),
+ .CLKOUT1 (clk_out2_clk_wiz_0),
+ .CLKOUT1B (clkout1b_unused),
+ .CLKOUT2 (clk_out3_clk_wiz_0),
+ .CLKOUT2B (clkout2b_unused),
+ .CLKOUT3 (clk_out4_clk_wiz_0),
+ .CLKOUT3B (clkout3b_unused),
+ .CLKOUT4 (clkout4_unused),
+ .CLKOUT5 (clkout5_unused),
+ .CLKOUT6 (clkout6_unused),
+ // Input clock control
+ .CLKFBIN (clkfbout_buf_clk_wiz_0),
+ .CLKIN1 (clk_in1_clk_wiz_0),
+ .CLKIN2 (1'b0),
+ // Tied to always select the primary input clock
+ .CLKINSEL (1'b1),
+ // Ports for dynamic reconfiguration
+ .DADDR (7'h0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'h0),
+ .DO (do_unused),
+ .DRDY (drdy_unused),
+ .DWE (1'b0),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (psdone_unused),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .CLKINSTOPPED (clkinstopped_unused),
+ .CLKFBSTOPPED (clkfbstopped_unused),
+ .PWRDWN (1'b0),
+ .RST (reset_high));
+
+ assign reset_high = reset;
+
+ assign locked = locked_int;
+
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkf_buf
+ (.O (clkfbout_buf_clk_wiz_0),
+ .I (clkfbout_clk_wiz_0));
+
+
+
+ BUFG clkout1_buf
+ (.O (clk_out1),
+ .I (clk_out1_clk_wiz_0));
+
+
+ BUFG clkout2_buf
+ (.O (clk_out2),
+ .I (clk_out2_clk_wiz_0));
+
+ BUFG clkout3_buf
+ (.O (clk_out3),
+ .I (clk_out3_clk_wiz_0));
+
+ BUFG clkout4_buf
+ (.O (clk_out4),
+ .I (clk_out4_clk_wiz_0));
+
+
+
+endmodule
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
new file mode 100644
index 0000000..41c79d7
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
@@ -0,0 +1,56 @@
+# file: clk_wiz_0_ooc.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints #
+############################################################
+#create_clock -period 10.0 [get_ports clk_in1]
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
new file mode 100644
index 0000000..e0a8184
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
@@ -0,0 +1,278 @@
+// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+// Date : Thu Jan 21 17:13:26 2016
+// Host : WK86 running 64-bit Service Pack 1 (build 7601)
+// Command : write_verilog -force -mode funcsim C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+// Design : clk_wiz_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+(* NotValidForBitStream *)
+module clk_wiz_0
+ (clk_in1,
+ clk_out1,
+ clk_out2,
+ clk_out3,
+ clk_out4,
+ reset,
+ locked);
+ input clk_in1;
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire clk_out2;
+ wire clk_out3;
+ wire clk_out4;
+ wire locked;
+ wire reset;
+
+ clk_wiz_0_clk_wiz_0_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .clk_out2(clk_out2),
+ .clk_out3(clk_out3),
+ .clk_out4(clk_out4),
+ .locked(locked),
+ .reset(reset));
+endmodule
+
+(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
+module clk_wiz_0_clk_wiz_0_clk_wiz
+ (clk_in1,
+ clk_out1,
+ clk_out2,
+ clk_out3,
+ clk_out4,
+ reset,
+ locked);
+ input clk_in1;
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+
+ wire clk_in1;
+ wire clk_in1_clk_wiz_0;
+ wire clk_out1;
+ wire clk_out1_clk_wiz_0;
+ wire clk_out2;
+ wire clk_out2_clk_wiz_0;
+ wire clk_out3;
+ wire clk_out3_clk_wiz_0;
+ wire clk_out4;
+ wire clk_out4_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfbout_clk_wiz_0;
+ wire locked;
+ wire reset;
+ wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+ wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_clk_wiz_0),
+ .O(clkfbout_buf_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_clk_wiz_0),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout2_buf
+ (.I(clk_out2_clk_wiz_0),
+ .O(clk_out2));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout3_buf
+ (.I(clk_out3_clk_wiz_0),
+ .O(clk_out3));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout4_buf
+ (.I(clk_out4_clk_wiz_0),
+ .O(clk_out4));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ MMCME2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(6.000000),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKFBOUT_USE_FINE_PS("FALSE"),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE_F(6.000000),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT0_USE_FINE_PS("FALSE"),
+ .CLKOUT1_DIVIDE(3),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT1_USE_FINE_PS("FALSE"),
+ .CLKOUT2_DIVIDE(50),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT2_USE_FINE_PS("FALSE"),
+ .CLKOUT3_DIVIDE(12),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT3_USE_FINE_PS("FALSE"),
+ .CLKOUT4_CASCADE("FALSE"),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT4_USE_FINE_PS("FALSE"),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .CLKOUT5_USE_FINE_PS("FALSE"),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.500000),
+ .CLKOUT6_PHASE(0.000000),
+ .CLKOUT6_USE_FINE_PS("FALSE"),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PSEN_INVERTED(1'b0),
+ .IS_PSINCDEC_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .SS_EN("FALSE"),
+ .SS_MODE("CENTER_HIGH"),
+ .SS_MOD_PERIOD(10000),
+ .STARTUP_WAIT("FALSE"))
+ mmcm_adv_inst
+ (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+ .CLKFBOUT(clkfbout_clk_wiz_0),
+ .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+ .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+ .CLKIN1(clk_in1_clk_wiz_0),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+ .CLKOUT0(clk_out1_clk_wiz_0),
+ .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+ .CLKOUT1(clk_out2_clk_wiz_0),
+ .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+ .CLKOUT2(clk_out3_clk_wiz_0),
+ .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+ .CLKOUT3(clk_out4_clk_wiz_0),
+ .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+ .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+ .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(locked),
+ .PSCLK(1'b0),
+ .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .PWRDWN(1'b0),
+ .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
new file mode 100644
index 0000000..84ae83d
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
@@ -0,0 +1,218 @@
+-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+-- Date : Thu Jan 21 17:13:26 2016
+-- Host : WK86 running 64-bit Service Pack 1 (build 7601)
+-- Command : write_vhdl -force -mode funcsim C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+-- Design : clk_wiz_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0_clk_wiz_0_clk_wiz is
+ port (
+ clk_in1 : in STD_LOGIC;
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
+end clk_wiz_0_clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
+ signal clk_in1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out2_clk_wiz_0 : STD_LOGIC;
+ signal clk_out3_clk_wiz_0 : STD_LOGIC;
+ signal clk_out4_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_clk_wiz_0 : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_clk_wiz_0,
+ O => clkfbout_buf_clk_wiz_0
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_clk_wiz_0
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_clk_wiz_0,
+ O => clk_out1
+ );
+clkout2_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out2_clk_wiz_0,
+ O => clk_out2
+ );
+clkout3_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out3_clk_wiz_0,
+ O => clk_out3
+ );
+clkout4_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out4_clk_wiz_0,
+ O => clk_out4
+ );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 6.000000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => false,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 6.000000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => false,
+ CLKOUT1_DIVIDE => 3,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => false,
+ CLKOUT2_DIVIDE => 50,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => false,
+ CLKOUT3_DIVIDE => 12,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => false,
+ CLKOUT4_CASCADE => false,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => false,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => false,
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => false,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => false
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_clk_wiz_0,
+ CLKFBOUT => clkfbout_clk_wiz_0,
+ CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1_clk_wiz_0,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_clk_wiz_0,
+ CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => clk_out2_clk_wiz_0,
+ CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => clk_out3_clk_wiz_0,
+ CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => clk_out4_clk_wiz_0,
+ CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PSCLK => '0',
+ PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => reset
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0 is
+ port (
+ clk_in1 : in STD_LOGIC;
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of clk_wiz_0 : entity is true;
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_2_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
+end clk_wiz_0;
+
+architecture STRUCTURE of clk_wiz_0 is
+begin
+inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ clk_out2 => clk_out2,
+ clk_out3 => clk_out3,
+ clk_out4 => clk_out4,
+ locked => locked,
+ reset => reset
+ );
+end STRUCTURE;
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.v b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.v
new file mode 100644
index 0000000..3e730b7
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -0,0 +1,24 @@
+// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+// Date : Thu Jan 21 17:13:26 2016
+// Host : WK86 running 64-bit Service Pack 1 (build 7601)
+// Command : write_verilog -force -mode synth_stub C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_in1, clk_out1, clk_out2, clk_out3, clk_out4, reset, locked)
+/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,clk_out2,clk_out3,clk_out4,reset,locked" */;
+ input clk_in1;
+ output clk_out1;
+ output clk_out2;
+ output clk_out3;
+ output clk_out4;
+ input reset;
+ output locked;
+endmodule
diff --git a/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
new file mode 100644
index 0000000..262c691
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -0,0 +1,33 @@
+-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
+-- Date : Thu Jan 21 17:13:26 2016
+-- Host : WK86 running 64-bit Service Pack 1 (build 7601)
+-- Command : write_vhdl -force -mode synth_stub C:/Work/Github/Working/Looper/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+ Port (
+ clk_in1 : in STD_LOGIC;
+ clk_out1 : out STD_LOGIC;
+ clk_out2 : out STD_LOGIC;
+ clk_out3 : out STD_LOGIC;
+ clk_out4 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC
+ );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,clk_out2,clk_out3,clk_out4,reset,locked";
+begin
+end;
diff --git a/tp_vivado/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt b/tp_vivado/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
new file mode 100644
index 0000000..c88739c
--- /dev/null
+++ b/tp_vivado/src/ip/clk_wiz_0/doc/clk_wiz_v5_2_changelog.txt
@@ -0,0 +1,115 @@
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2015 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
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+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
--
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