diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 30ffa402b4a5440dfd639740383f7229b380b3c1..76cfa08bc48722713a2cd658c4c363e8a49570bb 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -6,16 +6,89 @@ output: pdf_document
mainfont: sans-serif
---
-# Compte rendu du TP Carrefour
+# Compte rendu du TP ECG
## Diagramme de la FSM
+When a valid input sample is detected, the control unit begins processing with filter type 00. The first filter type is a FIR filter with symmetrical coefficients. Therefore, the state machine transitions to the State Filter Symmetrical state, which is divided into two processing loops:
+
+- The first loop increments the address from the beginning to the last coefficient.
+
+- The second loop decrements the address in reverse.
+
+This symmetrical structure allows reducing memory usage by half, since only half of the coefficients need to be stored.
+
+Next, the filter type is incremented, transitioning to filter type 01, corresponding to an IIR filter. This type is split into two parts: coefficient A and coefficient B. To optimize memory usage in the sample register, the increment address signal is disabled when transitioning from the A to the B coefficient state. This ensures that the same input samples are used while applying a different set of coefficients.
+
+The filter type is then incremented again to type 10, representing another FIR filter with different coefficients.
+
+After completing the three filter types, the state machine detects that the filter counter has reached its final value (SR_filter = 3). It then transitions to the State Output, where the accumulated sum is loaded and stored as the final output. Finally, the machine moves to the Wait end sample state, where it signals that the filtered sample is valid by setting O_FilteredSampleValid = '1'.
+
## Architecture de l'unité opérative
-## Remarques
+## Summation
+
+### Estimating for the Worst Case
+
+acc_size = ∑ (a_i * b_i), from i = 1 to N
+
+- All filters have the same size
+- **For Filter 1:**
+ - a has 12 bits, b has 11 bits
+ - Each product can have up to **23 bits**
+ - Max value for 12 bits: (2^12 - 1), for 11 bits: (2^11 - 1)
+ - Number of operations: N = 129
+
+ acc1 = log2(129 * (2^12 - 1)^2)
+ acc1 ≈ log2(129 * 8382465) = 30.0101 ≈ **31 bits**
+
+- **For Filter 2:**
+
+ acc2 = log2(6 * 8382465) = 25.5839 ≈ **26 bits**
+
+- **For Filter 3:**
+
+ acc3 = log2(11 * 8382465) = 26.4583 ≈ **27 bits**
+
+### Worst Case Summation
+
+log2(2^31 + 2^26 + 2^25) = 31.066 ≈ **32 bits**
+
+---
+
+## Optimizations
+
+Since the coefficients of Filter 1 and Filter 2 are **symmetric**, we can store only half + 1.
+To enable this, the increment address must be **disabled** during the mirrored part.
+
+- Removing zero coefficients → 95 remain
+- Considering symmetry: **48 coefficients** are sufficient
+- For Filter 3: only **6 coefficients** needed instead of 11
+
+### Recalculating:
+
+a = 12 bits, b = 11 bits, N = 65
+acc1 = log2(48 * 8382465) = 28.5839 ≈ **29 bits**
+
+a = 12 bits, b = 11 bits, N = 6
+acc2 = log2(6 * 8382465) = 25.5839 ≈ **26 bits**
+
+a = 12 bits, b = 8 bits, N = 6
+acc3 = log2(6 * 8382465) = 25.5839 ≈ **26 bits**
+
+### Worst Case Summation:
+
+log2(2^29 + 2^26 + 2^26) = 29.321 ≈ **30 bits**
+
+---
+
+- **Shift Accumulator**:
+ - Final result is shifted right by 18 bits
+ - If accumulator has 29 bits → 29 - 12 = 17 bits go to output
+
+---
-(Notez toute information qui vous semble pertinente)
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diff --git a/docs/img/OperativeUnit.png b/docs/img/OperativeUnit.png
index 64a947ab89b5c179f8cda30834baa893918774d1..f772c3dff6877f8e290fe5d227c9d9891f366a62 100644
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