diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 6099e5fe4cd71aaddc1f570912581c3bf5852460..475e8c16e663313fdbd2257e654a85dfed912528 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -4,35 +4,39 @@
## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
-Considering that an sensitivity list is a list of input signals, the signals should be the six inputs {I_0, I_1, I_2, I_3, I_4, I_5}
+Considering that an sensitivity list is a list of input signals, the signals are {I_0, I_1, I_2, I_3, I_4, I_5, I_sel}.
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
-The aswer its gonna be just '0', Yes but its cover by the code with an 'when others'.
+If the test is incomplete, some behaviors of the circuit may not be verified. This can lead to errors, where the output produces an incorrect or unexpected result, which is serious.
+For example, if the number of bits are bigger then expected it can give bugs.
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
Since we can see by the simulation that all the numbers from 0 to 5 were printed, it proves that our code is working as expected, so the simulation is important to validate the module.
+Despite that, a line to handle all cases that were not explicitly specified in the previous conditions should be considered, as ""0110000" when others;" in one of the other parts of the code.
## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
-In this sequential process the signals 0_CounterMod6(0), 0_CounterMod6(1), 0_CounterMod6(2), 0_CounterMod6(3), 0_CounterMod6(4) and 0_CounterMod6(5) should enter in the sensitivity list, two more than compared to the module 4. So, like that all the 6 signals would be covered.
+In this sequential process, the signals in the list of sensibility are {I_clk, I_rsr, I_block}, because they are the input of the code.
## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
-In this case the test is incomplete, because all values different from the combinations of 3 bits especified would return to the last signal, 0_CounterMod6(5)
+Just like in the previous program, if the test in incomplete, maybe we don't get the outputs as expected. Yes, it is serious.
## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+Yes, the test yielded the expected results for the simulations, as shown in the picture.
## Question Loto 7 : Combien de processus avez-vous décris ?
-9 process
+We made 1 process, including all the states.
## Question Loto 8 : De quel(s) type(s) sont-ils
-
+The process described in the code is sequential, as it operates within a process block and responds to events on the I_clk and I_rst signals.
+It implements a finite state machine (FSM), where the current state (`SR_STATE`) transitions based on input signal events, generating the respective outputs.
## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
-Yes, tirar green e red
+Yes, it could be possible. Our implementation uses a single sequential process that handles both the state update (SR_STATE) and the output assignments. But another approach could be made to separate these two parts. Like that, it would be a combinational process.
## Question Loto 10 : Ce test est-il concluant ? Justifiez.