diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index bcc655d66913928d7dcdede3d6b09390249d6a4f..6099e5fe4cd71aaddc1f570912581c3bf5852460 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -4,29 +4,35 @@
## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+Considering that an sensitivity list is a list of input signals, the signals should be the six inputs {I_0, I_1, I_2, I_3, I_4, I_5}
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+The aswer its gonna be just '0', Yes but its cover by the code with an 'when others'.
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
-## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+Since we can see by the simulation that all the numbers from 0 to 5 were printed, it proves that our code is working as expected, so the simulation is important to validate the module.
+## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+In this sequential process the signals 0_CounterMod6(0), 0_CounterMod6(1), 0_CounterMod6(2), 0_CounterMod6(3), 0_CounterMod6(4) and 0_CounterMod6(5) should enter in the sensitivity list, two more than compared to the module 4. So, like that all the 6 signals would be covered.
## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
-
+In this case the test is incomplete, because all values different from the combinations of 3 bits especified would return to the last signal, 0_CounterMod6(5)
## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
-
+
## Question Loto 7 : Combien de processus avez-vous décris ?
-
+9 process
## Question Loto 8 : De quel(s) type(s) sont-ils
## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+Yes, tirar green e red
## Question Loto 10 : Ce test est-il concluant ? Justifiez.
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diff --git a/docs/q6.png b/docs/q6.png
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diff --git a/src/automate.vhd b/src/automate.vhd
index 1ccb931d7fe12fa743f62a8460c95a6d7fb05343..9d83b725177fe545047bb3d27e3a68465ffd6c19 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,24 +36,75 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
- __BLANK_TO_FILL__
+ SR_STATE <= st_wait_success;
elsif rising_edge(I_clk)then
- case SR_STATE is
- case SR_STATE is
+ case SR_STATE is
+ when st_wait_failed =>
+ O_counting <= '0';
+ O_store <= '0';
+ O_l_red <= '1';
+ O_l_green <= '0';
+ if I_button = '1' then
+ SR_STATE <= st_counting;
+ end if;
when st_wait_success =>
- O_l_green <= '1';
+ O_counting <= '0';
+ O_store <= '0';
O_l_red <= '0';
- O_counting <= '0';
- O_store <= '0';
+ O_l_green <= '1';
if I_button = '1' then
SR_STATE <= st_counting;
end if;
- when __BLANK_TO_FILL__
+ when st_counting =>
+ O_counting <= '1';
+ O_store <= '0';
+ O_l_red <= '0';
+ O_l_green <= '0';
+ if I_button = '0' then
+ SR_STATE <= st_compar;
+ end if;
- __BLANK_TO_FILL__
+ when st_compar =>
+ O_counting <= '0';
+ O_store <= '0';
+ O_l_red <= '0';
+ O_l_green <= '0';
+ if I_invalide = '0' then
+ SR_STATE <= st_store;
+ else
+ SR_STATE <= st_wait_failed;
+ end if;
+
+ when st_store =>
+ O_counting <= '0';
+ O_store <= '1';
+ O_l_red <= '0';
+ O_l_green <= '0';
+ if I_end = '1' then
+ SR_STATE <= st_end_red;
+ elsif I_end = '0' then
+ SR_STATE <= st_wait_success;
+ end if;
+
+ when st_end_green =>
+ O_counting <= '0';
+ O_store <= '0';
+ O_l_red <= '0';
+ O_l_green <= '1';
+ if I_clk_display = '0' then
+ SR_STATE <= st_end_red;
+ end if;
+ when st_end_red =>
+ O_counting <= '0';
+ O_store <= '0';
+ O_l_red <= '1';
+ O_l_green <= '0';
+ if I_clk_display = '1' then
+ SR_STATE <= st_end_green;
+ end if;
end case;
end if;
end process;
diff --git a/src/compteur_modulo4_tb.vhd b/src/compteur_modulo4_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e762034a139e2105d212d8458e5ed50772d01c54
--- /dev/null
+++ b/src/compteur_modulo4_tb.vhd
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity compteur_modulo4_tb is
+end compteur_modulo4_tb;
+
+architecture behavior of compteur_modulo4_tb is
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ component compteur_modulo4
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ count : out std_logic_vector(1 downto 0)
+ );
+ end component;
+
+ -- Inputs
+ signal clk : std_logic := '0';
+ signal reset : std_logic := '0';
+
+ -- Outputs
+ signal count : std_logic_vector(1 downto 0);
+
+ -- Clock period definition
+ constant clk_period : time := 10 ns;
+
+begin
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: compteur_modulo4 port map (
+ clk => clk,
+ reset => reset,
+ count => count
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 20 ns.
+ reset <= '1';
+ wait for 20 ns;
+ reset <= '0';
+
+ -- insert stimulus here
+ wait for 100 ns;
+
+ -- Finish simulation
+ wait;
+ end process;
+
+end behavior;
\ No newline at end of file
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 7962a902901eb77362e130eb770ac5481684623d..1dcd787dde4cd7a2802eec6c292b9bad7bc4373f 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -20,12 +20,20 @@ architecture modulo6_a of compteur_modulo6 is
begin
- process (_BLANK_)
+ process (I_clk, I_rst)
begin
if I_rst = '1' then
- _BLANK_
+ SR_Counter <= "000";
elsif rising_edge(I_clk) then
- _BLANK_
+ if I_block = '1' then
+ SR_Counter <= "000";
+ else
+ if SR_Counter = "101" then
+ SR_Counter <= "000";
+ else
+ SR_Counter <= SR_Counter + 1;
+ end if;
+ end if;
end if;
end process;
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
index a689bef6c26f4dd324c13f5d0653dfd294f6d097..20550d56ec76b1db8ec12b8da1d32a69247e1189 100644
--- a/src/mux6_1.vhd
+++ b/src/mux6_1.vhd
@@ -20,8 +20,25 @@ end mux6_1;
architecture a_mux6_1 of mux6_1 is
begin
-__BLANK_TO_FILL__
-
+ process (I_sel, I_0, I_1, I_2, I_3, I_4, I_5)
+ begin
+ case I_sel is
+ when "000" =>
+ O_mux6 <= I_0;
+ when "001" =>
+ O_mux6 <= I_1;
+ when "010" =>
+ O_mux6 <= I_2;
+ when "011" =>
+ O_mux6 <= I_3;
+ when "100" =>
+ O_mux6 <= I_4;
+ when "101" =>
+ O_mux6 <= I_5;
+ when others =>
+ O_mux6 <= (others => '0');
+ end case;
+ end process;
end a_mux6_1;