diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index 44d68f01e8eef2c8c057ea0b214641c5c73232e7..6d2411d994a4b38e0090544ba0623654d0549723 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -53,8 +53,37 @@ Yes, we can verify the state changes and the values that correspond to it.
## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+The inferred circuit does not match the expected architecture. This is most likely due to errors in the VHDL description, as unclear hierarchy, improper encapsulation of finite state machines (FSMs), causing internal state signals to be exposed globally, all registers appear to be accessed in parallel instead of using a multiplexer as expected.
+
## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
-
-
+
+```
+7. Primitives
+-------------
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 84 | Flop & Latch |
+| LUT6 | 34 | LUT |
+| LUT5 | 20 | LUT |
+| LUT4 | 20 | LUT |
+| OBUF | 17 | IO |
+| LUT2 | 13 | LUT |
+| LUT3 | 10 | LUT |
+| CARRY4 | 7 | CarryLogic |
+| LUT1 | 4 | LUT |
+| IBUF | 4 | IO |
+| FDRE | 4 | Flop & Latch |
+| BUFG | 2 | Clock |
+| FDPE | 1 | Flop & Latch |
++----------+------+---------------------+
+```
+Ressources utilisées: Flip-Flops, Look-Up Tables (LUTs), IO Buffers.
+Quantité / proportion: Numbers are relatively small, indicating a low utilization of available FPGA resources. Under 100 of each shows that the design is resource-efficient.
+Latches: Technically, no latches were used, the primitives FDCE, FDRE, and FDPE are flip-flops.
+Positif: Yes, because latches are level-sensitive, which makes timing analysis and synthesis more complex and error-prone.
+
## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
+Human: Yes. Appears unpredictable, influenced by user actions.
+Machine: No. Fully deterministic with reproducible behavior.
\ No newline at end of file
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diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 1dcd787dde4cd7a2802eec6c292b9bad7bc4373f..f933d354c297e14021131d801a2ea3e3a461aaf7 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -8,7 +8,14 @@ entity compteur_modulo6 is
I_clk : in std_logic;
I_rst : in std_logic;
I_block : in std_logic;
- O_CounterMod6 : out std_logic_vector(2 downto 0)
+ O_CounterMod6 : out std_logic_vector(2 downto 0);
+ O_parallel1 : out std_logic;
+ O_parallel2 : out std_logic;
+ O_parallel3 : out std_logic;
+ O_parallel4 : out std_logic;
+ O_parallel5 : out std_logic;
+ O_parallel6 : out std_logic
+
);
end compteur_modulo6;
@@ -20,23 +27,75 @@ architecture modulo6_a of compteur_modulo6 is
begin
- process (I_clk, I_rst)
+ mod6: process (I_clk, I_rst, I_block)
begin
if I_rst = '1' then
SR_Counter <= "000";
elsif rising_edge(I_clk) then
if I_block = '1' then
+ SR_Counter <= SR_counter;
+ elsif SR_Counter = "101" then
SR_Counter <= "000";
else
- if SR_Counter = "101" then
- SR_Counter <= "000";
- else
- SR_Counter <= SR_Counter + 1;
- end if;
+ SR_Counter <= SR_Counter + 1;
end if;
end if;
end process;
O_CounterMod6 <= std_logic_vector(SR_Counter);
+ parallel : process (SR_Counter)
+ begin
+ case SR_Counter is
+ when "000" =>
+ O_parallel1 <= '0';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+ O_parallel5 <= '1';
+ O_parallel6 <= '1';
+ when "001" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '0';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+ O_parallel5 <= '1';
+ O_parallel6 <= '1';
+ when "010" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '0';
+ O_parallel4 <= '1';
+ O_parallel5 <= '1';
+ O_parallel6 <= '1';
+ when "011" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '0';
+ O_parallel5 <= '1';
+ O_parallel6 <= '1';
+ when "100" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+ O_parallel5 <= '0';
+ O_parallel6 <= '1';
+ when "101" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+ O_parallel5 <= '1';
+ O_parallel6 <= '0';
+ when others =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+ O_parallel5 <= '1';
+ O_parallel6 <= '1';
+ end case;
+ end process parallel;
end modulo6_a;
diff --git a/src/compteur_modulo6_tb.vhd b/src/compteur_modulo6_tb.vhd
index ff49f9ee1cda0fc808abfced8205fbb5f186547c..0c166dd9980fe73549a16bf459b9f3024c5b33ba 100644
--- a/src/compteur_modulo6_tb.vhd
+++ b/src/compteur_modulo6_tb.vhd
@@ -31,6 +31,7 @@ architecture arch of compteur_modulo6_tb is
signal SC_block : std_logic := '0';
signal SC_CounterMod6 : std_logic_vector(2 downto 0);
signal SR_Clk : std_logic := '1';
+ signal SC_parallel : std_logic_vector(5 downto 0);
begin
@@ -39,12 +40,19 @@ begin
I_clk => SR_Clk,
I_rst => SC_rst,
I_block => SC_block,
- O_counterMod6 => SC_CounterMod6);
-
- SR_Clk <= not SR_Clk after 7 ns;
- SC_rst <= '0', '1' after 11 ns, '0' after 29 ns, '1' after 123 ns, '0' after 147 ns;
- SC_block <= '0', '1' after 33 ns, '0' after 79 ns, '1' after 211 ns, '0' after 251 ns;
+ O_counterMod6 => SC_CounterMod6,
+ O_parallel1 => SC_parallel(0),
+ O_parallel2 => SC_parallel(1),
+ O_parallel3 => SC_parallel(2),
+ O_parallel4 => SC_parallel(3),
+ O_parallel5 => SC_parallel(4),
+ O_parallel6 => SC_parallel(5)
+ );
+ SR_Clk <= not SR_Clk after 7 ns;
+ SC_rst <= '0', '1' after 05 ns, '1' after 11 ns, '0' after 29 ns, '1' after 123 ns, '0' after 147 ns;
+ SC_block <= '0', '1' after 05 ns, '1' after 33 ns, '0' after 79 ns, '1' after 211 ns, '0' after 251 ns;
+
end architecture arch;
-------------------------------------------------------------------------------
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
index 20550d56ec76b1db8ec12b8da1d32a69247e1189..fa0605e9c3f51c36d1f99bc37af55911c4a7c872 100644
--- a/src/mux6_1.vhd
+++ b/src/mux6_1.vhd
@@ -36,7 +36,7 @@ begin
when "101" =>
O_mux6 <= I_5;
when others =>
- O_mux6 <= (others => '0');
+ O_mux6 <= (others => 'X');
end case;
end process;
diff --git a/src/mux6_1_tb.vhd b/src/mux6_1_tb.vhd
index a79053f265a6a6016ab52c8b3c8271a3bed13f3e..067c5161d1c2ae0fdba8c9e4423d0ea910dda586 100644
--- a/src/mux6_1_tb.vhd
+++ b/src/mux6_1_tb.vhd
@@ -58,7 +58,7 @@ begin
cpt : process (clk) is
begin
if rising_edge(clk) then
- if(COMMANDE = "101") then
+ if(COMMANDE = "111") then
COMMANDE <= "000";
else
COMMANDE <= std_logic_vector(unsigned(COMMANDE)+1);