diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
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@@ -8,8 +8,9 @@ Considering that an sensitivity list is a list of input signals, the signals are
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
-If the test is incomplete, some behaviors of the circuit may not be verified. This can lead to errors, where the output produces an incorrect or unexpected result, which is serious.
-For example, if the number of bits are bigger then expected it can give bugs.
+The aswer its gonna be just '0'. If the test is incomplete, some behaviors of the circuit may not be verified.
+
+Yes but its cover by the code with an 'when others'. This can lead to errors, where the output produces an incorrect or unexpected result, which is serious. For example, if the number of bits are bigger then expected it can give bugs.
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
@@ -19,17 +20,22 @@ Since we can see by the simulation that all the numbers from 0 to 5 were printed
Despite that, a line to handle all cases that were not explicitly specified in the previous conditions should be considered, as ""0110000" when others;" in one of the other parts of the code.
## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
-In this sequential process, the signals in the list of sensibility are {I_clk, I_rsr, I_block}, because they are the input of the code.
+In this sequential process the signals 0_CounterMod6(0), 0_CounterMod6(1), 0_CounterMod6(2), 0_CounterMod6(3), 0_CounterMod6(4) and 0_CounterMod6(5) should enter in the sensitivity list, two more than compared to the module 4. So, like that all the 6 signals would be covered.
## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à-dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
-Just like in the previous program, if the test in incomplete, maybe we don't get the outputs as expected. Yes, it is serious.
+
+In this case the test is incomplete, because all values different from the combinations of 3 bits especified would return to the last signal, 0_CounterMod6(5)
+
+Just like in the previous program, if the test in incomplete, maybe we don't get the outputs as expected.
## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
Yes, the test yielded the expected results for the simulations, as shown in the picture.
+With the test it's possible to validate that all signals from 0 to 5 are printed, but we can't identify for example which value (as others) was used to print 5.
+
## Question Loto 7 : Combien de processus avez-vous décris ?
-We made 1 process, including all the states.
+9 process. Considering all the transitions, includes the cases were depending on one variable more than one states could happen.
## Question Loto 8 : De quel(s) type(s) sont-ils
The process described in the code is sequential, as it operates within a process block and responds to events on the I_clk and I_rst signals.
@@ -37,15 +43,18 @@ It implements a finite state machine (FSM), where the current state (`SR_STATE`)
## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
Yes, it could be possible. Our implementation uses a single sequential process that handles both the state update (SR_STATE) and the output assignments. But another approach could be made to separate these two parts. Like that, it would be a combinational process.
+Also we can merge the st_wait_failed with st_end_green and st_wait_success with st_end_red because thay have the same setup of statements.
## Question Loto 10 : Ce test est-il concluant ? Justifiez.
-
+
+Yes, we can verify the state changes and the values that correspond to it.
## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
-
+
## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
-
+
+
## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
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