From 04ea2748a4dbcc7e1cb56212bc78c07c1ae98fc5 Mon Sep 17 00:00:00 2001
From: BAZIN Jean-Noel <jn.bazin@imt-atlantique.fr>
Date: Thu, 15 Feb 2024 14:09:16 +0100
Subject: [PATCH] =?UTF-8?q?Correction=20pb=20suite=20s=C3=A9ance=20MEDCON?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
src/Nexys4DDR-Master.xdc | 44 +++++++++++------------
src/automate.vhd | 71 ++++++++++++++++++-------------------
src/compteur_modulo6.vhd | 4 +--
src/compteur_modulo6_tb.vhd | 41 ++++++++-------------
src/compteur_valid.vhd | 2 +-
src/loto_tb.vhd | 2 +-
src/modulo4.vhd | 4 +--
src/mux6_1_tb.vhd | 2 +-
src/registres.vhd | 2 +-
9 files changed, 79 insertions(+), 93 deletions(-)
diff --git a/src/Nexys4DDR-Master.xdc b/src/Nexys4DDR-Master.xdc
index 2ae544a..c94f376 100644
--- a/src/Nexys4DDR-Master.xdc
+++ b/src/Nexys4DDR-Master.xdc
@@ -4,8 +4,8 @@
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
-set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100m }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100m}];
+set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { I_clk_100m }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {I_clk_100m}];
##Switches
@@ -25,7 +25,7 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
-set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { bloque }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { I_block }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
## LEDs
@@ -49,43 +49,43 @@ set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { bloque
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
-set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { rouge }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { O_red }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
-set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { vert}]; #IO_0_14 Sch=led17_g
+set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { O_green }]; #IO_0_14 Sch=led17_g
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
##7 segment display
-set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { s_aff[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
-set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { s_aff[1] }]; #IO_25_14 Sch=cb
-set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { s_aff[2] }]; #IO_25_15 Sch=cc
-set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { s_aff[3] }]; #IO_L17P_T2_A26_15 Sch=cd
-set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { s_aff[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
-set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { s_aff[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
-set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { s_aff[6] }]; #IO_L4P_T0_D04_14 Sch=cg
+set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[1] }]; #IO_25_14 Sch=cb
+set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[2] }]; #IO_25_15 Sch=cc
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[3] }]; #IO_L17P_T2_A26_15 Sch=cd
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentDisplay[6] }]; #IO_L4P_T0_D04_14 Sch=cg
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
-set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
-set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
-set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
-set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
-set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
-set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
-set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
-set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[6] }]; #IO_L23P_T3_35 Sch=an[6]
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { O_7segmentSelect[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
##Buttons
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
-set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { bouton }]; #IO_L9P_T1_DQS_14 Sch=btnc
+set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { I_button }]; #IO_L9P_T1_DQS_14 Sch=btnc
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
-set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { I_rst }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
##Pmod Headers
diff --git a/src/automate.vhd b/src/automate.vhd
index 4767f4e..1ccb931 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -5,59 +5,58 @@ use IEEE.numeric_std.all;
entity automate is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_bouton : in std_logic;
- I_clk_display : in std_logic;
- I_bouton : in std_logic;
- I_invalide : in std_logic;
- I_fin : in std_logic;
- O_comptage : out std_logic;
- O_enregistrement : out std_logic;
- O_l_rouge : out std_logic;
- O_l_verte : out std_logic
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_clk_display : in std_logic;
+ I_button : in std_logic;
+ I_invalide : in std_logic;
+ I_end : in std_logic;
+ O_counting : out std_logic;
+ O_store : out std_logic;
+ O_l_red : out std_logic;
+ O_l_green : out std_logic
);
end automate;
architecture a_automate of automate is
type TYPE_ETAT is (
- st_attente_echec,
- st_attente_succes,
- st_comptage,
- st_comparaison,
- st_enregistrement,
- st_fin_vert,
- st_fin_rouge
+ st_wait_failed,
+ st_wait_success,
+ st_counting,
+ st_compar,
+ st_store,
+ st_end_green,
+ st_end_red
);
- signal ST_ETAT : TYPE_ETAT;
+ signal SR_STATE : TYPE_ETAT;
begin
-
- UpdateState : process (I_clk, I_rst)
-
+ process (I_clk, I_rst)
begin
if(I_rst = '1')then
__BLANK_TO_FILL__
- case ETAT is
-
- when st_attente_succes =>
- l_verte <= '1';
- l_rouge <= '0';
- comptage <= '0';
- enregistrement <= '0';
- if bouton = '1' then
- ST_ETAT <= st_comptage;
- else
- ST_ETAT <= st_attente_succes;
+ elsif rising_edge(I_clk)then
+ case SR_STATE is
+ case SR_STATE is
+
+ when st_wait_success =>
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_button = '1' then
+ SR_STATE <= st_counting;
end if;
when __BLANK_TO_FILL__
- end case;
+ __BLANK_TO_FILL__
- end process COMB;
+ end case;
+ end if;
+ end process;
- end a_automate;
+end a_automate;
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index d5a63bc..7962a90 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -20,14 +20,14 @@ architecture modulo6_a of compteur_modulo6 is
begin
- mod6 : process (_BLANK_)
+ process (_BLANK_)
begin
if I_rst = '1' then
_BLANK_
elsif rising_edge(I_clk) then
_BLANK_
end if;
- end process mod6;
+ end process;
O_CounterMod6 <= std_logic_vector(SR_Counter);
diff --git a/src/compteur_modulo6_tb.vhd b/src/compteur_modulo6_tb.vhd
index d700a88..ff49f9e 100644
--- a/src/compteur_modulo6_tb.vhd
+++ b/src/compteur_modulo6_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthieu Arzel <marzel@marzel-XPS-13-9350>
-- Company :
-- Created : 2019-01-10
--- Last update: 2023-10-04
+-- Last update: 2024-02-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -22,41 +22,28 @@
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-
entity compteur_modulo6_tb is
end entity compteur_modulo6_tb;
--------------------------------------------------------------------------------
-
architecture arch of compteur_modulo6_tb is
- -- component ports
- signal rst : std_logic := '0';
- signal bloque : std_logic := '0';
- signal sortie : std_logic_vector(2 downto 0);
-
- -- clock
- signal Clk : std_logic := '1';
+ signal SC_rst : std_logic := '0';
+ signal SC_block : std_logic := '0';
+ signal SC_CounterMod6 : std_logic_vector(2 downto 0);
+ signal SR_Clk : std_logic := '1';
-begin -- architecture arch
+begin
- -- component instantiation
DUT : entity work.compteur_modulo6
port map (
- I_clk => clk,
- I_rst => rst,
- I_bloque => bloque,
- O_counterMod6 => sortie);
-
- -- clock generation
- Clk <= not Clk after 10 ns;
-
- -- waveform generation
- rst <= '0', '1' after 6 ns, '0' after 27 ns, '1' after 128 ns, '0' after 147 ns;
- bloque <= '0', '1' after 33 ns, '0' after 76 ns;
-
-
+ I_clk => SR_Clk,
+ I_rst => SC_rst,
+ I_block => SC_block,
+ O_counterMod6 => SC_CounterMod6);
+
+ SR_Clk <= not SR_Clk after 7 ns;
+ SC_rst <= '0', '1' after 11 ns, '0' after 29 ns, '1' after 123 ns, '0' after 147 ns;
+ SC_block <= '0', '1' after 33 ns, '0' after 79 ns, '1' after 211 ns, '0' after 251 ns;
end architecture arch;
diff --git a/src/compteur_valid.vhd b/src/compteur_valid.vhd
index 201e6a8..7e799d2 100644
--- a/src/compteur_valid.vhd
+++ b/src/compteur_valid.vhd
@@ -31,7 +31,7 @@ begin
end if;
end if;
end if;
- end process cpt_valid;
+ end process;
O_adr <= std_logic_vector(to_unsigned(SR_Counter, 3));
O_fin <= '1' when SR_Counter = 5 else '0';
diff --git a/src/loto_tb.vhd b/src/loto_tb.vhd
index 7c951b1..c9efa48 100644
--- a/src/loto_tb.vhd
+++ b/src/loto_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthieu Arzel <mattieu.arzel@imt-atlantique.fr>
-- Company :
-- Created : 2018-06-14
--- Last update: 2023-10-12
+-- Last update: 2024-02-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
diff --git a/src/modulo4.vhd b/src/modulo4.vhd
index f8157be..42c2f6a 100644
--- a/src/modulo4.vhd
+++ b/src/modulo4.vhd
@@ -30,7 +30,7 @@ begin
SR_Counter <= SR_Counter + 1;
end if;
end if;
- end process mod4;
+ end process;
O_Mod4 <= std_logic_vector(SR_Counter);
@@ -46,6 +46,6 @@ begin
when "10" => O_decod(2) <= '0';
when others => O_decod(3) <= '0';
end case;
- end process decodproc;
+ end process;
end modulo4_a;
diff --git a/src/mux6_1_tb.vhd b/src/mux6_1_tb.vhd
index b92759f..a79053f 100644
--- a/src/mux6_1_tb.vhd
+++ b/src/mux6_1_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthieu Arzel
-- Company :
-- Created : 2018-12-17
--- Last update: 2023-10-04
+-- Last update: 2024-02-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
diff --git a/src/registres.vhd b/src/registres.vhd
index 8adf16b..3dbbadc 100644
--- a/src/registres.vhd
+++ b/src/registres.vhd
@@ -59,6 +59,6 @@ begin
end case;
end if;
end if;
- end process reg;
+ end process;
end a_registres;
--
GitLab