From 2cdc2accf7f5438ebaaf16df2f50b1998f1d3732 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jean-No=C3=ABl=20Bazin?= <jn.bazin@imt-atlantique.fr>
Date: Tue, 26 Mar 2024 16:16:20 +0100
Subject: [PATCH] remove reset
---
src/Nexys4DDR-Master.xdc | 15 +------
src/Nexys4_Master.xdc | 4 +-
src/automate.vhd | 39 +++++++++---------
src/compteur1_49.vhd | 10 ++---
src/compteur_modulo4.vhd | 9 ++---
src/compteur_modulo6.vhd | 10 +----
src/compteur_modulo6_tb.vhd | 8 ++--
src/compteur_valid.vhd | 20 +++++-----
src/diviseur_freq.vhd | 9 ++---
src/led_pwm.vhd | 16 +++-----
src/loto.vhd | 12 ++----
src/loto_tb.vhd | 4 +-
src/modulo4.vhd | 9 ++---
src/registres.vhd | 58 +++++++++++----------------
src/tirage.vhd | 79 ++++++++++++++++---------------------
15 files changed, 119 insertions(+), 183 deletions(-)
diff --git a/src/Nexys4DDR-Master.xdc b/src/Nexys4DDR-Master.xdc
index c94f376..102b413 100644
--- a/src/Nexys4DDR-Master.xdc
+++ b/src/Nexys4DDR-Master.xdc
@@ -85,7 +85,7 @@ set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { I_butt
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
-set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { I_rst }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { I_GlobalInit }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
##Pmod Headers
@@ -250,16 +250,3 @@ set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { I_rst
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/src/Nexys4_Master.xdc b/src/Nexys4_Master.xdc
index 8a19dd4..9176a7c 100644
--- a/src/Nexys4_Master.xdc
+++ b/src/Nexys4_Master.xdc
@@ -13,8 +13,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports I_clk_100m]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports I_clk_100m]
##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
-set_property PACKAGE_PIN V10 [get_ports I_rst]
-set_property IOSTANDARD LVCMOS33 [get_ports I_rst]
+set_property PACKAGE_PIN V10 [get_ports I_GlobalInit]
+set_property IOSTANDARD LVCMOS33 [get_ports I_GlobalInit]
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
diff --git a/src/automate.vhd b/src/automate.vhd
index 1ccb931..07bd947 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -6,7 +6,7 @@ use IEEE.numeric_std.all;
entity automate is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
+ I_GlobalInit : in std_logic;
I_clk_display : in std_logic;
I_button : in std_logic;
I_invalide : in std_logic;
@@ -29,34 +29,37 @@ architecture a_automate of automate is
st_end_green,
st_end_red
);
- signal SR_STATE : TYPE_ETAT;
+ signal SR_STATE : TYPE_ETAT := st_wait_success;
begin
- process (I_clk, I_rst)
+ process (I_clk)
begin
- if(I_rst = '1')then
- __BLANK_TO_FILL__
- elsif rising_edge(I_clk)then
- case SR_STATE is
+ if rising_edge(I_clk)then
+ if I_GlobalInit = '1' then
+ SR_STATE <= st_wait_success;
+ else
+
case SR_STATE is
- when st_wait_success =>
- O_l_green <= '1';
- O_l_red <= '0';
- O_counting <= '0';
- O_store <= '0';
- if I_button = '1' then
- SR_STATE <= st_counting;
- end if;
+ when st_wait_success =>
+ if I_button = '1' then
+ SR_STATE <= st_counting;
+ end if;
- when __BLANK_TO_FILL__
+ when __BLANK_TO_FILL__
- __BLANK_TO_FILL__
+ __BLANK_TO_FILL__
- end case;
+ end case;
+ end if;
end if;
end process;
+ O_counting <= '1' when(__BLANk_TO_FILL__
+ O_store <= '1' when(__BLANk_TO_FILL__
+ O_l_red <= '1' when(__BLANk_TO_FILL__
+ O_l_green <= '1' when(__BLANk_TO_FILL__
+
end a_automate;
diff --git a/src/compteur1_49.vhd b/src/compteur1_49.vhd
index f7f4b9e..c474422 100644
--- a/src/compteur1_49.vhd
+++ b/src/compteur1_49.vhd
@@ -6,7 +6,6 @@ use IEEE.numeric_std.all;
entity compteur1_49 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
I_comptage : in std_logic;
O_sortie : out std_logic_vector(5 downto 0)
);
@@ -15,16 +14,13 @@ end compteur1_49;
architecture compteur_a of compteur1_49 is
- signal SR_cpt_val : unsigned(5 downto 0);
+ signal SR_cpt_val : unsigned(5 downto 0) := to_unsigned(1, 6);
begin
- cpt : process (I_clk, I_rst)
-
+ cpt : process (I_clk)
begin
- if I_rst = '1' then
- SR_cpt_val <= to_unsigned(1, 6);
- elsif rising_edge(I_clk) then
+ if rising_edge(I_clk) then
if I_comptage = '1' then
if SR_cpt_val = 49 then
SR_cpt_val <= to_unsigned(1, 6);
diff --git a/src/compteur_modulo4.vhd b/src/compteur_modulo4.vhd
index f2b951f..d6cfc4a 100644
--- a/src/compteur_modulo4.vhd
+++ b/src/compteur_modulo4.vhd
@@ -5,7 +5,6 @@ use IEEE.numeric_std.all;
entity compteur_modulo4 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
O_CounterMod4 : out std_logic_vector(1 downto 0);
O_parallel1 : out std_logic;
O_parallel2 : out std_logic;
@@ -16,16 +15,14 @@ end compteur_modulo4;
architecture modulo4_a of compteur_modulo4 is
- signal SR_Counter : unsigned(1 downto 0);
+ signal SR_Counter : unsigned(1 downto 0) := (others => '0');
begin
- mod4 : process (clk, rst)
+ mod4 : process (clk)
begin
- if rst = '1' then
- SR_Counter <= "00";
- elsif rising_edge(clk) then
+ if rising_edge(clk) then
if SR_Counter = "11" then
SR_Counter <= "00";
else
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 7962a90..891bf59 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -2,29 +2,23 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity compteur_modulo6 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
I_block : in std_logic;
O_CounterMod6 : out std_logic_vector(2 downto 0)
);
-
end compteur_modulo6;
-
architecture modulo6_a of compteur_modulo6 is
- signal SR_Counter : unsigned(2 downto 0);
+ signal SR_Counter : unsigned(2 downto 0) := (others => '0');
begin
process (_BLANK_)
begin
- if I_rst = '1' then
- _BLANK_
- elsif rising_edge(I_clk) then
+ if rising_edge(I_clk) then
_BLANK_
end if;
end process;
diff --git a/src/compteur_modulo6_tb.vhd b/src/compteur_modulo6_tb.vhd
index ff49f9e..a7bf66a 100644
--- a/src/compteur_modulo6_tb.vhd
+++ b/src/compteur_modulo6_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthieu Arzel <marzel@marzel-XPS-13-9350>
-- Company :
-- Created : 2019-01-10
--- Last update: 2024-02-15
+-- Last update: 2024-03-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -27,7 +27,6 @@ end entity compteur_modulo6_tb;
architecture arch of compteur_modulo6_tb is
- signal SC_rst : std_logic := '0';
signal SC_block : std_logic := '0';
signal SC_CounterMod6 : std_logic_vector(2 downto 0);
signal SR_Clk : std_logic := '1';
@@ -37,12 +36,11 @@ begin
DUT : entity work.compteur_modulo6
port map (
I_clk => SR_Clk,
- I_rst => SC_rst,
I_block => SC_block,
- O_counterMod6 => SC_CounterMod6);
+ O_counterMod6 => SC_CounterMod6
+ );
SR_Clk <= not SR_Clk after 7 ns;
- SC_rst <= '0', '1' after 11 ns, '0' after 29 ns, '1' after 123 ns, '0' after 147 ns;
SC_block <= '0', '1' after 33 ns, '0' after 79 ns, '1' after 211 ns, '0' after 251 ns;
end architecture arch;
diff --git a/src/compteur_valid.vhd b/src/compteur_valid.vhd
index 7e799d2..1ee3080 100644
--- a/src/compteur_valid.vhd
+++ b/src/compteur_valid.vhd
@@ -4,11 +4,11 @@ use IEEE.numeric_std.all;
entity compteur_valid is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_comptage : in std_logic;
- O_adr : out std_logic_vector(2 downto 0);
- O_fin : out std_logic
+ I_clk : in std_logic;
+ I_GlobalInit : in std_logic;
+ I_comptage : in std_logic;
+ O_adr : out std_logic_vector(2 downto 0);
+ O_fin : out std_logic
);
end compteur_valid;
@@ -18,12 +18,12 @@ architecture a_compteur_valid of compteur_valid is
begin
- process (I_clk, I_rst)
+ process (I_clk)
begin
- if I_rst = '1' then
- SR_Counter <= 0;
- elsif rising_edge(I_clk) then
- if I_comptage = '1' then
+ if rising_edge(I_clk) then
+ if I_GlobalInit = '1' then
+ SR_Counter <= 0;
+ elsif I_comptage = '1' then
if SR_Counter = 5 then
SR_Counter <= 0;
else
diff --git a/src/diviseur_freq.vhd b/src/diviseur_freq.vhd
index 63883d3..0c55023 100644
--- a/src/diviseur_freq.vhd
+++ b/src/diviseur_freq.vhd
@@ -9,7 +9,6 @@ entity diviseur_freq is
);
port (
I_clk : in std_logic;
- I_rst : in std_logic;
O_fast : out std_logic;
O_slow : out std_logic
);
@@ -17,15 +16,13 @@ end diviseur_freq;
architecture Behavioral of diviseur_freq is
- signal SR_counter : unsigned (26 downto 0);
+ signal SR_counter : unsigned (26 downto 0) := (others => '0');
begin
- process (I_clk, I_rst)
+ process (I_clk)
begin
- if I_rst = '1' then
- SR_counter <= (others => '0');
- elsif rising_edge(I_clk) then
+ if rising_edge(I_clk) then
SR_counter <= SR_counter + 1;
end if;
end process;
diff --git a/src/led_pwm.vhd b/src/led_pwm.vhd
index d7729c3..1badba8 100644
--- a/src/led_pwm.vhd
+++ b/src/led_pwm.vhd
@@ -3,31 +3,25 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity led_pwm is
-
port (
I_clk : in std_logic;
- I_rst : in std_logic;
I_ledR : in std_logic;
I_ledV : in std_logic;
O_ledR_PWM : out std_logic;
O_ledV_PWM : out std_logic
);
-
end entity led_pwm;
architecture arch of led_pwm is
- signal SR_cpt_leds : unsigned(4 downto 0);
- signal SR_cpt_leds_reg : unsigned(4 downto 0);
+ signal SR_cpt_leds : unsigned(4 downto 0) := (others => '0');
+ signal SR_cpt_leds_reg : unsigned(4 downto 0) := (others => '0');
-begin -- architecture arch
+begin
- leds_pwm : process (I_clk, I_rst) is
+ leds_pwm : process (I_clk) is
begin
- if I_rst = '1' then
- SR_cpt_leds <= (others => '0');
- SR_cpt_leds_reg <= (others => '0');
- elsif rising_edge(I_clk) then
+ if rising_edge(I_clk) then
SR_cpt_leds <= SR_cpt_leds + 1;
SR_cpt_leds_reg <= SR_cpt_leds;
end if;
diff --git a/src/loto.vhd b/src/loto.vhd
index 3b7c175..8231be1 100644
--- a/src/loto.vhd
+++ b/src/loto.vhd
@@ -10,7 +10,7 @@ entity loto is
I_button : in std_logic;
I_block : in std_logic;
I_clk_100m : in std_logic;
- I_rst : in std_logic;
+ I_GlobalInit : in std_logic;
O_7segmentDisplay : out std_logic_vector(6 downto 0);
O_7segmentSelect : out std_logic_vector(7 downto 0);
O_red : out std_logic;
@@ -23,7 +23,7 @@ architecture arch of loto is
component tirage is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
+ I_GlobalInit : in std_logic;
I_clk_display : in std_logic;
I_button : in std_logic;
O_reg0 : out std_logic_vector(5 downto 0);
@@ -39,7 +39,6 @@ architecture arch of loto is
component compteur_modulo6 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
I_block : in std_logic;
O_CounterMod6 : out std_logic_vector(2 downto 0));
end component compteur_modulo6;
@@ -50,7 +49,6 @@ architecture arch of loto is
n_slow : natural);
port (
I_clk : in std_logic;
- I_rst : in std_logic;
O_fast : out std_logic;
O_slow : out std_logic
);
@@ -80,7 +78,6 @@ architecture arch of loto is
component modulo4 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
O_Mod4 : out std_logic_vector(1 downto 0);
O_decod : out std_logic_vector(3 downto 0)
);
@@ -107,7 +104,7 @@ begin
tirage_1 : entity work.tirage
port map (
I_clk => SC_clk,
- I_rst => I_rst,
+ I_GlobalInit => I_GlobalInit,
I_clk_display => SC_clkDisplay,
I_button => I_button,
O_reg0 => SC_reg0,
@@ -123,7 +120,6 @@ begin
modulo6_1 : entity work.compteur_modulo6
port map (
I_clk => SC_clkDisplay,
- I_rst => I_rst,
I_block => I_block,
O_CounterMod6 => SC_regReadAddress
);
@@ -134,7 +130,6 @@ begin
n_slow => n_slow)
port map (
I_clk => I_clk_100m,
- I_rst => I_rst,
O_fast => SC_clk,
O_slow => SC_clkDisplay
);
@@ -161,7 +156,6 @@ begin
modulo4_2 : entity work.modulo4
port map (
I_clk => SC_clk,
- I_rst => I_rst,
O_Mod4 => SC_displaySelect,
O_decod => O_7segmentSelect(3 downto 0)
);
diff --git a/src/loto_tb.vhd b/src/loto_tb.vhd
index c9efa48..b1ba6eb 100644
--- a/src/loto_tb.vhd
+++ b/src/loto_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthieu Arzel <mattieu.arzel@imt-atlantique.fr>
-- Company :
-- Created : 2018-06-14
--- Last update: 2024-02-15
+-- Last update: 2024-03-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -53,7 +53,7 @@ begin -- architecture ar
n_slow => n_slow)
port map (
I_clk_100m => clk_100m,
- I_rst => rst,
+ I_GlobalInit => rst,
I_button => bouton,
I_block => bloque,
O_7segmentDisplay => s_aff,
diff --git a/src/modulo4.vhd b/src/modulo4.vhd
index 42c2f6a..045d44b 100644
--- a/src/modulo4.vhd
+++ b/src/modulo4.vhd
@@ -6,7 +6,6 @@ use IEEE.numeric_std.all;
entity modulo4 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
O_Mod4 : out std_logic_vector(1 downto 0);
O_decod : out std_logic_vector(3 downto 0)
);
@@ -15,15 +14,13 @@ end modulo4;
architecture modulo4_a of modulo4 is
- signal SR_Counter : unsigned(1 downto 0);
+ signal SR_Counter : unsigned(1 downto 0) := (others => '0');
begin
- process (I_clk, I_rst)
+ process (I_clk)
begin
- if I_rst = '1' then
- SR_Counter <= "00";
- elsif rising_edge(I_clk) then
+ if rising_edge(I_clk) then
if SR_Counter = "11" then
SR_Counter <= "00";
else
diff --git a/src/registres.vhd b/src/registres.vhd
index 3dbbadc..0e1220e 100644
--- a/src/registres.vhd
+++ b/src/registres.vhd
@@ -5,17 +5,17 @@ use IEEE.numeric_std.all;
entity registres is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_wr : in std_logic;
- I_adr : in std_logic_vector(2 downto 0);
- I_data : in std_logic_vector(5 downto 0);
- O_reg0 : out std_logic_vector(5 downto 0);
- O_reg1 : out std_logic_vector(5 downto 0);
- O_reg2 : out std_logic_vector(5 downto 0);
- O_reg3 : out std_logic_vector(5 downto 0);
- O_reg4 : out std_logic_vector(5 downto 0);
- O_reg5 : out std_logic_vector(5 downto 0)
+ I_clk : in std_logic;
+ I_GlobalInit : in std_logic;
+ I_wr : in std_logic;
+ I_adr : in std_logic_vector(2 downto 0);
+ I_data : in std_logic_vector(5 downto 0);
+ O_reg0 : out std_logic_vector(5 downto 0);
+ O_reg1 : out std_logic_vector(5 downto 0);
+ O_reg2 : out std_logic_vector(5 downto 0);
+ O_reg3 : out std_logic_vector(5 downto 0);
+ O_reg4 : out std_logic_vector(5 downto 0);
+ O_reg5 : out std_logic_vector(5 downto 0)
);
end registres;
@@ -24,31 +24,19 @@ architecture a_registres of registres is
begin
- process (I_clk, I_rst)
+ process (I_clk)
begin
- if I_rst = '1' then
- O_reg0 <= (others => '0');
- O_reg1 <= (others => '0');
- O_reg2 <= (others => '0');
- O_reg3 <= (others => '0');
- O_reg4 <= (others => '0');
- O_reg5 <= (others => '0');
- elsif rising_edge(I_clk) then
- if I_wr = '1' then
- -- if I_adr = "000" then
- -- O_reg0 <= I_data;
- -- elsif I_adr = "001" then
- -- O_reg1 <= I_data;
- -- elsif I_adr = "010" then
- -- O_reg2 <= I_data;
- -- elsif I_adr = "011" then
- -- O_reg3 <= I_data;
- -- elsif I_adr = "100" then
- -- O_reg4 <= I_data;
- -- elsif I_adr = "101" then
- -- O_reg5 <= I_data;
- -- end if;
- case I_adr is
+
+ if rising_edge(I_clk) then
+ if I_GlobalInit = '1' then
+ O_reg0 <= (others => '0');
+ O_reg1 <= (others => '0');
+ O_reg2 <= (others => '0');
+ O_reg3 <= (others => '0');
+ O_reg4 <= (others => '0');
+ O_reg5 <= (others => '0');
+ elsif I_wr = '1' then
+ case I_adr is
when "000" => O_reg0 <= I_data;
when "001" => O_reg1 <= I_data;
when "010" => O_reg2 <= I_data;
diff --git a/src/tirage.vhd b/src/tirage.vhd
index 0082967..0ed7477 100644
--- a/src/tirage.vhd
+++ b/src/tirage.vhd
@@ -7,7 +7,7 @@ entity tirage is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
+ I_GlobalInit : in std_logic;
I_clk_display : in std_logic;
I_button : in std_logic;
O_reg0 : out std_logic_vector(5 downto 0);
@@ -27,7 +27,7 @@ architecture a_tirage of tirage is
component automate is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
+ I_GlobalInit : in std_logic;
I_clk_display : in std_logic;
I_button : in std_logic;
I_invalide : in std_logic;
@@ -40,26 +40,26 @@ architecture a_tirage of tirage is
component registres is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_wr : in std_logic;
- I_adr : in std_logic_vector(2 downto 0);
- I_data : in std_logic_vector(5 downto 0);
- O_reg0 : out std_logic_vector(5 downto 0);
- O_reg1 : out std_logic_vector(5 downto 0);
- O_reg2 : out std_logic_vector(5 downto 0);
- O_reg3 : out std_logic_vector(5 downto 0);
- O_reg4 : out std_logic_vector(5 downto 0);
- O_reg5 : out std_logic_vector(5 downto 0));
+ I_clk : in std_logic;
+ I_GlobalInit : in std_logic;
+ I_wr : in std_logic;
+ I_adr : in std_logic_vector(2 downto 0);
+ I_data : in std_logic_vector(5 downto 0);
+ O_reg0 : out std_logic_vector(5 downto 0);
+ O_reg1 : out std_logic_vector(5 downto 0);
+ O_reg2 : out std_logic_vector(5 downto 0);
+ O_reg3 : out std_logic_vector(5 downto 0);
+ O_reg4 : out std_logic_vector(5 downto 0);
+ O_reg5 : out std_logic_vector(5 downto 0));
end component registres;
component compteur_valid is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_comptage : in std_logic;
- O_adr : out std_logic_vector(2 downto 0);
- O_fin : out std_logic);
+ I_clk : in std_logic;
+ I_GlobalInit : in std_logic;
+ I_comptage : in std_logic;
+ O_adr : out std_logic_vector(2 downto 0);
+ O_fin : out std_logic);
end component compteur_valid;
component comparateur is
@@ -76,7 +76,6 @@ architecture a_tirage of tirage is
component compteur1_49 is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
I_comptage : in std_logic;
O_sortie : out std_logic_vector(5 downto 0));
end component compteur1_49;
@@ -84,7 +83,6 @@ architecture a_tirage of tirage is
component led_pwm is
port (
I_clk : in std_logic;
- I_rst : in std_logic;
I_ledR : in std_logic;
I_ledV : in std_logic;
O_ledR_PWM : out std_logic;
@@ -114,7 +112,7 @@ begin
automate_1 : entity work.automate
port map (
- I_rst => I_rst,
+ I_GlobalInit => I_GlobalInit,
I_clk => I_clk,
I_clk_display => I_clk_display,
I_button => I_button,
@@ -126,47 +124,40 @@ begin
O_l_green => SC_l_V
);
-
-
registres_2 : entity work.registres
port map (
- I_clk => I_clk,
- I_rst => I_rst,
- I_wr => SC_enregistrement,
- I_adr => SC_adr,
- I_data => SC_numero_courant,
- O_reg0 => SC_r0,
- O_reg1 => SC_r1,
- O_reg2 => SC_r2,
- O_reg3 => SC_r3,
- O_reg4 => SC_r4,
- O_reg5 => SC_r5
+ I_clk => I_clk,
+ I_GlobalInit => I_GlobalInit,
+ I_wr => SC_enregistrement,
+ I_adr => SC_adr,
+ I_data => SC_numero_courant,
+ O_reg0 => SC_r0,
+ O_reg1 => SC_r1,
+ O_reg2 => SC_r2,
+ O_reg3 => SC_r3,
+ O_reg4 => SC_r4,
+ O_reg5 => SC_r5
);
-
compteur_valid_1 : entity work.compteur_valid
port map (
- I_clk => I_clk,
- I_rst => I_rst,
- I_comptage => SC_enregistrement,
- O_adr => SC_adr,
- O_fin => SC_fin
+ I_clk => I_clk,
+ I_GlobalInit => I_GlobalInit,
+ I_comptage => SC_enregistrement,
+ O_adr => SC_adr,
+ O_fin => SC_fin
);
-
compteur_1 : entity work.compteur1_49
port map (
I_clk => I_clk,
- I_rst => I_rst,
I_comptage => SC_comptage,
O_sortie => SC_numero_courant
);
-
led_pwm_1 : entity work.led_pwm
port map (
I_clk => I_clk,
- I_rst => I_rst,
I_ledR => SC_l_R,
I_ledV => SC_l_V,
O_ledR_PWM => O_l_red,
--
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