diff --git a/src/Nexys4_Master.xdc b/src/Nexys4_Master.xdc
index c5210dd8c8a9ae4054bdc404666763eb780e6f68..8a19dd4d8db8feff080c24ec6c4a3cf028cad224 100644
--- a/src/Nexys4_Master.xdc
+++ b/src/Nexys4_Master.xdc
@@ -1,10 +1,10 @@
##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
-set_property PACKAGE_PIN E16 [get_ports I_bouton]
-set_property IOSTANDARD LVCMOS33 [get_ports I_bouton]
+set_property PACKAGE_PIN E16 [get_ports I_button]
+set_property IOSTANDARD LVCMOS33 [get_ports I_button]
##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
-set_property PACKAGE_PIN P4 [get_ports I_bloque]
-set_property IOSTANDARD LVCMOS33 [get_ports I_bloque]
+set_property PACKAGE_PIN P4 [get_ports I_block]
+set_property IOSTANDARD LVCMOS33 [get_ports I_block]
## Clock signal
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
@@ -18,57 +18,57 @@ set_property IOSTANDARD LVCMOS33 [get_ports I_rst]
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
-set_property PACKAGE_PIN K5 [get_ports O_rouge]
-set_property IOSTANDARD LVCMOS33 [get_ports O_rouge]
+set_property PACKAGE_PIN K5 [get_ports O_red]
+set_property IOSTANDARD LVCMOS33 [get_ports O_red]
##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
-set_property PACKAGE_PIN H6 [get_ports O_vert]
-set_property IOSTANDARD LVCMOS33 [get_ports O_vert]
+set_property PACKAGE_PIN H6 [get_ports O_green]
+set_property IOSTANDARD LVCMOS33 [get_ports O_green]
#7 O_affment display
#Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
-set_property PACKAGE_PIN L3 [get_ports {O_aff[0]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[0]}]
+set_property PACKAGE_PIN L3 [get_ports {O_7segmentDisplay[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[0]}]
#Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
-set_property PACKAGE_PIN N1 [get_ports {O_aff[1]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[1]}]
+set_property PACKAGE_PIN N1 [get_ports {O_7segmentDisplay[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[1]}]
#Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
-set_property PACKAGE_PIN L5 [get_ports {O_aff[2]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[2]}]
+set_property PACKAGE_PIN L5 [get_ports {O_7segmentDisplay[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[2]}]
#Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
-set_property PACKAGE_PIN L4 [get_ports {O_aff[3]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[3]}]
+set_property PACKAGE_PIN L4 [get_ports {O_7segmentDisplay[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[3]}]
#Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
-set_property PACKAGE_PIN K3 [get_ports {O_aff[4]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[4]}]
+set_property PACKAGE_PIN K3 [get_ports {O_7segmentDisplay[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[4]}]
#Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
-set_property PACKAGE_PIN M2 [get_ports {O_aff[5]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[5]}]
+set_property PACKAGE_PIN M2 [get_ports {O_7segmentDisplay[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[5]}]
#Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
-set_property PACKAGE_PIN L6 [get_ports {O_aff[6]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[6]}]
+set_property PACKAGE_PIN L6 [get_ports {O_7segmentDisplay[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentDisplay[6]}]
#Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
-set_property PACKAGE_PIN N6 [get_ports {O_an[0]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[0]}]
+set_property PACKAGE_PIN N6 [get_ports {O_7segmentSelect[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[0]}]
#Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
-set_property PACKAGE_PIN M6 [get_ports {O_an[1]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[1]}]
+set_property PACKAGE_PIN M6 [get_ports {O_7segmentSelect[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[1]}]
#Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
-set_property PACKAGE_PIN M3 [get_ports {O_an[2]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[2]}]
+set_property PACKAGE_PIN M3 [get_ports {O_7segmentSelect[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[2]}]
#Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
-set_property PACKAGE_PIN N5 [get_ports {O_an[3]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[3]}]
+set_property PACKAGE_PIN N5 [get_ports {O_7segmentSelect[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[3]}]
#Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
-set_property PACKAGE_PIN N2 [get_ports {O_an[4]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[4]}]
+set_property PACKAGE_PIN N2 [get_ports {O_7segmentSelect[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[4]}]
#Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
-set_property PACKAGE_PIN N4 [get_ports {O_an[5]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[5]}]
+set_property PACKAGE_PIN N4 [get_ports {O_7segmentSelect[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[5]}]
#Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
-set_property PACKAGE_PIN L1 [get_ports {O_an[6]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[6]}]
+set_property PACKAGE_PIN L1 [get_ports {O_7segmentSelect[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[6]}]
#Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
-set_property PACKAGE_PIN M1 [get_ports {O_an[7]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {O_an[7]}]
+set_property PACKAGE_PIN M1 [get_ports {O_7segmentSelect[7]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_7segmentSelect[7]}]
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 43420cea4e8b9c0448efd3459869bb6f0c25943b..d5a63bca18f677bfb194239b27eaffee0b5222da 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -7,7 +7,7 @@ entity compteur_modulo6 is
port (
I_clk : in std_logic;
I_rst : in std_logic;
- I_bloque : in std_logic;
+ I_block : in std_logic;
O_CounterMod6 : out std_logic_vector(2 downto 0)
);
@@ -25,7 +25,7 @@ begin
if I_rst = '1' then
_BLANK_
elsif rising_edge(I_clk) then
- _BLANK_
+ _BLANK_
end if;
end process mod6;
diff --git a/src/diviseur_freq.vhd b/src/diviseur_freq.vhd
index 3054bace8f44a77597ebbb0923e1ac6cc5d51b9a..63883d33883299352f3a4962989542468f324898 100644
--- a/src/diviseur_freq.vhd
+++ b/src/diviseur_freq.vhd
@@ -10,27 +10,27 @@ entity diviseur_freq is
port (
I_clk : in std_logic;
I_rst : in std_logic;
- O_FAST : out std_logic;
- O_SLOW : out std_logic
+ O_fast : out std_logic;
+ O_slow : out std_logic
);
end diviseur_freq;
architecture Behavioral of diviseur_freq is
- signal compt : unsigned (26 downto 0);
+ signal SR_counter : unsigned (26 downto 0);
begin
process (I_clk, I_rst)
begin
if I_rst = '1' then
- compt <= (others => '0');
+ SR_counter <= (others => '0');
elsif rising_edge(I_clk) then
- compt <= compt + 1;
+ SR_counter <= SR_counter + 1;
end if;
end process;
- O_FAST <= compt(n_fast);
- O_SLOW <= compt(n_slow);
+ O_fast <= SR_counter(n_fast);
+ O_slow <= SR_counter(n_slow);
end Behavioral;
diff --git a/src/loto.vhd b/src/loto.vhd
index 5e258b336bc8337a0c96bae023a0ae9f03174a7c..3b7c175fb82c89ce3b13cbe8ab238e0095e00f1d 100644
--- a/src/loto.vhd
+++ b/src/loto.vhd
@@ -7,14 +7,14 @@ entity loto is
n_fast : natural := 15;
n_slow : natural := 25);
port (
- I_bouton : in std_logic;
- I_bloque : in std_logic;
- I_clk_100m : in std_logic;
- I_rst : in std_logic;
- O_aff : out std_logic_vector(6 downto 0);
- O_rouge : out std_logic;
- O_vert : out std_logic;
- O_an : out std_logic_vector(7 downto 0)
+ I_button : in std_logic;
+ I_block : in std_logic;
+ I_clk_100m : in std_logic;
+ I_rst : in std_logic;
+ O_7segmentDisplay : out std_logic_vector(6 downto 0);
+ O_7segmentSelect : out std_logic_vector(7 downto 0);
+ O_red : out std_logic;
+ O_green : out std_logic
);
end entity loto;
@@ -25,22 +25,22 @@ architecture arch of loto is
I_clk : in std_logic;
I_rst : in std_logic;
I_clk_display : in std_logic;
- I_bouton : in std_logic;
+ I_button : in std_logic;
O_reg0 : out std_logic_vector(5 downto 0);
O_reg1 : out std_logic_vector(5 downto 0);
O_reg2 : out std_logic_vector(5 downto 0);
O_reg3 : out std_logic_vector(5 downto 0);
O_reg4 : out std_logic_vector(5 downto 0);
O_reg5 : out std_logic_vector(5 downto 0);
- O_l_rouge : out std_logic;
- O_l_verte : out std_logic);
+ O_l_red : out std_logic;
+ O_l_green : out std_logic);
end component tirage;
component compteur_modulo6 is
port (
I_clk : in std_logic;
I_rst : in std_logic;
- I_bloque : in std_logic;
+ I_block : in std_logic;
O_CounterMod6 : out std_logic_vector(2 downto 0));
end component compteur_modulo6;
@@ -51,16 +51,16 @@ architecture arch of loto is
port (
I_clk : in std_logic;
I_rst : in std_logic;
- O_FAST : out std_logic;
- O_SLOW : out std_logic
+ O_fast : out std_logic;
+ O_slow : out std_logic
);
end component diviseur_freq;
component transcodeur7s_d_u is
port (
- I_nombre : in std_logic_vector(5 downto 0);
- O_uni : out std_logic_vector (6 downto 0);
- O_diz : out std_logic_vector (6 downto 0)
+ I_number : in std_logic_vector(5 downto 0);
+ O_unit : out std_logic_vector (6 downto 0);
+ O_ten : out std_logic_vector (6 downto 0)
);
end component transcodeur7s_d_u;
@@ -77,36 +77,30 @@ architecture arch of loto is
);
end component mux6_1;
- component decodeur_uni is
- port (
- I_E : in std_logic_vector(2 downto 0);
- O_uni : out std_logic_vector(6 downto 0)
- );
- end component decodeur_uni;
-
component modulo4 is
port (
I_clk : in std_logic;
I_rst : in std_logic;
O_Mod4 : out std_logic_vector(1 downto 0);
- O_decod : out std_logic_vector(3 downto 0));
+ O_decod : out std_logic_vector(3 downto 0)
+ );
end component modulo4;
- signal SC_clkDisplay : std_logic;
- signal SC_clk : std_logic;
- signal SC_reg0 : std_logic_vector(5 downto 0);
- signal SC_reg1 : std_logic_vector(5 downto 0);
- signal SC_reg2 : std_logic_vector(5 downto 0);
- signal SC_reg3 : std_logic_vector(5 downto 0);
- signal SC_reg4 : std_logic_vector(5 downto 0);
- signal SC_reg5 : std_logic_vector(5 downto 0);
- signal SC_num : std_logic_vector(2 downto 0);
- signal SC_nombre : std_logic_vector(5 downto 0);
- signal SC_uni : std_logic_vector(6 downto 0);
- signal SC_diz : std_logic_vector(6 downto 0);
- signal SC_minus : std_logic_vector(6 downto 0);
- signal SC_numTranscode : std_logic_vector(6 downto 0);
- signal SC_affSelect : std_logic_vector(1 downto 0);
+ signal SC_clkDisplay : std_logic;
+ signal SC_clk : std_logic;
+ signal SC_reg0 : std_logic_vector(5 downto 0);
+ signal SC_reg1 : std_logic_vector(5 downto 0);
+ signal SC_reg2 : std_logic_vector(5 downto 0);
+ signal SC_reg3 : std_logic_vector(5 downto 0);
+ signal SC_reg4 : std_logic_vector(5 downto 0);
+ signal SC_reg5 : std_logic_vector(5 downto 0);
+ signal SC_regReadAddress : std_logic_vector(2 downto 0);
+ signal SC_selectedReg : std_logic_vector(5 downto 0);
+ signal SC_unit : std_logic_vector(6 downto 0);
+ signal SC_ten : std_logic_vector(6 downto 0);
+ signal SC_minus : std_logic_vector(6 downto 0);
+ signal SC_numTranscode : std_logic_vector(6 downto 0);
+ signal SC_displaySelect : std_logic_vector(1 downto 0);
begin
@@ -115,23 +109,23 @@ begin
I_clk => SC_clk,
I_rst => I_rst,
I_clk_display => SC_clkDisplay,
- I_bouton => I_bouton,
+ I_button => I_button,
O_reg0 => SC_reg0,
O_reg1 => SC_reg1,
O_reg2 => SC_reg2,
O_reg3 => SC_reg3,
O_reg4 => SC_reg4,
O_reg5 => SC_reg5,
- O_l_rouge => O_rouge,
- O_l_verte => O_vert
+ O_l_red => O_red,
+ O_l_green => O_green
);
modulo6_1 : entity work.compteur_modulo6
port map (
I_clk => SC_clkDisplay,
I_rst => I_rst,
- I_bloque => I_bloque,
- O_CounterMod6 => SC_num
+ I_block => I_block,
+ O_CounterMod6 => SC_regReadAddress
);
diviseur_freq_1 : entity work.diviseur_freq
@@ -141,8 +135,8 @@ begin
port map (
I_clk => I_clk_100m,
I_rst => I_rst,
- O_FAST => SC_clk,
- O_SLOW => SC_clkDisplay
+ O_fast => SC_clk,
+ O_slow => SC_clkDisplay
);
mux6_1_1 : entity work.mux6_1
@@ -153,41 +147,45 @@ begin
I_3 => SC_reg3,
I_4 => SC_reg4,
I_5 => SC_reg5,
- I_sel => SC_num,
- O_mux6 => SC_nombre
+ I_sel => SC_regReadAddress,
+ O_mux6 => SC_selectedReg
);
transcod_1 : entity work.transcodeur7s_d_u(transcod_int) --(transcod_ARCH)
port map (
- I_nombre => SC_nombre,
- O_uni => SC_uni,
- O_diz => SC_diz
- );
-
- decodeur_uni_1 : entity work.transcodeur7s_u
- port map (
- E => SC_num,
- Suni => SC_numTranscode
+ I_number => SC_selectedReg,
+ O_unit => SC_unit,
+ O_ten => SC_ten
);
modulo4_2 : entity work.modulo4
port map (
I_clk => SC_clk,
I_rst => I_rst,
- O_Mod4 => SC_affSelect,
- O_decod => O_an(3 downto 0)
+ O_Mod4 => SC_displaySelect,
+ O_decod => O_7segmentSelect(3 downto 0)
);
- O_an(4) <= '1';
- O_an(5) <= '1';
- O_an(6) <= '1';
- O_an(7) <= '1';
+
+ with to_integer(unsigned(SC_regReadAddress)) select SC_numTranscode <=
+ "1111001" when 0, -- 1 for a 0 for better readability
+ "0100100" when 1,
+ "0110000" when 2,
+ "0011001" when 3,
+ "0010010" when 4,
+ "0000010" when 5,
+ "0110000" when others;
+
+ O_7segmentSelect(4) <= '1';
+ O_7segmentSelect(5) <= '1';
+ O_7segmentSelect(6) <= '1';
+ O_7segmentSelect(7) <= '1';
SC_minus <= "0111111";
- with SC_affSelect select O_aff <=
- SC_uni when "00",
- SC_diz when "01",
+ with SC_displaySelect select O_7segmentDisplay <=
+ SC_unit when "00",
+ SC_ten when "01",
SC_minus when "10",
SC_numTranscode when others;
diff --git a/src/loto_tb.vhd b/src/loto_tb.vhd
index 72d3fdb1dacbe24a5090b43b1a45498ff9778d0a..7c951b1d67c78c52cbc1a620a20b4cf525f60190 100644
--- a/src/loto_tb.vhd
+++ b/src/loto_tb.vhd
@@ -6,7 +6,7 @@
-- Author : Matthieu Arzel <mattieu.arzel@imt-atlantique.fr>
-- Company :
-- Created : 2018-06-14
--- Last update: 2023-10-11
+-- Last update: 2023-10-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -52,14 +52,14 @@ begin -- architecture ar
n_fast => n_fast,
n_slow => n_slow)
port map (
- I_bouton => bouton,
- I_bloque => bloque,
- I_clk_100m => clk_100m,
- I_rst => rst,
- O_aff => s_aff,
- O_rouge => rouge,
- O_vert => vert,
- O_an => an
+ I_clk_100m => clk_100m,
+ I_rst => rst,
+ I_button => bouton,
+ I_block => bloque,
+ O_7segmentDisplay => s_aff,
+ O_7segmentSelect => an,
+ O_red => rouge,
+ O_green => vert
);
-- clock generation
diff --git a/src/tirage.vhd b/src/tirage.vhd
index e91e4626f2ad6a8a872c66435b900dd35b1d4440..008296732115c2fae93ab16e62830babf3da3116 100644
--- a/src/tirage.vhd
+++ b/src/tirage.vhd
@@ -9,15 +9,15 @@ entity tirage is
I_clk : in std_logic;
I_rst : in std_logic;
I_clk_display : in std_logic;
- I_bouton : in std_logic;
+ I_button : in std_logic;
O_reg0 : out std_logic_vector(5 downto 0);
O_reg1 : out std_logic_vector(5 downto 0);
O_reg2 : out std_logic_vector(5 downto 0);
O_reg3 : out std_logic_vector(5 downto 0);
O_reg4 : out std_logic_vector(5 downto 0);
O_reg5 : out std_logic_vector(5 downto 0);
- O_l_rouge : out std_logic;
- O_l_verte : out std_logic
+ O_l_red : out std_logic;
+ O_l_green : out std_logic
);
end tirage;
@@ -29,13 +29,13 @@ architecture a_tirage of tirage is
I_clk : in std_logic;
I_rst : in std_logic;
I_clk_display : in std_logic;
- I_bouton : in std_logic;
+ I_button : in std_logic;
I_invalide : in std_logic;
I_fin : in std_logic;
O_comptage : out std_logic;
O_enregistrement : out std_logic;
- O_l_rouge : out std_logic;
- O_l_verte : out std_logic);
+ O_l_red : out std_logic;
+ O_l_green : out std_logic);
end component automate;
component registres is
@@ -114,16 +114,16 @@ begin
automate_1 : entity work.automate
port map (
- I_rst => I_rst,
- I_clk => I_clk,
- I_clk_display => I_clk_display,
- I_bouton => I_bouton,
- I_invalide => SC_invalide,
- I_fin => SC_fin,
- O_comptage => SC_comptage,
- O_enregistrement => SC_enregistrement,
- O_l_rouge => SC_l_R,
- O_l_verte => SC_l_V
+ I_rst => I_rst,
+ I_clk => I_clk,
+ I_clk_display => I_clk_display,
+ I_button => I_button,
+ I_invalide => SC_invalide,
+ I_end => SC_fin,
+ O_counting => SC_comptage,
+ O_store => SC_enregistrement,
+ O_l_red => SC_l_R,
+ O_l_green => SC_l_V
);
@@ -169,8 +169,8 @@ begin
I_rst => I_rst,
I_ledR => SC_l_R,
I_ledV => SC_l_V,
- O_ledR_PWM => O_l_rouge,
- O_ledV_PWM => O_l_verte
+ O_ledR_PWM => O_l_red,
+ O_ledV_PWM => O_l_green
);
SC_invalide <= '1' when (SC_r0 = SC_numero_courant or
diff --git a/src/transcodeur7s_d_u.vhd b/src/transcodeur7s_d_u.vhd
index 31fb0d128a801762a3f42d47ac7e43fa83ca28f0..590cb8c01fdb20ac531247b3efd81682f4b97fbe 100644
--- a/src/transcodeur7s_d_u.vhd
+++ b/src/transcodeur7s_d_u.vhd
@@ -4,44 +4,43 @@ use IEEE.numeric_std.all;
entity transcodeur7s_d_u is
port (
- I_nombre : in std_logic_vector(5 downto 0);
- O_uni : out std_logic_vector (6 downto 0);
- O_diz : out std_logic_vector (6 downto 0)
+ I_number : in std_logic_vector(5 downto 0);
+ O_unit : out std_logic_vector (6 downto 0);
+ O_ten : out std_logic_vector (6 downto 0)
);
end transcodeur7s_d_u;
architecture transcod_ARCH of transcodeur7s_d_u is
signal SC_u_nombre : unsigned(5 downto 0);
- signal SC_u_uni : unsigned(5 downto 0);
- signal SC_u_diz : unsigned(2 downto 0);
+ signal SC_u_unit : unsigned(5 downto 0);
+ signal SC_u_ten : unsigned(2 downto 0);
begin
- SC_u_nombre <= unsigned(I_nombre);
+ SC_u_nombre <= unsigned(I_number);
p_diz : process (SC_u_nombre) is
begin
if (SC_u_nombre < 10) then
- SC_u_diz <= (others => '0');
- SC_u_uni <= SC_u_nombre;
+ SC_u_ten <= (others => '0');
+ SC_u_unit <= SC_u_nombre;
elsif SC_u_nombre < 20 then
- SC_u_diz <= to_unsigned(1, 3);
- SC_u_uni <= SC_u_nombre - 10;
+ SC_u_ten <= to_unsigned(1, 3);
+ SC_u_unit <= SC_u_nombre - 10;
elsif SC_u_nombre < 30 then
- SC_u_diz <= to_unsigned(2, 3);
- SC_u_uni <= SC_u_nombre - 20;
+ SC_u_ten <= to_unsigned(2, 3);
+ SC_u_unit <= SC_u_nombre - 20;
elsif SC_u_nombre < 40 then
- SC_u_diz <= to_unsigned(3, 3);
- SC_u_uni <= SC_u_nombre - 30;
+ SC_u_ten <= to_unsigned(3, 3);
+ SC_u_unit <= SC_u_nombre - 30;
else
- SC_u_diz <= to_unsigned(4, 3);
- SC_u_uni <= SC_u_nombre - 40;
+ SC_u_ten <= to_unsigned(4, 3);
+ SC_u_unit <= SC_u_nombre - 40;
end if;
end process p_diz;
-
- with to_integer(SC_u_uni) select O_uni <=
+ with to_integer(SC_u_unit) select O_unit <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
@@ -53,7 +52,7 @@ begin
"0000000" when 8,
"0010000" when others;
- with to_integer(SC_u_diz) select O_diz <=
+ with to_integer(SC_u_ten) select O_ten <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
@@ -64,17 +63,17 @@ end transcod_ARCH;
architecture transcod_int of transcodeur7s_d_u is
- signal SC_uni_int : integer range 0 to 9;
+ signal SC_unit_int : integer range 0 to 9;
signal SC_diz_int : integer range 0 to 4;
signal SC_num_int : integer range 0 to 49;
begin
- SC_num_int <= to_integer(unsigned(I_nombre));
- SC_uni_int <= SC_num_int rem 10;
+ SC_num_int <= to_integer(unsigned(I_number));
+ SC_unit_int <= SC_num_int rem 10;
SC_diz_int <= SC_num_int / 10;
- with SC_uni_int select O_uni <=
+ with SC_unit_int select O_unit <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
@@ -86,7 +85,7 @@ begin
"0000000" when 8,
"0010000" when others;
- with SC_diz_int select O_diz <=
+ with SC_diz_int select O_ten <=
"1000000" when 0,
"1111001" when 1,
"0100100" when 2,
diff --git a/src/transcodeur7s_u.vhd b/src/transcodeur7s_u.vhd
index 936844725f869b624aff1fa261d69b8e12eff358..ad82269687236fcaf902f4e52a56b3efbd629e97 100644
--- a/src/transcodeur7s_u.vhd
+++ b/src/transcodeur7s_u.vhd
@@ -1,30 +1,63 @@
+-------------------------------------------------------------------------------
+-- Title :
+-- Project :
+-------------------------------------------------------------------------------
+-- File : transcodeur7s_u.vhd
+-- Author : Jean-Noel BAZIN <jnbazin@pc-disi-026.enst-bretagne.fr>
+-- Company :
+-- Created : 2023-10-12
+-- Last update: 2023-10-12
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: converts the 3-bit representation of a decimal (I_nombre) into a 7-segment display command (O_uni).
+-- A display command is active low: to turn on a segment, apply 0.
+-- a (= O_uni(6)) is the MSB, g (=O_uni(0)) is the LSB.
+-- So, for digit 3 the output will be represented by "0000110".
+-- _______
+-- | a |
+-- f| |b
+-- | |
+-- |_______|
+-- | g |
+-- e| |c
+-- | |
+-- |_______|
+-- d
+--
+-- For this 7 segment transcoder, only the number between [0-5] are taken into account. In addition, there is a shift by 1. 0 will be represented by a 1 on the 7 segment display.
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2023
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-05-30 1.0 jnbazin Created
+-------------------------------------------------------------------------------
+
+
+
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity transcodeur7s_u is
- port (E : in std_logic_vector(2 downto 0);
- Suni : out std_logic_vector(6 downto 0));
+ port (
+ I_nombre : in std_logic_vector(2 downto 0);
+ O_uni : out std_logic_vector(6 downto 0)
+ );
end transcodeur7s_u;
architecture Behavioral of transcodeur7s_u is
begin
- P1 : process (E)
-
- begin
- case E is
- when "000" => Suni <= "1000000";
- when "001" => Suni <= "1111001";
- when "010" => Suni <= "0100100";
- when "011" => Suni <= "0110000";
- when "100" => Suni <= "0011001";
- when "101" => Suni <= "0010010";
- when "110" => Suni <= "0000010";
- when others => Suni <= "0000000";
- end case;
- end process;
-
-
+ with to_integer(I_nombre) select O_uni <=
+ "1111001" when 0, -- 1 for a 0
+ "0100100" when 1,
+ "0110000" when 2,
+ "0011001" when 3,
+ "0010010" when 4,
+ "0000010" when 5,
+ "0110000" when others;
end Behavioral;