diff --git a/src/Nexys4DDR-Master.xdc b/src/Nexys4DDR-Master.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..2ae544a9ef6274f99b4a4316b906ba3f407e867e
--- /dev/null
+++ b/src/Nexys4DDR-Master.xdc
@@ -0,0 +1,265 @@
+## This file is a general .xdc for the Nexys4 DDR Rev. C
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100m }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100m}];
+
+
+##Switches
+
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
+#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
+#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
+#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
+#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
+#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
+#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
+#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
+#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
+#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
+set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { bloque }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+
+
+## LEDs
+
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
+#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
+set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { rouge }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { vert}]; #IO_0_14 Sch=led17_g
+#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+
+##7 segment display
+
+set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { s_aff[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { s_aff[1] }]; #IO_25_14 Sch=cb
+set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { s_aff[2] }]; #IO_25_15 Sch=cc
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { s_aff[3] }]; #IO_L17P_T2_A26_15 Sch=cd
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { s_aff[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { s_aff[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { s_aff[6] }]; #IO_L4P_T0_D04_14 Sch=cg
+
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
+
+set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+
+
+##Buttons
+
+#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+
+set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { bouton }]; #IO_L9P_T1_DQS_14 Sch=btnc
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
+#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
+#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+
+
+##Pmod Headers
+
+
+##Pmod Header JA
+
+#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
+
+
+##Pmod Header JB
+
+#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
+#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+
+
+##Pmod Header JC
+
+#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
+#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
+#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
+#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
+#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
+#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
+
+
+##Pmod Header JD
+
+#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
+#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
+#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
+#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
+#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
+#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+
+
+##Pmod Header JXADC
+
+#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
+#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
+#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
+#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
+#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
+#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
+#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
+#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
+
+
+##VGA Connector
+
+#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
+#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
+#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
+#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
+
+#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
+#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
+#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
+#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
+
+#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
+#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
+#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
+#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
+
+#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
+#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
+
+
+##Micro SD Connector
+
+#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
+#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
+#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
+#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
+#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
+#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
+#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
+#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+
+
+##Accelerometer
+
+#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
+#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
+#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
+#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
+#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
+#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
+
+
+##Temperature Sensor
+
+#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
+#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
+#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
+#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
+
+##Omnidirectional Microphone
+
+#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
+#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
+#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+
+
+##PWM Audio Amplifier
+
+#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
+#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+
+
+##USB-RS232 Interface
+
+#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
+#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+
+##USB HID (PS/2)
+
+#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
+#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+
+
+##SMSC Ethernet PHY
+
+#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
+#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
+#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
+#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+
+
+##Quad SPI Flash
+
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/Nexys4_Master.xdc b/src/Nexys4_Master.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..ffcb724628c80469163547ec4378f85b5638ba95
--- /dev/null
+++ b/src/Nexys4_Master.xdc
@@ -0,0 +1,78 @@
+##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
+set_property PACKAGE_PIN E16 [get_ports bouton]
+set_property IOSTANDARD LVCMOS33 [get_ports bouton]
+
+##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
+set_property PACKAGE_PIN P4 [get_ports bloque]
+set_property IOSTANDARD LVCMOS33 [get_ports bloque]
+
+## Clock signal
+##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
+set_property PACKAGE_PIN E3 [get_ports clk_100m]
+set_property IOSTANDARD LVCMOS33 [get_ports clk_100m]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_100m]
+
+##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
+set_property PACKAGE_PIN V10 [get_ports rst]
+set_property IOSTANDARD LVCMOS33 [get_ports rst]
+
+
+ ##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
+set_property PACKAGE_PIN K5 [get_ports rouge]
+set_property IOSTANDARD LVCMOS33 [get_ports rouge]
+
+##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
+set_property PACKAGE_PIN H6 [get_ports vert]
+set_property IOSTANDARD LVCMOS33 [get_ports vert]
+
+#7 s_affment display
+#Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
+set_property PACKAGE_PIN L3 [get_ports {s_aff[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[0]}]
+#Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
+set_property PACKAGE_PIN N1 [get_ports {s_aff[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[1]}]
+#Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
+set_property PACKAGE_PIN L5 [get_ports {s_aff[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[2]}]
+#Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
+set_property PACKAGE_PIN L4 [get_ports {s_aff[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[3]}]
+#Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
+set_property PACKAGE_PIN K3 [get_ports {s_aff[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[4]}]
+#Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
+set_property PACKAGE_PIN M2 [get_ports {s_aff[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[5]}]
+#Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
+set_property PACKAGE_PIN L6 [get_ports {s_aff[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[6]}]
+
+##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
+#set_property PACKAGE_PIN M4 [get_ports dp]
+# set_property IOSTANDARD LVCMOS33 [get_ports dp]
+
+#Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
+set_property PACKAGE_PIN N6 [get_ports {an[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+#Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
+set_property PACKAGE_PIN M6 [get_ports {an[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+#Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
+set_property PACKAGE_PIN M3 [get_ports {an[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+#Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
+set_property PACKAGE_PIN N5 [get_ports {an[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+#Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
+set_property PACKAGE_PIN N2 [get_ports {an[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
+#Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
+set_property PACKAGE_PIN N4 [get_ports {an[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
+#Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
+set_property PACKAGE_PIN L1 [get_ports {an[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
+#Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
+set_property PACKAGE_PIN M1 [get_ports {an[7]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
\ No newline at end of file
diff --git a/src/automate.vhd b/src/automate.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4767f4e0067a22f045f44a7022057ec682e7cdf7
--- /dev/null
+++ b/src/automate.vhd
@@ -0,0 +1,63 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity automate is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_bouton : in std_logic;
+ I_clk_display : in std_logic;
+ I_bouton : in std_logic;
+ I_invalide : in std_logic;
+ I_fin : in std_logic;
+ O_comptage : out std_logic;
+ O_enregistrement : out std_logic;
+ O_l_rouge : out std_logic;
+ O_l_verte : out std_logic
+ );
+end automate;
+
+architecture a_automate of automate is
+
+ type TYPE_ETAT is (
+ st_attente_echec,
+ st_attente_succes,
+ st_comptage,
+ st_comparaison,
+ st_enregistrement,
+ st_fin_vert,
+ st_fin_rouge
+ );
+ signal ST_ETAT : TYPE_ETAT;
+
+begin
+
+
+ UpdateState : process (I_clk, I_rst)
+
+ begin
+ if(I_rst = '1')then
+ __BLANK_TO_FILL__
+ case ETAT is
+
+ when st_attente_succes =>
+ l_verte <= '1';
+ l_rouge <= '0';
+ comptage <= '0';
+ enregistrement <= '0';
+ if bouton = '1' then
+ ST_ETAT <= st_comptage;
+ else
+ ST_ETAT <= st_attente_succes;
+ end if;
+
+ when __BLANK_TO_FILL__
+
+ end case;
+
+ end process COMB;
+
+
+ end a_automate;
diff --git a/src/comparateur.vhd b/src/comparateur.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..af9a8b441400f210e200f44504983a984115a704
--- /dev/null
+++ b/src/comparateur.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity comparateur is
+
+ port(
+ I_reg0 : in std_logic_vector(5 downto 0);
+ I_reg1 : in std_logic_vector(5 downto 0);
+ I_reg2 : in std_logic_vector(5 downto 0);
+ I_reg3 : in std_logic_vector(5 downto 0);
+ I_reg4 : in std_logic_vector(5 downto 0);
+ I_nombre_courant : in std_logic_vector(5 downto 0);
+ O_invalide : out std_logic
+ );
+
+end entity comparateur;
+
+architecture arch of comparateur is
+
+begin
+
+ invalide <= '1' when (I_reg0 = I_nombre_courant
+ or I_reg1 = I_nombre_courant
+ or I_reg2 = I_nombre_courant
+ or I_reg3 = I_nombre_courant
+ or I_reg4 = I_nombre_courant
+ ) else '0';
+
+end architecture arch;
diff --git a/src/compteur1_49.vhd b/src/compteur1_49.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e24736c865565286fc46d0787712ffe16307507e
--- /dev/null
+++ b/src/compteur1_49.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity compteur1_49 is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_comptage : in std_logic;
+ O_sortie : out std_logic_vector(5 downto 0)
+ );
+
+end compteur1_49;
+
+architecture compteur_a of compteur1_49 is
+
+ signal SR_cpt_val : unsigned(5 downto 0);
+
+begin
+
+ cpt : process (I_clk, I_rst)
+
+ begin
+ if I_rst = '1' then
+ SR_cpt_val <= to_unsigned(1, 6);
+ elsif rising_edge(I_clk) then
+ if I_comptage = '1' then
+ if SR_cpt_val = 49 then
+ SR_cpt_val <= to_unsigned(1, 6);
+ else
+ SR_cpt_val <= SR_cpt_val + 1;
+ end if;
+ end if;
+ end if;
+ end process cpt;
+
+ sortie <= std_logic_vector(SR_cpt_val);
+
+end compteur_a;
diff --git a/src/compteur_modulo4.vhd b/src/compteur_modulo4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8d7c529c6adca3520662d23272576cd02a62d33e
--- /dev/null
+++ b/src/compteur_modulo4.vhd
@@ -0,0 +1,69 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity compteur_modulo4 is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ O_CounterMod4 : out std_logic_vector(1 downto 0);
+ O_parallel1 : out std_logic
+ O_parallel2 : out std_logic
+ O_parallel3 : out std_logic
+ O_parallel4 : out std_logic
+ );
+end compteur_modulo4;
+
+architecture modulo4_a of compteur_modulo4 is
+
+ signal SR_Counter : unsigned(1 downto 0);
+
+begin
+
+ mod4 : process (clk, rst)
+
+ begin
+ if rst = '1' then
+ SR_Counter <= "00";
+ elsif rising_edge(clk) then
+ if SR_Counter = "11" then
+ SR_Counter <= "00";
+ else
+ SR_Counter <= SR_Counter + 1;
+ end if;
+ end if;
+ end process mod4;
+
+ O_CounterMod4 <= std_logic_vector(SR_Counter);
+
+ parallel : process (SR_Counter)
+ begin
+ case SR_Counter is
+ when "00" =>
+ O_parallel1 <= '0';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+
+ when "01" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '0';
+ O_parallel3 <= '1';
+ O_parallel4 <= '1';
+
+ when "10" =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '0';
+ O_parallel4 <= '1';
+
+ when others =>
+ O_parallel1 <= '1';
+ O_parallel2 <= '1';
+ O_parallel3 <= '1';
+ O_parallel4 <= '0';
+
+ end case;
+ end process parallel;
+
+end modulo4_a;
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f0359a26e39d357d4089fac2e2fef1e023a02da0
--- /dev/null
+++ b/src/compteur_modulo6.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity compteur_modulo6 is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_bloque : in std_logic;
+ O_CounterMod6 : out std_logic_vector(2 downto 0)
+ );
+
+end compteur_modulo6;
+
+
+architecture modulo6_a of compteur_modulo6 is
+
+ signal SR_Counter : unsigned(2 downto 0);
+
+begin
+
+ mod6 : process (_BLANK_)
+
+ begin
+ if rst = '1' then
+ _BLANK_
+ elsif rising_edge(clk) then
+ _BLANK_
+ end if;
+ end process mod6;
+
+ O_CounterMod6 <= std_logic_vector(SR_Counter);
+
+end modulo6_a;
diff --git a/src/compteur_modulo6_tb.vhd b/src/compteur_modulo6_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d700a882f63d7041b2477a1d8f0d9db607cd8f32
--- /dev/null
+++ b/src/compteur_modulo6_tb.vhd
@@ -0,0 +1,70 @@
+-------------------------------------------------------------------------------
+-- Title : Testbench for design "compteur_modulo6"
+-- Project :
+-------------------------------------------------------------------------------
+-- File : compteur_modulo6_tb.vhd
+-- Author : Matthieu Arzel <marzel@marzel-XPS-13-9350>
+-- Company :
+-- Created : 2019-01-10
+-- Last update: 2023-10-04
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2019-01-10 1.0 marzel Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+-------------------------------------------------------------------------------
+
+entity compteur_modulo6_tb is
+end entity compteur_modulo6_tb;
+
+-------------------------------------------------------------------------------
+
+architecture arch of compteur_modulo6_tb is
+
+ -- component ports
+ signal rst : std_logic := '0';
+ signal bloque : std_logic := '0';
+ signal sortie : std_logic_vector(2 downto 0);
+
+ -- clock
+ signal Clk : std_logic := '1';
+
+begin -- architecture arch
+
+ -- component instantiation
+ DUT : entity work.compteur_modulo6
+ port map (
+ I_clk => clk,
+ I_rst => rst,
+ I_bloque => bloque,
+ O_counterMod6 => sortie);
+
+ -- clock generation
+ Clk <= not Clk after 10 ns;
+
+ -- waveform generation
+ rst <= '0', '1' after 6 ns, '0' after 27 ns, '1' after 128 ns, '0' after 147 ns;
+ bloque <= '0', '1' after 33 ns, '0' after 76 ns;
+
+
+
+end architecture arch;
+
+-------------------------------------------------------------------------------
+
+configuration compteur_modulo6_tb_arch_cfg of compteur_modulo6_tb is
+ for arch
+ end for;
+end compteur_modulo6_tb_arch_cfg;
+
+-------------------------------------------------------------------------------
diff --git a/src/compteur_valid.vhd b/src/compteur_valid.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..201e6a8c568883c2aed6699b6507f2dedf73b9f6
--- /dev/null
+++ b/src/compteur_valid.vhd
@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity compteur_valid is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_comptage : in std_logic;
+ O_adr : out std_logic_vector(2 downto 0);
+ O_fin : out std_logic
+ );
+end compteur_valid;
+
+architecture a_compteur_valid of compteur_valid is
+
+ signal SR_Counter : integer range 0 to 5;
+
+begin
+
+ process (I_clk, I_rst)
+ begin
+ if I_rst = '1' then
+ SR_Counter <= 0;
+ elsif rising_edge(I_clk) then
+ if I_comptage = '1' then
+ if SR_Counter = 5 then
+ SR_Counter <= 0;
+ else
+ SR_Counter <= SR_Counter + 1;
+ end if;
+ end if;
+ end if;
+ end process cpt_valid;
+
+ O_adr <= std_logic_vector(to_unsigned(SR_Counter, 3));
+ O_fin <= '1' when SR_Counter = 5 else '0';
+
+end a_compteur_valid;
diff --git a/src/diviseur_freq.vhd b/src/diviseur_freq.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..12fe6d6f6bfbd82341f1f803c32ba3cbd4b36b5d
--- /dev/null
+++ b/src/diviseur_freq.vhd
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity diviseur_freq is
+ generic (
+ n_fast : natural := 15;
+ n_slow : natural := 24
+ );
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ O_FAST : out std_logic;
+ O_SLOW : out std_logic
+ );
+end diviseur_freq;
+
+architecture Behavioral of diviseur_freq is
+
+ signal compt : unsigned (26 downto 0);
+
+begin
+
+ process (I_clk, rst)
+ begin
+ if rst = '1' then
+ compt <= (others => '0');
+ elsif rising_edge(I_clk) then
+ compt <= compt + 1;
+ end if;
+ end process;
+
+ S_FAST <= compt(n_fast);
+ S_SLOW <= compt(n_slow);
+
+end Behavioral;
diff --git a/src/led_pwm.vhd b/src/led_pwm.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..57cb5a2509ae9024ced23776374c896878526b41
--- /dev/null
+++ b/src/led_pwm.vhd
@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity led_pwm is
+
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_ledR : in std_logic;
+ I_ledV : in std_logic;
+ O_ledR_PWM : out std_logic;
+ O_ledV_PWM : out std_logic
+ );
+
+end entity led_pwm;
+
+architecture arch of led_pwm is
+
+ signal SR_cpt_leds : unsigned(4 downto 0);
+ signal SR_cpt_leds_reg : unsigned(4 downto 0);
+
+begin -- architecture arch
+
+ leds_pwm : process (clk, rst) is
+ begin
+ if rst = '1' then
+ SR_cpt_leds <= (others => '0');
+ SR_cpt_leds_reg <= (others => '0');
+ elsif rising_edge(clk) then
+ SR_cpt_leds <= SR_cpt_leds + 1;
+ SR_cpt_leds_reg <= SR_cpt_leds;
+ end if;
+ end process leds_pwm;
+
+ O_ledR_PWM <= I_ledR and SR_cpt_leds(4) and not(SR_cpt_leds_reg(4));
+ O_ledV_PWM <= I_ledV and SR_cpt_leds(4) and not(SR_cpt_leds_reg(4));
+
+end architecture arch;
diff --git a/src/loto.vhd b/src/loto.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..86d14eeb0524e2a8b723aaa136be1248f68a1e74
--- /dev/null
+++ b/src/loto.vhd
@@ -0,0 +1,204 @@
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity loto is
+ generic (
+ n_fast : natural := 15;
+ n_slow : natural := 25);
+ port (
+ I_bouton : in std_logic;
+ I_bloque : in std_logic;
+ I_clk_100m : in std_logic;
+ I_rst : in std_logic;
+ O_aff : out std_logic_vector(6 downto 0);
+ O_rouge : out std_logic;
+ O_vert : out std_logic;
+ O_an : out std_logic_vector(7 downto 0)
+ );
+
+end entity loto;
+
+architecture arch of loto is
+ component tirage is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_clk_display : in std_logic;
+ I_bouton : in std_logic;
+ O_reg0 : out std_logic_vector(5 downto 0);
+ O_reg1 : out std_logic_vector(5 downto 0);
+ O_reg2 : out std_logic_vector(5 downto 0);
+ O_reg3 : out std_logic_vector(5 downto 0);
+ O_reg4 : out std_logic_vector(5 downto 0);
+ O_reg5 : out std_logic_vector(5 downto 0);
+ O_l_rouge : out std_logic;
+ O_l_verte : out std_logic);
+ end component tirage;
+
+ component modulo6 is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_enable : in std_logic;
+ I_bloque : in std_logic;
+ O_sortie : out std_logic_vector(2 downto 0));
+ end component modulo6;
+
+ component diviseur_freq is
+ generic (
+ n_fast : natural;
+ n_slow : natural);
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ O_FAST : out std_logic;
+ O_SLOW : out std_logic
+ );
+ end component diviseur_freq;
+
+ component mux6_1 is
+ port (
+ I_E0 : in std_logic_vector(5 downto 0);
+ I_E1 : in std_logic_vector(5 downto 0);
+ I_E2 : in std_logic_vector(5 downto 0);
+ I_E3 : in std_logic_vector(5 downto 0);
+ I_E4 : in std_logic_vector(5 downto 0);
+ I_E5 : in std_logic_vector(5 downto 0);
+ I_COMMANDE : in std_logic_vector(2 downto 0);
+ O_S : out std_logic_vector(5 downto 0)
+ );
+ end component mux6_1;
+
+ component transcodeur is
+ port (
+ I_nombre : in std_logic_vector(5 downto 0);
+ O_uni : out std_logic_vector (6 downto 0);
+ O_diz : out std_logic_vector (6 downto 0)
+ );
+ end component transcodeur;
+
+ component decodeur_uni is
+ port (
+ I_E : in std_logic_vector(2 downto 0);
+ O_uni : out std_logic_vector(6 downto 0)
+ );
+ end component decodeur_uni;
+
+ component modulo4 is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_enable : in std_logic;
+ O_sortie : out std_logic_vector(1 downto 0);
+ O_decod : out std_logic_vector(3 downto 0)
+ );
+ end component modulo4;
+
+ signal SC_clkDisplay : std_logic;
+ signal SC_clk : std_logic;
+ signal SC_reg0 : std_logic_vector(5 downto 0);
+ signal SC_reg1 : std_logic_vector(5 downto 0);
+ signal SC_reg2 : std_logic_vector(5 downto 0);
+ signal SC_reg3 : std_logic_vector(5 downto 0);
+ signal SC_reg4 : std_logic_vector(5 downto 0);
+ signal SC_reg5 : std_logic_vector(5 downto 0);
+ signal SC_num : std_logic_vector(2 downto 0);
+ signal SC_nombre : std_logic_vector(5 downto 0);
+ signal SC_uni : std_logic_vector(6 downto 0);
+ signal SC_diz : std_logic_vector(6 downto 0);
+ signal SC_minus : std_logic_vector(6 downto 0);
+ signal SC_numTranscode : std_logic_vector(6 downto 0);
+ signal SC_affSelect : std_logic_vector(1 downto 0);
+
+begin -- architecture arch
+
+ tirage_1 : entity work.tirage
+ port map (
+ I_clk => SC_clk,
+ I_rst => I_rst,
+ I_clk_display => SC_clkDisplay,
+ I_bouton => I_bouton,
+ O_reg0 => SC_reg0,
+ O_reg1 => SC_reg1,
+ O_reg2 => SC_reg2,
+ O_reg3 => SC_reg3,
+ O_reg4 => SC_reg4,
+ O_reg5 => SC_reg5,
+ O_l_rouge => O_rouge,
+ O_l_verte => O_vert
+ );
+
+ modulo6_1 : entity work.compteur_modulo6
+ port map (
+ I_clk => SC_clkDisplay,
+ I_rst => I_rst,
+ O_bloque => I_bloque,
+ O_sortie => SC_num
+ );
+
+ diviseur_freq_1 : entity work.diviseur_freq
+ generic map (
+ n_fast => n_fast,
+ n_slow => n_slow)
+ port map (
+ I_clk => I_clk_100m,
+ I_rst => I_rst,
+ O_FAST => SC_clk,
+ O_SLOW => SC_clkDisplay
+ );
+
+ mux6_1_1 : entity work.mux6_1
+ port map (
+ E0 => SC_reg0,
+ E1 => SC_reg1,
+ E2 => SC_reg2,
+ E3 => SC_reg3,
+ E4 => SC_reg4,
+ E5 => SC_reg5,
+ COMMANDE => SC_num,
+ S => SC_nombre
+ );
+
+
+ transcod_1 : entity work.transcodeur7s_d_u(transcod_int) --(transcod_ARCH)
+ port map (
+ S_uni => S_uni,
+ nombre => nombre,
+ S_diz => S_diz
+ );
+
+
+ decodeur_uni_1 : entity work.transcodeur7s_u
+ port map (
+ E => SC_num,
+ Suni => SC_numTranscode
+ );
+
+ modulo4_1 : entity work.modulo4
+ port map (
+ clk => clk,
+ rst => rst,
+ sortie => SC_affSelect,
+ decod => an(3 downto 0)
+ );
+
+ O_an(4) <= '1';
+ O_an(5) <= '1';
+ O_an(6) <= '1';
+ O_an(7) <= '1';
+
+ SC_minus <= "0111111";
+
+ with SC_affSelect select O_aff <=
+ S_uni when "00",
+ S_diz when "01",
+ S_minus when "10",
+ SC_numTranscode when "11";
+
+
+
+
+end architecture arch;
diff --git a/src/loto_tb.vhd b/src/loto_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dc87ab3f42ecaa48db2469e645ff3d3aa3f86026
--- /dev/null
+++ b/src/loto_tb.vhd
@@ -0,0 +1,88 @@
+--------------------------------------------------------------
+-- Title : Testbench for design "loto"
+-- Project :
+-------------------------------------------------------------------------------
+-- File : loto_tb.vhd
+-- Author : Matthieu Arzel <mattieu.arzel@imt-atlantique.fr>
+-- Company :
+-- Created : 2018-06-14
+-- Last update: 2018-06-14
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-06-14 1.0 marzel Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+-------------------------------------------------------------------------------
+
+entity loto_tb is
+
+end entity loto_tb;
+
+-------------------------------------------------------------------------------
+
+architecture ar of loto_tb is
+
+ -- component generics
+ constant n_fast : natural := 0;
+ constant n_slow : natural := 3;
+
+ -- component ports
+ signal bouton, bloque, clk_100m, rst : std_logic := '0';
+ signal s_aff : std_logic_vector(6 downto 0);
+ signal rouge, vert : std_logic;
+ signal an : std_logic_vector(7 downto 0);
+
+
+
+begin -- architecture ar
+
+ -- component instantiation
+ DUT: entity work.loto
+ generic map (
+ n_fast => n_fast,
+ n_slow => n_slow)
+ port map (
+ bouton => bouton,
+ bloque => bloque,
+ clk_100m => clk_100m,
+ rst => rst,
+ s_aff => s_aff,
+ rouge => rouge,
+ vert => vert,
+ an => an);
+
+ -- clock generation
+ clk_100m <= not clk_100m after 10 ns;
+
+ bloque <='0';
+ rst <= '0', '1' after 2 ns, '0' after 14 ns;
+
+ bouton <= '0', '1' after 37 ns, '0' after 137 ns, '1' after 184 ns,
+ '0' after 259 ns, '1' after 312 ns, '0' after 496 ns,
+ '1' after 532 ns, '0' after 876 ns, '1' after 935 ns,
+ '0' after 1023 ns, '1' after 1232 ns, '0' after 1543 ns,
+ '1' after 1670 ns, '0' after 2450 ns, '1' after 2634 ns,
+ '0' after 2872 ns, '1' after 3212 ns, '0' after 3398 ns;
+
+
+
+end architecture ar;
+
+-------------------------------------------------------------------------------
+
+configuration loto_tb_ar_cfg of loto_tb is
+ for ar
+ end for;
+end loto_tb_ar_cfg;
+
+-------------------------------------------------------------------------------
diff --git a/src/modulo4.vhd b/src/modulo4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f8157be00c6f0e1d158ef68fadaebbc8680a5406
--- /dev/null
+++ b/src/modulo4.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity modulo4 is
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ O_Mod4 : out std_logic_vector(1 downto 0);
+ O_decod : out std_logic_vector(3 downto 0)
+ );
+
+end modulo4;
+
+architecture modulo4_a of modulo4 is
+
+ signal SR_Counter : unsigned(1 downto 0);
+
+begin
+
+ process (I_clk, I_rst)
+ begin
+ if I_rst = '1' then
+ SR_Counter <= "00";
+ elsif rising_edge(I_clk) then
+ if SR_Counter = "11" then
+ SR_Counter <= "00";
+ else
+ SR_Counter <= SR_Counter + 1;
+ end if;
+ end if;
+ end process mod4;
+
+ O_Mod4 <= std_logic_vector(SR_Counter);
+
+ process (SR_Counter)
+ begin
+ O_decod(0) <= '1';
+ O_decod(1) <= '1';
+ O_decod(2) <= '1';
+ O_decod(3) <= '1';
+ case SR_Counter is
+ when "00" => O_decod(0) <= '0';
+ when "01" => O_decod(1) <= '0';
+ when "10" => O_decod(2) <= '0';
+ when others => O_decod(3) <= '0';
+ end case;
+ end process decodproc;
+
+end modulo4_a;
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..481d867ab90f94136a50518e6416aa01e24a5cf6
--- /dev/null
+++ b/src/mux6_1.vhd
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity mux6_1 is
+ port (
+ I_0 : in std_logic_vector(5 downto 0);
+ I_1 : in std_logic_vector(5 downto 0);
+ I_2 : in std_logic_vector(5 downto 0);
+ I_3 : in std_logic_vector(5 downto 0);
+ I_4 : in std_logic_vector(5 downto 0);
+ I_5 : in std_logic_vector(5 downto 0);
+ I_sel : in std_logic_vector(2 downto 0);
+ O_mux6 : out std_logic_vector(5 downto 0)
+ );
+
+end mux6_1;
+
+-------------------------------------------------------------------------
+
+architecture a_mux6_1 of mux6_1 is
+begin
+
+with __BLANK_TO_FILL__
+
+
+
+end a_mux6_1;
diff --git a/src/mux6_1_tb.vhd b/src/mux6_1_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b92759fa658750e5fd51c68e03b9ecd394cd3692
--- /dev/null
+++ b/src/mux6_1_tb.vhd
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------------
+-- Title : Testbench for design "mux6_1"
+-- Project :
+-------------------------------------------------------------------------------
+-- File : mux6_1_tb.vhd
+-- Author : Matthieu Arzel
+-- Company :
+-- Created : 2018-12-17
+-- Last update: 2023-10-04
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2018
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2018-12-17 1.0 marzel Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity mux6_1_tb is
+
+end entity mux6_1_tb;
+
+architecture arch of mux6_1_tb is
+
+ signal E0 : std_logic_vector(5 downto 0) := (0 => '1', others => '0');
+ signal E1 : std_logic_vector(5 downto 0) := (1 => '1', others => '0');
+ signal E2 : std_logic_vector(5 downto 0) := (2 => '1', others => '0');
+ signal E3 : std_logic_vector(5 downto 0) := (3 => '1', others => '0');
+ signal E4 : std_logic_vector(5 downto 0) := (4 => '1', others => '0');
+ signal E5 : std_logic_vector(5 downto 0) := (5 => '1', others => '0');
+ signal COMMANDE : std_logic_vector(2 downto 0) := (others => '0');
+ signal S : std_logic_vector(5 downto 0);
+ signal Clk : std_logic := '1';
+
+begin
+ DUT : entity work.mux6_1
+ port map (
+ I_0 => E0,
+ I_1 => E1,
+ I_2 => E2,
+ I_3 => E3,
+ I_4 => E4,
+ I_5 => E5,
+ I_sel => COMMANDE,
+ O_mux6 => S);
+
+ Clk <= not Clk after 10 ns;
+
+ cpt : process (clk) is
+ begin
+ if rising_edge(clk) then
+ if(COMMANDE = "101") then
+ COMMANDE <= "000";
+ else
+ COMMANDE <= std_logic_vector(unsigned(COMMANDE)+1);
+ end if;
+ end if;
+ end process cpt;
+
+end architecture arch;
+
+-------------------------------------------------------------------------------
+
+configuration mux6_1_tb_arch_cfg of mux6_1_tb is
+ for arch
+ end for;
+end mux6_1_tb_arch_cfg;
+
+
+-------------------------------------------------------------------------------
diff --git a/src/registres.vhd b/src/registres.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d19a39b45b447e65d99cf072c0a8b61dfc48e0ec
--- /dev/null
+++ b/src/registres.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity registres is
+
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_wr : in std_logic;
+ I_adr : in std_logic_vector(2 downto 0);
+ I_data : in std_logic_vector(5 downto 0);
+ O_reg0 : out std_logic_vector(5 downto 0)
+ O_reg1 : out std_logic_vector(5 downto 0)
+ O_reg2 : out std_logic_vector(5 downto 0)
+ O_reg3 : out std_logic_vector(5 downto 0)
+ O_reg4 : out std_logic_vector(5 downto 0)
+ O_reg5 : out std_logic_vector(5 downto 0)
+ );
+
+end registres;
+
+architecture a_registres of registres is
+
+begin
+
+ process (I_clk, I_rst)
+ begin
+ if I_rst = '1' then
+ O_reg0 <= (others => '0');
+ O_reg1 <= (others => '0');
+ O_reg2 <= (others => '0');
+ O_reg3 <= (others => '0');
+ O_reg4 <= (others => '0');
+ O_reg5 <= (others => '0');
+ elsif rising_edge(I_clk) then
+ if I_wr = '1' then
+ case adr is
+ when "000" => O_reg0 <= I_data;
+ when "001" => O_reg1 <= I_data;
+ when "010" => O_reg2 <= I_data;
+ when "011" => O_reg3 <= I_data;
+ when "100" => O_reg4 <= I_data;
+ when "101" => O_reg5 <= I_data;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process reg;
+
+end a_registres;
diff --git a/src/tirage.vhd b/src/tirage.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9e4563d57c261872f8b9b0190a9303ab363c4c32
--- /dev/null
+++ b/src/tirage.vhd
@@ -0,0 +1,166 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity tirage is
+
+ port (
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_clk_display : in std_logic;
+ I_bouton : in std_logic;
+ O_reg0 : out std_logic_vector(5 downto 0);
+ O_reg1 : out std_logic_vector(5 downto 0);
+ O_reg2 : out std_logic_vector(5 downto 0);
+ O_reg3 : out std_logic_vector(5 downto 0);
+ O_reg4 : out std_logic_vector(5 downto 0);
+ O_reg5 : out std_logic_vector(5 downto 0);
+ O_l_rouge : out std_logic
+ O_l_rouge : out std_logic
+ );
+
+end tirage;
+
+architecture a_tirage of tirage is
+
+ component automate is
+ port (
+ rst, clk : in std_logic;
+ clk_display, bouton, invalide, fin : in std_logic;
+ comptage : out std_logic;
+ enregistrement : out std_logic;
+ l_rouge : out std_logic;
+ l_verte : out std_logic
+ );
+ end component;
+
+
+ component registres is
+ port (
+ clk, rst : in std_logic;
+ enregistre : in std_logic;
+ adr : in std_logic_vector(2 downto 0);
+ numero_courant : in std_logic_vector(5 downto 0);
+ reg0, reg1, reg2, reg3, reg4, reg5 : out std_logic_vector(5 downto 0)
+ );
+ end component;
+
+ component compteur_valid is
+ port (
+ clk, rst, comptage : in std_logic;
+ adr : out std_logic_vector(2 downto 0);
+ fin : out std_logic
+ );
+ end component;
+
+
+ component comparateur is
+ port (
+ reg0, reg1, reg2, reg3, reg4 : in std_logic_vector(5 downto 0);
+ nombre_courant : in std_logic_vector(5 downto 0);
+ invalide : out std_logic
+ );
+ end component;
+
+
+ component compteur1_49 is
+ port (
+ clk, rst, comptage : in std_logic;
+ sortie : out std_logic_vector(5 downto 0)
+ );
+ end component;
+
+ component led_pwm is
+ port(
+ clk, rst : in std_logic;
+ ledR, ledV : in std_logic;
+ ledR_PWM, ledV_PWM : out std_logic
+ );
+ end component led_pwm;
+
+ signal recom, comptage : std_logic;
+ signal enregistrement, invalide, fin : std_logic;
+ signal adr : std_logic_vector(2 downto 0);
+ signal numero_courant, r0, r1, r2, r3, r4, r5 : std_logic_vector(5 downto 0);
+
+ signal l_V, l_R : std_logic;
+ signal cpt_leds, cpt_leds_reg : unsigned(4 downto 0);
+
+begin
+
+ automate_1 : entity work.automate
+ port map (
+ rst => rst,
+ clk => clk,
+ clk_display => clk_display,
+ bouton => bouton,
+ invalide => invalide,
+ fin => fin,
+ comptage => comptage,
+ enregistrement => enregistrement,
+ l_rouge => l_R,
+ l_verte => l_V
+ );
+
+ registres_1 : entity work.registres
+ port map (
+ clk => clk,
+ rst => rst,
+ enregistre => enregistrement,
+ adr => adr,
+ numero_courant => numero_courant,
+ reg0 => r0,
+ reg1 => r1,
+ reg2 => r2,
+ reg3 => r3,
+ reg4 => r4,
+ reg5 => r5
+ );
+
+ compteur_valid_1 : entity work.compteur_valid
+ port map (
+ clk => clk,
+ rst => rst,
+ comptage => enregistrement,
+ adr => adr,
+ fin => fin
+ );
+
+ comparateur_1 : entity work.comparateur
+ port map (
+ reg0 => r0,
+ reg1 => r1,
+ reg2 => r2,
+ reg3 => r3,
+ reg4 => r4,
+ nombre_courant => numero_courant,
+ invalide => invalide
+ );
+
+ compteur_1 : entity work.compteur1_49
+ port map (
+ clk => clk,
+ rst => rst,
+ comptage => comptage,
+ sortie => numero_courant
+ );
+
+
+ led_pwm_1 : entity work.led_pwm
+ port map (
+ clk => clk,
+ rst => rst,
+ ledR => l_R,
+ ledV => l_V,
+ ledR_PWM => l_rouge,
+ ledV_PWM => l_verte
+ );
+
+ reg0 <= r0;
+ reg1 <= r1;
+ reg2 <= r2;
+ reg3 <= r3;
+ reg4 <= r4;
+ reg5 <= r5;
+end a_tirage;
diff --git a/src/transcodeur7s_d_u.vhd b/src/transcodeur7s_d_u.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1ad932b12b7b448fdc4674eb5f0868b77d05989a
--- /dev/null
+++ b/src/transcodeur7s_d_u.vhd
@@ -0,0 +1,115 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+entity transcodeur7s_d_u is
+ port (
+ I_nombre : in std_logic_vector(5 downto 0);
+ O_uni : out std_logic_vector (6 downto 0);
+ O_diz : out std_logic_vector (6 downto 0)
+ );
+end transcodeur7s_d_u;
+
+architecture transcod_ARCH of transcodeur7s_d_u is
+
+ signal SC_u_nombre : unsigned(5 downto 0);
+ signal SC_u_uni : unsigned(5 downto 0);
+ signal SC_u_diz : unsigned(2 downto 0);
+
+begin
+
+ SC_u_nombre <= unsigned(I_nombre);
+
+ p_diz : process (SC_u_nombre) is
+ begin
+ if (SC_u_nombre < 10) then
+ SC_u_diz <= (others => '0');
+ SC_u_uni <= SC_u_nombre;
+ elsif SC_u_nombre < 20 then
+ SC_u_diz <= to_unsigned(1, 3);
+ SC_u_uni <= SC_u_nombre - 10;
+ elsif SC_u_nombre < 30 then
+ SC_u_diz <= to_unsigned(2, 3);
+ SC_u_uni <= SC_u_nombre - 20;
+ elsif SC_u_nombre < 40 then
+ SC_u_diz <= to_unsigned(3, 3);
+ SC_u_uni <= SC_u_nombre - 30;
+ else
+ SC_u_diz <= to_unsigned(4, 3);
+ SC_u_uni <= SC_u_nombre - 40;
+ end if;
+ end process p_diz;
+
+
+ p_7s_uni : process (SC_u_uni) is
+ begin
+ case to_integer(SC_u_uni) is
+ when 0 => O_uni <= "1000000";
+ when 1 => O_uni <= "1111001";
+ when 2 => O_uni <= "0100100";
+ when 3 => O_uni <= "0110000";
+ when 4 => O_uni <= "0011001";
+ when 5 => O_uni <= "0010010";
+ when 6 => O_uni <= "0000010";
+ when 7 => O_uni <= "1111000";
+ when 8 => O_uni <= "0000000";
+ when others => O_uni <= "0010000";
+ end case;
+ end process p_7s_uni;
+
+ p_7s_diz : process (SC_u_diz) is
+ begin
+ case to_integer(SC_u_diz) is
+ when 0 => O_diz <= "1000000";
+ when 1 => O_diz <= "1111001";
+ when 2 => O_diz <= "0100100";
+ when 3 => O_diz <= "0110000";
+ when others => O_diz <= "0011001";
+ end case;
+ end process p_7s_diz;
+
+
+
+end transcod_ARCH;
+
+architecture transcod_int of transcodeur7s_d_u is
+
+ signal uni_int : integer range 0 to 9;
+ signal diz_int : integer range 0 to 4;
+ signal num_int : integer range 0 to 49;
+
+begin
+
+
+ num_int <= to_integer(unsigned(nombre));
+ uni_int <= num_int rem 10;
+ diz_int <= num_int / 10;
+
+ transc_uni : process (uni_int) is
+ begin -- process transc_uni
+ case uni_int is
+ when 0 => S_uni <= "1000000";
+ when 1 => S_uni <= "1111001";
+ when 2 => S_uni <= "0100100";
+ when 3 => S_uni <= "0110000";
+ when 4 => S_uni <= "0011001";
+ when 5 => S_uni <= "0010010";
+ when 6 => S_uni <= "0000010";
+ when 7 => S_uni <= "1111000";
+ when 8 => S_uni <= "0000000";
+ when others => S_uni <= "0010000";
+ end case;
+ end process transc_uni;
+
+ transc_diz : process (diz_int) is
+ begin -- process transc_uni
+ case diz_int is
+ when 0 => S_diz <= "1000000";
+ when 1 => S_diz <= "1111001";
+ when 2 => S_diz <= "0100100";
+ when 3 => S_diz <= "0110000";
+ when others => S_diz <= "0011001";
+ end case;
+ end process transc_diz;
+
+end transcod_int;
diff --git a/src/transcodeur7s_u.vhd b/src/transcodeur7s_u.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..936844725f869b624aff1fa261d69b8e12eff358
--- /dev/null
+++ b/src/transcodeur7s_u.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity transcodeur7s_u is
+ port (E : in std_logic_vector(2 downto 0);
+ Suni : out std_logic_vector(6 downto 0));
+end transcodeur7s_u;
+
+architecture Behavioral of transcodeur7s_u is
+
+begin
+
+ P1 : process (E)
+
+ begin
+ case E is
+ when "000" => Suni <= "1000000";
+ when "001" => Suni <= "1111001";
+ when "010" => Suni <= "0100100";
+ when "011" => Suni <= "0110000";
+ when "100" => Suni <= "0011001";
+ when "101" => Suni <= "0010010";
+ when "110" => Suni <= "0000010";
+ when others => Suni <= "0000000";
+ end case;
+ end process;
+
+
+
+end Behavioral;