From f0b909ebdbcd847bab9e89202c3b53b81a924adb Mon Sep 17 00:00:00 2001
From: BAZIN Jean-Noel <jn.bazin@imt-atlantique.fr>
Date: Wed, 11 Oct 2023 16:59:48 +0200
Subject: [PATCH] remise au propre du code
---
src/Nexys4_Master.xdc | 98 ++++++++++++++++-----------------
src/automate.vhd | 12 ++--
src/compteur1_49.vhd | 2 +-
src/compteur_modulo6.vhd | 5 +-
src/diviseur_freq.vhd | 8 +--
src/led_pwm.vhd | 6 +-
src/loto.vhd | 112 +++++++++++++++++---------------------
src/loto_tb.vhd | 93 +++++++++++++++----------------
src/registres.vhd | 15 ++++-
src/tirage.vhd | 12 ++--
src/transcodeur7s_d_u.vhd | 105 +++++++++++++++--------------------
11 files changed, 225 insertions(+), 243 deletions(-)
diff --git a/src/Nexys4_Master.xdc b/src/Nexys4_Master.xdc
index ffcb724..c5210dd 100644
--- a/src/Nexys4_Master.xdc
+++ b/src/Nexys4_Master.xdc
@@ -1,78 +1,74 @@
##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
-set_property PACKAGE_PIN E16 [get_ports bouton]
-set_property IOSTANDARD LVCMOS33 [get_ports bouton]
+set_property PACKAGE_PIN E16 [get_ports I_bouton]
+set_property IOSTANDARD LVCMOS33 [get_ports I_bouton]
##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
-set_property PACKAGE_PIN P4 [get_ports bloque]
-set_property IOSTANDARD LVCMOS33 [get_ports bloque]
+set_property PACKAGE_PIN P4 [get_ports I_bloque]
+set_property IOSTANDARD LVCMOS33 [get_ports I_bloque]
## Clock signal
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
-set_property PACKAGE_PIN E3 [get_ports clk_100m]
-set_property IOSTANDARD LVCMOS33 [get_ports clk_100m]
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_100m]
+set_property PACKAGE_PIN E3 [get_ports I_clk_100m]
+set_property IOSTANDARD LVCMOS33 [get_ports I_clk_100m]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports I_clk_100m]
##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
-set_property PACKAGE_PIN V10 [get_ports rst]
-set_property IOSTANDARD LVCMOS33 [get_ports rst]
-
-
+set_property PACKAGE_PIN V10 [get_ports I_rst]
+set_property IOSTANDARD LVCMOS33 [get_ports I_rst]
+
+
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
-set_property PACKAGE_PIN K5 [get_ports rouge]
-set_property IOSTANDARD LVCMOS33 [get_ports rouge]
+set_property PACKAGE_PIN K5 [get_ports O_rouge]
+set_property IOSTANDARD LVCMOS33 [get_ports O_rouge]
##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
-set_property PACKAGE_PIN H6 [get_ports vert]
-set_property IOSTANDARD LVCMOS33 [get_ports vert]
+set_property PACKAGE_PIN H6 [get_ports O_vert]
+set_property IOSTANDARD LVCMOS33 [get_ports O_vert]
-#7 s_affment display
+#7 O_affment display
#Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
-set_property PACKAGE_PIN L3 [get_ports {s_aff[0]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[0]}]
+set_property PACKAGE_PIN L3 [get_ports {O_aff[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[0]}]
#Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
-set_property PACKAGE_PIN N1 [get_ports {s_aff[1]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[1]}]
+set_property PACKAGE_PIN N1 [get_ports {O_aff[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[1]}]
#Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
-set_property PACKAGE_PIN L5 [get_ports {s_aff[2]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[2]}]
+set_property PACKAGE_PIN L5 [get_ports {O_aff[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[2]}]
#Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
-set_property PACKAGE_PIN L4 [get_ports {s_aff[3]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[3]}]
+set_property PACKAGE_PIN L4 [get_ports {O_aff[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[3]}]
#Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
-set_property PACKAGE_PIN K3 [get_ports {s_aff[4]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[4]}]
+set_property PACKAGE_PIN K3 [get_ports {O_aff[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[4]}]
#Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
-set_property PACKAGE_PIN M2 [get_ports {s_aff[5]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[5]}]
+set_property PACKAGE_PIN M2 [get_ports {O_aff[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[5]}]
#Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
-set_property PACKAGE_PIN L6 [get_ports {s_aff[6]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {s_aff[6]}]
-
-##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
-#set_property PACKAGE_PIN M4 [get_ports dp]
-# set_property IOSTANDARD LVCMOS33 [get_ports dp]
+set_property PACKAGE_PIN L6 [get_ports {O_aff[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_aff[6]}]
#Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
-set_property PACKAGE_PIN N6 [get_ports {an[0]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+set_property PACKAGE_PIN N6 [get_ports {O_an[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[0]}]
#Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
-set_property PACKAGE_PIN M6 [get_ports {an[1]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+set_property PACKAGE_PIN M6 [get_ports {O_an[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[1]}]
#Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
-set_property PACKAGE_PIN M3 [get_ports {an[2]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+set_property PACKAGE_PIN M3 [get_ports {O_an[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[2]}]
#Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
-set_property PACKAGE_PIN N5 [get_ports {an[3]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+set_property PACKAGE_PIN N5 [get_ports {O_an[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[3]}]
#Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
-set_property PACKAGE_PIN N2 [get_ports {an[4]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
+set_property PACKAGE_PIN N2 [get_ports {O_an[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[4]}]
#Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
-set_property PACKAGE_PIN N4 [get_ports {an[5]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
+set_property PACKAGE_PIN N4 [get_ports {O_an[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[5]}]
#Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
-set_property PACKAGE_PIN L1 [get_ports {an[6]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
-#Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
-set_property PACKAGE_PIN M1 [get_ports {an[7]}]
- set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
\ No newline at end of file
+set_property PACKAGE_PIN L1 [get_ports {O_an[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[6]}]
+#Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
+set_property PACKAGE_PIN M1 [get_ports {O_an[7]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {O_an[7]}]
diff --git a/src/automate.vhd b/src/automate.vhd
index 6a539f6..4767f4e 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -7,6 +7,7 @@ entity automate is
port (
I_clk : in std_logic;
I_rst : in std_logic;
+ I_bouton : in std_logic;
I_clk_display : in std_logic;
I_bouton : in std_logic;
I_invalide : in std_logic;
@@ -29,16 +30,17 @@ architecture a_automate of automate is
st_fin_vert,
st_fin_rouge
);
- signal SR_ETAT : TYPE_ETAT;
+ signal ST_ETAT : TYPE_ETAT;
begin
- process (I_clk, I_rst)
+ UpdateState : process (I_clk, I_rst)
+
begin
if(I_rst = '1')then
__BLANK_TO_FILL__
- case SR_ETAT is
+ case ETAT is
when st_attente_succes =>
l_verte <= '1';
@@ -46,9 +48,9 @@ begin
comptage <= '0';
enregistrement <= '0';
if bouton = '1' then
- SR_ETAT <= st_comptage;
+ ST_ETAT <= st_comptage;
else
- SR_ETAT <= st_attente_succes;
+ ST_ETAT <= st_attente_succes;
end if;
when __BLANK_TO_FILL__
diff --git a/src/compteur1_49.vhd b/src/compteur1_49.vhd
index e24736c..f7f4b9e 100644
--- a/src/compteur1_49.vhd
+++ b/src/compteur1_49.vhd
@@ -35,6 +35,6 @@ begin
end if;
end process cpt;
- sortie <= std_logic_vector(SR_cpt_val);
+ O_sortie <= std_logic_vector(SR_cpt_val);
end compteur_a;
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index f0359a2..43420ce 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -21,11 +21,10 @@ architecture modulo6_a of compteur_modulo6 is
begin
mod6 : process (_BLANK_)
-
begin
- if rst = '1' then
+ if I_rst = '1' then
_BLANK_
- elsif rising_edge(clk) then
+ elsif rising_edge(I_clk) then
_BLANK_
end if;
end process mod6;
diff --git a/src/diviseur_freq.vhd b/src/diviseur_freq.vhd
index 12fe6d6..3054bac 100644
--- a/src/diviseur_freq.vhd
+++ b/src/diviseur_freq.vhd
@@ -21,16 +21,16 @@ architecture Behavioral of diviseur_freq is
begin
- process (I_clk, rst)
+ process (I_clk, I_rst)
begin
- if rst = '1' then
+ if I_rst = '1' then
compt <= (others => '0');
elsif rising_edge(I_clk) then
compt <= compt + 1;
end if;
end process;
- S_FAST <= compt(n_fast);
- S_SLOW <= compt(n_slow);
+ O_FAST <= compt(n_fast);
+ O_SLOW <= compt(n_slow);
end Behavioral;
diff --git a/src/led_pwm.vhd b/src/led_pwm.vhd
index 57cb5a2..d7729c3 100644
--- a/src/led_pwm.vhd
+++ b/src/led_pwm.vhd
@@ -22,12 +22,12 @@ architecture arch of led_pwm is
begin -- architecture arch
- leds_pwm : process (clk, rst) is
+ leds_pwm : process (I_clk, I_rst) is
begin
- if rst = '1' then
+ if I_rst = '1' then
SR_cpt_leds <= (others => '0');
SR_cpt_leds_reg <= (others => '0');
- elsif rising_edge(clk) then
+ elsif rising_edge(I_clk) then
SR_cpt_leds <= SR_cpt_leds + 1;
SR_cpt_leds_reg <= SR_cpt_leds;
end if;
diff --git a/src/loto.vhd b/src/loto.vhd
index 86d14ee..5e258b3 100644
--- a/src/loto.vhd
+++ b/src/loto.vhd
@@ -1,5 +1,3 @@
-
-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -18,10 +16,10 @@ entity loto is
O_vert : out std_logic;
O_an : out std_logic_vector(7 downto 0)
);
-
end entity loto;
architecture arch of loto is
+
component tirage is
port (
I_clk : in std_logic;
@@ -38,14 +36,13 @@ architecture arch of loto is
O_l_verte : out std_logic);
end component tirage;
- component modulo6 is
+ component compteur_modulo6 is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_enable : in std_logic;
- I_bloque : in std_logic;
- O_sortie : out std_logic_vector(2 downto 0));
- end component modulo6;
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ I_bloque : in std_logic;
+ O_CounterMod6 : out std_logic_vector(2 downto 0));
+ end component compteur_modulo6;
component diviseur_freq is
generic (
@@ -59,26 +56,26 @@ architecture arch of loto is
);
end component diviseur_freq;
- component mux6_1 is
- port (
- I_E0 : in std_logic_vector(5 downto 0);
- I_E1 : in std_logic_vector(5 downto 0);
- I_E2 : in std_logic_vector(5 downto 0);
- I_E3 : in std_logic_vector(5 downto 0);
- I_E4 : in std_logic_vector(5 downto 0);
- I_E5 : in std_logic_vector(5 downto 0);
- I_COMMANDE : in std_logic_vector(2 downto 0);
- O_S : out std_logic_vector(5 downto 0)
- );
- end component mux6_1;
-
- component transcodeur is
+ component transcodeur7s_d_u is
port (
I_nombre : in std_logic_vector(5 downto 0);
O_uni : out std_logic_vector (6 downto 0);
O_diz : out std_logic_vector (6 downto 0)
);
- end component transcodeur;
+ end component transcodeur7s_d_u;
+
+ component mux6_1 is
+ port (
+ I_0 : in std_logic_vector(5 downto 0);
+ I_1 : in std_logic_vector(5 downto 0);
+ I_2 : in std_logic_vector(5 downto 0);
+ I_3 : in std_logic_vector(5 downto 0);
+ I_4 : in std_logic_vector(5 downto 0);
+ I_5 : in std_logic_vector(5 downto 0);
+ I_sel : in std_logic_vector(2 downto 0);
+ O_mux6 : out std_logic_vector(5 downto 0)
+ );
+ end component mux6_1;
component decodeur_uni is
port (
@@ -89,12 +86,10 @@ architecture arch of loto is
component modulo4 is
port (
- I_clk : in std_logic;
- I_rst : in std_logic;
- I_enable : in std_logic;
- O_sortie : out std_logic_vector(1 downto 0);
- O_decod : out std_logic_vector(3 downto 0)
- );
+ I_clk : in std_logic;
+ I_rst : in std_logic;
+ O_Mod4 : out std_logic_vector(1 downto 0);
+ O_decod : out std_logic_vector(3 downto 0));
end component modulo4;
signal SC_clkDisplay : std_logic;
@@ -113,7 +108,7 @@ architecture arch of loto is
signal SC_numTranscode : std_logic_vector(6 downto 0);
signal SC_affSelect : std_logic_vector(1 downto 0);
-begin -- architecture arch
+begin
tirage_1 : entity work.tirage
port map (
@@ -133,10 +128,10 @@ begin -- architecture arch
modulo6_1 : entity work.compteur_modulo6
port map (
- I_clk => SC_clkDisplay,
- I_rst => I_rst,
- O_bloque => I_bloque,
- O_sortie => SC_num
+ I_clk => SC_clkDisplay,
+ I_rst => I_rst,
+ I_bloque => I_bloque,
+ O_CounterMod6 => SC_num
);
diviseur_freq_1 : entity work.diviseur_freq
@@ -152,37 +147,35 @@ begin -- architecture arch
mux6_1_1 : entity work.mux6_1
port map (
- E0 => SC_reg0,
- E1 => SC_reg1,
- E2 => SC_reg2,
- E3 => SC_reg3,
- E4 => SC_reg4,
- E5 => SC_reg5,
- COMMANDE => SC_num,
- S => SC_nombre
+ I_0 => SC_reg0,
+ I_1 => SC_reg1,
+ I_2 => SC_reg2,
+ I_3 => SC_reg3,
+ I_4 => SC_reg4,
+ I_5 => SC_reg5,
+ I_sel => SC_num,
+ O_mux6 => SC_nombre
);
-
transcod_1 : entity work.transcodeur7s_d_u(transcod_int) --(transcod_ARCH)
port map (
- S_uni => S_uni,
- nombre => nombre,
- S_diz => S_diz
+ I_nombre => SC_nombre,
+ O_uni => SC_uni,
+ O_diz => SC_diz
);
-
decodeur_uni_1 : entity work.transcodeur7s_u
port map (
E => SC_num,
Suni => SC_numTranscode
);
- modulo4_1 : entity work.modulo4
+ modulo4_2 : entity work.modulo4
port map (
- clk => clk,
- rst => rst,
- sortie => SC_affSelect,
- decod => an(3 downto 0)
+ I_clk => SC_clk,
+ I_rst => I_rst,
+ O_Mod4 => SC_affSelect,
+ O_decod => O_an(3 downto 0)
);
O_an(4) <= '1';
@@ -193,12 +186,9 @@ begin -- architecture arch
SC_minus <= "0111111";
with SC_affSelect select O_aff <=
- S_uni when "00",
- S_diz when "01",
- S_minus when "10",
- SC_numTranscode when "11";
-
-
-
+ SC_uni when "00",
+ SC_diz when "01",
+ SC_minus when "10",
+ SC_numTranscode when others;
end architecture arch;
diff --git a/src/loto_tb.vhd b/src/loto_tb.vhd
index dc87ab3..72d3fdb 100644
--- a/src/loto_tb.vhd
+++ b/src/loto_tb.vhd
@@ -1,22 +1,22 @@
--------------------------------------------------------------
-- Title : Testbench for design "loto"
--- Project :
+-- Project :
-------------------------------------------------------------------------------
-- File : loto_tb.vhd
-- Author : Matthieu Arzel <mattieu.arzel@imt-atlantique.fr>
--- Company :
+-- Company :
-- Created : 2018-06-14
--- Last update: 2018-06-14
--- Platform :
+-- Last update: 2023-10-11
+-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--- Description:
+-- Description:
-------------------------------------------------------------------------------
--- Copyright (c) 2018
+-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
--- 2018-06-14 1.0 marzel Created
+-- 2018-06-14 1.0 marzel Created
-------------------------------------------------------------------------------
library ieee;
@@ -32,57 +32,58 @@ end entity loto_tb;
architecture ar of loto_tb is
- -- component generics
- constant n_fast : natural := 0;
- constant n_slow : natural := 3;
+ -- component generics
+ constant n_fast : natural := 0;
+ constant n_slow : natural := 3;
- -- component ports
- signal bouton, bloque, clk_100m, rst : std_logic := '0';
- signal s_aff : std_logic_vector(6 downto 0);
- signal rouge, vert : std_logic;
- signal an : std_logic_vector(7 downto 0);
+ -- component ports
+ signal bouton, bloque, clk_100m, rst : std_logic := '0';
+ signal s_aff : std_logic_vector(6 downto 0);
+ signal rouge, vert : std_logic;
+ signal an : std_logic_vector(7 downto 0);
begin -- architecture ar
- -- component instantiation
- DUT: entity work.loto
- generic map (
- n_fast => n_fast,
- n_slow => n_slow)
- port map (
- bouton => bouton,
- bloque => bloque,
- clk_100m => clk_100m,
- rst => rst,
- s_aff => s_aff,
- rouge => rouge,
- vert => vert,
- an => an);
-
- -- clock generation
- clk_100m <= not clk_100m after 10 ns;
-
- bloque <='0';
- rst <= '0', '1' after 2 ns, '0' after 14 ns;
-
- bouton <= '0', '1' after 37 ns, '0' after 137 ns, '1' after 184 ns,
- '0' after 259 ns, '1' after 312 ns, '0' after 496 ns,
- '1' after 532 ns, '0' after 876 ns, '1' after 935 ns,
- '0' after 1023 ns, '1' after 1232 ns, '0' after 1543 ns,
- '1' after 1670 ns, '0' after 2450 ns, '1' after 2634 ns,
- '0' after 2872 ns, '1' after 3212 ns, '0' after 3398 ns;
-
-
+ -- component instantiation
+ DUT : entity work.loto
+ generic map (
+ n_fast => n_fast,
+ n_slow => n_slow)
+ port map (
+ I_bouton => bouton,
+ I_bloque => bloque,
+ I_clk_100m => clk_100m,
+ I_rst => rst,
+ O_aff => s_aff,
+ O_rouge => rouge,
+ O_vert => vert,
+ O_an => an
+ );
+
+ -- clock generation
+ clk_100m <= not clk_100m after 10 ns;
+
+ bloque <= '0';
+ rst <= '0', '1' after 2 ns, '0' after 14 ns;
+
+ bouton <= '0', '1' after 37 ns, '0' after 137 ns, '1' after 184 ns,
+ '0' after 259 ns, '1' after 312 ns, '0' after 496 ns,
+ '1' after 532 ns, '0' after 876 ns, '1' after 935 ns,
+ '0' after 1023 ns, '1' after 1232 ns, '0' after 1543 ns,
+ '1' after 1670 ns, '0' after 4523 ns, '1' after 6634 ns,
+ '0' after 7872 ns, '1' after 8212 ns, '0' after 8398 ns;
+
+
end architecture ar;
-------------------------------------------------------------------------------
configuration loto_tb_ar_cfg of loto_tb is
- for ar
- end for;
+ for ar
+ end for;
end loto_tb_ar_cfg;
-------------------------------------------------------------------------------
diff --git a/src/registres.vhd b/src/registres.vhd
index ea57aa6..8adf16b 100644
--- a/src/registres.vhd
+++ b/src/registres.vhd
@@ -35,7 +35,20 @@ begin
O_reg5 <= (others => '0');
elsif rising_edge(I_clk) then
if I_wr = '1' then
- case adr is
+ -- if I_adr = "000" then
+ -- O_reg0 <= I_data;
+ -- elsif I_adr = "001" then
+ -- O_reg1 <= I_data;
+ -- elsif I_adr = "010" then
+ -- O_reg2 <= I_data;
+ -- elsif I_adr = "011" then
+ -- O_reg3 <= I_data;
+ -- elsif I_adr = "100" then
+ -- O_reg4 <= I_data;
+ -- elsif I_adr = "101" then
+ -- O_reg5 <= I_data;
+ -- end if;
+ case I_adr is
when "000" => O_reg0 <= I_data;
when "001" => O_reg1 <= I_data;
when "010" => O_reg2 <= I_data;
diff --git a/src/tirage.vhd b/src/tirage.vhd
index 8349cc8..e91e462 100644
--- a/src/tirage.vhd
+++ b/src/tirage.vhd
@@ -135,12 +135,12 @@ begin
I_wr => SC_enregistrement,
I_adr => SC_adr,
I_data => SC_numero_courant,
- O_reg0 => O_Reg0,
- O_reg1 => O_Reg1,
- O_reg2 => O_Reg2,
- O_reg3 => O_Reg3,
- O_reg4 => O_Reg4,
- O_reg5 => O_Reg5
+ O_reg0 => SC_r0,
+ O_reg1 => SC_r1,
+ O_reg2 => SC_r2,
+ O_reg3 => SC_r3,
+ O_reg4 => SC_r4,
+ O_reg5 => SC_r5
);
diff --git a/src/transcodeur7s_d_u.vhd b/src/transcodeur7s_d_u.vhd
index 1ad932b..31fb0d1 100644
--- a/src/transcodeur7s_d_u.vhd
+++ b/src/transcodeur7s_d_u.vhd
@@ -41,75 +41,56 @@ begin
end process p_diz;
- p_7s_uni : process (SC_u_uni) is
- begin
- case to_integer(SC_u_uni) is
- when 0 => O_uni <= "1000000";
- when 1 => O_uni <= "1111001";
- when 2 => O_uni <= "0100100";
- when 3 => O_uni <= "0110000";
- when 4 => O_uni <= "0011001";
- when 5 => O_uni <= "0010010";
- when 6 => O_uni <= "0000010";
- when 7 => O_uni <= "1111000";
- when 8 => O_uni <= "0000000";
- when others => O_uni <= "0010000";
- end case;
- end process p_7s_uni;
-
- p_7s_diz : process (SC_u_diz) is
- begin
- case to_integer(SC_u_diz) is
- when 0 => O_diz <= "1000000";
- when 1 => O_diz <= "1111001";
- when 2 => O_diz <= "0100100";
- when 3 => O_diz <= "0110000";
- when others => O_diz <= "0011001";
- end case;
- end process p_7s_diz;
-
-
+ with to_integer(SC_u_uni) select O_uni <=
+ "1000000" when 0,
+ "1111001" when 1,
+ "0100100" when 2,
+ "0110000" when 3,
+ "0011001" when 4,
+ "0010010" when 5,
+ "0000010" when 6,
+ "1111000" when 7,
+ "0000000" when 8,
+ "0010000" when others;
+
+ with to_integer(SC_u_diz) select O_diz <=
+ "1000000" when 0,
+ "1111001" when 1,
+ "0100100" when 2,
+ "0110000" when 3,
+ "0011001" when others;
end transcod_ARCH;
architecture transcod_int of transcodeur7s_d_u is
- signal uni_int : integer range 0 to 9;
- signal diz_int : integer range 0 to 4;
- signal num_int : integer range 0 to 49;
+ signal SC_uni_int : integer range 0 to 9;
+ signal SC_diz_int : integer range 0 to 4;
+ signal SC_num_int : integer range 0 to 49;
begin
-
- num_int <= to_integer(unsigned(nombre));
- uni_int <= num_int rem 10;
- diz_int <= num_int / 10;
-
- transc_uni : process (uni_int) is
- begin -- process transc_uni
- case uni_int is
- when 0 => S_uni <= "1000000";
- when 1 => S_uni <= "1111001";
- when 2 => S_uni <= "0100100";
- when 3 => S_uni <= "0110000";
- when 4 => S_uni <= "0011001";
- when 5 => S_uni <= "0010010";
- when 6 => S_uni <= "0000010";
- when 7 => S_uni <= "1111000";
- when 8 => S_uni <= "0000000";
- when others => S_uni <= "0010000";
- end case;
- end process transc_uni;
-
- transc_diz : process (diz_int) is
- begin -- process transc_uni
- case diz_int is
- when 0 => S_diz <= "1000000";
- when 1 => S_diz <= "1111001";
- when 2 => S_diz <= "0100100";
- when 3 => S_diz <= "0110000";
- when others => S_diz <= "0011001";
- end case;
- end process transc_diz;
+ SC_num_int <= to_integer(unsigned(I_nombre));
+ SC_uni_int <= SC_num_int rem 10;
+ SC_diz_int <= SC_num_int / 10;
+
+ with SC_uni_int select O_uni <=
+ "1000000" when 0,
+ "1111001" when 1,
+ "0100100" when 2,
+ "0110000" when 3,
+ "0011001" when 4,
+ "0010010" when 5,
+ "0000010" when 6,
+ "1111000" when 7,
+ "0000000" when 8,
+ "0010000" when others;
+
+ with SC_diz_int select O_diz <=
+ "1000000" when 0,
+ "1111001" when 1,
+ "0100100" when 2,
+ "0110000" when 3,
+ "0011001" when others;
end transcod_int;
--
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