diff --git a/src/automate.vhd b/src/automate.vhd
index 75e4df53c189ee0c9ff1ad5df9df9f3690ec0e5e..03673519d98e74373455eef1fce76efc922592f1 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,6 +36,10 @@ begin
     process (I_clk, I_rst)
     begin
         if(I_rst = '1')then
+            O_counting     <= '0';
+            O_store        <= '0';
+            O_l_red        <= '0';
+            O_l_green      <= '1';
             SR_STATE <= st_wait_success;
             
         elsif rising_edge(I_clk)then
@@ -69,7 +73,7 @@ begin
                 
                     if I_invalide = '0' then
                         SR_STATE <= st_store;
-                    elsif I_invalide = '1' then
+                    else
                         SR_STATE <= st_wait_failed;
                     end if;
                     
@@ -81,7 +85,7 @@ begin
                 
                     if I_end = '1' then
                         SR_STATE <= st_end_red;
-                    elsif I_end = '0' then
+                    else
                         SR_STATE <= st_wait_success; 
                     end if;   
                     
@@ -105,7 +109,7 @@ begin
                         SR_STATE <= st_end_red;
                     end if;
                     
-               when st_wait_failed =>
+               when others =>
                     O_counting <= '0';
                     O_store    <= '0';
                     O_l_red    <= '1';
@@ -115,8 +119,6 @@ begin
                         SR_STATE <= st_counting;
                     end if;             
 
-               when others =>
-                    SR_STATE <= st_wait_success;
    
             end case;
         end if;
diff --git a/src/compteur_modulo4.vhd b/src/compteur_modulo4.vhd
index f2b951f07572fe0ebb6ed5fc58e6aaa9f185547b..c7d26dc03f3e61e1159f06be797fcd769b6da9e9 100644
--- a/src/compteur_modulo4.vhd
+++ b/src/compteur_modulo4.vhd
@@ -20,12 +20,12 @@ architecture modulo4_a of compteur_modulo4 is
 
 begin
 
-    mod4 : process (clk, rst)
+    mod4 : process (I_clk, I_rst)
 
     begin
-        if rst = '1' then
+        if I_rst = '1' then
             SR_Counter <= "00";
-        elsif rising_edge(clk) then
+        elsif rising_edge(I_clk) then
             if SR_Counter = "11" then
                 SR_Counter <= "00";
             else
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 74e4689562b58c20191ae65bd246abd9f4b9f743..df436b26389794e418e3363fc89551fbd565cb4f 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -29,7 +29,7 @@ begin
         
             if I_block = '0' then 
               SR_Counter <= SR_Counter + 1;
-                if SR_Counter = "111" then
+                if SR_Counter = "101" then
                     SR_Counter <= "000";
                 end if;
             else