From 7b2773a0e767b4dedab51752482b8483ea540990 Mon Sep 17 00:00:00 2001
From: Michelly LUIS LACERDA <m24luisl@fl-tp-br-603.imta.fr>
Date: Wed, 26 Feb 2025 10:34:57 +0100
Subject: [PATCH] tp fini
---
src/automate.vhd | 12 +++++++-----
src/compteur_modulo4.vhd | 6 +++---
src/compteur_modulo6.vhd | 2 +-
3 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/automate.vhd b/src/automate.vhd
index 75e4df5..0367351 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,6 +36,10 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
+ O_counting <= '0';
+ O_store <= '0';
+ O_l_red <= '0';
+ O_l_green <= '1';
SR_STATE <= st_wait_success;
elsif rising_edge(I_clk)then
@@ -69,7 +73,7 @@ begin
if I_invalide = '0' then
SR_STATE <= st_store;
- elsif I_invalide = '1' then
+ else
SR_STATE <= st_wait_failed;
end if;
@@ -81,7 +85,7 @@ begin
if I_end = '1' then
SR_STATE <= st_end_red;
- elsif I_end = '0' then
+ else
SR_STATE <= st_wait_success;
end if;
@@ -105,7 +109,7 @@ begin
SR_STATE <= st_end_red;
end if;
- when st_wait_failed =>
+ when others =>
O_counting <= '0';
O_store <= '0';
O_l_red <= '1';
@@ -115,8 +119,6 @@ begin
SR_STATE <= st_counting;
end if;
- when others =>
- SR_STATE <= st_wait_success;
end case;
end if;
diff --git a/src/compteur_modulo4.vhd b/src/compteur_modulo4.vhd
index f2b951f..c7d26dc 100644
--- a/src/compteur_modulo4.vhd
+++ b/src/compteur_modulo4.vhd
@@ -20,12 +20,12 @@ architecture modulo4_a of compteur_modulo4 is
begin
- mod4 : process (clk, rst)
+ mod4 : process (I_clk, I_rst)
begin
- if rst = '1' then
+ if I_rst = '1' then
SR_Counter <= "00";
- elsif rising_edge(clk) then
+ elsif rising_edge(I_clk) then
if SR_Counter = "11" then
SR_Counter <= "00";
else
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 74e4689..df436b2 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -29,7 +29,7 @@ begin
if I_block = '0' then
SR_Counter <= SR_Counter + 1;
- if SR_Counter = "111" then
+ if SR_Counter = "101" then
SR_Counter <= "000";
end if;
else
--
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