diff --git a/LOTO/LOTO.cache/sim/ssm.db b/LOTO/LOTO.cache/sim/ssm.db
new file mode 100644
index 0000000000000000000000000000000000000000..e6fa3388254d276398bb7ea9d47943902c3525a6
--- /dev/null
+++ b/LOTO/LOTO.cache/sim/ssm.db
@@ -0,0 +1,10 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Wed Feb 12 10:21:38 2025)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
diff --git a/LOTO/LOTO.cache/wt/project.wpc b/LOTO/LOTO.cache/wt/project.wpc
new file mode 100644
index 0000000000000000000000000000000000000000..9b342093142bd1b298b4af63bdebdead3a3ef56e
--- /dev/null
+++ b/LOTO/LOTO.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
diff --git a/LOTO/LOTO.cache/wt/synthesis.wdf b/LOTO/LOTO.cache/wt/synthesis.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..0e7e81d28fd1ccf3192f82abb99a31bf38cbc0c6
--- /dev/null
+++ b/LOTO/LOTO.cache/wt/synthesis.wdf
@@ -0,0 +1,52 @@
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diff --git a/LOTO/LOTO.cache/wt/synthesis_details.wdf b/LOTO/LOTO.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/LOTO/LOTO.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
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diff --git a/LOTO/LOTO.cache/wt/webtalk_pa.xml b/LOTO/LOTO.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..98af0dbcf8d00c05fc5cb79422cb6ef18b025115
--- /dev/null
+++ b/LOTO/LOTO.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Feb 12 11:54:19 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="f50fa2234be14825882bc86cf9c1e727" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/LOTO/LOTO.cache/wt/xsim.wdf b/LOTO/LOTO.cache/wt/xsim.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af
--- /dev/null
+++ b/LOTO/LOTO.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
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diff --git a/LOTO/LOTO.hw/LOTO.lpr b/LOTO/LOTO.hw/LOTO.lpr
new file mode 100644
index 0000000000000000000000000000000000000000..aa18adc095c6432a86aa8a7a331502559213b706
--- /dev/null
+++ b/LOTO/LOTO.hw/LOTO.lpr
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0">
+ <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/LOTO/LOTO.hw/hw_1/hw.xml b/LOTO/LOTO.hw/hw_1/hw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6007f734907eb2df84628274dc8bba4ed06a190b
--- /dev/null
+++ b/LOTO/LOTO.hw/hw_1/hw.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<hwsession version="1" minor="2">
+ <device name="xc7a100t_0" gui_info=""/>
+ <ObjectList object_type="hw_device" gui_info="">
+ <Object name="xc7a100t_0" gui_info="">
+ <Properties Property="FULL_PROBES.FILE" value=""/>
+ <Properties Property="PROBES.FILE" value=""/>
+ <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/loto.bit"/>
+ <Properties Property="SLR.COUNT" value="1"/>
+ </Object>
+ </ObjectList>
+ <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/LOTO/LOTO.ip_user_files/README.txt b/LOTO/LOTO.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/LOTO/LOTO.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/LOTO/LOTO.runs/.jobs/vrs_config_1.xml b/LOTO/LOTO.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6f1f46303ae90388b355136859d6ee25b1b84a55
--- /dev/null
+++ b/LOTO/LOTO.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/LOTO/LOTO.runs/impl_1/.Vivado_Implementation.queue.rst b/LOTO/LOTO.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.init_design.begin.rst b/LOTO/LOTO.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9ae6608217fbfe72b021a41e92905d94a3dd2f96
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23delau" Host="" Pid="55837">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.init_design.end.rst b/LOTO/LOTO.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.opt_design.begin.rst b/LOTO/LOTO.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9ae6608217fbfe72b021a41e92905d94a3dd2f96
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23delau" Host="" Pid="55837">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.opt_design.end.rst b/LOTO/LOTO.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.phys_opt_design.begin.rst b/LOTO/LOTO.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9ae6608217fbfe72b021a41e92905d94a3dd2f96
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23delau" Host="" Pid="55837">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.phys_opt_design.end.rst b/LOTO/LOTO.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.place_design.begin.rst b/LOTO/LOTO.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9ae6608217fbfe72b021a41e92905d94a3dd2f96
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23delau" Host="" Pid="55837">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.place_design.end.rst b/LOTO/LOTO.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.route_design.begin.rst b/LOTO/LOTO.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9ae6608217fbfe72b021a41e92905d94a3dd2f96
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23delau" Host="" Pid="55837">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.route_design.end.rst b/LOTO/LOTO.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.vivado.begin.rst b/LOTO/LOTO.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..35d13e91d3b07d47f1e098e1fea5c8af18aa2218
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="a23delau" Host="fl-tp-br-664" Pid="55765" HostCore="4" HostMemory="16258244">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.vivado.end.rst b/LOTO/LOTO.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/.write_bitstream.begin.rst b/LOTO/LOTO.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9ae6608217fbfe72b021a41e92905d94a3dd2f96
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="a23delau" Host="" Pid="55837">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/impl_1/.write_bitstream.end.rst b/LOTO/LOTO.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/impl_1/ISEWrap.js b/LOTO/LOTO.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/LOTO/LOTO.runs/impl_1/ISEWrap.sh b/LOTO/LOTO.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/LOTO/LOTO.runs/impl_1/clockInfo.txt b/LOTO/LOTO.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6311681612c81d68ddc77c675e935f2c948a275d
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.1
+| Date : Wed Feb 12 11:56:09 2025
+| Host : fl-tp-br-664
+| Design : design_1
+| Device : xc7a100t-csg324-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/LOTO/LOTO.runs/impl_1/gen_run.xml b/LOTO/LOTO.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..db1074b1783067f3d335e37f9073853b2bf5b771
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/gen_run.xml
@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1739357658">
+ <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS" Name="loto_postroute_physopted.rqs"/>
+ <File Type="ROUTE-RQS" Name="loto_routed.rqs"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BG-BGN" Name="loto.bgn"/>
+ <File Type="BITSTR-SYSDEF" Name="loto.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="loto.ltx"/>
+ <File Type="RBD_FILE" Name="loto.rbd"/>
+ <File Type="NPI_FILE" Name="loto.npi"/>
+ <File Type="RNPI_FILE" Name="loto.rnpi"/>
+ <File Type="CFI_FILE" Name="loto.cfi"/>
+ <File Type="RCFI_FILE" Name="loto.rcfi"/>
+ <File Type="PL-PDI-FILE" Name="loto_pld.pdi"/>
+ <File Type="BOOT-PDI-FILE" Name="loto_boot.pdi"/>
+ <File Type="RDI-RDI" Name="loto.vdi"/>
+ <File Type="PDI-FILE" Name="loto.pdi"/>
+ <File Type="BITSTR-MMI" Name="loto.mmi"/>
+ <File Type="BITSTR-BMM" Name="loto_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="loto.nky"/>
+ <File Type="BITSTR-RBT" Name="loto.rbt"/>
+ <File Type="BITSTR-MSK" Name="loto.msk"/>
+ <File Type="BG-BIN" Name="loto.bin"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+ <File Type="BG-BIT" Name="loto.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="loto_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="loto_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="loto_bus_skew_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="loto_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="loto_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="loto_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="loto_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="loto_postroute_physopt.dcp"/>
+ <File Type="BG-DRC" Name="loto.drc"/>
+ <File Type="ROUTE-RQS-PB" Name="loto_rqs_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="loto_bus_skew_routed.rpx"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="loto_bus_skew_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW" Name="loto_bus_skew_routed.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="loto_utilization_placed.pb"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="loto_methodology_drc_opted.rpt"/>
+ <File Type="PLACE-UTIL" Name="loto_utilization_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="loto_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-IO" Name="loto_io_placed.rpt"/>
+ <File Type="PHYSOPT-TIMING" Name="loto_timing_summary_physopted.rpt"/>
+ <File Type="PWROPT-DRC" Name="loto_drc_pwropted.rpt"/>
+ <File Type="PWROPT-TIMING" Name="loto_timing_summary_pwropted.rpt"/>
+ <File Type="OPT-DRC" Name="loto_drc_opted.rpt"/>
+ <File Type="PLACE-TIMING" Name="loto_timing_summary_placed.rpt"/>
+ <File Type="INIT-TIMING" Name="loto_timing_summary_init.rpt"/>
+ <File Type="PA-TCL" Name="loto.tcl"/>
+ <File Type="PLACE-CTRL" Name="loto_control_sets_placed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="loto_methodology_drc_routed.rpt"/>
+ <File Type="OPT-DCP" Name="loto_opt.dcp"/>
+ <File Type="OPT-RQA-PB" Name="loto_rqa_opted.pb"/>
+ <File Type="OPT-HWDEF" Name="loto.hwdef"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="loto_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="REPORTS-TCL" Name="loto_reports.tcl"/>
+ <File Type="OPT-TIMING" Name="loto_timing_summary_opted.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="loto_incremental_reuse_placed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="loto_methodology_drc_routed.pb"/>
+ <File Type="PLACE-DCP" Name="loto_placed.dcp"/>
+ <File Type="PLACE-RQA-PB" Name="loto_rqa_placed.pb"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="loto_incremental_reuse_pre_placed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="loto_drc_routed.rpx"/>
+ <File Type="PWROPT-DCP" Name="loto_pwropt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="loto_postplace_pwropt.dcp"/>
+ <File Type="PHYSOPT-DCP" Name="loto_physopt.dcp"/>
+ <File Type="PHYSOPT-DRC" Name="loto_drc_physopted.rpt"/>
+ <File Type="ROUTE-ERROR-DCP" Name="loto_routed_error.dcp"/>
+ <File Type="ROUTE-DCP" Name="loto_routed.dcp"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="loto_routed_bb.dcp"/>
+ <File Type="ROUTE-DRC" Name="loto_drc_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="loto_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="loto_drc_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="loto_power_routed.rpt"/>
+ <File Type="ROUTE-PWR-SUM" Name="loto_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR-RPX" Name="loto_power_routed.rpx"/>
+ <File Type="ROUTE-STATUS" Name="loto_route_status.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="loto_route_status.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="loto_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-TIMING-PB" Name="loto_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMING-RPX" Name="loto_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-SIMILARITY" Name="loto_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="loto_clock_utilization_routed.rpt"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/automate.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur1_49.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_valid.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/diviseur_freq.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/led_pwm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/registres.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/tirage.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_d_u.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/modulo4.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/loto.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo4.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_u.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+</GenRun>
diff --git a/LOTO/LOTO.runs/impl_1/htr.txt b/LOTO/LOTO.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0691ed231558a984358b398cd818739ae5a8c82a
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
diff --git a/LOTO/LOTO.runs/impl_1/init_design.pb b/LOTO/LOTO.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..66e8e296ffcd453808c8f8e9ddf711affc69405f
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/init_design.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto.bit b/LOTO/LOTO.runs/impl_1/loto.bit
new file mode 100644
index 0000000000000000000000000000000000000000..fd608aa9832e4c08e494c11edd2fdd5236cfe23f
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto.bit differ
diff --git a/LOTO/LOTO.runs/impl_1/loto.tcl b/LOTO/LOTO.runs/impl_1/loto.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..64527d8b30170f420dd9d893177f755200d9d908
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto.tcl
@@ -0,0 +1,313 @@
+namespace eval ::optrace {
+ variable script "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param checkpoint.writeSynthRtdsInDcp 1
+ set_param chipscope.maxJobs 1
+ set_param synth.incrementalSynthesisCache ./.Xil/Vivado-6007-fl-tp-br-664/incrSyn
+ set_param runs.launchOptions { -jobs 2 }
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7a100tcsg324-1
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.cache/wt [current_project]
+ set_property parent.project_path /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.xpr [current_project]
+ set_property ip_output_repo /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/loto.dcp
+OPTRACE "read constraints: implementation" START { }
+ read_xdc /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ link_design -top loto -part xc7a100tcsg324-1
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx" }
+ set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_io -file loto_io_placed.rpt" "report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb" "report_control_sets -verbose -file loto_control_sets_placed.rpt" }
+ set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+ create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+ phys_opt_design
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+ close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed phys_opt_design
+ return -code error $RESULT
+} else {
+ end_step phys_opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+ set_param project.isImplRun true
+ generate_parallel_reports -reports { "report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx" "report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx" "report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx" "report_route_status -file loto_route_status.rpt -pb loto_route_status.pb" "report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file loto_incremental_reuse_routed.rpt" "report_clock_utilization -file loto_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx" }
+ set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force loto_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+ write_checkpoint -force loto_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ catch { write_mem_info -force -no_partial_mmi loto.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force loto.bit
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force loto}
+ catch {file copy -force loto.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/LOTO/LOTO.runs/impl_1/loto.vdi b/LOTO/LOTO.runs/impl_1/loto.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..d32e0763d498ca3e335a614d43b1b548134c50f7
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto.vdi
@@ -0,0 +1,740 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:55:27 2025
+# Process ID: 55837
+# Current directory: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1
+# Command line: vivado -log loto.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+# Log file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.vdi
+# Journal file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-664
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3394.958 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16648 MB
+# Swap memory :4294 MB
+# Total Virtual :20943 MB
+# Available Virtual :16413 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1574.262 ; gain = 143.809 ; free physical = 6423 ; free virtual = 15130
+Command: link_design -top loto -part xc7a100tcsg324-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1933.391 ; gain = 0.000 ; free physical = 6041 ; free virtual = 14748
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2141.883 ; gain = 0.000 ; free physical = 5931 ; free virtual = 14641
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2141.883 ; gain = 567.621 ; free physical = 5931 ; free virtual = 14641
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2153.461 ; gain = 11.578 ; free physical = 5901 ; free virtual = 14611
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2653.289 ; gain = 499.828 ; free physical = 5453 ; free virtual = 14194
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 1 Initialization | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 2 Timer Update And Timing Data Collection | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Retarget | Checksum: 214b59dec
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Constant propagation | Checksum: 214b59dec
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Sweep | Checksum: 27dfe16e6
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+BUFG optimization | Checksum: 27dfe16e6
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Shift Register Optimization | Checksum: 27dfe16e6
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Post Processing Netlist | Checksum: 27dfe16e6
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 9 Finalization | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 0 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Ending Netlist Obfuscation Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+INFO: [Common 17-83] Releasing license: Implementation
+26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2966.125 ; gain = 824.242 ; free physical = 5130 ; free virtual = 13872
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+Command: report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5126 ; free virtual = 13869
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5126 ; free virtual = 13869
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5126 ; free virtual = 13869
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+Write Physdb Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5119 ; free virtual = 13863
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d3c97407
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5119 ; free virtual = 13863
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5119 ; free virtual = 13863
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1637776cc
+
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13857
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 229232f06
+
+Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13858
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 229232f06
+
+Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13858
+Phase 1 Placer Initialization | Checksum: 229232f06
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13858
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1951284e8
+
+Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19dd6cbc3
+
+Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 19dd6cbc3
+
+Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1f606059d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.86 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1f606059d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+Phase 2.4 Global Placement Core | Checksum: 246383a97
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+Phase 2 Global Placement | Checksum: 246383a97
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 246819dcf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fb19f5f2
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1a2ad0221
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 22f8f661d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1c7afcdaf
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 192e0fece
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 1c40322ca
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+Phase 3 Detail Placement | Checksum: 1c40322ca
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 246144c51
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=5.911 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 17b4bc2a7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 1cc767b81
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+Phase 4.1.1.1 BUFG Insertion | Checksum: 246144c51
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=5.911. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+Phase 4.1 Post Commit Optimization | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+Phase 4.3 Placer Reporting | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f16fc791
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+Ending Placer Task | Checksum: 17ca2ca6b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file loto_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file loto_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Write Physdb Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5062 ; free virtual = 13817
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 5.911 | TNS= 0.000 |
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5062 ; free virtual = 13817
+Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 3f758dcf ConstDB: 0 ShapeSum: 8b5add06 RouteDB: b1d25f96
+Post Restoration Checksum: NetGraph: cc74fed7 | NumContArr: 7897af87 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2ca5ea398
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.176 ; gain = 110.027 ; free physical = 4898 ; free virtual = 13655
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2ca5ea398
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.176 ; gain = 110.027 ; free physical = 4898 ; free virtual = 13655
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2ca5ea398
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.176 ; gain = 110.027 ; free physical = 4898 ; free virtual = 13655
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 2b0c90ab1
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4885 ; free virtual = 13643
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.765 | TNS=0.000 | WHS=-0.017 | THS=-0.162 |
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 4.35218e-05 %
+ Global Horizontal Routing Utilization = 0.000213129 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 165
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 163
+ Number of Partially Routed Nets = 2
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 2fc60a036
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 2fc60a036
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 1e5a8b0d8
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+Phase 4 Initial Routing | Checksum: 1e5a8b0d8
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 12
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.767 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Phase 5 Rip-up And Reroute | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Phase 6 Delay and Skew Optimization | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.767 | TNS=0.000 | WHS=0.093 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Phase 7 Post Hold Fix | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0203682 %
+ Global Horizontal Routing Utilization = 0.0458227 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 267fec3ed
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 267fec3ed
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=5.767 | TNS=0.000 | WHS=0.093 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 267fec3ed
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Total Elapsed time in route_design: 21.52 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 150960f3f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 150960f3f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+Command: report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+Command: report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 4 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file loto_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file loto_route_status.rpt -pb loto_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Command: report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+107 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file loto_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Wrote PlaceDB: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4886 ; free virtual = 13646
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4885 ; free virtual = 13645
+Write Physdb Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4885 ; free virtual = 13645
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_routed.dcp' has been generated.
+Command: write_bitstream -force loto.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./loto.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+118 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3497.434 ; gain = 280.945 ; free physical = 4541 ; free virtual = 13311
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:56:49 2025...
diff --git a/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.pb b/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.rpt b/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c7782f47b8a014674eef60fdb8b53d11890d335d
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:36 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx
+| Design : loto
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.rpx b/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..97b4bed5a4ebed62bb71885707d61511be5e9f51
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_bus_skew_routed.rpx differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_clock_utilization_routed.rpt b/LOTO/LOTO.runs/impl_1/loto_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..77f4ec27cc5472d1e30d3986546b223a8514e80c
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_clock_utilization_routed.rpt
@@ -0,0 +1,215 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:36 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_clock_utilization -file loto_clock_utilization_routed.rpt
+| Design : loto
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Local Clock Details
+5. Clock Regions: Key Resource Utilization
+6. Clock Regions : Global Clock Summary
+7. Device Cell Placement Summary for Global Clock g0
+8. Device Cell Placement Summary for Global Clock g1
+9. Clock Region Cell Placement per Global Clock: Region X0Y1
+10. Clock Region Cell Placement per Global Clock: Region X0Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 96 | 0 | 0 | 0 |
+| BUFIO | 0 | 24 | 0 | 0 | 0 |
+| BUFMR | 0 | 12 | 0 | 0 | 0 |
+| BUFR | 0 | 24 | 0 | 0 | 0 |
+| MMCM | 0 | 6 | 0 | 0 | 0 |
+| PLL | 0 | 6 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-----------------------------+----------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-----------------------------+----------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 60 | 1 | | | SC_clk_BUFG_inst/O | SC_clk_BUFG |
+| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 26 | 0 | 10.000 | sys_clk_pin | I_clk_100m_IBUF_BUFG_inst/O | I_clk_100m_IBUF_BUFG |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------------+-----------------------------+----------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+------------------------+
+| src0 | g0 | FDCE/Q | None | SLICE_X51Y97 | X0Y1 | 1 | 0 | | | diviseur_freq_1/SR_counter_reg[15]/Q | diviseur_freq_1/out[0] |
+| src1 | g1 | IBUF/O | IOB_X1Y126 | IOB_X1Y126 | X1Y2 | 1 | 0 | 10.000 | sys_clk_pin | I_clk_100m_IBUF_inst/O | I_clk_100m_IBUF |
++-----------+-----------+-----------------+------------+--------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Local Clock Details
+----------------------
+
++----------+-----------------+------------+-------------------+--------------+-------------+-----------------+--------------+-------+--------------------------------------+------------------------+
+| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++----------+-----------------+------------+-------------------+--------------+-------------+-----------------+--------------+-------+--------------------------------------+------------------------+
+| 0 | FDCE/Q | None | SLICE_X51Y100/BFF | X0Y2 | 3 | 3 | | | diviseur_freq_1/SR_counter_reg[25]/Q | diviseur_freq_1/out[1] |
++----------+-----------------+------------+-------------------+--------------+-------------+-----------------+--------------+-------+--------------------------------------+------------------------+
+* Local Clocks in this context represents only clocks driven by non-global buffers
+** Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+*** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+5. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 41 | 2000 | 11 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y2 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 48 | 2000 | 22 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+6. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y3 | 0 | 0 |
+| Y2 | 0 | 0 |
+| Y1 | 0 | 0 |
+| Y0 | 0 | 0 |
++----+----+----+
+
+
+7. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+| g0 | BUFG/O | n/a | | | | 61 | 0 | 0 | 0 | SC_clk_BUFG |
++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+-----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+-----+----+-----------------------+
+| Y3 | 0 | 0 | - |
+| Y2 | 46 | 0 | 0 |
+| Y1 | 15 | 0 | 0 |
+| Y0 | 0 | 0 | - |
++----+-----+----+-----------------------+
+
+
+8. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
+| g1 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | 26 | 0 | 0 | 0 | I_clk_100m_IBUF_BUFG |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+-----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+-----+----+-----------------------+
+| Y3 | 0 | 0 | - |
+| Y2 | 2 | 0 | 0 |
+| Y1 | 24 | 0 | 0 |
+| Y0 | 0 | 0 | - |
++----+-----+----+-----------------------+
+
+
+9. Clock Region Cell Placement per Global Clock: Region X0Y1
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+| g0 | n/a | BUFG/O | None | 14 | 1 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SC_clk_BUFG |
+| g1 | n/a | BUFG/O | None | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | I_clk_100m_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+10. Clock Region Cell Placement per Global Clock: Region X0Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+| g0 | n/a | BUFG/O | None | 46 | 0 | 46 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SC_clk_BUFG |
+| g1 | n/a | BUFG/O | None | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | I_clk_100m_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y0 [get_cells SC_clk_BUFG_inst]
+set_property LOC BUFGCTRL_X0Y16 [get_cells I_clk_100m_IBUF_BUFG_inst]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y126 [get_ports I_clk_100m]
+
+# Clock net "SC_clk_BUFG" driven by instance "SC_clk_BUFG_inst" located at site "BUFGCTRL_X0Y0"
+#startgroup
+create_pblock {CLKAG_SC_clk_BUFG}
+add_cells_to_pblock [get_pblocks {CLKAG_SC_clk_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="SC_clk_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_SC_clk_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}
+#endgroup
+
+# Clock net "I_clk_100m_IBUF_BUFG" driven by instance "I_clk_100m_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
+#startgroup
+create_pblock {CLKAG_I_clk_100m_IBUF_BUFG}
+add_cells_to_pblock [get_pblocks {CLKAG_I_clk_100m_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="I_clk_100m_IBUF_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_I_clk_100m_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}
+#endgroup
diff --git a/LOTO/LOTO.runs/impl_1/loto_control_sets_placed.rpt b/LOTO/LOTO.runs/impl_1/loto_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..898bf1a80322a1f5298445a7a46ad875a19bf5a8
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_control_sets_placed.rpt
@@ -0,0 +1,89 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:10 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_control_sets -verbose -file loto_control_sets_placed.rpt
+| Design : loto
+| Device : xc7a100t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 11 |
+| Minimum number of control sets | 11 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 31 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 11 |
+| >= 0 to < 4 | 2 |
+| >= 4 to < 6 | 0 |
+| >= 6 to < 8 | 7 |
+| >= 8 to < 10 | 0 |
+| >= 10 to < 12 | 0 |
+| >= 12 to < 14 | 0 |
+| >= 14 to < 16 | 1 |
+| >= 16 | 1 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 3 | 1 |
+| No | No | Yes | 44 | 12 |
+| No | Yes | No | 0 | 0 |
+| Yes | No | No | 0 | 0 |
+| Yes | No | Yes | 42 | 15 |
+| Yes | Yes | No | 0 | 0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++-------------------------+--------------------------------------------------+------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++-------------------------+--------------------------------------------------+------------------+------------------+----------------+--------------+
+| diviseur_freq_1/out[1] | | I_rst_IBUF | 1 | 3 | 3.00 |
+| SC_clk_BUFG | | | 1 | 3 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[2]_1[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/E[0] | I_rst_IBUF | 1 | 6 | 6.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[0]_1[0] | I_rst_IBUF | 4 | 6 | 1.50 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[1]_0[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[1]_1[0] | I_rst_IBUF | 1 | 6 | 6.00 |
+| SC_clk_BUFG | tirage_1/compteur_valid_1/SR_Counter_reg[2]_0[0] | I_rst_IBUF | 2 | 6 | 3.00 |
+| SC_clk_BUFG | tirage_1/automate_1/E[0] | I_rst_IBUF | 3 | 6 | 2.00 |
+| SC_clk_BUFG | | I_rst_IBUF | 4 | 15 | 3.75 |
+| I_clk_100m_IBUF_BUFG | | I_rst_IBUF | 7 | 26 | 3.71 |
++-------------------------+--------------------------------------------------+------------------+------------------+----------------+--------------+
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_drc_opted.pb b/LOTO/LOTO.runs/impl_1/loto_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_drc_opted.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpt b/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3632b3eac57b34700d3cea404785830ad1f0e658
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:07 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpx b/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..19b93ae59f3aadce0d167580f56b71b7679ac61e
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpx differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_drc_routed.pb b/LOTO/LOTO.runs/impl_1/loto_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_drc_routed.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpt b/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..99bf91039b718387706709c364e5ddf3ad2d79e1
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:35 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpx b/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..433ced1d950e8da2e0f5545e4ab06e472e48d209
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpx differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_io_placed.rpt b/LOTO/LOTO.runs/impl_1/loto_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..fbef07f7963e0e8d67c051427ecc213c3bc27867
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_io_placed.rpt
@@ -0,0 +1,366 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:11 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_io -file loto_io_placed.rpt
+| Design : loto
+| Device : xc7a100t
+| Speed File : -1
+| Package : csg324
+| Package Version : FINAL 2012-07-17
+| Package Pin Delay Version : VERS. 2.0 2012-07-17
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 21 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+----------------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+----------------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
+| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | I_clk_100m | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E16 | I_button | High Range | IO_L11N_T1_SRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | O_green | High Range | IO_L24P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | O_7segmentDisplay[4] | High Range | IO_L2P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| K5 | O_red | High Range | IO_L5P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L1 | O_7segmentSelect[6] | High Range | IO_L1P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | O_7segmentDisplay[0] | High Range | IO_L2N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L4 | O_7segmentDisplay[3] | High Range | IO_L5N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L5 | O_7segmentDisplay[2] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L6 | O_7segmentDisplay[6] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M1 | O_7segmentSelect[7] | High Range | IO_L1N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M2 | O_7segmentDisplay[5] | High Range | IO_L4N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M3 | O_7segmentSelect[2] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M6 | O_7segmentSelect[1] | High Range | IO_L18P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N1 | O_7segmentDisplay[1] | High Range | IO_L3N_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N2 | O_7segmentSelect[4] | High Range | IO_L3P_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| N4 | O_7segmentSelect[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N5 | O_7segmentSelect[3] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N6 | O_7segmentSelect[0] | High Range | IO_L18N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P4 | I_block | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
+| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V10 | I_rst | High Range | IO_L21P_T3_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
+| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
++------------+----------------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.pb b/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..f66a4238534222d6a9fd3a8e4ef5b4622c10c0a1
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpt b/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..784759a0f7f835e6e38753bc259f75a30adf5c80
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpt
@@ -0,0 +1,356 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:36 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 64
++-----------+------------------+-------------------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+------------------+-------------------------------+------------+
+| TIMING-17 | Critical Warning | Non-clocked sequential cell | 63 |
+| TIMING-18 | Warning | Missing input or output delay | 1 |
++-----------+------------------+-------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-17#1 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo4_2/SR_Counter_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#2 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo4_2/SR_Counter_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#3 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo6_1/SR_Counter_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#4 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo6_1/SR_Counter_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#5 Critical Warning
+Non-clocked sequential cell
+The clock pin modulo6_1/SR_Counter_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#6 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#7 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/FSM_sequential_SR_STATE_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#8 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#9 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_counting_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#10 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_l_green_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#11 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_l_red_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#12 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/automate_1/O_store_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#13 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#14 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#15 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#16 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#17 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#18 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_1/SR_cpt_val_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#19 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_valid_1/SR_Counter_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#20 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_valid_1/SR_Counter_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#21 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/compteur_valid_1/SR_Counter_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#22 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#23 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#24 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#25 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#26 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#27 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/led_pwm_1/SR_cpt_leds_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#28 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#29 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#30 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#31 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#32 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#33 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg0_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#34 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#35 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#36 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#37 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#38 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#39 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg1_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#40 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#41 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#42 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#43 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#44 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#45 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg2_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#46 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#47 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#48 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#49 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#50 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#51 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg3_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#52 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#53 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#54 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#55 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#56 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#57 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg4_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#58 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#59 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#60 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#61 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#62 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#63 Critical Warning
+Non-clocked sequential cell
+The clock pin tirage_1/registres_2/O_reg5_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-18#1 Warning
+Missing input or output delay
+An input delay is missing on I_rst relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpx b/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..bcf5891fdcdcb94c53c8805bb169f0919c7a6a32
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diff --git a/LOTO/LOTO.runs/impl_1/loto_opt.dcp b/LOTO/LOTO.runs/impl_1/loto_opt.dcp
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diff --git a/LOTO/LOTO.runs/impl_1/loto_physopt.dcp b/LOTO/LOTO.runs/impl_1/loto_physopt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..3de8c7e810d5155de1f03ebcb479cdb113e43ebd
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diff --git a/LOTO/LOTO.runs/impl_1/loto_placed.dcp b/LOTO/LOTO.runs/impl_1/loto_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..5d155fda00ef825c1bab5d23e83aaddc8cda70e9
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diff --git a/LOTO/LOTO.runs/impl_1/loto_power_routed.rpt b/LOTO/LOTO.runs/impl_1/loto_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..bdee281c137dae7ce07e2ec700ba7ead079a6646
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_power_routed.rpt
@@ -0,0 +1,148 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:36 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 0.132 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 0.035 |
+| Device Static (W) | 0.097 |
+| Effective TJA (C/W) | 4.6 |
+| Max Ambient (C) | 84.4 |
+| Junction Temperature (C) | 25.6 |
+| Confidence Level | Low |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks | <0.001 | 3 | --- | --- |
+| Slice Logic | <0.001 | 199 | --- | --- |
+| LUT as Logic | <0.001 | 73 | 63400 | 0.12 |
+| Register | <0.001 | 89 | 126800 | 0.07 |
+| CARRY4 | <0.001 | 7 | 15850 | 0.04 |
+| BUFG | <0.001 | 1 | 32 | 3.13 |
+| Others | 0.000 | 9 | --- | --- |
+| Signals | 0.001 | 165 | --- | --- |
+| I/O | 0.032 | 21 | 210 | 10.00 |
+| Static Power | 0.097 | | | |
+| Total | 0.132 | | | |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.018 | 0.003 | 0.015 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.019 | 0.001 | 0.018 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.013 | 0.009 | 0.004 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
+| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Low | | |
++-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 4.6 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------------+------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++-------------+------------+-----------------+
+| sys_clk_pin | I_clk_100m | 10.0 |
++-------------+------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++------------+-----------+
+| Name | Power (W) |
++------------+-----------+
+| loto | 0.035 |
+| tirage_1 | 0.001 |
++------------+-----------+
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_power_routed.rpx b/LOTO/LOTO.runs/impl_1/loto_power_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..ab132756f634355b07b9eebcd17849a4b1abfe73
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diff --git a/LOTO/LOTO.runs/impl_1/loto_power_summary_routed.pb b/LOTO/LOTO.runs/impl_1/loto_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..afc2030e126e637b24e62a96dfcb3f6f16e9e253
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diff --git a/LOTO/LOTO.runs/impl_1/loto_route_status.pb b/LOTO/LOTO.runs/impl_1/loto_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..0034f199fa1f1ff36696f979252c0acb5c961500
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_route_status.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_route_status.rpt b/LOTO/LOTO.runs/impl_1/loto_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..6030b4459ef947b873875f339697dbecd2e9b45f
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 243 :
+ # of nets not needing routing.......... : 74 :
+ # of internally routed nets........ : 74 :
+ # of routable nets..................... : 169 :
+ # of fully routed nets............. : 169 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_routed.dcp b/LOTO/LOTO.runs/impl_1/loto_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..714b422954b13127acf7aad1c27fc3cc27da9507
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diff --git a/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.pb b/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..563d9db7daae4ec36861dcbc899c1b4a76798700
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.rpt b/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..434dca0539a316aa093e7dd401d77b6913364243
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.rpt
@@ -0,0 +1,2879 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:36 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation
+| Design : loto
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+ Inter-SLR Compensation : Conservative
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule Severity Description Violations
+--------- ---------------- ----------------------------- ----------
+TIMING-17 Critical Warning Non-clocked sequential cell 63
+TIMING-18 Warning Missing input or output delay 1
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (63)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (165)
+5. checking no_input_delay (3)
+6. checking no_output_delay (13)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (63)
+-------------------------
+ There are 60 register/latch pins with no clock driven by root clock pin: diviseur_freq_1/SR_counter_reg[15]/Q (HIGH)
+
+ There are 3 register/latch pins with no clock driven by root clock pin: diviseur_freq_1/SR_counter_reg[25]/Q (HIGH)
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (165)
+--------------------------------------------------
+ There are 165 pins that are not constrained for maximum delay. (HIGH)
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (3)
+------------------------------
+ There are 3 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (13)
+--------------------------------
+ There are 13 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 5.769 0.000 0 26 0.095 0.000 0 26 4.500 0.000 0 27
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+sys_clk_pin {0.000 5.000} 10.000 100.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+sys_clk_pin 5.769 0.000 0 26 0.095 0.000 0 26 4.500 0.000 0 27
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock
+---------- ---------- --------
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock
+---------- ---------- --------
+(none)
+(none) sys_clk_pin
+(none) sys_clk_pin
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: sys_clk_pin
+ To Clock: sys_clk_pin
+
+Setup : 0 Failing Endpoints, Worst Slack 5.769ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 5.769ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[25]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 4.120ns (logic 1.639ns (39.784%) route 2.481ns (60.216%))
+ Logic Levels: 5 (BUFG=1 CARRY4=4)
+ Clock Path Skew: -0.138ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.918ns = ( 14.918 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.180ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.907 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.907 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X51Y99 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 9.021 r diviseur_freq_1/SR_counter_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.001 9.021 diviseur_freq_1/SR_counter_reg[20]_i_1_n_0
+ SLICE_X51Y100 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 9.355 r diviseur_freq_1/SR_counter_reg[24]_i_1/O[1]
+ net (fo=1, routed) 0.000 9.355 diviseur_freq_1/SR_counter_reg[24]_i_1_n_6
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.496 14.918 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ clock pessimism 0.180 15.098
+ clock uncertainty -0.035 15.063
+ SLICE_X51Y100 FDCE (Setup_fdce_C_D) 0.062 15.125 diviseur_freq_1/SR_counter_reg[25]
+ -------------------------------------------------------------------
+ required time 15.125
+ arrival time -9.355
+ -------------------------------------------------------------------
+ slack 5.769
+
+Slack (MET) : 5.880ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[24]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 4.009ns (logic 1.528ns (38.117%) route 2.481ns (61.883%))
+ Logic Levels: 5 (BUFG=1 CARRY4=4)
+ Clock Path Skew: -0.138ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.918ns = ( 14.918 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.180ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.907 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.907 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X51Y99 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 9.021 r diviseur_freq_1/SR_counter_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.001 9.021 diviseur_freq_1/SR_counter_reg[20]_i_1_n_0
+ SLICE_X51Y100 CARRY4 (Prop_carry4_CI_O[0])
+ 0.223 9.244 r diviseur_freq_1/SR_counter_reg[24]_i_1/O[0]
+ net (fo=1, routed) 0.000 9.244 diviseur_freq_1/SR_counter_reg[24]_i_1_n_7
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[24]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.496 14.918 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[24]/C
+ clock pessimism 0.180 15.098
+ clock uncertainty -0.035 15.063
+ SLICE_X51Y100 FDCE (Setup_fdce_C_D) 0.062 15.125 diviseur_freq_1/SR_counter_reg[24]
+ -------------------------------------------------------------------
+ required time 15.125
+ arrival time -9.244
+ -------------------------------------------------------------------
+ slack 5.880
+
+Slack (MET) : 5.997ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[21]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 4.005ns (logic 1.525ns (38.077%) route 2.480ns (61.923%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.907 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.907 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X51Y99 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 9.241 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[1]
+ net (fo=1, routed) 0.000 9.241 diviseur_freq_1/SR_counter_reg[20]_i_1_n_6
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[21]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[21]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y99 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[21]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.241
+ -------------------------------------------------------------------
+ slack 5.997
+
+Slack (MET) : 6.018ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[23]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.984ns (logic 1.504ns (37.751%) route 2.480ns (62.249%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.907 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.907 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X51Y99 CARRY4 (Prop_carry4_CI_O[3])
+ 0.313 9.220 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[3]
+ net (fo=1, routed) 0.000 9.220 diviseur_freq_1/SR_counter_reg[20]_i_1_n_4
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y99 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[23]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.220
+ -------------------------------------------------------------------
+ slack 6.018
+
+Slack (MET) : 6.092ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[22]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.910ns (logic 1.430ns (36.573%) route 2.480ns (63.427%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.907 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.907 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X51Y99 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 9.146 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[2]
+ net (fo=1, routed) 0.000 9.146 diviseur_freq_1/SR_counter_reg[20]_i_1_n_5
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[22]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[22]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y99 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[22]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.146
+ -------------------------------------------------------------------
+ slack 6.092
+
+Slack (MET) : 6.108ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[20]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.894ns (logic 1.414ns (36.312%) route 2.480ns (63.688%))
+ Logic Levels: 4 (BUFG=1 CARRY4=3)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 8.907 r diviseur_freq_1/SR_counter_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.907 diviseur_freq_1/SR_counter_reg[16]_i_1_n_0
+ SLICE_X51Y99 CARRY4 (Prop_carry4_CI_O[0])
+ 0.223 9.130 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[0]
+ net (fo=1, routed) 0.000 9.130 diviseur_freq_1/SR_counter_reg[20]_i_1_n_7
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[20]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[20]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y99 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[20]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.130
+ -------------------------------------------------------------------
+ slack 6.108
+
+Slack (MET) : 6.111ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[17]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.891ns (logic 1.411ns (36.263%) route 2.480ns (63.737%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_O[1])
+ 0.334 9.127 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[1]
+ net (fo=1, routed) 0.000 9.127 diviseur_freq_1/SR_counter_reg[16]_i_1_n_6
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[17]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y98 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[17]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.127
+ -------------------------------------------------------------------
+ slack 6.111
+
+Slack (MET) : 6.132ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[19]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.870ns (logic 1.390ns (35.917%) route 2.480ns (64.083%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_O[3])
+ 0.313 9.106 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[3]
+ net (fo=1, routed) 0.000 9.106 diviseur_freq_1/SR_counter_reg[16]_i_1_n_4
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y98 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[19]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.106
+ -------------------------------------------------------------------
+ slack 6.132
+
+Slack (MET) : 6.206ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[18]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.796ns (logic 1.316ns (34.668%) route 2.480ns (65.332%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 9.032 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[2]
+ net (fo=1, routed) 0.000 9.032 diviseur_freq_1/SR_counter_reg[16]_i_1_n_5
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[18]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y98 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[18]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.032
+ -------------------------------------------------------------------
+ slack 6.206
+
+Slack (MET) : 6.222ns (required time - arrival time)
+ Source: diviseur_freq_1/SR_counter_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[16]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 10.000ns (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 3.780ns (logic 1.300ns (34.391%) route 2.480ns (65.609%))
+ Logic Levels: 3 (BUFG=1 CARRY4=2)
+ Clock Path Skew: -0.025ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.935ns = ( 14.935 - 10.000 )
+ Source Clock Delay (SCD): 5.236ns
+ Clock Pessimism Removal (CPR): 0.276ns
+ Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.633 5.236 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.456 5.692 r diviseur_freq_1/SR_counter_reg[15]/Q
+ net (fo=1, routed) 0.698 6.390 SC_clk
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 6.486 r SC_clk_BUFG_inst/O
+ net (fo=61, routed) 1.782 8.268 diviseur_freq_1/CLK
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.525 8.793 r diviseur_freq_1/SR_counter_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 8.793 diviseur_freq_1/SR_counter_reg[12]_i_1_n_0
+ SLICE_X51Y98 CARRY4 (Prop_carry4_CI_O[0])
+ 0.223 9.016 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[0]
+ net (fo=1, routed) 0.000 9.016 diviseur_freq_1/SR_counter_reg[16]_i_1_n_7
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[16]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 10.000 10.000 r
+ E3 0.000 10.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 10.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 13.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.512 14.935 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[16]/C
+ clock pessimism 0.276 15.211
+ clock uncertainty -0.035 15.175
+ SLICE_X51Y98 FDCE (Setup_fdce_C_D) 0.062 15.237 diviseur_freq_1/SR_counter_reg[16]
+ -------------------------------------------------------------------
+ required time 15.237
+ arrival time -9.016
+ -------------------------------------------------------------------
+ slack 6.222
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.095ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[23]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[24]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.464ns (logic 0.355ns (76.531%) route 0.109ns (23.469%))
+ Logic Levels: 2 (CARRY4=2)
+ Clock Path Skew: 0.264ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.995ns
+ Source Clock Delay (SCD): 1.485ns
+ Clock Pessimism Removal (CPR): 0.245ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.566 1.485 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y99 FDCE (Prop_fdce_C_Q) 0.141 1.626 r diviseur_freq_1/SR_counter_reg[23]/Q
+ net (fo=1, routed) 0.108 1.735 diviseur_freq_1/SR_counter_reg_n_0_[23]
+ SLICE_X51Y99 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.160 1.895 r diviseur_freq_1/SR_counter_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.001 1.895 diviseur_freq_1/SR_counter_reg[20]_i_1_n_0
+ SLICE_X51Y100 CARRY4 (Prop_carry4_CI_O[0])
+ 0.054 1.949 r diviseur_freq_1/SR_counter_reg[24]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.949 diviseur_freq_1/SR_counter_reg[24]_i_1_n_7
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[24]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.830 1.995 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[24]/C
+ clock pessimism -0.245 1.749
+ SLICE_X51Y100 FDCE (Hold_fdce_C_D) 0.105 1.854 diviseur_freq_1/SR_counter_reg[24]
+ -------------------------------------------------------------------
+ required time -1.854
+ arrival time 1.949
+ -------------------------------------------------------------------
+ slack 0.095
+
+Slack (MET) : 0.131ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[23]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[25]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.500ns (logic 0.391ns (78.221%) route 0.109ns (21.779%))
+ Logic Levels: 2 (CARRY4=2)
+ Clock Path Skew: 0.264ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.995ns
+ Source Clock Delay (SCD): 1.485ns
+ Clock Pessimism Removal (CPR): 0.245ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.566 1.485 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y99 FDCE (Prop_fdce_C_Q) 0.141 1.626 r diviseur_freq_1/SR_counter_reg[23]/Q
+ net (fo=1, routed) 0.108 1.735 diviseur_freq_1/SR_counter_reg_n_0_[23]
+ SLICE_X51Y99 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.160 1.895 r diviseur_freq_1/SR_counter_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.001 1.895 diviseur_freq_1/SR_counter_reg[20]_i_1_n_0
+ SLICE_X51Y100 CARRY4 (Prop_carry4_CI_O[1])
+ 0.090 1.985 r diviseur_freq_1/SR_counter_reg[24]_i_1/O[1]
+ net (fo=1, routed) 0.000 1.985 diviseur_freq_1/SR_counter_reg[24]_i_1_n_6
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.830 1.995 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ clock pessimism -0.245 1.749
+ SLICE_X51Y100 FDCE (Hold_fdce_C_D) 0.105 1.854 diviseur_freq_1/SR_counter_reg[25]
+ -------------------------------------------------------------------
+ required time -1.854
+ arrival time 1.985
+ -------------------------------------------------------------------
+ slack 0.131
+
+Slack (MET) : 0.252ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[11]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[11]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.357ns (logic 0.249ns (69.714%) route 0.108ns (30.286%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I16
+ SLICE_X51Y96 FDCE r diviseur_freq_1/SR_counter_reg[11]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y96 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[11]/Q
+ net (fo=1, routed) 0.108 1.734 diviseur_freq_1/SR_counter_reg_n_0_[11]
+ SLICE_X51Y96 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.842 r diviseur_freq_1/SR_counter_reg[8]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.842 diviseur_freq_1/SR_counter_reg[8]_i_1_n_4
+ SLICE_X51Y96 FDCE r diviseur_freq_1/SR_counter_reg[11]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I16
+ SLICE_X51Y96 FDCE r diviseur_freq_1/SR_counter_reg[11]/C
+ clock pessimism -0.515 1.484
+ SLICE_X51Y96 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[11]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.842
+ -------------------------------------------------------------------
+ slack 0.252
+
+Slack (MET) : 0.252ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[19]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[19]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.357ns (logic 0.249ns (69.714%) route 0.108ns (30.286%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 1.485ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.566 1.485 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y98 FDCE (Prop_fdce_C_Q) 0.141 1.626 r diviseur_freq_1/SR_counter_reg[19]/Q
+ net (fo=1, routed) 0.108 1.735 diviseur_freq_1/SR_counter_reg_n_0_[19]
+ SLICE_X51Y98 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.843 r diviseur_freq_1/SR_counter_reg[16]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.843 diviseur_freq_1/SR_counter_reg[16]_i_1_n_4
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+ clock pessimism -0.515 1.485
+ SLICE_X51Y98 FDCE (Hold_fdce_C_D) 0.105 1.590 diviseur_freq_1/SR_counter_reg[19]
+ -------------------------------------------------------------------
+ required time -1.590
+ arrival time 1.843
+ -------------------------------------------------------------------
+ slack 0.252
+
+Slack (MET) : 0.252ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[23]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[23]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.357ns (logic 0.249ns (69.714%) route 0.108ns (30.286%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 1.485ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.566 1.485 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y99 FDCE (Prop_fdce_C_Q) 0.141 1.626 r diviseur_freq_1/SR_counter_reg[23]/Q
+ net (fo=1, routed) 0.108 1.735 diviseur_freq_1/SR_counter_reg_n_0_[23]
+ SLICE_X51Y99 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.843 r diviseur_freq_1/SR_counter_reg[20]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.843 diviseur_freq_1/SR_counter_reg[20]_i_1_n_4
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[23]/C
+ clock pessimism -0.515 1.485
+ SLICE_X51Y99 FDCE (Hold_fdce_C_D) 0.105 1.590 diviseur_freq_1/SR_counter_reg[23]
+ -------------------------------------------------------------------
+ required time -1.590
+ arrival time 1.843
+ -------------------------------------------------------------------
+ slack 0.252
+
+Slack (MET) : 0.252ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[3]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.357ns (logic 0.249ns (69.714%) route 0.108ns (30.286%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I16
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y94 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[3]/Q
+ net (fo=1, routed) 0.108 1.734 diviseur_freq_1/SR_counter_reg_n_0_[3]
+ SLICE_X51Y94 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.842 r diviseur_freq_1/SR_counter_reg[0]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.842 diviseur_freq_1/SR_counter_reg[0]_i_1_n_4
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I16
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[3]/C
+ clock pessimism -0.515 1.484
+ SLICE_X51Y94 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[3]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.842
+ -------------------------------------------------------------------
+ slack 0.252
+
+Slack (MET) : 0.252ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.357ns (logic 0.249ns (69.714%) route 0.108ns (30.286%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y95 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[7]/Q
+ net (fo=1, routed) 0.108 1.734 diviseur_freq_1/SR_counter_reg_n_0_[7]
+ SLICE_X51Y95 CARRY4 (Prop_carry4_S[3]_O[3])
+ 0.108 1.842 r diviseur_freq_1/SR_counter_reg[4]_i_1/O[3]
+ net (fo=1, routed) 0.000 1.842 diviseur_freq_1/SR_counter_reg[4]_i_1_n_4
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[7]/C
+ clock pessimism -0.515 1.484
+ SLICE_X51Y95 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[7]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.842
+ -------------------------------------------------------------------
+ slack 0.252
+
+Slack (MET) : 0.256ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.361ns (logic 0.256ns (70.880%) route 0.105ns (29.120%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y95 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[4]/Q
+ net (fo=1, routed) 0.105 1.731 diviseur_freq_1/SR_counter_reg_n_0_[4]
+ SLICE_X51Y95 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.115 1.846 r diviseur_freq_1/SR_counter_reg[4]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.846 diviseur_freq_1/SR_counter_reg[4]_i_1_n_7
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[4]/C
+ clock pessimism -0.515 1.484
+ SLICE_X51Y95 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[4]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.846
+ -------------------------------------------------------------------
+ slack 0.256
+
+Slack (MET) : 0.256ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[8]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[8]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.361ns (logic 0.256ns (70.880%) route 0.105ns (29.120%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.000ns
+ Source Clock Delay (SCD): 1.484ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.565 1.484 diviseur_freq_1/I16
+ SLICE_X51Y96 FDCE r diviseur_freq_1/SR_counter_reg[8]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y96 FDCE (Prop_fdce_C_Q) 0.141 1.625 r diviseur_freq_1/SR_counter_reg[8]/Q
+ net (fo=1, routed) 0.105 1.731 diviseur_freq_1/SR_counter_reg_n_0_[8]
+ SLICE_X51Y96 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.115 1.846 r diviseur_freq_1/SR_counter_reg[8]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.846 diviseur_freq_1/SR_counter_reg[8]_i_1_n_7
+ SLICE_X51Y96 FDCE r diviseur_freq_1/SR_counter_reg[8]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.835 2.000 diviseur_freq_1/I16
+ SLICE_X51Y96 FDCE r diviseur_freq_1/SR_counter_reg[8]/C
+ clock pessimism -0.515 1.484
+ SLICE_X51Y96 FDCE (Hold_fdce_C_D) 0.105 1.589 diviseur_freq_1/SR_counter_reg[8]
+ -------------------------------------------------------------------
+ required time -1.589
+ arrival time 1.846
+ -------------------------------------------------------------------
+ slack 0.256
+
+Slack (MET) : 0.256ns (arrival time - required time)
+ Source: diviseur_freq_1/SR_counter_reg[12]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: diviseur_freq_1/SR_counter_reg[12]/D
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: sys_clk_pin
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+ Data Path Delay: 0.361ns (logic 0.256ns (70.880%) route 0.105ns (29.120%))
+ Logic Levels: 1 (CARRY4=1)
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 1.485ns
+ Clock Pessimism Removal (CPR): 0.515ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.566 1.485 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[12]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y97 FDCE (Prop_fdce_C_Q) 0.141 1.626 r diviseur_freq_1/SR_counter_reg[12]/Q
+ net (fo=1, routed) 0.105 1.732 diviseur_freq_1/SR_counter_reg_n_0_[12]
+ SLICE_X51Y97 CARRY4 (Prop_carry4_S[0]_O[0])
+ 0.115 1.847 r diviseur_freq_1/SR_counter_reg[12]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.847 diviseur_freq_1/SR_counter_reg[12]_i_1_n_7
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[12]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[12]/C
+ clock pessimism -0.515 1.485
+ SLICE_X51Y97 FDCE (Hold_fdce_C_D) 0.105 1.590 diviseur_freq_1/SR_counter_reg[12]
+ -------------------------------------------------------------------
+ required time -1.590
+ arrival time 1.847
+ -------------------------------------------------------------------
+ slack 0.256
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: sys_clk_pin
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { I_clk_100m }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y16 I_clk_100m_IBUF_BUFG_inst/I
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y94 diviseur_freq_1/SR_counter_reg[0]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[10]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[11]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[12]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[13]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[14]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[15]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y98 diviseur_freq_1/SR_counter_reg[16]/C
+Min Period n/a FDCE/C n/a 1.000 10.000 9.000 SLICE_X51Y98 diviseur_freq_1/SR_counter_reg[17]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y94 diviseur_freq_1/SR_counter_reg[0]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y94 diviseur_freq_1/SR_counter_reg[0]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[10]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[10]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[11]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[11]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[12]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[12]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[13]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[13]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y94 diviseur_freq_1/SR_counter_reg[0]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y94 diviseur_freq_1/SR_counter_reg[0]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[10]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[10]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[11]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y96 diviseur_freq_1/SR_counter_reg[11]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[12]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[12]/C
+High Pulse Width Slow FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[13]/C
+High Pulse Width Fast FDCE/C n/a 0.500 5.000 4.500 SLICE_X51Y97 diviseur_freq_1/SR_counter_reg[13]/C
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock:
+ To Clock:
+
+Max Delay 178 Endpoints
+Min Delay 178 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[1]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.519ns (logic 4.672ns (40.558%) route 6.847ns (59.442%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[1]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[1]/Q
+ net (fo=20, routed) 1.523 1.979 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2
+ SLICE_X47Y101 LUT6 (Prop_lut6_I2_O) 0.124 2.103 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_17/O
+ net (fo=1, routed) 0.426 2.528 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_17_n_0
+ SLICE_X46Y99 LUT6 (Prop_lut6_I0_O) 0.124 2.652 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 0.643 3.295 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X47Y98 LUT5 (Prop_lut5_I4_O) 0.118 3.413 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5/O
+ net (fo=3, routed) 1.222 4.636 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5_n_0
+ SLICE_X49Y97 LUT6 (Prop_lut6_I2_O) 0.326 4.962 r tirage_1/registres_2/O_7segmentDisplay_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.034 7.995 O_7segmentDisplay_OBUF[3]
+ L4 OBUF (Prop_obuf_I_O) 3.524 11.519 r O_7segmentDisplay_OBUF[3]_inst/O
+ net (fo=0) 0.000 11.519 O_7segmentDisplay[3]
+ L4 r O_7segmentDisplay[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.397ns (logic 4.474ns (39.256%) route 6.923ns (60.744%))
+ Logic Levels: 6 (FDCE=1 LUT6=4 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[0]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[0]/Q
+ net (fo=20, routed) 1.263 1.719 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2_0
+ SLICE_X46Y101 LUT6 (Prop_lut6_I4_O) 0.124 1.843 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_7/O
+ net (fo=1, routed) 0.608 2.452 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_7_n_0
+ SLICE_X46Y99 LUT6 (Prop_lut6_I0_O) 0.124 2.576 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2/O
+ net (fo=7, routed) 0.935 3.511 tirage_1/registres_2/SR_Counter_reg[1]
+ SLICE_X46Y97 LUT6 (Prop_lut6_I5_O) 0.124 3.635 r tirage_1/registres_2/O_7segmentDisplay_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.941 4.576 tirage_1/registres_2/O_7segmentDisplay_OBUF[0]_inst_i_2_n_0
+ SLICE_X49Y97 LUT6 (Prop_lut6_I3_O) 0.124 4.700 r tirage_1/registres_2/O_7segmentDisplay_OBUF[0]_inst_i_1/O
+ net (fo=1, routed) 3.175 7.875 O_7segmentDisplay_OBUF[0]
+ L3 OBUF (Prop_obuf_I_O) 3.522 11.397 r O_7segmentDisplay_OBUF[0]_inst/O
+ net (fo=0) 0.000 11.397 O_7segmentDisplay[0]
+ L3 r O_7segmentDisplay[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[1]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[2]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.380ns (logic 4.698ns (41.284%) route 6.682ns (58.716%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[1]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[1]/Q
+ net (fo=20, routed) 1.175 1.631 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2
+ SLICE_X47Y101 LUT6 (Prop_lut6_I2_O) 0.124 1.755 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_15/O
+ net (fo=1, routed) 0.451 2.206 modulo6_1/O_7segmentDisplay_OBUF[6]_inst_i_6_1
+ SLICE_X47Y99 LUT6 (Prop_lut6_I4_O) 0.124 2.330 r modulo6_1/O_7segmentDisplay_OBUF[6]_inst_i_9/O
+ net (fo=12, routed) 1.148 3.479 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_1_2
+ SLICE_X46Y97 LUT5 (Prop_lut5_I2_O) 0.153 3.632 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_3/O
+ net (fo=3, routed) 0.517 4.148 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_3_n_0
+ SLICE_X47Y97 LUT6 (Prop_lut6_I0_O) 0.331 4.479 r tirage_1/registres_2/O_7segmentDisplay_OBUF[2]_inst_i_1/O
+ net (fo=1, routed) 3.391 7.870 O_7segmentDisplay_OBUF[2]
+ L5 OBUF (Prop_obuf_I_O) 3.510 11.380 r O_7segmentDisplay_OBUF[2]_inst/O
+ net (fo=0) 0.000 11.380 O_7segmentDisplay[2]
+ L5 r O_7segmentDisplay[2] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[1]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[6]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.348ns (logic 4.671ns (41.161%) route 6.677ns (58.839%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[1]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[1]/Q
+ net (fo=20, routed) 1.523 1.979 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2
+ SLICE_X47Y101 LUT6 (Prop_lut6_I2_O) 0.124 2.103 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_17/O
+ net (fo=1, routed) 0.426 2.528 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_17_n_0
+ SLICE_X46Y99 LUT6 (Prop_lut6_I0_O) 0.124 2.652 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 0.643 3.295 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X47Y98 LUT5 (Prop_lut5_I4_O) 0.118 3.413 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5/O
+ net (fo=3, routed) 1.033 4.446 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_5_n_0
+ SLICE_X48Y97 LUT6 (Prop_lut6_I4_O) 0.326 4.772 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_1/O
+ net (fo=1, routed) 3.053 7.825 O_7segmentDisplay_OBUF[6]
+ L6 OBUF (Prop_obuf_I_O) 3.523 11.348 r O_7segmentDisplay_OBUF[6]_inst/O
+ net (fo=0) 0.000 11.348 O_7segmentDisplay[6]
+ L6 r O_7segmentDisplay[6] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[4]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.324ns (logic 4.475ns (39.516%) route 6.849ns (60.484%))
+ Logic Levels: 6 (FDCE=1 LUT3=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[0]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[0]/Q
+ net (fo=20, routed) 1.263 1.719 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2_0
+ SLICE_X46Y101 LUT6 (Prop_lut6_I4_O) 0.124 1.843 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_7/O
+ net (fo=1, routed) 0.608 2.452 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_7_n_0
+ SLICE_X46Y99 LUT6 (Prop_lut6_I0_O) 0.124 2.576 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2/O
+ net (fo=7, routed) 0.991 3.567 modulo4_2/O_7segmentDisplay_OBUF[4]_inst_i_1_1
+ SLICE_X48Y97 LUT3 (Prop_lut3_I2_O) 0.124 3.691 r modulo4_2/O_7segmentDisplay_OBUF[4]_inst_i_2/O
+ net (fo=1, routed) 0.811 4.502 tirage_1/registres_2/O_7segmentDisplay[4]
+ SLICE_X48Y98 LUT6 (Prop_lut6_I0_O) 0.124 4.626 r tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_1/O
+ net (fo=1, routed) 3.175 7.801 O_7segmentDisplay_OBUF[4]
+ K3 OBUF (Prop_obuf_I_O) 3.523 11.324 r O_7segmentDisplay_OBUF[4]_inst/O
+ net (fo=0) 0.000 11.324 O_7segmentDisplay[4]
+ K3 r O_7segmentDisplay[4] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[1]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.248ns (logic 4.485ns (39.874%) route 6.763ns (60.126%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[1]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[1]/Q
+ net (fo=20, routed) 1.523 1.979 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2
+ SLICE_X47Y101 LUT6 (Prop_lut6_I2_O) 0.124 2.103 f tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_17/O
+ net (fo=1, routed) 0.426 2.528 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_17_n_0
+ SLICE_X46Y99 LUT6 (Prop_lut6_I0_O) 0.124 2.652 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11/O
+ net (fo=12, routed) 0.643 3.295 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_11_n_0
+ SLICE_X47Y98 LUT5 (Prop_lut5_I4_O) 0.124 3.419 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_4/O
+ net (fo=4, routed) 0.970 4.389 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_4_n_0
+ SLICE_X48Y98 LUT6 (Prop_lut6_I2_O) 0.124 4.513 r tirage_1/registres_2/O_7segmentDisplay_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.202 7.715 O_7segmentDisplay_OBUF[1]
+ N1 OBUF (Prop_obuf_I_O) 3.533 11.248 r O_7segmentDisplay_OBUF[1]_inst/O
+ net (fo=0) 0.000 11.248 O_7segmentDisplay[1]
+ N1 r O_7segmentDisplay[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo6_1/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentDisplay[5]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 11.232ns (logic 4.484ns (39.917%) route 6.749ns (60.083%))
+ Logic Levels: 6 (FDCE=1 LUT5=1 LUT6=3 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X48Y99 FDCE 0.000 0.000 r modulo6_1/SR_Counter_reg[0]/C
+ SLICE_X48Y99 FDCE (Prop_fdce_C_Q) 0.456 0.456 r modulo6_1/SR_Counter_reg[0]/Q
+ net (fo=20, routed) 1.263 1.719 tirage_1/registres_2/O_7segmentDisplay_OBUF[4]_inst_i_2_0
+ SLICE_X46Y101 LUT6 (Prop_lut6_I4_O) 0.124 1.843 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_7/O
+ net (fo=1, routed) 0.608 2.452 tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_7_n_0
+ SLICE_X46Y99 LUT6 (Prop_lut6_I0_O) 0.124 2.576 r tirage_1/registres_2/O_7segmentDisplay_OBUF[6]_inst_i_2/O
+ net (fo=7, routed) 1.265 3.841 tirage_1/registres_2/SR_Counter_reg[1]
+ SLICE_X47Y98 LUT6 (Prop_lut6_I0_O) 0.124 3.965 r tirage_1/registres_2/O_7segmentDisplay_OBUF[5]_inst_i_2/O
+ net (fo=1, routed) 0.805 4.770 tirage_1/registres_2/O_7segmentDisplay_OBUF[5]_inst_i_2_n_0
+ SLICE_X47Y97 LUT5 (Prop_lut5_I0_O) 0.124 4.894 r tirage_1/registres_2/O_7segmentDisplay_OBUF[5]_inst_i_1/O
+ net (fo=1, routed) 2.807 7.701 O_7segmentDisplay_OBUF[5]
+ M2 OBUF (Prop_obuf_I_O) 3.532 11.232 r O_7segmentDisplay_OBUF[5]_inst/O
+ net (fo=0) 0.000 11.232 O_7segmentDisplay[5]
+ M2 r O_7segmentDisplay[5] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo4_2/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentSelect[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 9.151ns (logic 4.169ns (45.551%) route 4.983ns (54.449%))
+ Logic Levels: 3 (FDCE=1 LUT2=1 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X46Y97 FDCE 0.000 0.000 r modulo4_2/SR_Counter_reg[0]/C
+ SLICE_X46Y97 FDCE (Prop_fdce_C_Q) 0.518 0.518 r modulo4_2/SR_Counter_reg[0]/Q
+ net (fo=19, routed) 0.892 1.410 modulo4_2/Q[0]
+ SLICE_X49Y97 LUT2 (Prop_lut2_I1_O) 0.124 1.534 r modulo4_2/O_7segmentSelect_OBUF[0]_inst_i_1/O
+ net (fo=2, routed) 4.091 5.625 O_7segmentSelect_OBUF[0]
+ N6 OBUF (Prop_obuf_I_O) 3.527 9.151 r O_7segmentSelect_OBUF[0]_inst/O
+ net (fo=0) 0.000 9.151 O_7segmentSelect[0]
+ N6 r O_7segmentSelect[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo4_2/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentSelect[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 8.989ns (logic 4.173ns (46.423%) route 4.816ns (53.577%))
+ Logic Levels: 3 (FDCE=1 LUT2=1 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X46Y97 FDCE 0.000 0.000 r modulo4_2/SR_Counter_reg[0]/C
+ SLICE_X46Y97 FDCE (Prop_fdce_C_Q) 0.518 0.518 f modulo4_2/SR_Counter_reg[0]/Q
+ net (fo=19, routed) 0.891 1.409 modulo4_2/Q[0]
+ SLICE_X49Y97 LUT2 (Prop_lut2_I1_O) 0.124 1.533 r modulo4_2/O_7segmentSelect_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.925 5.458 O_7segmentSelect_OBUF[1]
+ M6 OBUF (Prop_obuf_I_O) 3.531 8.989 r O_7segmentSelect_OBUF[1]_inst/O
+ net (fo=0) 0.000 8.989 O_7segmentSelect[1]
+ M6 r O_7segmentSelect[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: modulo4_2/SR_Counter_reg[0]/C
+ (rising edge-triggered cell FDCE)
+ Destination: O_7segmentSelect[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 8.834ns (logic 4.173ns (47.243%) route 4.661ns (52.757%))
+ Logic Levels: 3 (FDCE=1 LUT2=1 OBUF=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X46Y97 FDCE 0.000 0.000 r modulo4_2/SR_Counter_reg[0]/C
+ SLICE_X46Y97 FDCE (Prop_fdce_C_Q) 0.518 0.518 f modulo4_2/SR_Counter_reg[0]/Q
+ net (fo=19, routed) 0.830 1.348 modulo4_2/Q[0]
+ SLICE_X48Y98 LUT2 (Prop_lut2_I0_O) 0.124 1.472 r modulo4_2/O_7segmentSelect_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.831 5.303 O_7segmentSelect_OBUF[3]
+ N5 OBUF (Prop_obuf_I_O) 3.531 8.834 r O_7segmentSelect_OBUF[3]_inst/O
+ net (fo=0) 0.000 8.834 O_7segmentSelect[3]
+ N5 r O_7segmentSelect[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[0]/C
+ (rising edge-triggered cell FDPE)
+ Destination: tirage_1/registres_2/O_reg2_reg[0]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.304ns (logic 0.141ns (46.436%) route 0.163ns (53.564%))
+ Logic Levels: 1 (FDPE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X47Y101 FDPE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[0]/C
+ SLICE_X47Y101 FDPE (Prop_fdpe_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[0]/Q
+ net (fo=17, routed) 0.163 0.304 tirage_1/registres_2/O_reg1_reg[5]_0[0]
+ SLICE_X46Y101 FDCE r tirage_1/registres_2/O_reg2_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[5]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg1_reg[5]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.310ns (logic 0.141ns (45.457%) route 0.169ns (54.543%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X44Y101 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[5]/C
+ SLICE_X44Y101 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[5]/Q
+ net (fo=15, routed) 0.169 0.310 tirage_1/registres_2/O_reg1_reg[5]_0[5]
+ SLICE_X47Y100 FDCE r tirage_1/registres_2/O_reg1_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[5]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg0_reg[5]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.313ns (logic 0.141ns (45.111%) route 0.172ns (54.889%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X44Y101 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[5]/C
+ SLICE_X44Y101 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[5]/Q
+ net (fo=15, routed) 0.172 0.313 tirage_1/registres_2/O_reg1_reg[5]_0[5]
+ SLICE_X46Y102 FDCE r tirage_1/registres_2/O_reg0_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[3]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg2_reg[3]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.314ns (logic 0.148ns (47.193%) route 0.166ns (52.807%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X46Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[3]/C
+ SLICE_X46Y100 FDCE (Prop_fdce_C_Q) 0.148 0.148 r tirage_1/compteur_1/SR_cpt_val_reg[3]/Q
+ net (fo=16, routed) 0.166 0.314 tirage_1/registres_2/O_reg1_reg[5]_0[3]
+ SLICE_X48Y100 FDCE r tirage_1/registres_2/O_reg2_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg3_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.314ns (logic 0.141ns (44.859%) route 0.173ns (55.141%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X44Y101 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[4]/C
+ SLICE_X44Y101 FDCE (Prop_fdce_C_Q) 0.141 0.141 r tirage_1/compteur_1/SR_cpt_val_reg[4]/Q
+ net (fo=15, routed) 0.173 0.314 tirage_1/registres_2/O_reg1_reg[5]_0[4]
+ SLICE_X47Y102 FDCE r tirage_1/registres_2/O_reg3_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.326ns (logic 0.226ns (69.310%) route 0.100ns (30.690%))
+ Logic Levels: 2 (FDCE=1 LUT4=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y102 FDCE 0.000 0.000 r tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/C
+ SLICE_X51Y102 FDCE (Prop_fdce_C_Q) 0.128 0.128 r tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/Q
+ net (fo=3, routed) 0.100 0.228 tirage_1/led_pwm_1/SR_cpt_leds_reg_n_0_[2]
+ SLICE_X51Y102 LUT4 (Prop_lut4_I3_O) 0.098 0.326 r tirage_1/led_pwm_1/SR_cpt_leds[3]_i_1/O
+ net (fo=1, routed) 0.000 0.326 tirage_1/led_pwm_1/plusOp[3]
+ SLICE_X51Y102 FDCE r tirage_1/led_pwm_1/SR_cpt_leds_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.332ns (logic 0.232ns (69.864%) route 0.100ns (30.136%))
+ Logic Levels: 2 (FDCE=1 LUT5=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y102 FDCE 0.000 0.000 r tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/C
+ SLICE_X51Y102 FDCE (Prop_fdce_C_Q) 0.128 0.128 r tirage_1/led_pwm_1/SR_cpt_leds_reg[2]/Q
+ net (fo=3, routed) 0.100 0.228 tirage_1/led_pwm_1/SR_cpt_leds_reg_n_0_[2]
+ SLICE_X51Y102 LUT5 (Prop_lut5_I1_O) 0.104 0.332 r tirage_1/led_pwm_1/SR_cpt_leds[4]_i_1/O
+ net (fo=1, routed) 0.000 0.332 tirage_1/led_pwm_1/plusOp[4]
+ SLICE_X51Y102 FDCE r tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/led_pwm_1/SR_cpt_leds_reg_reg[4]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.347ns (logic 0.128ns (36.884%) route 0.219ns (63.116%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y102 FDCE 0.000 0.000 r tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/C
+ SLICE_X51Y102 FDCE (Prop_fdce_C_Q) 0.128 0.128 r tirage_1/led_pwm_1/SR_cpt_leds_reg[4]/Q
+ net (fo=4, routed) 0.219 0.347 tirage_1/led_pwm_1/p_0_in
+ SLICE_X51Y102 FDCE r tirage_1/led_pwm_1/SR_cpt_leds_reg_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[1]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg1_reg[1]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.352ns (logic 0.164ns (46.529%) route 0.188ns (53.471%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X46Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[1]/C
+ SLICE_X46Y100 FDCE (Prop_fdce_C_Q) 0.164 0.164 r tirage_1/compteur_1/SR_cpt_val_reg[1]/Q
+ net (fo=17, routed) 0.188 0.352 tirage_1/registres_2/O_reg1_reg[5]_0[1]
+ SLICE_X47Y100 FDCE r tirage_1/registres_2/O_reg1_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: tirage_1/compteur_1/SR_cpt_val_reg[1]/C
+ (rising edge-triggered cell FDCE)
+ Destination: tirage_1/registres_2/O_reg4_reg[1]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.359ns (logic 0.164ns (45.651%) route 0.195ns (54.349%))
+ Logic Levels: 1 (FDCE=1)
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ SLICE_X46Y100 FDCE 0.000 0.000 r tirage_1/compteur_1/SR_cpt_val_reg[1]/C
+ SLICE_X46Y100 FDCE (Prop_fdce_C_Q) 0.164 0.164 r tirage_1/compteur_1/SR_cpt_val_reg[1]/Q
+ net (fo=17, routed) 0.195 0.359 tirage_1/registres_2/O_reg1_reg[5]_0[1]
+ SLICE_X46Y98 FDCE r tirage_1/registres_2/O_reg4_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock: sys_clk_pin
+ To Clock:
+
+Max Delay 3 Endpoints
+Min Delay 3 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 1.719ns (logic 0.704ns (40.946%) route 1.015ns (59.054%))
+ Logic Levels: 2 (LUT6=2)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.617 5.219 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 5.675 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.345 6.021 tirage_1/automate_1/out[0]
+ SLICE_X50Y101 LUT6 (Prop_lut6_I5_O) 0.124 6.145 r tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_3/O
+ net (fo=2, routed) 0.670 6.815 tirage_1/automate_1/SR_STATE0
+ SLICE_X50Y101 LUT6 (Prop_lut6_I4_O) 0.124 6.939 r tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1/O
+ net (fo=1, routed) 0.000 6.939 tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1_n_0
+ SLICE_X50Y101 FDRE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[1]/D
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 1.439ns (logic 0.704ns (48.930%) route 0.735ns (51.070%))
+ Logic Levels: 2 (LUT5=1 LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.617 5.219 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 5.675 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.345 6.021 tirage_1/automate_1/out[0]
+ SLICE_X50Y101 LUT6 (Prop_lut6_I5_O) 0.124 6.145 r tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_3/O
+ net (fo=2, routed) 0.389 6.534 tirage_1/automate_1/SR_STATE0
+ SLICE_X50Y101 LUT5 (Prop_lut5_I3_O) 0.124 6.658 r tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_1/O
+ net (fo=1, routed) 0.000 6.658 tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_1_n_0
+ SLICE_X50Y101 FDRE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 1.206ns (logic 0.580ns (48.081%) route 0.626ns (51.919%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 2.025 3.506 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.617 5.219 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.456 5.675 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.626 6.302 tirage_1/automate_1/out[0]
+ SLICE_X50Y101 LUT6 (Prop_lut6_I5_O) 0.124 6.426 r tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1/O
+ net (fo=1, routed) 0.000 6.426 tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1_n_0
+ SLICE_X50Y101 FDRE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.414ns (logic 0.186ns (44.894%) route 0.228ns (55.106%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.560 1.479 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.141 1.620 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.228 1.849 tirage_1/automate_1/out[0]
+ SLICE_X50Y101 LUT6 (Prop_lut6_I5_O) 0.045 1.894 r tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1/O
+ net (fo=1, routed) 0.000 1.894 tirage_1/automate_1/FSM_sequential_SR_STATE[2]_i_1_n_0
+ SLICE_X50Y101 FDRE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[1]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.517ns (logic 0.231ns (44.699%) route 0.286ns (55.301%))
+ Logic Levels: 2 (LUT5=1 LUT6=1)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.560 1.479 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.141 1.620 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.140 1.761 tirage_1/automate_1/out[0]
+ SLICE_X50Y101 LUT6 (Prop_lut6_I5_O) 0.045 1.806 r tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_3/O
+ net (fo=2, routed) 0.145 1.951 tirage_1/automate_1/SR_STATE0
+ SLICE_X50Y101 LUT5 (Prop_lut5_I3_O) 0.045 1.996 r tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_1/O
+ net (fo=1, routed) 0.000 1.996 tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_1_n_0
+ SLICE_X50Y101 FDRE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: diviseur_freq_1/SR_counter_reg[25]/C
+ (rising edge-triggered cell FDCE clocked by sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 0.595ns (logic 0.231ns (38.802%) route 0.364ns (61.198%))
+ Logic Levels: 2 (LUT6=2)
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.644 0.894 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.920 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.560 1.479 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y100 FDCE (Prop_fdce_C_Q) 0.141 1.620 r diviseur_freq_1/SR_counter_reg[25]/Q
+ net (fo=6, routed) 0.140 1.761 tirage_1/automate_1/out[0]
+ SLICE_X50Y101 LUT6 (Prop_lut6_I5_O) 0.045 1.806 r tirage_1/automate_1/FSM_sequential_SR_STATE[1]_i_3/O
+ net (fo=2, routed) 0.224 2.030 tirage_1/automate_1/SR_STATE0
+ SLICE_X50Y101 LUT6 (Prop_lut6_I4_O) 0.045 2.075 r tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1/O
+ net (fo=1, routed) 0.000 2.075 tirage_1/automate_1/FSM_sequential_SR_STATE[0]_i_1_n_0
+ SLICE_X50Y101 FDRE r tirage_1/automate_1/FSM_sequential_SR_STATE_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock:
+ To Clock: sys_clk_pin
+
+Max Delay 26 Endpoints
+Min Delay 26 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[0]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.945ns (logic 1.524ns (25.639%) route 4.420ns (74.361%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.420 5.945 diviseur_freq_1/AR[0]
+ SLICE_X51Y94 FDCE f diviseur_freq_1/SR_counter_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[0]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[1]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.945ns (logic 1.524ns (25.639%) route 4.420ns (74.361%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.420 5.945 diviseur_freq_1/AR[0]
+ SLICE_X51Y94 FDCE f diviseur_freq_1/SR_counter_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[1]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[2]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.945ns (logic 1.524ns (25.639%) route 4.420ns (74.361%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.420 5.945 diviseur_freq_1/AR[0]
+ SLICE_X51Y94 FDCE f diviseur_freq_1/SR_counter_reg[2]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[2]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[3]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.945ns (logic 1.524ns (25.639%) route 4.420ns (74.361%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.420 5.945 diviseur_freq_1/AR[0]
+ SLICE_X51Y94 FDCE f diviseur_freq_1/SR_counter_reg[3]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y94 FDCE r diviseur_freq_1/SR_counter_reg[3]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[4]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.804ns (logic 1.524ns (26.261%) route 4.280ns (73.739%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.280 5.804 diviseur_freq_1/AR[0]
+ SLICE_X51Y95 FDCE f diviseur_freq_1/SR_counter_reg[4]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[4]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[5]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.804ns (logic 1.524ns (26.261%) route 4.280ns (73.739%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.280 5.804 diviseur_freq_1/AR[0]
+ SLICE_X51Y95 FDCE f diviseur_freq_1/SR_counter_reg[5]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[5]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[6]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.804ns (logic 1.524ns (26.261%) route 4.280ns (73.739%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.280 5.804 diviseur_freq_1/AR[0]
+ SLICE_X51Y95 FDCE f diviseur_freq_1/SR_counter_reg[6]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[6]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[7]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.804ns (logic 1.524ns (26.261%) route 4.280ns (73.739%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.934ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.934ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.280 5.804 diviseur_freq_1/AR[0]
+ SLICE_X51Y95 FDCE f diviseur_freq_1/SR_counter_reg[7]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.511 4.934 diviseur_freq_1/I16
+ SLICE_X51Y95 FDCE r diviseur_freq_1/SR_counter_reg[7]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[24]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.737ns (logic 1.524ns (26.565%) route 4.213ns (73.435%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.918ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.918ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.213 5.737 diviseur_freq_1/AR[0]
+ SLICE_X51Y100 FDCE f diviseur_freq_1/SR_counter_reg[24]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.496 4.918 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[24]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[25]/CLR
+ (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 5.737ns (logic 1.524ns (26.565%) route 4.213ns (73.435%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 4.918ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 4.918ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Total Input Jitter (TIJ): 0.000ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 1.524 1.524 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 4.213 5.737 diviseur_freq_1/AR[0]
+ SLICE_X51Y100 FDCE f diviseur_freq_1/SR_counter_reg[25]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 1.920 3.331 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 3.422 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 1.496 4.918 diviseur_freq_1/I16
+ SLICE_X51Y100 FDCE r diviseur_freq_1/SR_counter_reg[25]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[16]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.031ns (logic 0.292ns (14.355%) route 1.739ns (85.645%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.739 2.031 diviseur_freq_1/AR[0]
+ SLICE_X51Y98 FDCE f diviseur_freq_1/SR_counter_reg[16]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[16]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[17]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.031ns (logic 0.292ns (14.355%) route 1.739ns (85.645%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.739 2.031 diviseur_freq_1/AR[0]
+ SLICE_X51Y98 FDCE f diviseur_freq_1/SR_counter_reg[17]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[17]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[18]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.031ns (logic 0.292ns (14.355%) route 1.739ns (85.645%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.739 2.031 diviseur_freq_1/AR[0]
+ SLICE_X51Y98 FDCE f diviseur_freq_1/SR_counter_reg[18]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[18]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[19]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.031ns (logic 0.292ns (14.355%) route 1.739ns (85.645%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.739 2.031 diviseur_freq_1/AR[0]
+ SLICE_X51Y98 FDCE f diviseur_freq_1/SR_counter_reg[19]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y98 FDCE r diviseur_freq_1/SR_counter_reg[19]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[12]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.084ns (logic 0.292ns (13.992%) route 1.792ns (86.008%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.792 2.084 diviseur_freq_1/AR[0]
+ SLICE_X51Y97 FDCE f diviseur_freq_1/SR_counter_reg[12]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[12]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[13]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.084ns (logic 0.292ns (13.992%) route 1.792ns (86.008%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.792 2.084 diviseur_freq_1/AR[0]
+ SLICE_X51Y97 FDCE f diviseur_freq_1/SR_counter_reg[13]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[13]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[14]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.084ns (logic 0.292ns (13.992%) route 1.792ns (86.008%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.792 2.084 diviseur_freq_1/AR[0]
+ SLICE_X51Y97 FDCE f diviseur_freq_1/SR_counter_reg[14]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[14]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[15]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.084ns (logic 0.292ns (13.992%) route 1.792ns (86.008%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.792 2.084 diviseur_freq_1/AR[0]
+ SLICE_X51Y97 FDCE f diviseur_freq_1/SR_counter_reg[15]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y97 FDCE r diviseur_freq_1/SR_counter_reg[15]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[20]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.094ns (logic 0.292ns (13.921%) route 1.803ns (86.079%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.803 2.094 diviseur_freq_1/AR[0]
+ SLICE_X51Y99 FDCE f diviseur_freq_1/SR_counter_reg[20]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[20]/C
+
+Slack: inf
+ Source: I_rst
+ (input port)
+ Destination: diviseur_freq_1/SR_counter_reg[21]/CLR
+ (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@5.000ns period=10.000ns})
+ Path Group: (none)
+ Path Type: Removal (Min at Fast Process Corner)
+ Data Path Delay: 2.094ns (logic 0.292ns (13.921%) route 1.803ns (86.079%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: 2.001ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 2.001ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ V10 0.000 0.000 f I_rst (IN)
+ net (fo=0) 0.000 0.000 I_rst
+ V10 IBUF (Prop_ibuf_I_O) 0.292 0.292 f I_rst_IBUF_inst/O
+ net (fo=88, routed) 1.803 2.094 diviseur_freq_1/AR[0]
+ SLICE_X51Y99 FDCE f diviseur_freq_1/SR_counter_reg[21]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock sys_clk_pin rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r I_clk_100m (IN)
+ net (fo=0) 0.000 0.000 I_clk_100m
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r I_clk_100m_IBUF_inst/O
+ net (fo=1, routed) 0.699 1.136 I_clk_100m_IBUF
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.165 r I_clk_100m_IBUF_BUFG_inst/O
+ net (fo=26, routed) 0.836 2.001 diviseur_freq_1/I16
+ SLICE_X51Y99 FDCE r diviseur_freq_1/SR_counter_reg[21]/C
+
+
+
+
+
diff --git a/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.rpx b/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..d82836991978ac40b18d2452de50f1db30dd81e9
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_timing_summary_routed.rpx differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_utilization_placed.pb b/LOTO/LOTO.runs/impl_1/loto_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ee88f8592858a46f5d3c8129b65abde689377e72
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/loto_utilization_placed.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/loto_utilization_placed.rpt b/LOTO/LOTO.runs/impl_1/loto_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f46422314c5ed14c01de326755ce5c5b74c995e9
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/loto_utilization_placed.rpt
@@ -0,0 +1,216 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:56:11 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs | 73 | 0 | 0 | 63400 | 0.12 |
+| LUT as Logic | 73 | 0 | 0 | 63400 | 0.12 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Flip Flop | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 84 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 3 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice | 33 | 0 | 0 | 15850 | 0.21 |
+| SLICEL | 25 | 0 | | | |
+| SLICEM | 8 | 0 | | | |
+| LUT as Logic | 73 | 0 | 0 | 63400 | 0.12 |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 53 | | | | |
+| using O5 and O6 | 20 | | | | |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| LUT as Distributed RAM | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| LUT as Shift Register | 0 | 0 | | | |
+| using O5 output only | 0 | | | | |
+| using O6 output only | 0 | | | | |
+| using O5 and O6 | 0 | | | | |
+| Slice Registers | 89 | 0 | 0 | 126800 | 0.07 |
+| Register driven from within the Slice | 53 | | | | |
+| Register driven from outside the Slice | 36 | | | | |
+| LUT in front of the register is unused | 18 | | | | |
+| LUT in front of the register is used | 18 | | | | |
+| Unique Control Sets | 11 | | 0 | 15850 | 0.07 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 21 | 21 | 0 | 210 | 10.00 |
+| IOB Master Pads | 12 | | | | |
+| IOB Slave Pads | 9 | | | | |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 84 | Flop & Latch |
+| LUT6 | 43 | LUT |
+| OBUF | 17 | IO |
+| LUT4 | 15 | LUT |
+| LUT5 | 11 | LUT |
+| LUT2 | 11 | LUT |
+| LUT3 | 10 | LUT |
+| CARRY4 | 7 | CarryLogic |
+| IBUF | 4 | IO |
+| LUT1 | 3 | LUT |
+| FDRE | 3 | Flop & Latch |
+| FDPE | 2 | Flop & Latch |
+| BUFG | 2 | Clock |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/LOTO/LOTO.runs/impl_1/opt_design.pb b/LOTO/LOTO.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..5e5241a7efbcef6921ed020a45e5d1021c0e6784
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/opt_design.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/phys_opt_design.pb b/LOTO/LOTO.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ac92c5b098d6d4569cf63ef56540904122fce550
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/phys_opt_design.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/place_design.pb b/LOTO/LOTO.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e02de1d8772d68356e70171f51019b4068c574d6
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/place_design.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/project.wdf b/LOTO/LOTO.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..ebecd80ac99251ec32e74b51f20c7cce1e26556d
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
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diff --git a/LOTO/LOTO.runs/impl_1/route_design.pb b/LOTO/LOTO.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e366e626161ded5836e98cfb724a3c9ab6faeb4f
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/route_design.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/rundef.js b/LOTO/LOTO.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..84765151197df8b4050d3ae16fb9d5cdd27cd742
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/rundef.js
@@ -0,0 +1,45 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/LOTO/LOTO.runs/impl_1/runme.bat b/LOTO/LOTO.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/LOTO/LOTO.runs/impl_1/runme.log b/LOTO/LOTO.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..54f27d60cc43ba3ac9253e523d250d36375c0ea4
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/runme.log
@@ -0,0 +1,730 @@
+
+*** Running vivado
+ with args -log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 12 11:55:27 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1574.262 ; gain = 143.809 ; free physical = 6423 ; free virtual = 15130
+Command: link_design -top loto -part xc7a100tcsg324-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1933.391 ; gain = 0.000 ; free physical = 6041 ; free virtual = 14748
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2141.883 ; gain = 0.000 ; free physical = 5931 ; free virtual = 14641
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2141.883 ; gain = 567.621 ; free physical = 5931 ; free virtual = 14641
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2153.461 ; gain = 11.578 ; free physical = 5901 ; free virtual = 14611
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2653.289 ; gain = 499.828 ; free physical = 5453 ; free virtual = 14194
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 1 Initialization | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 2 Timer Update And Timing Data Collection | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Retarget | Checksum: 214b59dec
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 214b59dec
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Constant propagation | Checksum: 214b59dec
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Sweep | Checksum: 27dfe16e6
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+BUFG optimization | Checksum: 27dfe16e6
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Shift Register Optimization | Checksum: 27dfe16e6
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 27dfe16e6
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Post Processing Netlist | Checksum: 27dfe16e6
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Phase 9 Finalization | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 0 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+Ending Netlist Obfuscation Task | Checksum: 1fa48d7c2
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2966.125 ; gain = 0.000 ; free physical = 5130 ; free virtual = 13872
+INFO: [Common 17-83] Releasing license: Implementation
+26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2966.125 ; gain = 824.242 ; free physical = 5130 ; free virtual = 13872
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+Command: report_drc -file loto_drc_opted.rpt -pb loto_drc_opted.pb -rpx loto_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5126 ; free virtual = 13869
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5126 ; free virtual = 13869
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5126 ; free virtual = 13869
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+Write Physdb Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5125 ; free virtual = 13868
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5119 ; free virtual = 13863
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d3c97407
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5119 ; free virtual = 13863
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5119 ; free virtual = 13863
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1637776cc
+
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13857
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 229232f06
+
+Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.45 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13858
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 229232f06
+
+Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13858
+Phase 1 Placer Initialization | Checksum: 229232f06
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5110 ; free virtual = 13858
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1951284e8
+
+Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 19dd6cbc3
+
+Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 19dd6cbc3
+
+Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1f606059d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.86 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5109 ; free virtual = 13858
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1f606059d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+Phase 2.4 Global Placement Core | Checksum: 246383a97
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+Phase 2 Global Placement | Checksum: 246383a97
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 246819dcf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fb19f5f2
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1a2ad0221
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 22f8f661d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5098 ; free virtual = 13850
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1c7afcdaf
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 192e0fece
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 1c40322ca
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+Phase 3 Detail Placement | Checksum: 1c40322ca
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 246144c51
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=5.911 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 17b4bc2a7
+
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 1cc767b81
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+Phase 4.1.1.1 BUFG Insertion | Checksum: 246144c51
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=5.911. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+Phase 4.1 Post Commit Optimization | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5094 ; free virtual = 13846
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+Phase 4.3 Placer Reporting | Checksum: 21ac414ec
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f16fc791
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+Ending Placer Task | Checksum: 17ca2ca6b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5090 ; free virtual = 13845
+62 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file loto_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_placed.rpt -pb loto_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file loto_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.2 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5087 ; free virtual = 13841
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+Write Physdb Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5086 ; free virtual = 13841
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5062 ; free virtual = 13817
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 5.911 | TNS= 0.000 |
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5062 ; free virtual = 13817
+Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+Write Physdb Complete: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3014.148 ; gain = 0.000 ; free physical = 5060 ; free virtual = 13814
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 3f758dcf ConstDB: 0 ShapeSum: 8b5add06 RouteDB: b1d25f96
+Post Restoration Checksum: NetGraph: cc74fed7 | NumContArr: 7897af87 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2ca5ea398
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.176 ; gain = 110.027 ; free physical = 4898 ; free virtual = 13655
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2ca5ea398
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.176 ; gain = 110.027 ; free physical = 4898 ; free virtual = 13655
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2ca5ea398
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 3124.176 ; gain = 110.027 ; free physical = 4898 ; free virtual = 13655
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 2b0c90ab1
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4885 ; free virtual = 13643
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.765 | TNS=0.000 | WHS=-0.017 | THS=-0.162 |
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 4.35218e-05 %
+ Global Horizontal Routing Utilization = 0.000213129 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 165
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 163
+ Number of Partially Routed Nets = 2
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 2fc60a036
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 2fc60a036
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 1e5a8b0d8
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+Phase 4 Initial Routing | Checksum: 1e5a8b0d8
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4908 ; free virtual = 13666
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 12
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.767 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Phase 5 Rip-up And Reroute | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Phase 6 Delay and Skew Optimization | Checksum: 290cf978f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.767 | TNS=0.000 | WHS=0.093 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Phase 7 Post Hold Fix | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0203682 %
+ Global Horizontal Routing Utilization = 0.0458227 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 2a2364fa2
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 267fec3ed
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 267fec3ed
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=5.767 | TNS=0.000 | WHS=0.093 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 267fec3ed
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+Total Elapsed time in route_design: 21.52 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 150960f3f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 150960f3f
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 3152.754 ; gain = 138.605 ; free physical = 4907 ; free virtual = 13666
+INFO: [Vivado 12-24828] Executing command : report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+Command: report_drc -file loto_drc_routed.rpt -pb loto_drc_routed.pb -rpx loto_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+Command: report_methodology -file loto_methodology_drc_routed.rpt -pb loto_methodology_drc_routed.pb -rpx loto_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 4 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file loto_timing_summary_routed.rpt -pb loto_timing_summary_routed.pb -rpx loto_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file loto_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file loto_route_status.rpt -pb loto_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file loto_bus_skew_routed.rpt -pb loto_bus_skew_routed.pb -rpx loto_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Command: report_power -file loto_power_routed.rpt -pb loto_power_summary_routed.pb -rpx loto_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+107 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file loto_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Wrote PlaceDB: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4887 ; free virtual = 13646
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4886 ; free virtual = 13646
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4885 ; free virtual = 13645
+Write Physdb Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3216.488 ; gain = 0.000 ; free physical = 4885 ; free virtual = 13645
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto_routed.dcp' has been generated.
+Command: write_bitstream -force loto.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./loto.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+118 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3497.434 ; gain = 280.945 ; free physical = 4541 ; free virtual = 13311
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:56:49 2025...
diff --git a/LOTO/LOTO.runs/impl_1/runme.sh b/LOTO/LOTO.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ec23d7bc20e975af934c48dd7714a416d902cf03
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log loto.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+
+
diff --git a/LOTO/LOTO.runs/impl_1/vivado.jou b/LOTO/LOTO.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..10b5dafd8455229799c40e1a960e62339be60555
--- /dev/null
+++ b/LOTO/LOTO.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:55:27 2025
+# Process ID: 55837
+# Current directory: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1
+# Command line: vivado -log loto.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source loto.tcl -notrace
+# Log file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.vdi
+# Journal file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/vivado.jou
+# Running On :fl-tp-br-664
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3394.958 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16648 MB
+# Swap memory :4294 MB
+# Total Virtual :20943 MB
+# Available Virtual :16413 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
diff --git a/LOTO/LOTO.runs/impl_1/vivado.pb b/LOTO/LOTO.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..442b69f05467d821626a77aa02466a7c7323ed6d
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/vivado.pb differ
diff --git a/LOTO/LOTO.runs/impl_1/write_bitstream.pb b/LOTO/LOTO.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8c1a56954742625e7f7e4c1fdfab2c028193ad9b
Binary files /dev/null and b/LOTO/LOTO.runs/impl_1/write_bitstream.pb differ
diff --git a/LOTO/LOTO.runs/synth_1/.Vivado_Synthesis.queue.rst b/LOTO/LOTO.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/synth_1/.Xil/loto_propImpl.xdc b/LOTO/LOTO.runs/synth_1/.Xil/loto_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..21d52f88dff9aa71610675061fc8b509f933c38f
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/.Xil/loto_propImpl.xdc
@@ -0,0 +1,43 @@
+set_property SRC_FILE_INFO {cfile:/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc rfile:../../../../src/Nexys4_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E16 [get_ports I_button]
+set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P4 [get_ports I_block]
+set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E3 [get_ports I_clk_100m]
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V10 [get_ports I_rst]
+set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN K5 [get_ports O_red]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN H6 [get_ports O_green]
+set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L3 [get_ports {O_7segmentDisplay[0]}]
+set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N1 [get_ports {O_7segmentDisplay[1]}]
+set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L5 [get_ports {O_7segmentDisplay[2]}]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L4 [get_ports {O_7segmentDisplay[3]}]
+set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN K3 [get_ports {O_7segmentDisplay[4]}]
+set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M2 [get_ports {O_7segmentDisplay[5]}]
+set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L6 [get_ports {O_7segmentDisplay[6]}]
+set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N6 [get_ports {O_7segmentSelect[0]}]
+set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M6 [get_ports {O_7segmentSelect[1]}]
+set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M3 [get_ports {O_7segmentSelect[2]}]
+set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N5 [get_ports {O_7segmentSelect[3]}]
+set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N2 [get_ports {O_7segmentSelect[4]}]
+set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN N4 [get_ports {O_7segmentSelect[5]}]
+set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN L1 [get_ports {O_7segmentSelect[6]}]
+set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN M1 [get_ports {O_7segmentSelect[7]}]
diff --git a/LOTO/LOTO.runs/synth_1/.vivado.begin.rst b/LOTO/LOTO.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..05d0a0c1b9f55a7933305b75872bb2c104f97d71
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="a23delau" Host="fl-tp-br-664" Pid="55085" HostCore="4" HostMemory="16258244">
+ </Process>
+</ProcessHandle>
diff --git a/LOTO/LOTO.runs/synth_1/.vivado.end.rst b/LOTO/LOTO.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/synth_1/ISEWrap.js b/LOTO/LOTO.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..61806d02710bd275f7cfe41a9d52914e7a1e63df
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/LOTO/LOTO.runs/synth_1/ISEWrap.sh b/LOTO/LOTO.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05d5381379bf87abb6918978ce23d53b6a3e9a78
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/LOTO/LOTO.runs/synth_1/__synthesis_is_complete__ b/LOTO/LOTO.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.runs/synth_1/gen_run.xml b/LOTO/LOTO.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..82e38d37c26b14722fc71291532eeb0341c55b18
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/gen_run.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1739357658">
+ <File Type="VDS-TIMINGSUMMARY" Name="loto_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="loto.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="loto_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="loto_utilization_synth.rpt"/>
+ <File Type="VDS-TIMING-PB" Name="loto_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="loto.tcl"/>
+ <File Type="REPORTS-TCL" Name="loto_reports.tcl"/>
+ <File Type="RDS-RDS" Name="loto.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="loto_drc_synth.rpt"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/automate.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur1_49.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_valid.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/diviseur_freq.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/led_pwm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/registres.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/tirage.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_d_u.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/modulo4.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/loto.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo4.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_u.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+</GenRun>
diff --git a/LOTO/LOTO.runs/synth_1/htr.txt b/LOTO/LOTO.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9c114a1ac75a75379ab1b9b1ff66764984b67be5
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
diff --git a/LOTO/LOTO.runs/synth_1/loto.dcp b/LOTO/LOTO.runs/synth_1/loto.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..07016f8c06b66885b61d51319cd61ae17d47b878
Binary files /dev/null and b/LOTO/LOTO.runs/synth_1/loto.dcp differ
diff --git a/LOTO/LOTO.runs/synth_1/loto.tcl b/LOTO/LOTO.runs/synth_1/loto.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3e81a162c6660455deb2a5e2729444943dea6335
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/loto.tcl
@@ -0,0 +1,124 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/loto.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param checkpoint.writeSynthRtdsInDcp 1
+set_param synth.incrementalSynthesisCache ./.Xil/Vivado-6007-fl-tp-br-664/incrSyn
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a100tcsg324-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.cache/wt [current_project]
+set_property parent.project_path /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_output_repo /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib {
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd
+ /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd
+}
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc
+set_property used_in_implementation false [get_files /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top loto -part xc7a100tcsg324-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef loto.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb" }
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/LOTO/LOTO.runs/synth_1/loto.vds b/LOTO/LOTO.runs/synth_1/loto.vds
new file mode 100644
index 0000000000000000000000000000000000000000..5d1fc680856b8a1900f5432fc03567c067c5ab9a
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/loto.vds
@@ -0,0 +1,296 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:54:22 2025
+# Process ID: 55157
+# Current directory: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1
+# Command line: vivado -log loto.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
+# Log file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/loto.vds
+# Journal file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-664
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :900.021 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16648 MB
+# Swap memory :4294 MB
+# Total Virtual :20943 MB
+# Available Virtual :16390 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.879 ; gain = 202.840 ; free physical = 6408 ; free virtual = 15100
+Command: synth_design -top loto -part xc7a100tcsg324-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 55423
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2350.508 ; gain = 420.469 ; free physical = 5358 ; free virtual = 14047
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'loto' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'tirage' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'automate' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:21]
+INFO: [Synth 8-256] done synthesizing module 'automate' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'registres' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'registres' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd:23]
+INFO: [Synth 8-638] synthesizing module 'compteur_valid' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd:15]
+INFO: [Synth 8-256] done synthesizing module 'compteur_valid' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd:15]
+INFO: [Synth 8-638] synthesizing module 'compteur1_49' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'compteur1_49' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd:16]
+INFO: [Synth 8-638] synthesizing module 'led_pwm' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'led_pwm' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'tirage' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'compteur_modulo6' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-256] done synthesizing module 'compteur_modulo6' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-638] synthesizing module 'diviseur_freq' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd:18]
+ Parameter n_fast bound to: 15 - type: integer
+ Parameter n_slow bound to: 25 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'diviseur_freq' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd:18]
+INFO: [Synth 8-638] synthesizing module 'mux6_1' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:20]
+WARNING: [Synth 8-614] signal 'I_2' is read in the process but is not in the sensitivity list [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'mux6_1' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:20]
+INFO: [Synth 8-638] synthesizing module 'transcodeur7s_d_u_transcod_int' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-256] done synthesizing module 'transcodeur7s_d_u_transcod_int' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-638] synthesizing module 'modulo4' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'modulo4' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'loto' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd:21]
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2428.477 ; gain = 498.438 ; free physical = 5282 ; free virtual = 13971
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2446.289 ; gain = 516.250 ; free physical = 5274 ; free virtual = 13963
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2446.289 ; gain = 516.250 ; free physical = 5274 ; free virtual = 13963
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2446.289 ; gain = 0.000 ; free physical = 5274 ; free virtual = 13962
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/loto_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/loto_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.039 ; gain = 0.000 ; free physical = 5252 ; free virtual = 13942
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.039 ; gain = 0.000 ; free physical = 5252 ; free virtual = 13942
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5255 ; free virtual = 13945
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5255 ; free virtual = 13945
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5254 ; free virtual = 13945
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_STATE_reg' in module 'automate'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ st_wait_failed | 000 | 000
+ st_counting | 001 | 010
+ st_compar | 010 | 011
+ st_store | 011 | 100
+ st_wait_success | 100 | 001
+ st_end_red | 101 | 110
+ st_end_green | 110 | 101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_STATE_reg' using encoding 'sequential' in module 'automate'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5251 ; free virtual = 13942
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 6 Bit Adders := 1
+ 2 Input 5 Bit Adders := 1
+ 2 Input 3 Bit Adders := 2
+ 2 Input 2 Bit Adders := 1
++---Registers :
+ 6 Bit Registers := 7
+ 5 Bit Registers := 2
+ 3 Bit Registers := 2
+ 2 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 7 Bit Muxes := 1
+ 4 Input 7 Bit Muxes := 1
+ 4 Input 4 Bit Muxes := 1
+ 7 Input 3 Bit Muxes := 1
+ 2 Input 3 Bit Muxes := 4
+ 2 Input 2 Bit Muxes := 1
+ 7 Input 1 Bit Muxes := 11
+ 2 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5225 ; free virtual = 13922
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5213 ; free virtual = 13924
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5213 ; free virtual = 13924
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5209 ; free virtual = 13920
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-------+------+
+| |Cell |Count |
++------+-------+------+
+|1 |BUFG | 2|
+|2 |CARRY4 | 7|
+|3 |LUT1 | 3|
+|4 |LUT2 | 11|
+|5 |LUT3 | 10|
+|6 |LUT4 | 15|
+|7 |LUT5 | 11|
+|8 |LUT6 | 43|
+|9 |FDCE | 84|
+|10 |FDPE | 2|
+|11 |FDRE | 3|
+|12 |IBUF | 4|
+|13 |OBUF | 17|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2594.039 ; gain = 516.250 ; free physical = 5207 ; free virtual = 13917
+Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.047 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.047 ; gain = 0.000 ; free physical = 5506 ; free virtual = 14217
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.047 ; gain = 0.000 ; free physical = 5504 ; free virtual = 14216
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: ad434a8
+INFO: [Common 17-83] Releasing license: Synthesis
+42 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2594.047 ; gain = 1022.168 ; free physical = 5505 ; free virtual = 14217
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2097.210; main = 1756.832; forked = 398.990
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3655.121; main = 2594.043; forked = 1061.078
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2618.051 ; gain = 0.000 ; free physical = 5505 ; free virtual = 14216
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/loto.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:55:22 2025...
diff --git a/LOTO/LOTO.runs/synth_1/loto_utilization_synth.pb b/LOTO/LOTO.runs/synth_1/loto_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ee88f8592858a46f5d3c8129b65abde689377e72
Binary files /dev/null and b/LOTO/LOTO.runs/synth_1/loto_utilization_synth.pb differ
diff --git a/LOTO/LOTO.runs/synth_1/loto_utilization_synth.rpt b/LOTO/LOTO.runs/synth_1/loto_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3c1f21d13a9b203c43c5cfc991e95193f6884f33
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/loto_utilization_synth.rpt
@@ -0,0 +1,183 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+| Date : Wed Feb 12 11:55:21 2025
+| Host : fl-tp-br-664 running 64-bit Ubuntu 24.04.1 LTS
+| Command : report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb
+| Design : loto
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 73 | 0 | 0 | 63400 | 0.12 |
+| LUT as Logic | 73 | 0 | 0 | 63400 | 0.12 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Flip Flop | 89 | 0 | 0 | 126800 | 0.07 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 84 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 3 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 21 | 0 | 0 | 210 | 10.00 |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE | 84 | Flop & Latch |
+| LUT6 | 43 | LUT |
+| OBUF | 17 | IO |
+| LUT4 | 15 | LUT |
+| LUT5 | 11 | LUT |
+| LUT2 | 11 | LUT |
+| LUT3 | 10 | LUT |
+| CARRY4 | 7 | CarryLogic |
+| IBUF | 4 | IO |
+| LUT1 | 3 | LUT |
+| FDRE | 3 | Flop & Latch |
+| FDPE | 2 | Flop & Latch |
+| BUFG | 2 | Clock |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/LOTO/LOTO.runs/synth_1/rundef.js b/LOTO/LOTO.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..1e14633f30e4d69dcffbedaf25cbac2d09b4ad31
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;";
+} else {
+ PathVal = "/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64;/opt/img/Vivado2024.1/Vivado/2024.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/LOTO/LOTO.runs/synth_1/runme.bat b/LOTO/LOTO.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..637899f0be2c412b7962cc0b1c6107b95c906461
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/LOTO/LOTO.runs/synth_1/runme.log b/LOTO/LOTO.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..2d8379adc76cb8bb14ee1da17361d673954771d2
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/runme.log
@@ -0,0 +1,286 @@
+
+*** Running vivado
+ with args -log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
+
+
+****** Vivado v2024.1 (64-bit)
+ **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+ **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+ **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+ **** Start of session at: Wed Feb 12 11:54:22 2025
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source loto.tcl -notrace
+create_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1571.879 ; gain = 202.840 ; free physical = 6408 ; free virtual = 15100
+Command: synth_design -top loto -part xc7a100tcsg324-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 55423
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2350.508 ; gain = 420.469 ; free physical = 5358 ; free virtual = 14047
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'loto' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'tirage' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'automate' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:21]
+INFO: [Synth 8-256] done synthesizing module 'automate' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'registres' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'registres' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd:23]
+INFO: [Synth 8-638] synthesizing module 'compteur_valid' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd:15]
+INFO: [Synth 8-256] done synthesizing module 'compteur_valid' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd:15]
+INFO: [Synth 8-638] synthesizing module 'compteur1_49' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'compteur1_49' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd:16]
+INFO: [Synth 8-638] synthesizing module 'led_pwm' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'led_pwm' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'tirage' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'compteur_modulo6' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-256] done synthesizing module 'compteur_modulo6' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-638] synthesizing module 'diviseur_freq' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd:18]
+ Parameter n_fast bound to: 15 - type: integer
+ Parameter n_slow bound to: 25 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'diviseur_freq' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd:18]
+INFO: [Synth 8-638] synthesizing module 'mux6_1' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:20]
+WARNING: [Synth 8-614] signal 'I_2' is read in the process but is not in the sensitivity list [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'mux6_1' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:20]
+INFO: [Synth 8-638] synthesizing module 'transcodeur7s_d_u_transcod_int' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-256] done synthesizing module 'transcodeur7s_d_u_transcod_int' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-638] synthesizing module 'modulo4' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'modulo4' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'loto' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd:21]
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2428.477 ; gain = 498.438 ; free physical = 5282 ; free virtual = 13971
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2446.289 ; gain = 516.250 ; free physical = 5274 ; free virtual = 13963
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2446.289 ; gain = 516.250 ; free physical = 5274 ; free virtual = 13963
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2446.289 ; gain = 0.000 ; free physical = 5274 ; free virtual = 13962
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+Finished Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/loto_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/loto_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.039 ; gain = 0.000 ; free physical = 5252 ; free virtual = 13942
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.039 ; gain = 0.000 ; free physical = 5252 ; free virtual = 13942
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5255 ; free virtual = 13945
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5255 ; free virtual = 13945
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5254 ; free virtual = 13945
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'SR_STATE_reg' in module 'automate'
+---------------------------------------------------------------------------------------------------
+ State | New Encoding | Previous Encoding
+---------------------------------------------------------------------------------------------------
+ st_wait_failed | 000 | 000
+ st_counting | 001 | 010
+ st_compar | 010 | 011
+ st_store | 011 | 100
+ st_wait_success | 100 | 001
+ st_end_red | 101 | 110
+ st_end_green | 110 | 101
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'SR_STATE_reg' using encoding 'sequential' in module 'automate'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5251 ; free virtual = 13942
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 6 Bit Adders := 1
+ 2 Input 5 Bit Adders := 1
+ 2 Input 3 Bit Adders := 2
+ 2 Input 2 Bit Adders := 1
++---Registers :
+ 6 Bit Registers := 7
+ 5 Bit Registers := 2
+ 3 Bit Registers := 2
+ 2 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 7 Bit Muxes := 1
+ 4 Input 7 Bit Muxes := 1
+ 4 Input 4 Bit Muxes := 1
+ 7 Input 3 Bit Muxes := 1
+ 2 Input 3 Bit Muxes := 4
+ 2 Input 2 Bit Muxes := 1
+ 7 Input 1 Bit Muxes := 11
+ 2 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5225 ; free virtual = 13922
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5213 ; free virtual = 13924
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5213 ; free virtual = 13924
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5209 ; free virtual = 13920
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-------+------+
+| |Cell |Count |
++------+-------+------+
+|1 |BUFG | 2|
+|2 |CARRY4 | 7|
+|3 |LUT1 | 3|
+|4 |LUT2 | 11|
+|5 |LUT3 | 10|
+|6 |LUT4 | 15|
+|7 |LUT5 | 11|
+|8 |LUT6 | 43|
+|9 |FDCE | 84|
+|10 |FDPE | 2|
+|11 |FDRE | 3|
+|12 |IBUF | 4|
+|13 |OBUF | 17|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.039 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2594.039 ; gain = 516.250 ; free physical = 5207 ; free virtual = 13917
+Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2594.047 ; gain = 664.000 ; free physical = 5207 ; free virtual = 13917
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.047 ; gain = 0.000 ; free physical = 5506 ; free virtual = 14217
+INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.047 ; gain = 0.000 ; free physical = 5504 ; free virtual = 14216
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: ad434a8
+INFO: [Common 17-83] Releasing license: Synthesis
+42 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2594.047 ; gain = 1022.168 ; free physical = 5505 ; free virtual = 14217
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2097.210; main = 1756.832; forked = 398.990
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3655.121; main = 2594.043; forked = 1061.078
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2618.051 ; gain = 0.000 ; free physical = 5505 ; free virtual = 14216
+INFO: [Common 17-1381] The checkpoint '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/loto.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file loto_utilization_synth.rpt -pb loto_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 11:55:22 2025...
diff --git a/LOTO/LOTO.runs/synth_1/runme.sh b/LOTO/LOTO.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..bcd9f708fe0142e93123d6169522ae5b22ffa1e3
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin
+else
+ PATH=/opt/img/Vivado2024.1/Vitis/2024.1/bin:/opt/img/Vivado2024.1/Vivado/2024.1/ids_lite/ISE/bin/lin64:/opt/img/Vivado2024.1/Vivado/2024.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log loto.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
diff --git a/LOTO/LOTO.runs/synth_1/vivado.jou b/LOTO/LOTO.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..dc10ae4d632e745ccc0ca44229efb086542939af
--- /dev/null
+++ b/LOTO/LOTO.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 11:54:22 2025
+# Process ID: 55157
+# Current directory: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1
+# Command line: vivado -log loto.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source loto.tcl
+# Log file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/loto.vds
+# Journal file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/vivado.jou
+# Running On :fl-tp-br-664
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :900.021 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16648 MB
+# Swap memory :4294 MB
+# Total Virtual :20943 MB
+# Available Virtual :16390 MB
+#-----------------------------------------------------------
+source loto.tcl -notrace
diff --git a/LOTO/LOTO.runs/synth_1/vivado.pb b/LOTO/LOTO.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..95eff09a4bb418a040f58580e5dc69733a31d025
Binary files /dev/null and b/LOTO/LOTO.runs/synth_1/vivado.pb differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/compile.log b/LOTO/LOTO.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000000000000000000000000000000000000..40d8324737cdac2149cedb19867994dd634939f2
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,8 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/compile.sh b/LOTO/LOTO.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3e8eeabfef197f64d55927bf8e7a5bd016da36c5
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Wed Feb 12 11:39:09 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj"
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl b/LOTO/LOTO.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg_behav.wdb b/LOTO/LOTO.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..d11da2450dd32cd9342b1780679d0fd56685b897
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/compteur_modulo6_tb_arch_cfg_behav.wdb differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log b/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000000000000000000000000000000000000..605c691bb326e62196d2ba4a5cf44ff1a645f839
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,28 @@
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_automate of entity xil_defaultlib.automate [automate_default]
+Compiling architecture a_registres of entity xil_defaultlib.registres [registres_default]
+Compiling architecture a_compteur_valid of entity xil_defaultlib.compteur_valid [compteur_valid_default]
+Compiling architecture compteur_a of entity xil_defaultlib.compteur1_49 [compteur1_49_default]
+Compiling architecture arch of entity xil_defaultlib.led_pwm [led_pwm_default]
+Compiling architecture a_tirage of entity xil_defaultlib.tirage [tirage_default]
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture behavioral of entity xil_defaultlib.diviseur_freq [\diviseur_freq(n_fast=0,n_slow=3...]
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture transcod_int of entity xil_defaultlib.transcodeur7s_d_u [transcodeur7s_d_u_default]
+Compiling architecture modulo4_a of entity xil_defaultlib.modulo4 [modulo4_default]
+Compiling architecture arch of entity xil_defaultlib.loto [\loto(n_fast=0,n_slow=3)\]
+Compiling architecture ar of entity xil_defaultlib.loto_tb [loto_tb]
+Built simulation snapshot loto_tb_ar_cfg_behav
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.sh b/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4c019e12c0d6c24bf967ea178e882b10306d8530
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Wed Feb 12 11:39:11 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl b/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb b/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..73aece90432d26ebb601900eb4f686f2ecdb806e
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg_behav.wdb differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj b/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..81dda96880eb85aaa245b404ea63eae26efaa141
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/loto_tb_ar_cfg_vhdl.prj
@@ -0,0 +1,18 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../../src/automate.vhd" \
+"../../../../../src/compteur1_49.vhd" \
+"../../../../../src/compteur_modulo6.vhd" \
+"../../../../../src/compteur_valid.vhd" \
+"../../../../../src/diviseur_freq.vhd" \
+"../../../../../src/led_pwm.vhd" \
+"../../../../../src/registres.vhd" \
+"../../../../../src/tirage.vhd" \
+"../../../../../src/mux6_1.vhd" \
+"../../../../../src/transcodeur7s_d_u.vhd" \
+"../../../../../src/modulo4.vhd" \
+"../../../../../src/loto.vhd" \
+"../../../../../src/loto_tb.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl b/LOTO/LOTO.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg_behav.wdb b/LOTO/LOTO.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..8642eaf721df78927cdb00d610ded869954d46d7
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/mux6_1_tb_arch_cfg_behav.wdb differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/simulate.log b/LOTO/LOTO.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000000000000000000000000000000000000..3a14ee624a9f4bdaa2d11739bbf5670fa4d48b6c
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/simulate.sh b/LOTO/LOTO.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..585a6d49ff6c5e1158779b1c03b13e6dd6670866
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+# ****************************************************************************
+# Vivado (TM) v2024.1 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Wed Feb 12 11:39:13 CET 2025
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch loto_tb_ar_cfg.tcl -log simulate.log"
+xsim loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch loto_tb_ar_cfg.tcl -log simulate.log
+
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xelab.pb b/LOTO/LOTO.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e96f1a9e120e79894d59ae04c782374cc444d5fb
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5ae6a8bef5e02315ec5e890ce9518059ab9b680b
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "compteur_modulo6_tb_arch_cfg_behav" "xil_defaultlib.compteur_modulo6_tb_arch_cfg" -log "elaborate.log"
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..ed748663423f2faf9d2b4e00dcdcfb01700a6ab3
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.c b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..ffee61c973c383c188b87776a6f5da9b7f73afc1
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.c
@@ -0,0 +1,113 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_25(char*, char *);
+IKI_DLLESPEC extern void execute_26(char*, char *);
+IKI_DLLESPEC extern void execute_27(char*, char *);
+IKI_DLLESPEC extern void execute_23(char*, char *);
+IKI_DLLESPEC extern void execute_24(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[7] = {(funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_23, (funcp)execute_24, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_3};
+const int NumRelocateId= 7;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc", (void **)funcTab, 7);
+ iki_vhdl_file_variable_register(dp + 3016);
+ iki_vhdl_file_variable_register(dp + 3072);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..5b05482f2aa378ffba9085ddeca40bd34a4d53d7
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.dbg b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..e884e264b83902646086d892b643149cc56f0887
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.dbg differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.mem b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..4305e69ac72988a32fb9da57e4a98df3bf6e76b7
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.mem differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..a6252acea219c274f4b536412d808147239c0c98
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.reloc differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rlx b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..e95bdd7e868e0f9832f5726b0f0b08acbe400f01
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 1617504403332869057 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk\" \"xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/compteur_modulo6_tb_arch_cfg_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rtti b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..376739d39c499ce14db51e41cbd62d9287fab817
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.svtype b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..6dc1deb65a85fafe2dcea36f677983510a180e28
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.type b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..59528b4e45f7e6d8c1919d8f335d86acf8f4f8e7
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.xdbg b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..b8dcc8d8ace3b23c3c5a7b4e5e2f533623890582
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsim.xdbg differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimSettings.ini b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..ada0faf7f09a3d55a5071ce46bcff31395d8234c
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=188
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=196
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
+OBJECT_NAME_COLUMN_WIDTH=176
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimcrash.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..962a5860a43318c3ff6be1fe0de9128a3a5c87cc
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimkernel.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..cce55e9c14bf3ab84ae0309c72b7f9a94cde35f4
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/compteur_modulo6_tb_arch_cfg_behav/xsimk -simmode gui -wdb compteur_modulo6_tb_arch_cfg_behav.wdb -simrunnum 0 -socket 38951
+Design successfully loaded
+Design Loading Memory Usage: 20148 KB (Peak: 20744 KB)
+Design Loading CPU Usage: 30 ms
+Simulation completed
+Simulation Memory Usage: 110084 KB (Peak: 159416 KB)
+Simulation CPU Usage: 30 ms
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/Compile_Options.txt b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2fb2e349f232bbe5522acd7897d9a0410892dbdf
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "loto_tb_ar_cfg_behav" "xil_defaultlib.loto_tb_ar_cfg" -log "elaborate.log"
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/TempBreakPointFile.txt b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..99e7acb22a72b95875a6bd5b65be34cc0b93ac1b
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.c b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0f211186accabeb63c98fe97400e399d7dd14cff
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.c
@@ -0,0 +1,152 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_75(char*, char *);
+IKI_DLLESPEC extern void execute_76(char*, char *);
+IKI_DLLESPEC extern void execute_77(char*, char *);
+IKI_DLLESPEC extern void execute_78(char*, char *);
+IKI_DLLESPEC extern void execute_68(char*, char *);
+IKI_DLLESPEC extern void execute_69(char*, char *);
+IKI_DLLESPEC extern void execute_70(char*, char *);
+IKI_DLLESPEC extern void execute_71(char*, char *);
+IKI_DLLESPEC extern void execute_72(char*, char *);
+IKI_DLLESPEC extern void execute_73(char*, char *);
+IKI_DLLESPEC extern void execute_74(char*, char *);
+IKI_DLLESPEC extern void execute_42(char*, char *);
+IKI_DLLESPEC extern void execute_43(char*, char *);
+IKI_DLLESPEC extern void execute_44(char*, char *);
+IKI_DLLESPEC extern void execute_45(char*, char *);
+IKI_DLLESPEC extern void execute_46(char*, char *);
+IKI_DLLESPEC extern void execute_47(char*, char *);
+IKI_DLLESPEC extern void execute_48(char*, char *);
+IKI_DLLESPEC extern void execute_28(char*, char *);
+IKI_DLLESPEC extern void execute_30(char*, char *);
+IKI_DLLESPEC extern void execute_32(char*, char *);
+IKI_DLLESPEC extern void execute_33(char*, char *);
+IKI_DLLESPEC extern void execute_34(char*, char *);
+IKI_DLLESPEC extern void execute_36(char*, char *);
+IKI_DLLESPEC extern void execute_37(char*, char *);
+IKI_DLLESPEC extern void execute_39(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_50(char*, char *);
+IKI_DLLESPEC extern void execute_51(char*, char *);
+IKI_DLLESPEC extern void execute_53(char*, char *);
+IKI_DLLESPEC extern void execute_54(char*, char *);
+IKI_DLLESPEC extern void execute_55(char*, char *);
+IKI_DLLESPEC extern void execute_57(char*, char *);
+IKI_DLLESPEC extern void execute_59(char*, char *);
+IKI_DLLESPEC extern void execute_60(char*, char *);
+IKI_DLLESPEC extern void execute_61(char*, char *);
+IKI_DLLESPEC extern void execute_62(char*, char *);
+IKI_DLLESPEC extern void execute_63(char*, char *);
+IKI_DLLESPEC extern void execute_65(char*, char *);
+IKI_DLLESPEC extern void execute_66(char*, char *);
+IKI_DLLESPEC extern void execute_67(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_2(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_8(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_9(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[46] = {(funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_47, (funcp)execute_48, (funcp)execute_28, (funcp)execute_30, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_36, (funcp)execute_37, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_50, (funcp)execute_51, (funcp)execute_53, (funcp)execute_54, (funcp)execute_55, (funcp)execute_57, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_2, (funcp)transaction_8, (funcp)transaction_9};
+const int NumRelocateId= 46;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc", (void **)funcTab, 46);
+ iki_vhdl_file_variable_register(dp + 13864);
+ iki_vhdl_file_variable_register(dp + 13920);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/loto_tb_ar_cfg_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/loto_tb_ar_cfg_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..0a03bc1b006d514728558952df39beeca889fd80
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.dbg b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..118a9db509f69ad44028dfe5ada9b423c78ad2e7
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.dbg differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.mem b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..f52e61c0f3db4ca666ee1c8bd2dacb2aa2b995bd
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.mem differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..cf92797bb421897baf519cfde986cc0714206151
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.reloc differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..7bd4a87b92bfb575468e3c91f434ae2c8de22b18
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 5292524187475659302 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/loto_tb_ar_cfg_behav/xsimk\" \"xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/loto_tb_ar_cfg_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rtti b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..c62de5339b72c96447708d83d879d024c0cbfd7d
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.rtti differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..6dc1deb65a85fafe2dcea36f677983510a180e28
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.svtype differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.type b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..f8afe5bd4f635221ad276f30c838eb283b5a565a
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.type differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.xdbg b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..104a89d78068a99e621a725f6e4748e34c428e94
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsim.xdbg differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimSettings.ini b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..8d10fc5e1be52d9b5a6ffd4307a874559221665b
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=199
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=209
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
+OBJECT_NAME_COLUMN_WIDTH=106
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimcrash.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimk b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..2a449619d62b82d115204e8a6eb0a0ff97a67f6c
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimk differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimkernel.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..25efd5f60a037a355157cd64fa1389b15670a9af
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/loto_tb_ar_cfg_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/loto_tb_ar_cfg_behav/xsimk -simmode gui -wdb loto_tb_ar_cfg_behav.wdb -simrunnum 0 -socket 59409
+Design successfully loaded
+Design Loading Memory Usage: 20192 KB (Peak: 20756 KB)
+Design Loading CPU Usage: 20 ms
+Simulation completed
+Simulation Memory Usage: 101928 KB (Peak: 159460 KB)
+Simulation CPU Usage: 160 ms
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/Compile_Options.txt b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..3523bba8f96673904d3c511564ada706d0c8fa09
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "mux6_1_tb_arch_cfg_behav" "xil_defaultlib.mux6_1_tb_arch_cfg" -log "elaborate.log"
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/TempBreakPointFile.txt b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_0.lnx64.o b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..2b3ff8d6cc55ae8780bde919a74284e4d94abf78
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_0.lnx64.o differ
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.c b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..8998a5e51509c604d4a0813c3192324f0237cd7a
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.c
@@ -0,0 +1,111 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_22(char*, char *);
+IKI_DLLESPEC extern void execute_23(char*, char *);
+IKI_DLLESPEC extern void execute_21(char*, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_8(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[5] = {(funcp)execute_22, (funcp)execute_23, (funcp)execute_21, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_8};
+const int NumRelocateId= 5;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc", (void **)funcTab, 5);
+ iki_vhdl_file_variable_register(dp + 3592);
+ iki_vhdl_file_variable_register(dp + 3648);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc");
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc");
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_xsimdir_location_if_remapped(argc, argv) ;
+ iki_set_sv_type_file_path_name("xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.lnx64.o b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..b7efc309c9184c9e4aa6bae6e628adf7b336f9ef
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.dbg b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.dbg
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index 0000000000000000000000000000000000000000..a94274287361f9c148956c1a9082312b1fedf9b0
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.mem b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.mem
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index 0000000000000000000000000000000000000000..42f4acd08e910b85fccd6c5ee0391425406f5cec
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.reloc
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index 0000000000000000000000000000000000000000..758533509da4a79d413d013748ed66de182f3a60
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rlx b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..f6016fc7b14f9cbd861523b5c3a0686c1203ec7e
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 2904300941018487095 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg" ,
+ buildDate : "May 22 2024" ,
+ buildTime : "18:54:44" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk\" \"xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/mux6_1_tb_arch_cfg_behav/obj/xsim_1.lnx64.o\" -L\"/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o\" -lrdi_simulator_kernel -L/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/img/Vivado2024.1/Vivado/2024.1/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rtti b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsim.rtti
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimSettings.ini b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..c9e7b636e67fefcd526bbc8c5c1a8e0095f78ef8
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=118
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=125
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
+OBJECT_NAME_COLUMN_WIDTH=151
+OBJECT_VALUE_COLUMN_WIDTH=49
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimcrash.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimcrash.log
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index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk
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index 0000000000000000000000000000000000000000..a37a79aa94883fc4ba30ced84d83d65b3a59471e
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimkernel.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..77499e67b3fe57de85515073c457423001a7cfe5
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/mux6_1_tb_arch_cfg_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/mux6_1_tb_arch_cfg_behav/xsimk -simmode gui -wdb mux6_1_tb_arch_cfg_behav.wdb -simrunnum 0 -socket 33283
+Design successfully loaded
+Design Loading Memory Usage: 20148 KB (Peak: 20744 KB)
+Design Loading CPU Usage: 20 ms
+Simulation completed
+Simulation Memory Usage: 101884 KB (Peak: 159416 KB)
+Simulation CPU Usage: 70 ms
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/automate.vdb b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/automate.vdb
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/transcodeur7s_d_u.vdb b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/transcodeur7s_d_u.vdb
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index 0000000000000000000000000000000000000000..50c7bd8962fdab50894b70801ca7247d9e4d3136
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diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..309efec3d96e215a77fb76d1eb041f0551089841
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,19 @@
+0.7
+2020.2
+May 22 2024
+18:54:44
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd,1739356744,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd,,,automate,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd,,,compteur1_49,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd,1739354474,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,,,compteur_modulo6,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd,1739350592,vhdl,,,,compteur_modulo6_tb;compteur_modulo6_tb_arch_cfg,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd,,,compteur_valid,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,,,diviseur_freq,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd,,,led_pwm,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd,,,loto,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd,1739350592,vhdl,,,,loto_tb;loto_tb_ar_cfg,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,,,modulo4,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd,1739352786,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,,,mux6_1,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd,1739350592,vhdl,,,,mux6_1_tb;mux6_1_tb_arch_cfg,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd,,,registres,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,,,tirage,,,,,,,,
+/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd,1739350592,vhdl,/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd,,,transcodeur7s_d_u,,,,,,,,
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.ini b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..e8199b2597fb201d9f6673368b7b003f11b596e4
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xvhdl.log b/LOTO/LOTO.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000000000000000000000000000000000000..40d8324737cdac2149cedb19867994dd634939f2
--- /dev/null
+++ b/LOTO/LOTO.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,8 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
diff --git a/LOTO/LOTO.sim/sim_1/behav/xsim/xvhdl.pb b/LOTO/LOTO.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a49301e53ce70fd1b6466cbfc68f8cf1d2c8930b
Binary files /dev/null and b/LOTO/LOTO.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/LOTO/LOTO.xpr b/LOTO/LOTO.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..b56773ef96913e3b1faab5de332574d4343af5a3
--- /dev/null
+++ b/LOTO/LOTO.xpr
@@ -0,0 +1,323 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="5000217eb5d949a689c08e2b7c50b9b3"/>
+ <Option Name="Part" Val="xc7a100tcsg324-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+ <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+ <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+ <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+ <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="14"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="32">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../src/automate.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur1_49.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_valid.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/diviseur_freq.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/led_pwm.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/registres.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/tirage.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_d_u.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/modulo4.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/loto.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo4.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/compteur_modulo6_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/mux6_1_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../src/transcodeur7s_u.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../src/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <File Path="$PPRDIR/../src/loto_tb.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="loto_tb_ar_cfg"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="22">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/docs/.nfs00000000004d6ef90000009f b/docs/.nfs00000000004d6ef90000009f
new file mode 100644
index 0000000000000000000000000000000000000000..2d6ce0dc47bcfde9638963fe7336dca3743401fc
--- /dev/null
+++ b/docs/.nfs00000000004d6ef90000009f
@@ -0,0 +1,67 @@
+# TP Loto
+
+Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
+
+## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+
+On renseigne les signaux I_0, I_1, I_3, I_4, I_5 et I_sel. A chaque fois qu'une modification est notée sur l'un de ces signaux, le process se lance. Il est sensible à une modification de chaun de ces signaux.
+
+
+## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+
+Lorsqu'on retire un when des combinaisons d'entrées du module, la commande when others attribue automatiquement à cette combinaison non renseignée le signal de sortie. On a donc pas de problèmes de simulation mais deux combinaisons qui donnent la même sortie.
+En revanche, lorsque le when others est supprimé, il y'a des combinaisons non traitées, la simulation ne se lance alors pas.
+
+
+## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+Ce test n'est pas complètement concluant. Le multiplexer est fonctionnel mais le programme test bench ne couvre pas les cas où I_sel est égal à 6 ou 7. Le when others du process permet de son côté de couvrir ces cas.
+Il faudrait modifier la condition dans le test bench pour que la variable commande puisse prendre les valeurs 110 et 111.
+
+
+
+
+
+## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+
+On renseigne I_clk, I_rst et I_block. Le processus doit être sensible à chacun de ses signaux.
+
+
+## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
+
+Si le test est imcomplet et c'est la cas ici car on ne teste pas toutes les combinaisosn à chaque état du compteur, on ne peut pas conclure sur un fonctionnement parfait du compteur et ce n'est pas grave car la valeur I_block est indépendante de l'état du compteur. .
+
+
+## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+Le test bench teste toutes les combinaisons possible entre les signaux d'entrée comme par exemple un I_block =1 juste après un I_rst =1. La réinitialisation et le blocage sont fonctionnels ainsi que le comptage de 0 à 5.
+
+
+
+## Question Loto 7 : Combien de processus avez-vous décris ?
+
+Nous avons décris un process.
+
+
+## Question Loto 8 : De quel(s) type(s) sont-ils
+
+c'est un process synchrone.
+
+
+## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+
+Oui, on aurait pu utiliser deux process, l'un synchrone pour passer de l'état présent à l'état futur à chaque front montant d'horloge. Le second est asynchrone et suit l'architecture de la FSM.
+
+## Question Loto 10 : Ce test est-il concluant ? Justifiez.
+
+Oui, le test est concluant. On teste bien tous les états et on a vérifié les attributions de chaque signal lors des fronts montants d'horloge.
+
+## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+
+
+
+
+## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+
+
+## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
diff --git a/docs/.nfs0000000000ce1ef60000004c b/docs/.nfs0000000000ce1ef60000004c
new file mode 100644
index 0000000000000000000000000000000000000000..8a71903ef371eea81e6b8ebeedc27b458aa2d17c
--- /dev/null
+++ b/docs/.nfs0000000000ce1ef60000004c
@@ -0,0 +1,52 @@
+# TP Loto
+
+Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
+
+## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+
+On renseigne les signaux I_0, I_1, I_3, I_4, I_5 et I_sel. A chaque fois qu'une modification est notée sur l'un de ces signaux, le process se lance. Il est sensible à une modification de chaun de ces signaux.
+
+
+## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+
+Lorsqu'on retire un when des combinaisons d'entrées du module, la commande when others attribue automatiquement à cette combinaison non renseignée le signal de sortie. On a donc pas de problèmes de simulation mais deux combinaisons qui donnent la même sortie.
+En revanche, lorsque le when others est supprimé, il y'a des combinaisons non traitées, la simulation ne se lance alors pas.
+
+
+## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+Ce test n'est pas complètement concluant. Le multiplexer est fonctionnel mais le programme test bench ne couvre pas les cas où I_sel est égal à 6 ou 7. Le when others du process permet de son côté de couvrir ces cas.
+Il faudrait modifier la condition dans le test bench pour que la variable commande puisse prendre les valeurs 110 et 111.
+
+
+
+
+
+## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+
+
+## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
+
+
+## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+
+## Question Loto 7 : Combien de processus avez-vous décris ?
+
+
+## Question Loto 8 : De quel(s) type(s) sont-ils
+
+
+## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+
+
+## Question Loto 10 : Ce test est-il concluant ? Justifiez.
+
+
+## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+
+
+## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+
+
+## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
diff --git a/docs/.nfs0000000001b52a4d0000004b b/docs/.nfs0000000001b52a4d0000004b
new file mode 100644
index 0000000000000000000000000000000000000000..df35c9a4aef82bbe9f4b06482d9cd99f3861512c
--- /dev/null
+++ b/docs/.nfs0000000001b52a4d0000004b
@@ -0,0 +1,52 @@
+# TP Loto
+
+Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
+
+## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+
+On renseigne les signaux I_0, I_1, I_3, I_4, I_5 et I_sel. A chaque fois qu'une modification est notée sur l'un de ces signaux, le process se lance. Il est sensible à une modification de chaun de ces signaux.
+
+
+## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+
+Lorsqu'on retire un when des combinaisons d'entrées du module, la commande when others attribue automatiquement à cette combinaison non renseignée le signal de sortie. On a donc pas de problèmes de simulation mais deux combinaisons qui donnent la même sortie.
+En revanche, lorsque le when others est supprimé, il y'a des combinaisons non traitées, la simulation ne se lance alors pas.
+
+
+## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+Ce test n'est pas complètement concluant. Le multiplexer est fonctionnel mais le programme test bench ne couvre pas les cas où I_sel est égal à 6 ou 7. Le when others du process permet de son côté de couvrir ces cas.
+Il faudrait modifier la condition dans le test bench pour que la variable commande puisse prendre les valeurs 110 et 111.
+
+
+
+
+
+## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+
+
+## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
+
+
+## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+
+## Question Loto 7 : Combien de processus avez-vous décris ?
+
+
+## Question Loto 8 : De quel(s) type(s) sont-ils
+
+
+## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+
+
+## Question Loto 10 : Ce test est-il concluant ? Justifiez.
+
+
+## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+
+
+## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+
+
+## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
diff --git a/docs/.nfs0000000001b555ac00000049 b/docs/.nfs0000000001b555ac00000049
new file mode 100644
index 0000000000000000000000000000000000000000..5d0c7cfaeef4997f6ca693f90473adbb393348f8
--- /dev/null
+++ b/docs/.nfs0000000001b555ac00000049
@@ -0,0 +1,49 @@
+# TP Loto
+
+Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
+
+## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+
+On renseigne les signaux I_0, I_1, I_3, I_4, I_5 et I_sel. A chaque fois qu'une modification est notée sur l'un de ces signaux, le process se lance. Il est sensible à une modification de chaun de ces signaux.
+
+
+## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+
+Lorsqu'on retire un when des combinaisons d'entrées du module, la commande when others attribue automatiquement à cette combinaison non renseignée le signal de sortie. On a donc pas de problèmes de simulation mais deux combinaisons qui donnent la même sortie.
+En revanche, lorsque le when others est supprimé, il y'a des combinaisons non traitées, la simulation ne se lance alors pas.
+
+
+## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+Ce test est concluant, on observe bien que le singla
+
+
+
+## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+
+
+## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
+
+
+## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+
+## Question Loto 7 : Combien de processus avez-vous décris ?
+
+
+## Question Loto 8 : De quel(s) type(s) sont-ils
+
+
+## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+
+
+## Question Loto 10 : Ce test est-il concluant ? Justifiez.
+
+
+## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+
+
+## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+
+
+## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
diff --git a/docs/.nfs0000000001b82afb0000009b b/docs/.nfs0000000001b82afb0000009b
new file mode 100644
index 0000000000000000000000000000000000000000..2c7e12b06393b69a4841a9932e88e442c8786ae9
--- /dev/null
+++ b/docs/.nfs0000000001b82afb0000009b
@@ -0,0 +1,52 @@
+# TP Loto
+
+Énoncé du TP : [https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/](https://tp-vhdl.gitlab-pages.imt-atlantique.fr/loto/)
+
+## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+
+On renseigne les signaux I_0, I_1, I_3, I_4, I_5 et I_sel. A chaque fois qu'une modification est notée sur l'un de ces signaux, le process se lance. Il est sensible à une modification de chaun de ces signaux.
+
+
+## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+
+Lorsqu'on retire un when des combinaisons d'entrées du module, la commande when others attribue automatiquement à cette combinaison non renseignée le signal de sortie. On a donc pas de problèmes de simulation mais deux combinaisons qui donnent la même sortie.
+En revanche, lorsque le when others est supprimé, il y'a des combinaisons non traitées, la simulation ne se lance alors pas.
+
+
+## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+Ce test n'est pas complètement concluant. Le multiplexer est fonctionnel mais le programme test bench ne couvre pas les cas où I_sel est égal à 6 ou 7. Le when others du process permet de son côté de couvrir ces cas.
+Il faudrait modifier la condition dans le test bench pour que la variable commande puisse prendre les valeurs 110 et 111.
+
+
+
+
+
+## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+
+
+## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
+
+
+## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+
+
+## Question Loto 7 : Combien de processus avez-vous décris ?
+
+
+## Question Loto 8 : De quel(s) type(s) sont-ils
+
+
+## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+
+
+## Question Loto 10 : Ce test est-il concluant ? Justifiez.
+
+
+## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+
+
+## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+
+
+## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
diff --git a/docs/compte-rendu.md b/docs/compte-rendu.md
index bcc655d66913928d7dcdede3d6b09390249d6a4f..ecd5437a2ba9c9308991707994cb430440f5819c 100644
--- a/docs/compte-rendu.md
+++ b/docs/compte-rendu.md
@@ -4,38 +4,70 @@
## Question Loto 1 : Quels sont les signaux à renseigner dans la liste de sensibilité (si vous utilisez un process explicite) ?
+On renseigne les signaux I_0, I_1, I_3, I_4, I_5 et I_sel. A chaque fois qu'une modification est notée sur l'un de ces signaux, le process se lance. Il est sensible à une modification de chaun de ces signaux.
+
## Question Loto 2 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ?
+Lorsqu'on retire un when des combinaisons d'entrées du module, la commande when others attribue automatiquement à cette combinaison non renseignée le signal de sortie. On a donc pas de problèmes de simulation mais deux combinaisons qui donnent la même sortie.
+En revanche, lorsque le when others est supprimé, il y'a des combinaisons non traitées, la simulation ne se lance alors pas.
+
## Question Loto 3 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+Ce test n'est pas complètement concluant. Le multiplexer est fonctionnel mais le programme test bench ne couvre pas les cas où I_sel est égal à 6 ou 7. Le when others du process permet de son côté de couvrir ces cas.
+Il faudrait modifier la condition dans le test bench pour que la variable commande puisse prendre les valeurs 110 et 111.
+
+
+
+
## Question Loto 4 : Quel(s) signal(aux) doit on renseigner dans la liste de sensibilité de ce processus séquentiel ? Pourquoi ?
+On renseigne I_clk, I_rst et I_block. Le processus doit être sensible à chacun de ses signaux.
+
## Question Loto 5 : Que se passe-t-il si le test est incomplet, c’est-à -dire s’il ne couvre pas toutes les combinaisons d’entrées du module ? Est-ce grave ici ?
+Si le test est imcomplet et c'est la cas ici car on ne teste pas toutes les combinaisosn à chaque état du compteur, on ne peut pas conclure sur un fonctionnement parfait du compteur et ce n'est pas grave car la valeur I_block est indépendante de l'état du compteur. .
+
## Question Loto 6 : Ce test est-il concluant ? Est-il suffisant pour valider le module ? Justifiez.
+Le test bench teste toutes les combinaisons possible entre les signaux d'entrée comme par exemple un I_block =1 juste après un I_rst =1. La réinitialisation et le blocage sont fonctionnels ainsi que le comptage de 0 à 5.
+
+
## Question Loto 7 : Combien de processus avez-vous décris ?
+Nous avons décris un process.
+
## Question Loto 8 : De quel(s) type(s) sont-ils
+c'est un process synchrone.
+
## Question Loto 9 : Serait-il possible de décrire cette machine d'état de manière différente, en terme de nombre et de type de process ?
+Oui, on aurait pu utiliser deux process, l'un synchrone pour passer de l'état présent à l'état futur à chaque front montant d'horloge. Le second est asynchrone et suit l'architecture de la FSM.
## Question Loto 10 : Ce test est-il concluant ? Justifiez.
+Oui, le test est concluant. On teste bien tous les états et on a vérifié les attributions de chaque signal lors des fronts montants d'horloge.
## Question Loto 11 : Le circuit inféré par l’outil est-il conforme à l’attendu ? Sinon, en quoi diffère-t-il et est-ce lié à une erreur de description VHDL ?
+Il n'y a pas le bufr présent sur le design du sujet. Non , il n'ya pas d'erreur.
## Question Loto 12 : Quelles sont les ressources utilisées sur le FPGA ? En quelle quantité/proportion des ressources disponibles ? Des **LATCHES** sont-ils utilisés ? Est-ce positif ou pas, pourquoi ?
+
+
+On n'utilise pas de latches. C'est positif car on n'a ainsi pas de mémoire asynchrone.
+
## Question Loto 13 : Le tirage est-il aléatoire pour un humain ? pour une machine ? Justifiez.
+
+Il est aléatoire pour l'humain qui ne voit ce qu'il se passe dans le compteur tirage mais ne l'est pour la machine qui suit le cycle du compteur.
+
diff --git a/docs/question12.png b/docs/question12.png
new file mode 100644
index 0000000000000000000000000000000000000000..f6ab83958951f2e6c49993added293a971ab3073
Binary files /dev/null and b/docs/question12.png differ
diff --git a/docs/question3-1.png b/docs/question3-1.png
new file mode 100644
index 0000000000000000000000000000000000000000..918e065e397e7c330d5a300782332990b4682541
Binary files /dev/null and b/docs/question3-1.png differ
diff --git a/docs/question3-2.png b/docs/question3-2.png
new file mode 100644
index 0000000000000000000000000000000000000000..9f956f6af85db29269df32eee437cf1deab5da1e
Binary files /dev/null and b/docs/question3-2.png differ
diff --git a/docs/question6.png b/docs/question6.png
new file mode 100644
index 0000000000000000000000000000000000000000..2b8fc3f4447b20c20e44a9a67800e5eb5a9d8ded
Binary files /dev/null and b/docs/question6.png differ
diff --git a/src/automate.vhd b/src/automate.vhd
index 1ccb931d7fe12fa743f62a8460c95a6d7fb05343..46b318325fea475bb0d281f7f89193bcf13676d6 100644
--- a/src/automate.vhd
+++ b/src/automate.vhd
@@ -36,11 +36,12 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
- __BLANK_TO_FILL__
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
elsif rising_edge(I_clk)then
case SR_STATE is
- case SR_STATE is
-
when st_wait_success =>
O_l_green <= '1';
O_l_red <= '0';
@@ -50,10 +51,67 @@ begin
SR_STATE <= st_counting;
end if;
- when __BLANK_TO_FILL__
-
- __BLANK_TO_FILL__
+ when st_counting =>
+
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '1';
+ O_store <= '0';
+ if I_button = '0' then
+ SR_STATE <= st_compar;
+ end if;
+
+ when st_compar =>
+
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_invalide = '0' then
+ SR_STATE <= st_store;
+ else
+ SR_STATE <= st_wait_failed;
+ end if;
+ when st_wait_failed =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_button = '1' then
+ SR_STATE <= st_counting;
+ end if;
+
+ when st_store =>
+ O_l_green <= '0';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '1';
+ if I_end ='0' then
+ SR_STATE <= st_wait_success;
+ elsif I_end='1' then
+ SR_STATE <= st_end_red;
+ end if;
+
+ when st_end_red =>
+ O_l_green <= '0';
+ O_l_red <= '1';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_clk_display ='1' then
+ SR_STATE <= st_end_green;
+ end if;
+
+
+ when st_end_green =>
+ O_l_green <= '1';
+ O_l_red <= '0';
+ O_counting <= '0';
+ O_store <= '0';
+ if I_clk_display ='0' then
+ SR_STATE <= st_end_red;
+ end if;
+
end case;
end if;
end process;
diff --git a/src/compteur_modulo6.vhd b/src/compteur_modulo6.vhd
index 7962a902901eb77362e130eb770ac5481684623d..910b4a4c5e9cede944c19d00e34b5aa629bfef25 100644
--- a/src/compteur_modulo6.vhd
+++ b/src/compteur_modulo6.vhd
@@ -20,12 +20,18 @@ architecture modulo6_a of compteur_modulo6 is
begin
- process (_BLANK_)
+ process (I_clk, I_rst, I_block)
begin
if I_rst = '1' then
- _BLANK_
+ SR_Counter <= "000";
elsif rising_edge(I_clk) then
- _BLANK_
+ if (I_block= '0') then
+ if (SR_Counter = "101") then
+ SR_Counter <= "000" ;
+ else
+ SR_Counter<= SR_Counter +1;
+ end if;
+ end if ;
end if;
end process;
diff --git a/src/mux6_1.vhd b/src/mux6_1.vhd
index a689bef6c26f4dd324c13f5d0653dfd294f6d097..7222323235e7e83cb9de056ab5b8f3e5b20e3156 100644
--- a/src/mux6_1.vhd
+++ b/src/mux6_1.vhd
@@ -20,8 +20,27 @@ end mux6_1;
architecture a_mux6_1 of mux6_1 is
begin
-__BLANK_TO_FILL__
-
-
+process(I_0, I_1, I_3, I_4, I_5,I_sel)
+begin
+ case I_sel is
+ when "000" =>
+ O_mux6 <= I_0;
+
+ when "001"=>
+ O_mux6 <= I_1;
+
+ when "010" =>
+ O_mux6 <= I_2;
+
+ when "011" =>
+ O_mux6 <= I_3;
+
+ when "100" =>
+ O_mux6 <= I_4;
+
+ when others =>
+ O_mux6 <= I_5;
+ end case;
+end process;
end a_mux6_1;
diff --git a/vivado.jou b/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..88b4798e2ab27279a1b483c18d1bd04165476f08
--- /dev/null
+++ b/vivado.jou
@@ -0,0 +1,108 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 09:58:57 2025
+# Process ID: 6007
+# Current directory: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch
+# Command line: vivado
+# Log file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/vivado.log
+# Journal file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/vivado.jou
+# Running On :fl-tp-br-664
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3491.038 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16648 MB
+# Swap memory :4294 MB
+# Total Virtual :20943 MB
+# Available Virtual :19413 MB
+#-----------------------------------------------------------
+start_gui
+create_project LOTO /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO -part xc7a100tcsg324-1
+set_property target_language VHDL [current_project]
+add_files -norecurse {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo4.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_u.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd}
+add_files -fileset sim_1 -norecurse /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd
+add_files -fileset constrs_1 -norecurse /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+set_property used_in_synthesis false [get_files /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd]
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top mux6_1_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source mux6_1_tb_arch_cfg.tcl
+restart
+run 100 us
+restart
+run 100 us
+close_sim
+launch_simulation
+source mux6_1_tb_arch_cfg.tcl
+close_sim
+launch_simulation
+launch_simulation
+launch_simulation
+launch_simulation
+source mux6_1_tb_arch_cfg.tcl
+restart
+run 100 us
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top compteur_modulo6_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source compteur_modulo6_tb_arch_cfg.tcl
+restart
+run 100 us
+restart
+relaunch_sim
+# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top loto_tb_ar_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+update_compile_order -fileset sim_1
+launch_simulation
+launch_simulation
+launch_simulation
+launch_simulation
+launch_simulation
+source loto_tb_ar_cfg.tcl
+restart
+run 100 us
+restart
+run 100 us
+synth_design -rtl -rtl_skip_mlo -name rtl_1
+export_ip_user_files -of_objects [get_files /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc] -no_script -reset -force -quiet
+remove_files -fileset constrs_1 /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc
+add_files -fileset constrs_1 -norecurse /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+wait_on_run impl_1
+open_hw_manager
+connect_hw_server -allow_non_jtag
+open_hw_target
+set_property PROGRAM.FILE {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+current_hw_device [get_hw_devices xc7a100t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+undo
+undo
+close_sim
+current_sim simulation_4
+close_sim
+close_sim
diff --git a/vivado.log b/vivado.log
new file mode 100644
index 0000000000000000000000000000000000000000..f3714aeabe95310e2c493f4c1ef0cd1df05844fc
--- /dev/null
+++ b/vivado.log
@@ -0,0 +1,1144 @@
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Wed Feb 12 09:58:57 2025
+# Process ID: 6007
+# Current directory: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch
+# Command line: vivado
+# Log file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/vivado.log
+# Journal file: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/vivado.jou
+# Running On :fl-tp-br-664
+# Platform :Ubuntu
+# Operating System :Ubuntu 24.04.1 LTS
+# Processor Detail :Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz
+# CPU Frequency :3491.038 MHz
+# CPU Physical cores:4
+# CPU Logical cores :4
+# Host memory :16648 MB
+# Swap memory :4294 MB
+# Total Virtual :20943 MB
+# Available Virtual :19413 MB
+#-----------------------------------------------------------
+start_gui
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa100_2ms:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa100_2ms/1.0/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa100_2ms:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa100_2ms/1.2/1.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa101_2ms:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa101_2ms/1.1/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admpa101_2ms:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admpa101_2ms/1.2/1.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part alpha-data.com:admva600_dev:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/AlphaData/admva600_dev/1.0/1.0/board.xml as part xcvc1902-vsva2197-1mp-i-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v1:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v1/1.2/1.2/board.xml as part xczu3eg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v2:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v2/1.1/1.1/board.xml as part xczu3eg-sbva484-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultra96v2:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultra96v2/1.2/1.2/board.xml as part xczu3eg-sbva484-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_7ev_cc:part0:1.5 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_7ev_cc/1.5/1.5/board.xml as part xczu7ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_eg_iocc_production:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_3eg_iocc/1.2/1.2/board.xml as part xczu3eg-sfva625-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:ultrazed_eg_pciecc_production:part0:1.3 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/ultrazed_3eg_pciecc/1.3/1.3/board.xml as part xczu3eg-sfva625-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part avnet.com:zuboard_1cg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Avnet/zub1cg/1.0/1.0/board.xml as part xczu1cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-25/E.0/1.0/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-25:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-25/1.1/1.1/board.xml as part xc7s25csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-50/B.0/1.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:arty-s7-50:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/arty-s7-50/1.1/1.1/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:cmod-s7-25:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/cmod-s7-25/B.0/1.0/board.xml as part xc7s25csga225-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys2/H/1.1/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-3eg/B.0/1.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_3eg:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-3eg/D.0/1.1/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part digilentinc.com:gzu_5ev:part0:1.1 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Digilent/genesys-zu-5ev/C.0/1.1/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4cg-4e002g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/2.4/board.xml as part xczu4cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4eg-4e002g-e008g-bid:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/2.C/board.xml as part xczu4eg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c4ev-4e002g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c4ev-4e002g-e008g-lia/1.0/2.8/board.xml as part xczu4ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c5ev-4e002g-e008g-bid:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/2.D/board.xml as part xczu5ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c5ev-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/2.5/board.xml as part xczu5ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7cg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/2.1/board.xml as part xczu7cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7cg-4e004g-e008g-liy:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/2.H/board.xml as part xczu7cg-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7ev-4e004g-e008g-lea:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lea/1.0/2.0/board.xml as part xczu7ev-fbvb900-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g30m-c7ev-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/2.B/board.xml as part xczu7ev-fbvb900-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-11eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-11eg-4e004g-e008g-lia/1.0/1.2/board.xml as part xczu11eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-11eg-4e008g-e008g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/1.9/board.xml as part xczu11eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-17eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-17eg-4e004g-e008g-lia/1.0/1.1/board.xml as part xczu17eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bef:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/1.7/board.xml as part xczu19eg-ffvc1760-3-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-big:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/1.6/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bii:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/1.C/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-bij:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/1.D/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g35m-19eg-4e004g-e008g-lia/1.0/1.5/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lie:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/1.4/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e008g-lih:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/1.8/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e004g-e128g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/1.3/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e008g-bie:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/1.A/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e008g-bij:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/1.E/board.xml as part xczu19eg-ffvc1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g35m-19eg-4e008g-e016g-bia:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/1.B/board.xml as part xczu19eg-ffvc1760-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-2cg1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-2cg1-4e002g-e008g-bee/1.0/2.2/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-3eg1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-3eg1-4e002g-e008g-bee/1.0/2.1/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-4ev1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-4ev1-4e002g-e008g-bee/1.0/2.0/board.xml as part xczu4ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-5ev1-4e002g-e008g-bed:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-5ev1-4e002g-e008g-bed/1.0/2.4/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part iwavesystems.com:iw-g36s-5ev1-4e002g-e008g-bee:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/iWave/iw-g36s-5ev1-4e002g-e008g-bee/1.0/2.3/board.xml as part xczu5ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7cg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7CG/1.0/1.0/board.xml as part xczu7cg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7cg:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7CG/2.0/2.0/board.xml as part xczu7cg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7eg:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EG/1.0/1.0/board.xml as part xczu7eg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7eg:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EG/2.0/2.0/board.xml as part xczu7eg-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7ev:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EV/1.0/1.0/board.xml as part xczu7ev-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:brk1900-7ev:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/BRK1900-7EV/2.0/2.0/board.xml as part xczu7ev-ffvc1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7305-s50:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7305-S50/1.0/1.0/board.xml as part xc7s50csga324-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k160t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K160T/1.0/1.0/board.xml as part xc7k160tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k410t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K410T-3E/1.0/1.0/board.xml as part xc7k410tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k410t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K410T/1.0/1.0/board.xml as part xc7k410tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7350-k70t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7350-K70T/1.0/1.0/board.xml as part xc7k70tfbg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k160t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K160T-3E/1.0/1.0/board.xml as part xc7k160tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k160t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K160T/1.0/1.0/board.xml as part xc7k160tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k410t-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K410T-3E/1.0/1.0/board.xml as part xc7k410tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem7360-k410t:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM7360-K410T/1.0/1.0/board.xml as part xc7k410tffg676-1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8305-au15p-1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8305-AU15P-1E/1.0/1.0/board.xml as part xcau15p-ffvb676-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8305-au15p-2e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8305-AU15P-2E/1.0/1.0/board.xml as part xcau15p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8310-au25p:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8310-AU25P/1.0/1.0/board.xml as part xcau25p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8320-au25p:part0:1.2 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8320-AU25P/1.2/1.2/board.xml as part xcau25p-ffvb676-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku060-3e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU060-3E/1.0/1.0/board.xml as part xcku060-ffva1517-3-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku060:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU060/1.0/1.0/board.xml as part xcku060-ffva1517-1-c specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8350-ku115:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8350-KU115/1.0/1.0/board.xml as part xcku115-flva1517-1-c specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part opalkelly.com:xem8370-ku11p:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/OpalKelly/XEM8370-KU11P/1.0/1.0/board.xml as part xcku11p-ffva1156-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:am0010_3eg_1i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/AM0010_3EG_1I/1.0/1.0/board.xml as part xczu3eg-sfvc784-1-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:am0010_4ev_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/AM0010_4EV_1E/1.0/1.0/board.xml as part xczu4ev-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_070_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_70_2C/1.0/1.0/board.xml as part xc7k70tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_070_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_70_2I/1.0/1.0/board.xml as part xc7k70tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2C/1.0/1.0/board.xml as part xc7k160tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2c:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2C/2.0/2.0/board.xml as part xc7k160tffg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_2I/1.0/1.0/board.xml as part xc7k160tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_160_3e:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_160_3E/2.0/2.0/board.xml as part xc7k160tffg676-3 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_325_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_325_2C/1.0/1.0/board.xml as part xc7k325tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_325_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_325_2I/1.0/1.0/board.xml as part xc7k325tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_410_2c:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_410_2C/1.0/1.0/board.xml as part xc7k410tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0741_410_2i:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0741_410_2I/1.0/1.0/board.xml as part xc7k410tfbg676-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0802_2cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0802_2CG_1E/1.0/1.0/board.xml as part xczu2cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0802_2cg_1e:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0802_2CG_1E/2.0/2.0/board.xml as part xczu2cg-sbva484-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2CG_1E/1.0/1.0/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2cg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2CG_1E/2.0/2.0/board.xml as part xczu2cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2eg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2EG_1E/1.0/1.0/board.xml as part xczu2eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_2eg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_2EG_1E/2.0/2.0/board.xml as part xczu2eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/1.0/1.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e:part0:5.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/5.0/5.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/2.0/2.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3cg_1e_tebf0808:part0:6.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3CG_1E/6.0/6.0/board.xml as part xczu3cg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:1.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/1.0/1.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:3.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/3.0/3.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e:part0:5.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/5.0/5.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:2.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/2.0/2.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:4.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/4.0/4.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_3eg_1e_tebf0808:part0:6.0 available at /opt/img/Vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Trenz_Electronic/TE0803_3EG_1E/6.0/6.0/board.xml as part xczu3eg-sfvc784-1-e specified in board_part file is either invalid or not available
+INFO: [Common 17-14] Message 'Board 49-26' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+create_project LOTO /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO -part xc7a100tcsg324-1
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/img/Vivado2024.1/Vivado/2024.1/data/ip'.
+set_property target_language VHDL [current_project]
+add_files -norecurse {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo4.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_u.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd}
+add_files -fileset sim_1 -norecurse /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd
+add_files -fileset constrs_1 -norecurse /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc
+update_compile_order -fileset sources_1
+update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+set_property used_in_synthesis false [get_files /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd]
+set_property top mux6_1_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture arch of entity xil_defaultlib.mux6_1_tb [mux6_1_tb]
+Built simulation snapshot mux6_1_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source mux6_1_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 8254.766 ; gain = 87.168 ; free physical = 8452 ; free virtual = 16896
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 100 us
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 100 us
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture arch of entity xil_defaultlib.mux6_1_tb [mux6_1_tb]
+Built simulation snapshot mux6_1_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source mux6_1_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 8289.652 ; gain = 17.965 ; free physical = 8405 ; free virtual = 16852
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:25]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit mux6_1_tb_arch_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:25]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit mux6_1_tb_arch_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:25]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit mux6_1_tb_arch_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'mux6_1_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'mux6_1_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj mux6_1_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'mux6_1_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot mux6_1_tb_arch_cfg_behav xil_defaultlib.mux6_1_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture arch of entity xil_defaultlib.mux6_1_tb [mux6_1_tb]
+Built simulation snapshot mux6_1_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "mux6_1_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:mux6_1_tb_arch_cfg} -tclbatch {mux6_1_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source mux6_1_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'mux6_1_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 8323.664 ; gain = 34.012 ; free physical = 8419 ; free virtual = 16851
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 100 us
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+set_property top compteur_modulo6_tb_arch_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture arch of entity xil_defaultlib.compteur_modulo6_tb [compteur_modulo6_tb]
+Built simulation snapshot compteur_modulo6_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "compteur_modulo6_tb_arch_cfg_behav -key {Behavioral:sim_1:Functional:compteur_modulo6_tb_arch_cfg} -tclbatch {compteur_modulo6_tb_arch_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source compteur_modulo6_tb_arch_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'compteur_modulo6_tb_arch_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8495.492 ; gain = 65.781 ; free physical = 8092 ; free virtual = 16737
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 100 us
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+relaunch_sim
+Command: launch_simulation -step compile -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'compteur_modulo6_tb_arch_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj compteur_modulo6_tb_arch_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_modulo6_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
+INFO: [Vivado 12-12493] Simulation top is 'compteur_modulo6_tb_arch_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot compteur_modulo6_tb_arch_cfg_behav xil_defaultlib.compteur_modulo6_tb_arch_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture arch of entity xil_defaultlib.compteur_modulo6_tb [compteur_modulo6_tb]
+Built simulation snapshot compteur_modulo6_tb_arch_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+Time resolution is 1 ps
+relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 8543.516 ; gain = 0.000 ; free physical = 8105 ; free virtual = 16693
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+set_property top loto_tb_ar_cfg [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+update_compile_order -fileset sim_1
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur1_49'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'compteur_valid'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'diviseur_freq'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'led_pwm'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'registres'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'transcodeur7s_d_u'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'modulo4'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-3219] choice 'st_wait_success' is already covered [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:76]
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:44]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-3219] choice 'st_wait_success' is already covered [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:76]
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:44]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-3219] choice 'st_wait_success' is already covered [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:76]
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:44]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+ERROR: [VRFC 10-8554] case statement does not cover all choices; 'others' clause is needed [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:44]
+ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit loto_tb_ar_cfg in library work failed.
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-99] Step results log file:'/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log'
+ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim/elaborate.log' file for more information.
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+launch_simulation
+Command: launch_simulation
+INFO: [Vivado 12-12493] Simulation top is 'loto_tb_ar_cfg'
+INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
+INFO: [SIM-utils-72] Using boost library from '/opt/img/Vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
+INFO: [SIM-utils-54] Inspecting design source files for 'loto_tb_ar_cfg' in fileset 'sim_1'...
+INFO: [USF-XSim-97] Finding global include files...
+INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
+INFO: [USF-XSim-2] XSim::Compile design
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xvhdl --incr --relax -prj loto_tb_ar_cfg_vhdl.prj
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'automate'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'tirage'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto'
+INFO: [VRFC 10-163] Analyzing VHDL file "/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto_tb.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'loto_tb'
+Waiting for jobs to finish...
+No pending jobs, compilation finished.
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
+INFO: [USF-XSim-3] XSim::Elaborate design
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Vivado Simulator v2024.1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot loto_tb_ar_cfg_behav xil_defaultlib.loto_tb_ar_cfg -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture a_automate of entity xil_defaultlib.automate [automate_default]
+Compiling architecture a_registres of entity xil_defaultlib.registres [registres_default]
+Compiling architecture a_compteur_valid of entity xil_defaultlib.compteur_valid [compteur_valid_default]
+Compiling architecture compteur_a of entity xil_defaultlib.compteur1_49 [compteur1_49_default]
+Compiling architecture arch of entity xil_defaultlib.led_pwm [led_pwm_default]
+Compiling architecture a_tirage of entity xil_defaultlib.tirage [tirage_default]
+Compiling architecture modulo6_a of entity xil_defaultlib.compteur_modulo6 [compteur_modulo6_default]
+Compiling architecture behavioral of entity xil_defaultlib.diviseur_freq [\diviseur_freq(n_fast=0,n_slow=3...]
+Compiling architecture a_mux6_1 of entity xil_defaultlib.mux6_1 [mux6_1_default]
+Compiling architecture transcod_int of entity xil_defaultlib.transcodeur7s_d_u [transcodeur7s_d_u_default]
+Compiling architecture modulo4_a of entity xil_defaultlib.modulo4 [modulo4_default]
+Compiling architecture arch of entity xil_defaultlib.loto [\loto(n_fast=0,n_slow=3)\]
+Compiling architecture ar of entity xil_defaultlib.loto_tb [loto_tb]
+Built simulation snapshot loto_tb_ar_cfg_behav
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
+INFO: [USF-XSim-4] XSim::Simulate design
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.sim/sim_1/behav/xsim'
+INFO: [USF-XSim-98] *** Running xsim
+ with args "loto_tb_ar_cfg_behav -key {Behavioral:sim_1:Functional:loto_tb_ar_cfg} -tclbatch {loto_tb_ar_cfg.tcl} -log {simulate.log}"
+INFO: [USF-XSim-8] Loading simulator feature
+Time resolution is 1 ps
+source loto_tb_ar_cfg.tcl
+# set curr_wave [current_wave_config]
+# if { [string length $curr_wave] == 0 } {
+# if { [llength [get_objects]] > 0} {
+# add_wave /
+# set_property needs_save false [current_wave_config]
+# } else {
+# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+# }
+# }
+# run 1000ns
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'loto_tb_ar_cfg_behav' loaded.
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
+launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 8734.340 ; gain = 62.820 ; free physical = 8003 ; free virtual = 16648
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 100 us
+restart
+INFO: [Wavedata 42-604] Simulation restarted
+run 100 us
+synth_design -rtl -rtl_skip_mlo -name rtl_1
+Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
+Starting synth_design
+Using part: xc7a100tcsg324-1
+Top: loto
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library.
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 53197
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 9461.027 ; gain = 419.711 ; free physical = 6947 ; free virtual = 15595
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'loto' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'tirage' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'automate' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:21]
+INFO: [Synth 8-256] done synthesizing module 'automate' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:21]
+INFO: [Synth 8-638] synthesizing module 'registres' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'registres' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/registres.vhd:23]
+INFO: [Synth 8-638] synthesizing module 'compteur_valid' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd:15]
+INFO: [Synth 8-256] done synthesizing module 'compteur_valid' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_valid.vhd:15]
+INFO: [Synth 8-638] synthesizing module 'compteur1_49' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'compteur1_49' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur1_49.vhd:16]
+INFO: [Synth 8-638] synthesizing module 'led_pwm' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'led_pwm' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/led_pwm.vhd:18]
+INFO: [Synth 8-256] done synthesizing module 'tirage' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/tirage.vhd:25]
+INFO: [Synth 8-638] synthesizing module 'compteur_modulo6' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-256] done synthesizing module 'compteur_modulo6' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:17]
+INFO: [Synth 8-638] synthesizing module 'diviseur_freq' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd:18]
+ Parameter n_fast bound to: 15 - type: integer
+ Parameter n_slow bound to: 25 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'diviseur_freq' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/diviseur_freq.vhd:18]
+INFO: [Synth 8-638] synthesizing module 'mux6_1' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:20]
+WARNING: [Synth 8-614] signal 'I_2' is read in the process but is not in the sensitivity list [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:23]
+INFO: [Synth 8-256] done synthesizing module 'mux6_1' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:20]
+INFO: [Synth 8-638] synthesizing module 'transcodeur7s_d_u_transcod_int' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-256] done synthesizing module 'transcodeur7s_d_u_transcod_int' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/transcodeur7s_d_u.vhd:64]
+INFO: [Synth 8-638] synthesizing module 'modulo4' [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'modulo4' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/modulo4.vhd:16]
+INFO: [Synth 8-256] done synthesizing module 'loto' (0#1) [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/loto.vhd:21]
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[7] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[6] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[5] driven by constant 1
+WARNING: [Synth 8-3917] design loto has port O_7segmentSelect[4] driven by constant 1
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 9530.996 ; gain = 489.680 ; free physical = 6870 ; free virtual = 15522
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 9542.871 ; gain = 501.555 ; free physical = 6870 ; free virtual = 15522
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 9542.871 ; gain = 501.555 ; free physical = 6870 ; free virtual = 15522
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 9542.879 ; gain = 0.000 ; free physical = 6870 ; free virtual = 15523
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc]
+Finished Parsing XDC File [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9672.621 ; gain = 0.000 ; free physical = 7134 ; free virtual = 15804
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+RTL Elaboration Complete: : Time (s): cpu = 00:00:16 ; elapsed = 00:00:12 . Memory (MB): peak = 9705.465 ; gain = 664.148 ; free physical = 7086 ; free virtual = 15778
+31 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 9705.465 ; gain = 971.125 ; free physical = 7086 ; free virtual = 15778
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2638.097; main = 2627.608; forked = 10.488
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 10012.020; main = 9705.469; forked = 306.551
+export_ip_user_files -of_objects [get_files /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc] -no_script -reset -force -quiet
+remove_files -fileset constrs_1 /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4DDR-Master.xdc
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+add_files -fileset constrs_1 -norecurse /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/Nexys4_Master.xdc
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/automate.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/compteur_modulo6_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/src/mux6_1_tb.vhd:]
+launch_runs impl_1 -to_step write_bitstream -jobs 2
+[Wed Feb 12 11:54:19 2025] Launched synth_1...
+Run output will be captured here: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/synth_1/runme.log
+[Wed Feb 12 11:54:19 2025] Launched impl_1...
+Run output will be captured here: /homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/runme.log
+open_hw_manager
+connect_hw_server -allow_non_jtag
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
+INFO: [Labtools 27-2222] Launching hw_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+****** Xilinx hw_server v2024.1
+ **** Build date : May 22 2024 at 19:19:01
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+
+INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
+INFO: [Labtools 27-3417] Launching cs_server...
+INFO: [Labtools 27-2221] Launch Output:
+
+
+******** Xilinx cs_server v2024.1.0
+ ****** Build date : Apr 27 2024-03:40:49
+ **** Build number : 2024.1.1714182049
+ ** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
+ ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+
+open_hw_target
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210274674965A
+set_property PROGRAM.FILE {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+current_hw_device [get_hw_devices xc7a100t_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
+INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
+set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
+set_property PROGRAM.FILE {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]
+program_hw_devices [get_hw_devices xc7a100t_0]
+INFO: [Labtools 27-3164] End of startup status: HIGH
+refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
+INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
+ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210274674965A
+undo
+INFO: [Common 17-17] undo 'set_property PROGRAM.FILE {/homes/a23delau/MEDCON/tp-loto-etudiant-n23bouch/LOTO/LOTO.runs/impl_1/loto.bit} [get_hw_devices xc7a100t_0]'
+undo
+INFO: [Common 17-17] undo 'set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]'
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+current_sim simulation_4
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+close_sim
+INFO: [Simtcl 6-16] Simulation closed
+exit
+INFO: [Common 17-206] Exiting Vivado at Wed Feb 12 12:17:49 2025...